Circuit and method for detecting clock abnormality, clock circuit, chip and radar

Abstract

The present application relates to a circuit and method for detecting clock anomalies, a clock circuit, a chip, and a radar. The circuit for detecting clock anomalies includes: a first clock frequency determination unit configured to determine a first clock frequency of a received first clock signal; a reference quantity determination unit configured to determine a reference quantity corresponding to the first clock signal, where the reference quantity is determined based on a second clock signal and / or a time stamp; and a clock anomaly detection unit connected to the first clock frequency determination unit and the reference quantity determination unit respectively, and configured to perform anomaly detection on the first clock signal based on the first clock frequency and the reference quantity. The present application can improve the reliability of the clock signal, thereby enhancing the personal safety and property safety of users.

Description

Technical Field

[0001] This application relates to the field of computer technology, and in particular, to a circuit and method for detecting clock anomalies, a clock circuit, a chip, and a radar. Background Art

[0002] With the rapid development of computer technology, information technology, etc., circuits play an increasingly important role in users' daily lives and work. A clock signal can act as a timer in a circuit, ensuring that related electronic components operate synchronously, thereby realizing the preset functions of the circuit.

[0003] Taking autonomous driving technology as an example, a radar can collect environmental information so that the decision-making system of autonomous driving can adopt driving strategies adapted to the environmental information, such as obstacle avoidance. The clock generation unit of the main control chip of the radar is responsible for providing the clock signals required for the operation of the main control chip and at least some functional circuits. Therefore, this clock signal is an important signal relied on by multiple digital circuit functions. The applicant has found that the clock generation unit may physically fail due to factors such as manufacturing or aging, or the clock generation unit may be hacked or controlled, resulting in abnormal radar functions and unable to guarantee the personal and property safety of users. Summary of the Invention

[0004] To solve or partially solve the problems existing in the related art, this application provides a circuit and method for detecting clock anomalies, a clock circuit, a chip, and a radar, which can detect clock anomalies, improve the reliability of clock signals, and thereby improve the personal and property safety of users.

[0005] In a first aspect of this application, a circuit for detecting clock anomalies is provided, including a first clock frequency determination unit, a reference quantity determination unit, and a clock anomaly detection unit. Among them, the first clock frequency determination unit is configured to determine the first clock frequency of the received first clock signal. The reference quantity determination unit is configured to determine a reference quantity corresponding to the first clock signal, and the reference quantity is determined based on a second clock signal and / or a time stamp. The clock anomaly detection unit is respectively connected to the first clock frequency determination unit and the reference quantity determination unit, and is configured to perform anomaly detection on the first clock signal based on the first clock frequency and the reference quantity.

[0006] In a second aspect of this application, a clock circuit is provided, including a first clock generation unit and the circuit for detecting clock anomalies as shown above. Among them, the first clock generation unit is configured to output a first clock signal. The circuit for detecting clock anomalies is connected to the first clock generation unit and is configured to detect the first clock signal.

[0007] A third aspect of the present application provides a chip, including a functional circuit and at least one of the following: the clock circuit as described above or a circuit for detecting clock anomalies. The functional circuit is configured to implement a specific function based on the first clock signal or the second clock signal.

[0008] A fourth aspect of the present application provides a board card, including a circuit for detecting clock anomalies, a clock circuit or a chip as described above.

[0009] A fifth aspect of the present application provides a radar, including at least one of a circuit for detecting clock anomalies, a clock circuit, a chip or a board card as described above.

[0010] A sixth aspect of the present application provides a method for detecting clock anomalies, including: determining a reference quantity corresponding to the first clock signal; determining a first clock frequency of the first clock signal based on the reference quantity; performing anomaly detection on the first clock signal based on the reference quantity and the first clock frequency; wherein the reference quantity is determined based on the second clock signal and / or a timestamp.

[0011] A seventh aspect of the present application provides an electronic device, including: a processor; and a memory storing executable code thereon, which when executed by the processor, causes the processor to execute the method as described above.

[0012] An eighth aspect of the present application provides a computer-readable storage medium storing executable code thereon, which when executed by a processor of an electronic device, causes the processor to execute the method as above.

[0013] A ninth aspect of the present application provides a computer program product including executable code, which when executed, implements the method as above.

[0014] The technical solution provided by the present application may include the following beneficial effects:

[0015] In some embodiments of the present application, the reference quantity for the first clock signal can be determined according to the second clock signal and / or the timestamp, which facilitates the use of the reference quantity to perform anomaly detection on the first clock frequency of the first clock signal. In these embodiments, the reliability of the first clock signal can be detected to perform anomaly detection on the clock circuit, improving the reliability of the clock signal, which helps to improve the personal safety and property safety of users.

[0016] In some embodiments of the present application, the reference quantity may be a reference time period, and the reference time period may be a statistical value of the pulses of a reference clock signal. This facilitates determining whether the number of pulses of the first clock signal occurring within the first reference time period is normal based on the number of pulses of the reference clock signal occurring within the first reference time period, so as to achieve the detection of the first clock signal. In addition, the reference time period may also be the number of pulses that the first clock signal should occur within the time period between any two timestamps. For example, since the preset clock frequency of the first clock signal is a known quantity, the number of pulses that the first clock signal should occur within the time period between any two timestamps can be calculated. Therefore, it is possible to determine whether there is an abnormality in the first clock signal by comparing the number of pulses actually occurring of the first clock signal and the number of pulses that the first clock signal should occur within the above-mentioned time period.

[0017] In some embodiments of the present application, the enable signal and the termination counting instruction provided by the counting control unit can be utilized to ensure the synchronous counting and synchronous stop counting of the two counters, guarantee the accuracy of the counting result, and further improve the accuracy of the detection result.

[0018] In some embodiments of the present application, the threshold corresponding to the number of pulses can be set or modified to facilitate meeting the diverse needs of users. In addition, when a certain clock signal is abnormal, abnormal processing can be performed, and a redundant clock signal can be provided to improve the reliability of the system.

[0019] In some embodiments of the present application, a dedicated second clock generation unit is provided in the circuit for detecting clock abnormalities. This can effectively reduce the probability that the reference clock signal is affected when the first clock generation unit is attacked, and effectively improve the reliability of the detection result.

[0020] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present application. Brief Description of the Drawings

[0021] By describing the exemplary embodiments of the present application in more detail in conjunction with the drawings, the above and other objects, features, and advantages of the present application will become more obvious. Among them, in the exemplary embodiments of the present application, the same reference numerals generally represent the same components.

[0022] Figure 1 It is a schematic diagram of an application scenario of a circuit and method for detecting clock abnormalities, a clock circuit, a chip, and a radar shown in an embodiment of the present application;

[0023] Figure 2 It is a schematic diagram of another application scenario of a circuit and method for detecting clock abnormalities, a clock circuit, a chip, and a radar shown in an embodiment of the present application;

[0024] Figure 3 It is a block diagram of a circuit for detecting clock anomalies shown in an embodiment of the present application;

[0025] Figure 4 It is a schematic diagram of a side-channel attack shown in an embodiment of the present application;

[0026] Figure 5 It is a block diagram of a reference quantity determination unit shown in an embodiment of the present application;

[0027] Figure 6 It is a schematic diagram of a process for determining a reference time period shown in an embodiment of the present application;

[0028] Figure 7 It is a block diagram of a first reference time period determination circuit shown in an embodiment of the present application;

[0029] Figure 8 It is a block diagram of another clock detection circuit shown in an embodiment of the present application;

[0030] Figure 9 It is a schematic diagram of another process for determining a reference time period shown in an embodiment of the present application;

[0031] Figure 10 It is a block diagram of another clock detection circuit shown in an embodiment of the present application;

[0032] Figure 11 It is a circuit diagram of a comparison logic circuit for unit data shown in an embodiment of the present application;

[0033] Figure 12 It is a circuit diagram of a comparison logic circuit for eight-bit data shown in an embodiment of the present application;

[0034] Figure 13 It is a structural schematic diagram of a delay control circuit shown in an embodiment of the present application;

[0035] Figure 14 It is a timing diagram of a circuit for detecting clock anomalies shown in an embodiment of the present application;

[0036] Figure 15 It is a structural schematic diagram of a multiplexer shown in an embodiment of the present application;

[0037] Figure 16 It is a schematic diagram of a process flow for a method of detecting clock anomalies shown in an embodiment of the present application;

[0038] Figure 17 It is a structural schematic diagram of a device for detecting clock anomalies shown in an embodiment of the present application;

[0039] Figure 18It is a schematic structural diagram of a radar shown in an embodiment of the present application;

[0040] Figure 19 It is a schematic structural diagram of an electronic device shown in an embodiment of the present application. Detailed implementation manners

[0041] The embodiments of the present application will be described in more detail below with reference to the accompanying drawings. Although the embodiments of the present application are shown in the drawings, it should be understood that the present application can be implemented in various forms and should not be limited by the embodiments set forth herein. On the contrary, these embodiments are provided so that the present application will be more thorough and complete, and can fully convey the scope of the present application to those skilled in the art.

[0042] The terms used in the present application are only for the purpose of describing specific embodiments and are not intended to limit the present application. The singular forms "a" and "the" used in the present application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term "and / or" as used herein refers to and includes any or all possible combinations of one or more of the associated listed items.

[0043] It should be understood that although the terms "first", "second", "third", etc. may be used in the present application to describe various information, these information should not be limited to these terms. These terms are only used to distinguish the same type of information from each other. For example, without departing from the scope of the present application, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of these features. In the description of the present application, the meaning of "a plurality" is two or more unless otherwise specifically defined.

[0044] For the convenience of understanding the present application, some concepts involved in the present application will be described first.

[0045] Vehicle-mounted radar: The detection range is, for example, 200 meters to 500 meters, and the recognizable physical attributes may only include distance and reflectivity, and can be used for small machines such as vehicles and robots. Vehicle-mounted radars include vehicle-mounted lidar, vehicle-mounted millimeter-wave radar, vehicle-mounted ultrasonic radar, etc.

[0046] Vehicle-mounted lidar: By emitting outgoing light (such as a laser beam) with a wavelength of about 900 nm, the outgoing light will be reflected by an obstacle after encountering the obstacle, and the processing unit calculates the distance between the obstacle and the vehicle-mounted lidar according to the time difference between the reflected light and the outgoing light. In addition, the processing unit can also estimate the reflectivity of the target according to the cross-sectional situation of the reflected light signal obtained after receiving the reflected light. Vehicle-mounted lidar has a small volume and a high degree of integration.

[0047] In an autonomous driving scenario, the system architecture applicable to the autonomous driving scenario may include a mobile device, a network, and the cloud.

[0048] The cloud may include a server cluster or a distributed system composed of multiple physical servers. The cloud may be a cloud server that provides basic cloud computing services such as cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communications, middleware services, domain name services, security services, content delivery (CDN), and big data and artificial intelligence platforms.

[0049] Mobile devices include, but are not limited to: automobiles, ships, robots, aircraft, etc. Electronic devices such as sensors may be provided on the mobile device to obtain information about obstacles in the surrounding environment of the mobile device. The electronic devices may include: radars (including lidars), image sensors, etc. A variety of electronic devices need to use clock signals during operation or communication.

[0050] The embodiment of the present application provides a circuit and method for detecting clock anomalies, a clock circuit, a chip, and a radar. The first clock signal is detected for anomalies based on the first clock frequency of the first clock signal and a reference quantity, where the reference quantity may be determined based on the second clock frequency of the second clock signal, or the reference quantity may be determined based on the number of pulses that should be included between two timestamps. By providing this reference quantity, the clock signal can be detected to ensure the reliability of the clock signal, improve the reliability of the circuit adopted by the user, and further ensure the personal safety and property safety of the user in scenarios such as using assisted / autonomous driving.

[0051] The technical solutions of the embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0052] Figure 1 It is a schematic diagram of an application scenario of a circuit and method for detecting clock anomalies, a clock circuit, a chip, and a radar shown in an embodiment of the present application.

[0053] Figure 1Shows the hardware configuration of a vehicle 10 that supports assisted driving or autonomous driving functions. For example, at least one lidar (Light Detection and Ranging, abbreviated as LIDAR) 11 is mounted on the roof and / or side of the vehicle 10. The detection area of the LIDAR 11 can be fixed. For example, a certain LIDAR 11 can be only used to detect a preset area. The detection area of the LIDAR 11 can be adjustable. For example, the lidar on the vehicle body can scan multiple detection areas by adjusting its attitude, etc., or can scan multiple detection areas by adjusting the field of view range of the lidar itself. Specifically, the vehicle 10 can be equipped with 5 LIDARs 11: on the top of the vehicle, the front side of the vehicle, the rear side of the vehicle, the left side of the vehicle, and the right side of the vehicle. Through multiple LIDARs 11, it is possible to detect the contour of an object existing in the area around the vehicle and the distance to the object.

[0054] In addition, a photographing device can also be mounted on the vehicle 10. The photographing device can photograph the front environment of the view at a specified angle of view. For example, the photographing device can be a monocular camera, a multi-camera, etc.

[0055] In addition, multiple millimeter-wave radars can also be mounted on the vehicle 10 in a way that surrounds the vehicle 10. For example, the vehicle 10 is equipped with 4 millimeter-wave radars, with the left side in front of the vehicle, the right side in front of the vehicle, the left side behind the vehicle, and the right side behind the vehicle as the detection ranges. Through the millimeter-wave radars, it is possible to detect the distance of an object existing in their respective detection areas and can detect the relative speed of the object and the vehicle 10.

[0056] Furthermore, a positioning device 12, such as a Beidou positioning device, a Global Positioning System (abbreviated as GPS), etc., can also be mounted on the vehicle 10. Through the positioning device 12, the current position of the vehicle 10 can be determined.

[0057] In addition, an electronic control unit (abbreviated as ECU) can also be mounted on the vehicle 10. Detection signals of at least one of the above LIDAR 11, millimeter-wave radar, and positioning device 12 are sent to the ECU. The ECU can detect and identify obstacles (such as roadblocks, moving objects, trees, adjacent vehicles, etc. around the vehicle 10) based on these signals. In addition, the ECU can be physically divided into multiple units according to functions, and in this application, they are collectively referred to as the ECU.

[0058] It should be noted that although the movable device is described as an automobile, such a description is not restrictive, and a variety of movable devices are applicable, such as land robots, water robots, etc.

[0059] Figure 2 It is a schematic diagram of another application scenario of the circuit and method for detecting clock anomalies, clock circuit, chip, and radar shown in an embodiment of the present application.

[0060] Figure 2 The illustrated aircraft 20 can be an aircraft with assisted driving function or autonomous driving function. The aircraft 20 may include a sensing system 21 and a power mechanism 22.

[0061] Among them, the sensing system 21 may include one or more sensors to sense at least one of the surrounding obstacles, spatial orientation, speed, or acceleration of the aircraft 20. The types of sensors include but are not limited to: ranging sensors, position sensors, motion sensors, inertial sensors, or imaging sensors. The sensing data provided by the sensing system 21 can be used to control the spatial orientation, speed, and / or acceleration of the aircraft 20. The sensing system 21 is used to collect relevant information of the aircraft 20. Different types of sensors can sense different types of signals or signals from different sources. For example, the sensors include radar, inertial sensors, GPS sensors, or vision / imaging sensors (such as cameras), etc.

[0062] The circuit, method, and clock circuit for detecting clock anomalies in the embodiments of the present application can be applied to any one or more of the following electronic devices that require the use of a clock, such as Figure 1 or Figure 2 the LIDAR 11, millimeter-wave radar, positioning device 12, ECU, sensing system 21, or communication system shown in the figure.

[0063] In the above application scenarios such as assisted driving, autonomous driving, and intelligent transportation, quickly and accurately perceiving the surrounding environment of a movable device is a key point.

[0064] Here, the autonomous driving scenario of a vehicle is taken as an example for exemplary illustration. According to the vehicle position information, obstacle information, road information, etc. sensed by the sensing system, coordinate road signal control, so as to improve the quality and efficiency of road management. Specifically, the corresponding autonomous driving vehicle decisions can be determined according to the information sensed by the sensing system, and the safety distance between autonomous driving vehicles can be adjusted, so that it is convenient to realize that the vehicle can drive safely and reliably on the road.

[0065] As one of the most important sensors for autonomous driving, lidar can provide information such as the position, size, and motion information of traffic participants to the decision-making system in the fields of intelligent transportation, assisted driving, and autonomous driving. Lidar is equivalent to a person's eyes for an autonomous driving vehicle. How to protect the security of lidar data acquisition and transmission is particularly important, which is directly related to the personal safety, property safety, and even life safety of the passengers in the vehicle.

[0066] The main control chip of a lidar is the core component of the lidar. The main control chip is responsible for collecting, processing, and transmitting at least part of the lidar information. The clock of the main control chip provides the clock source required for the operation of relevant functional circuits, which is the basis for realizing the functions of relevant digital circuits. The stability of the clock signal is very important for the lidar and devices that need to use lidar data.

[0067] However, the applicant has found that the clock generation unit may physically fail due to manufacturing defects or aging factors, etc. For example, after aging, the clock generation unit will generate unqualified clock signals, such as clock glitch signals or inaccurate frequencies.

[0068] In addition, the clock generation unit can also be controlled and attacked by hackers, etc., resulting in the failure of the main control chip from the source.

[0069] For example, for the main control chip of a lidar, a hacker can control the clock of the chip to make its clock frequency exceed the maximum frequency of the chip. This will cause the chip to be unstable and make errors. In addition, if the clock of the control chip is unstable at the moment when the main control chip performs a critical command jump or operation, the chip security system will crash.

[0070] For example, a hacker can slow down the behavior of the chip by reducing the clock frequency of the chip, thereby greatly reducing the difficulty of side-channel information analysis and making it easy to analyze the behavior of the main control chip. Figure 3 It is a schematic diagram of a side-channel attack shown in an embodiment of the present application.

[0071] See Figure 3 , signals can be transmitted between Circuit 1 and Circuit 2 through the main channel. In the related art, research is mainly focused on how to avoid signals being stolen or damaged during the transmission process in the main channel. However, during the process of the circuit processing the signal (M) and outputting the signal (M'), the information leaked through the side channel may indirectly characterize the signal processed or transmitted by the circuit. For example, side-channel attacks can be directed against a type of resource-constrained cryptographic integrated circuit.

[0072] For example, the signal of a security chip can be stolen through side-channel analysis technology of the security chip. Specifically, information related to the key can be leaked through power consumption, sound information, electromagnetic radiation, transmission time, execution time, or other detectable information. If the integrated circuit does not take protection measures, it may be possible to crack and obtain the key with only a small cost. The side-channel analysis attack method has become a possible "shortcut" for cracking cryptographic chips and has attracted more and more attention from the academic and industrial communities.

[0073] In summary, the clock circuit may physically generate unqualified clocks due to interference or device aging factors. In the field of lidar technology, there is a lack of hardware monitoring solutions or defense strategies for the clock generation module in related technologies, or it can only rely on relatively complex analog circuits to achieve. There is a lack of a defense monitoring solution from the underlying hardware of the chip in related technologies, resulting in the need to improve the defense strategy against clock frequency attacks.

[0074] For the above reasons, the present application aims to provide a technical solution that can monitor and perform exception handling on the clock generation unit at a relatively low cost and conveniently.

[0075] For example, in some embodiments, for the clock signal output by the clock generation unit, by determining the number of pulses of the clock signal within a specific time period, it is determined whether the clock signal is abnormal.

[0076] For example, in some embodiments, the timestamp in the received data packet can also be used as the time reference period. Specifically, for a clock signal with a specific clock frequency, the number of pulses that should be included in the time period between two timestamps of the clock signal can be determined. Therefore, the clock signal can be detected for abnormalities based on the above number of pulses.

[0077] Detecting clock abnormalities from the above at least one angle can effectively ensure the reliability of the clock signal output by the clock generation unit, thereby facilitating better realization of the safe operation of the lidar, and further enhancing the personal safety and property safety of users.

[0078] In addition, in some embodiments, after detecting an abnormality in the clock generation unit, an interrupt signal or a reset signal can also be issued so that the system can protect and handle the clock generation unit.

[0079] Figure 4 It is a block diagram of a circuit for detecting clock abnormalities shown in an embodiment of the present application.

[0080] See Figure 4 , the circuit 400 for detecting clock abnormalities may include: a first clock frequency determination unit 410, a reference quantity determination unit 420, and a clock abnormality detection unit 430.

[0081] The first clock frequency determination unit 410 is configured to determine the first clock frequency of the received first clock signal. Among them, the first clock signal may be a signal generated by the clock generation unit. The first clock signal is used to periodically correct and synchronize the clocks of all circuits in the system (or all nodes in the network) through a synchronization signal, so that each circuit can achieve precise synchronization.

[0082] The reference quantity determination unit 420 is configured to determine a reference quantity corresponding to the first clock signal, and the reference quantity is determined based on the second clock signal and / or a time stamp. For example, the reference quantity may be a certain clock frequency or a pulse count value, etc.

[0083] The clock anomaly detection unit 430 is respectively connected to the first clock frequency determination unit and the reference quantity determination unit, and is configured to perform anomaly detection on the first clock signal based on the first clock frequency and the reference quantity. For example, by comparing the first clock frequency and the reference quantity to determine whether the first clock signal is normal. For example, by determining the difference between the first clock frequency and the reference quantity to determine whether the first clock signal is normal. For example, performing a logical operation on the first clock frequency and the reference quantity to determine whether the first clock signal is normal. For example, after performing a logical operation on the first clock frequency and the reference quantity, comparing it with a threshold value to determine whether the first clock signal is normal.

[0084] Figure 5 It is a block diagram of the reference quantity determination unit shown in an embodiment of the present application.

[0085] See Figure 5 , the reference quantity determination unit 420 includes a first reference time period determination circuit 4210 and / or a second reference time period determination circuit 4220.

[0086] In some embodiments, the first reference time period determination circuit 4210 is configured to determine a first reference time period, and the first reference time period is a time period determined when the number of pulses for the second clock signal reaches a first count value within the first reference time period. The first reference time period may be a time period with a specific duration or a time period with a random duration. For example, in order to facilitate improving the accuracy of the first reference time period, the pulses of the second clock signal can be counted, and when the count value reaches a preset value, it is considered that the first reference time period is completed. For example, in order to increase the randomness of the test, a random number can be determined, and the pulses of the second clock signal are counted, and when the count value reaches the random number, it is considered that the first reference time period is completed.

[0087] It should be noted that in order to detect the first clock signal based on the same standard as the reference value, the above first clock frequency can be determined based on the above first reference time period. For example, by counting the pulses of the first clock signal within the first reference time period, a count value that can represent the first clock frequency can be obtained for comparison with the count value corresponding to the second clock signal.

[0088] Figure 6 It is a schematic diagram of a process for determining a reference time period shown in an embodiment of the present application.

[0089] See Figure 6 ,Figure 6 The upper part represents a first clock signal, and the lower part represents a second clock signal. During the same first reference time period T1, the number of pulses included in the first clock signal is count 1, and the number of pulses included in the second clock signal is count 2. The respective clock frequencies of the first clock signal and the second clock signal may be the same or different. If the respective clock frequencies of the first clock signal and the second clock signal are the same, then it is possible to compare whether the difference between count 1 and count 2 is within the error range. If the respective clock frequencies of the first clock signal and the second clock signal are different, then it is possible to compare whether the difference between count 1 and count 2 is within the error range of a preset difference threshold (such as the preset difference threshold ± error).

[0090] In some embodiments, the second reference time period determination circuit 4220 is configured to determine a second reference time period, where the second reference time period is the time period between the respective timestamps of two data packets.

[0091] Figure 7 is a block diagram of a first reference time period determination circuit shown in an embodiment of the present application.

[0092] See Figure 7 , in this embodiment, the first reference time period determination circuit 4210 may include a count control unit 4211 and a second counter 4212.

[0093] For example, the second counter 4212 is connected to the clock anomaly detection unit and is configured to, in response to a first enable signal, perform pulse counting on the second clock signal until a preset first count value is reached, and transmit the first count value to the clock anomaly detection unit, and output a count completion signal. Wherein, the first enable signal may be a high-level signal or a low-level signal, such as a high-level pulse signal or a continuous high-level signal.

[0094] The count control unit 4211 is respectively connected to the first counter and the second counter 4212 as shown above, and is configured to output a first enable signal to the first counter and the second counter; and in response to the count completion signal, output a termination count instruction to the first counter, and send a second enable signal to the clock anomaly detection unit, so that the clock anomaly detection unit performs anomaly detection on the first clock signal based on the first count value and the second count value. The termination count instruction may be characterized by a high-level signal and / or a low-level signal. For example, the second counter outputs a count completion flag to the count control unit 4211. The second enable signal may be a high-level signal or a low-level signal, such as a high-level pulse signal or a continuous high-level signal.

[0095] The first counter and the second counter can each record the number of pulses. The counter consists of a basic counting unit and some control gates, and the counting unit can be composed of a series of various flip - flops with the function of storing information. It should be noted that the above - mentioned first counter and second counter can each be implemented by hardware, each can be implemented by software, and each can be implemented by a combination of software and hardware.

[0096] Taking the addition counter as an example, a binary addition counter can be constituted by flip - flops. Specifically, a 3 - bit binary asynchronous adder composed of 3 flip - flops T triggered by the falling edge. The output signal of the flip - flop T is controlled by the pulse signal, and the counter starts counting from the state Q2Q1Q0 = 000.

[0097] Under the trigger of the falling edge of the counting input pulse CP, the output Q0 of the flip - flop FF0 needs to be inverted, 0 becomes 1 or 1 becomes 0. Since CP1 is taken from Q0, under the trigger of the falling edge of Q0, the output Q1 of the flip - flop FF1 needs to be inverted. Similarly, since CP2 = Q1, under the trigger of the falling edge of Q1, the output Q2 of the flip - flop FF2 needs to be inverted. If flip - flops T′ triggered by the rising edge are used, an asynchronous binary addition counter can also be formed, but the carry pulse of each stage of the flip - flop should be changed to the output of the Qˉ end. This is because when the output Q end of the low - order flip - flop changes from 1 to 0, the rising edge of the Qˉ end can just be used as the trigger pulse for the high - order one.

[0098] Taking the subtraction counter as an example, if the flip - flops T′ are connected according to the binary subtraction rule, a binary subtraction counter can be obtained. According to the binary subtraction counting rule, if the low - order flip - flop is already 0, after inputting a subtraction counting pulse, it should be inverted to 1, and at the same time, a borrow signal is sent to the high - order one to make the high - order one flip.

[0099] Taking the example of counting by software, the operation: n&(n–1) can be repeatedly executed until n becomes 0. Among them, the function of the operation: n&(n–1) is to remove the last 1 of n, that is, the last 1 of n becomes 0. For example, let n = 11111, then the calculation process is as follows: n = 11110, the count is 1; n = 11100, the count is 2; n = 11000, the count is 3; n = 10000, the count is 4; n = 00000, the count is 5.

[0100] In some embodiments, the above - mentioned circuit may further include: an exception handling unit. Figure 8 It is a block diagram of another clock detection circuit shown in an embodiment of the present application.

[0101] See Figure 8, the exception handling unit may include at least one of the following: an interrupt signal generation module or a reset signal generation module.

[0102] Wherein, the interrupt signal generation module is configured to output an interrupt signal when the first clock signal is abnormal. The reset signal generation module is configured to output a reset signal when the first clock signal is abnormal.

[0103] For example, the reset signal is a signal output when the clock is abnormal for a short time (such as one or several cycles), and is used to improve the quality of the clock by means of reset and restart. If the clock generation circuit outputs an abnormal clock within a short time period due to external interference or other factors, in order to improve the quality of the clock signal, the reset signal generation module can output a reset signal to functional circuits such as a central processing unit (CPU).

[0104] For example, the interrupt signal is a signal output when the clock quality is continuously low for a long time (such as exceeding a specific number of counting times), and is used for clock exception handling. For example, when the clock signal is still in an abnormal state after the reset process based on the reset signal, in order to improve the personal safety and property safety of the user, the interrupt signal generation module can output an interrupt signal to a control unit such as a central processing unit (CPU) to control the clock generation unit to stop outputting the clock signal, or switch to an alternative clock signal, etc.

[0105] The following provides an exemplary description of anomaly detection based on a reference time period.

[0106] Figure 9 is a schematic diagram of another process for determining a reference time period shown in an embodiment of the present application.

[0107] See Figure 9 , Figure 9 The upper part of represents the first clock signal. The second time period T2 is determined based on the timestamps included in two data packets respectively, such as T2 = timestamp 2 - timestamp 1. Since the ideal clock frequency of the first clock signal is stable and known (such as a preset value or a fixed value), the expected count 2 of the pulses that should be included in the second time period T2 can be calculated based on the clock frequency. In addition, the number of pulses included in the first clock signal within the second time period T2 can also be determined by counting, etc., as count 1. In this way, it can be compared whether the difference between count 1 and the expected count 2 is within the error range.

[0108] To conveniently determine the clock frequency of the first clock signal, the counter counting method can be used to determine the clock frequency. Specifically, the first clock frequency determination unit includes a first counter, which is connected to the clock anomaly detection unit and is configured to perform pulse counting on the first clock signal within the first reference time period to obtain a second count value, and transmit the second count value to the clock anomaly detection unit.

[0109] Figure 10 It is a block diagram of another clock detection circuit shown in an embodiment of the present application. It should be noted that when performing anomaly detection based on a reference time period, Figure 10 the second clock generation unit, the second counter, the counting control unit in

[0110] and their connection relationships can be ignored or omitted. Figure 9 and Figure 10 Please refer to

[0111] simultaneously. The reference time period can be the time period length between two captured data packets, and it can be determined whether it is within a reasonable range based on the number of pulses included in the first clock signal within this time period length. Specifically, for a first clock signal with a specific clock frequency, the number of pulses it includes within a specific length time period should be within a fixed number interval. For example, for a clock signal with a clock frequency of 2.0 gigahertz (GHz), when the time period length is 1 second (s), this clock signal includes 2 billion pulses (signals), and each clock signal period is 0.5 nanosecond. Therefore, the number of pulses included in the first clock signal to be detected within 1 second can be counted. If the difference between the counting result and 2 billion is within the error range, it can be generally determined that the first clock signal is in a normal state.

[0112] For ease of understanding, first, an exemplary description of a comparator for 1-bit parallel values is given.

[0113] Assume that two 1-bit binary numbers are respectively A i , B i , then the comparison result is L A>B , L A<B , L A＝B . The truth table for 1-bit value comparison is shown in Table 1.

[0114] Table 1

[0115]

[0116] The three output functional expressions of the 1-bit parallel comparator can be shown as in Equations (1) to (3).

[0117]

[0118]

[0119]

[0120] Based on the above three output functions, a comparator circuit can be designed.

[0121] Reference Figure 11 As shown, Ci represents the comparator circuit, which may include a combination of multiple logic operation circuits. For example, Figure 11 in 1 can be represented by a high level. & represents bitwise AND, and the bitwise operation process includes: converting the character into binary representation and then performing bitwise operations.

[0122] For comparators of multi-bit values, the comparison principle of giving priority to the high bits can be adopted. For example, for two four-bit value comparators A and B, A = A4A3A2A1, B = B4B3B2B1. If A4 > B4, then A > B. If A4 < B4, then A < B. When the high bits are equal, compare the next high bits according to the same principle, and so on until the comparison of the lowest bit is completed.

[0123] In addition, in addition to comparing these four bits, when these four bits are equal, the comparison result input of the lower bits can also be compared to enable comparison of more bits. To implement the above functions, this embodiment also provides a truth table for four-bit value comparison, as shown in Table 2.

[0124] Table 2

[0125]

[0126]

[0127] Based on Table 2, output functions as shown in Equations (4) to (6) can be obtained. In Table 2, × indicates that no calculation is required. G4 represents that the value of the fourth bit of value A is greater than the value of the fourth bit of value B, and the meanings of G3, G2, and G1 are similar. L4 represents that the value of the fourth bit of value A is less than the value of the fourth bit of value B, and the meanings of L3, L2, and L1 are similar. E4 represents that the value of the fourth bit of value A is equal to the value of the fourth bit of value B, and the meanings of E3, E2, and E1 are similar.

[0128] L A>B = G4 + E4G3 + E4E3E2 + E4E3E2G1 + E4E3E2E1l A>B Equation (4)

[0129] L A<B = L4 + E4L3 + E4E3L2 + E4E3E2L1 + E4E3E2E1l A<B Equation (5)

[0130] LA＝B = E4E3E2E1l A＝B Equation (6)

[0131] where l A>B indicates that the lower four - bit value of data A is greater than the lower four - bit value of data B, l A<B indicates that the lower four - bit value of data A is less than the lower four - bit value of data B, l A＝B indicates that the lower four - bit value of data A is equal to the lower four - bit value of data B.

[0132] For the circuit diagram of the multi - bit value comparator, see Figure 12 . Among them, C1 - C4 each represent a combination of multiple logic operation circuits. For example, it can adopt the logic operation circuit as shown in Figure 11 where C i is shown.

[0133] It should be noted that Figure 11 and Figure 12 the combinations of the logic operation circuits shown are only exemplary examples and are not limited here. It should be noted that logical operations include but are not limited to: "OR", "AND", "NOT", "NOR", "NAND", "XOR", etc. Logic operation circuits include but are not limited to: "OR operation circuit", "AND operation circuit", "NOT operation circuit", "NOR operation circuit", "NAND operation circuit", "XOR operation circuit", etc. These logic operation circuits can also be called logic operation units. In order to implement the comparison of the magnitude relationship between two values, multiple combinations of logic operation circuits can be used for implementation. Correspondingly, multiple combinations of logic operation circuits can be used for implementation, which is not limited here.

[0134] Taking the comparison of values in software as an example, the comparison functions of the database include but are not limited to the functions shown below. BETWEEN AND: Determine whether it is between the two (including the boundaries), and the output results include not between the two (NOT) and between the two (BETWEEN). IN(x1, x2, x3,...): Determine whether the input value is equal to one of the values in the value list, and the output results can be not in the list (NOT) or in the list (IN). CASE WHEN: Output a certain result under certain conditions.

[0135] In some embodiments, the counting control unit includes a delay control circuit. For example, the monitoring process of the first clock signal is not carried out all the time (such as considering the influence of power consumption, heat dissipation, etc.). After completing one round of monitoring, such as after completing the monitoring of the first clock signal based on the first reference time period and / or the second reference time period, a certain delay duration can be set, and then an enable signal is sent to the counter to start the next round of monitoring.

[0136] Figure 13 It is a schematic structural diagram of the delay control circuit shown in the embodiments of the present application.

[0137] Refer to Figure 13 , before the delay control circuit is powered on, such as before the switch S is closed, the voltage U2 across the capacitor C is 0V, which is a stable state. When the switch S is closed, the voltage U2 across the capacitor C gradually rises and finally reaches the value U1 of the electromotive force of the power supply, and can be stabilized at this value. At this time, it is another stable state U2 = U1 of the delay control circuit.

[0138] Among them, the voltage U2 across the capacitor C does not change instantaneously from U2 = 0 to U2 = U1 after the switch S is closed, but has a gradual change process. The values of the resistor R and the capacitor C are different, and the duration of this process is also different. This characteristic can be used to implement the delay function, and a delay circuit with a specific extended duration can be implemented by selecting components with specific resistance values and capacitance values. It should be noted that in order to implement the above-mentioned gradual change process, it can be achieved by means of energy storage elements in the circuit, such as in addition to capacitor elements, inductance elements can also be used. The RC circuit adopted in this embodiment realizes the delay function. In addition, components with switch functions such as transistors are arranged in the RC circuit to realize the function of a delay switch.

[0139] For example, the delay duration t of the delay circuit can be calculated by formula (7).

[0140] t = -R × C × Ln((E - V) / E) Formula (7)

[0141] Among them, the resistor R and the capacitor C are connected in series. The unit of the resistor R is ohm, and the unit of the capacitor C is F. E is the voltage between the series resistor and the capacitor, and V is the voltage of the capacitor. Ln is the natural logarithm. For example, when R = 50K and C = 3mF, and the voltage of the capacitor is 12V, the duration when the voltage across the two poles of the capacitor C reaches 5V is: (50 × 1000 × 3 / 1000) × Ln(12 - 5) / 12 = 24.3 (seconds).

[0142] The above shows the embodiments of the comparator and the delay circuit. For the convenience of more comprehensively understanding the technical solution of the present application, the following makes an exemplary description of the first reference time period determination circuit, etc.

[0143] In some embodiments, in order to effectively detect the clock signal abnormality caused by external reasons, such as avoiding the detection result abnormality caused by the reference clock signal being affected by external reasons as well, a reference clock generation unit for generating a reference clock signal is further provided in the circuit for detecting clock abnormality in this embodiment.

[0144] Among them, the frequency of the reference clock signal (hereinafter simply referred to as the second clock signal) generated by the reference clock generation unit may be the same as or different from the frequency of the first clock signal. For example, a crystal oscillator with the same oscillation frequency as that in the first clock generation unit can be set in the second clock generation unit. For example, the second clock generation unit may include a crystal oscillator, a crystal oscillator control chip, and a capacitor. For example, an oscillation circuit can be set in the second clock generation unit to reduce the cost of generating the second clock signal.

[0145] In some embodiments, the first reference time period determination circuit further includes: a second clock generation unit, connected to the second counter, and configured to output a second clock signal to the second counter. Among them, the second clock generation unit may include an oscillation circuit.

[0146] The reasons for using an oscillation circuit to generate the second clock signal in this embodiment are as follows: On the one hand, the materials of the chip and the crystal oscillator are silicon and quartz respectively, which are not easy to be integrated in the same circuit and the cost is relatively high. On the other hand, once the crystal oscillator is packaged inside the chip, the oscillation frequency is fixed and it is not convenient to change the oscillation frequency. Although the fixed oscillation frequency can be adjusted by frequency multiplication / division such as a Phase Locked Loop (PLL), the cost is relatively high. On the other hand, setting an independent oscillation circuit in the first reference time period determination circuit helps to reduce the cost of the circuit for detecting clock anomalies and reduces the risk that the second clock signal and the first clock signal are interfered by the same interference source.

[0147] Among them, the oscillation circuit can adopt an RC oscillation circuit or an LC oscillation circuit, etc. The RC oscillation circuit is composed of an RC frequency selection network and is suitable for low-frequency oscillation, generally used to generate low-frequency signals of 1 Hz to 1 MHz (megahertz). For the RC oscillation circuit, increasing the resistance R can reduce the oscillation frequency, and increasing the resistance does not require additional cost. If an LC oscillation circuit is used, a sine wave with a higher frequency can be generated. If a sine oscillation with a lower frequency is to be generated, the oscillation loop requires a larger inductor and capacitor, and the required component volume is larger, and the cost is higher than that of the RC oscillation circuit. For example, for a sine oscillation circuit below 200 kHz, an RC oscillation circuit with a lower oscillation frequency can be adopted.

[0148] For example, the RC oscillation circuit can adopt an RC phase-shift oscillator. The oscillation frequency of the RC phase-shift oscillator is: f = 1 / (2πRC). Combining the RC series-parallel frequency selection network and an amplifier can form an RC oscillation circuit, and the amplifying device can adopt an integrated operational amplifier.

[0149] Specifically, an RC series-parallel frequency selection network is connected between the output terminal and the non-inverting input terminal of the operational amplifier to form positive feedback. And the resistor connected between the output terminal and the inverting input terminal of the operational amplifier forms negative feedback. The positive feedback circuit and the negative feedback circuit form a Wien bridge circuit, and the input terminal and the output terminal of the operational amplifier are respectively connected across the diagonals of the bridge to form an RC bridge oscillator circuit. In addition, an adjustable dual potentiometer or an adjustable dual capacitor can be used to conveniently adjust the oscillation frequency. For example, a high-stability capacitor can be switched to perform coarse tuning of the frequency, and then an adjustable dual potentiometer can be used to perform fine tuning of the frequency.

[0150] In some embodiments, the above circuit for detecting clock anomalies may further include: a first reference time period configuration unit for configuring data such as comparison thresholds.

[0151] For example, the first reference time period configuration unit is connected to the first count comparator and is configured to store a first preset difference threshold and / or a second preset difference threshold, and transmit the first preset difference threshold and / or the second preset difference threshold to the first count comparator.

[0152] Please refer to Figure 6 , the first frequency of the first clock signal and the second frequency of the second clock signal may be the same or different. For example, when the first frequency of the first clock signal is the same as the second frequency of the second clock signal, considering error problems (such as the accuracy of the clock signal generated by the RC oscillator circuit may be lower than that of the clock signal generated based on the crystal oscillator, resulting in a certain difference in the number of pulse signals included in the same time period T1. At this time, this problem can be eliminated by setting an error (such as the first preset difference threshold)). For example, when the first frequency of the first clock signal is different from the second frequency of the second clock signal, the number of pulse signals that should be included in the same time period T1 can be determined, so that the second preset difference threshold can be set based on the difference between the number of pulse signals that should be included. It should be noted that the second preset difference threshold may include the difference caused by the error.

[0153] In a specific embodiment, first, the legal high-frequency and low-frequency count value ranges are configured into the first reference time period configuration unit before the circuit is used, for subsequent comparison of the number of pulses.

[0154] Next, a first clock signal is received (such as the first clock signal provided by the system, which is supplied to all functional circuits of the system. The received first clock signal is transmitted to the clock anomaly detection unit for counting.

[0155] Then, the circuit for detecting clock anomalies performs clock anomaly detection at regular intervals. For example, when it is necessary to start the detection, the counting control unit transmits an enabling signal to the first counter and the second counter to start counting.

[0156] The first counter counts the clock to be detected, and the second counter counts the second clock signal generated by the built-in RC oscillator circuit. Among them, the built-in RC oscillator circuit is responsible for generating a stable low-frequency clock, which is used as a reference clock to measure the clock under test.

[0157] When the count value of the second counter reaches a preset value, such as 1000 clock cycles. It will transmit the completion flag to the counting control unit.

[0158] After receiving the counting completion flag of the second counter, the counting control unit simultaneously controls the counters to stop counting, and the count values of the first counter and the second counter are transmitted to the first count value comparator, and at the same time, a comparison enabling signal is output to the counter comparator to start the numerical value comparison.

[0159] The first count value comparator compares according to the difference between the two received count values and the legal high-frequency and low-frequency count value ranges configured by the user, and judges whether the difference between the two count values is within the legal range. If the difference is within the legal range, it is legal. If the difference is greater than the configured maximum count value or less than the minimum count value, it is considered illegal. A difference greater than the configured maximum count value indicates that the frequency is too high. A difference less than the minimum count value is considered to be too low a frequency. For example, if the difference between the count value of the first counter and the count value of the second counter is 1000, and the legal range is from 980 to 1020, exceeding this range is regarded as an illegal frequency.

[0160] The first count value comparator can transmit the detection result to the interrupt signal generation module and / or the reset signal generation module to generate an interrupt signal and / or a reset signal. For example, the interrupt signal causes the CPU to perform illegal clock processing. The reset signal can reset the key signals in the key information cache unit in the chip, making these signals return to the reset value state, and at the same time, it can also prevent hackers from obtaining these key signals.

[0161] The embodiment of the present application provides a security circuit design scheme with a real-time clock monitoring function, which can automatically detect whether there are illegal high-frequency or low-frequency signals on the clock signal, and issue an interrupt and / or a reset signal to protect the system after detecting a clock anomaly.

[0162] The embodiment of the present application is based on the design of digital circuits, which can enable the monitoring circuit to be implemented using digital circuits. Implementing using digital circuits is much better than implementing using analog circuits in terms of both cost and stability.

[0163] In some embodiments, in order to improve the generalizability of the solution for detecting clock anomalies, for the relevant application scenarios of clock anomaly detection for nodes in the network (such as controllers, upper computers, computers, etc.), it is not necessary to additionally add an oscillation circuit for generating a second clock signal, etc. Specifically, the time stamps can be obtained by parsing the data packets transmitted in the network, and the clock signal can be detected for anomalies based on the time stamps.

[0164] Specifically, the second reference time period determination circuit may include a time unpacking unit.

[0165] The time unpacking unit, connected to the first network, is configured to parse the data packets from the first network to obtain time stamps. The data packets transmitted by the first network have time stamps, so as to sort the received multiple data packets based on the chronological order of the time stamps.

[0166] For ease of understanding, Time-Sensitive Networking (TSN for short) is used for exemplary illustration. TSN is a protocol family that realizes the minimum time delay with certainty in non-deterministic Ethernet. It is a set of protocol standards developed by the TSN working group in the IEEE802.1 working group, which defines the time-sensitive mechanism for Ethernet data transmission, adding certainty and reliability to standard Ethernet to ensure the real-time, deterministic and reliable transmission of data. The data packets supporting the TSN network need to have time stamps (Time Stamp), and are played back according to the "time stamp" in the data packet header after the data arrives. Therefore, each network terminal device must perform "clock synchronization", that is, perform clock calibration.

[0167] The protocol data unit (PDU) of the physical layer is a data bit (bit), the PDU of the data link layer is a data frame (frame), the PDU of the network layer is a data packet (packet) or message, and the PDU of the transport layer is a data segment (segment).

[0168] A message is a data unit exchanged and transmitted in the network and is also a unit of network transmission. A message contains the complete data information to be sent, and its length does not need to be consistent. Messages will be continuously encapsulated into packets, packages, and frames during transmission. The encapsulation method is to add a header composed of some control information, which is the message header.

[0169] A data packet is a binary format unit in network transmission. A data packet is a data unit in TCP / IP communication protocol transmission. The basic unit of data transmitted through a network, which contains a header and the data itself. The header describes the destination of the data and its relationship with other data. It can be understood as a grouping of data transmission. We call the basic data unit transmitted through the network a Datagram.

[0170] The packets captured by packet capture operations are packets at the transport layer. When packet / frame / Datagram / segment exist in the same record, these are given different names based on the different protocol layers they belong to.

[0171] For example, a log includes the following information: 11x.9x.1xx.xx--13575743 "GET http: / / www.examples.com / index.htm HTTP / 1.1" 200 14702 "http: / / www.examples.com / " "Moz / 4.0 (compatible; MSIE 6.0; Windows NT x.1; SVx)" TCP_HIT:NONE 1

[0172] Among them, the fourth field 13575743 of the log is a timestamp, which is the number of seconds since January 1, 1970 00:00:00 UTC. A timestamp is a series of characters that can provide the actual date and time (sometimes accurate to a fraction of a second) to help identify the occurrence time of a specific event. The arrival time interval of the smallest 64-byte data packet in a gigabit network is 0.512 microseconds, that is, 512 nanoseconds.

[0173] In some embodiments, the conversion can be performed through built-in functions, such as #head access.log|awk '{print strftime("%y / %m / %d %T",$4)}'.

[0174] Taking hardware decoding as an example for exemplary illustration. The received message includes the following string:...68 2c 866f 00 00 00 00 6f 0a 08 00.... Then the second information is: 0x6f862c68, and the microsecond information is: 0x080a6f. In this way, the complete timestamp can also be parsed.

[0175] The process of extracting the timestamp depends on how the first timestamp is added. The first timestamp can be protected by at least one of integrity protection, authentication protection, and encryption. And thus, when applicable, the extraction will involve the reversal of these operations. Therefore, the extraction may involve integrity verification, authentication verification, and decryption.

[0176] In some embodiments, the clock anomaly detection unit includes a second count value comparator, and the second count value comparator includes a buffer unit configured to store the count value from the first counter in response to the second count value comparator receiving a timestamp. Specifically, after the clock anomaly detection unit is powered on, the first counter starts to operate, the time unpacking unit starts to capture and unpack packets, and outputs the unpacked timestamp to the count value comparator. The count value comparator includes a buffer that stores the first time count value from the first counter in response to the first timestamp. The count value comparator compares the first time count value with the second time count value from the first counter in response to the second timestamp to obtain a clock monitoring result. In addition, the second time count value can be used to replace the first time count value. Repeat the above operations until the clock anomaly detection unit is powered off.

[0177] It should be noted that after the count value comparator completes one round of count value comparison, it can output signals such as initialization signals to the first counter to cause the first counter to restart counting, reducing the risk of data overflow.

[0178] In some embodiments, the above circuit for detecting clock anomalies may further include a second reference time period configuration unit. For example, the second reference time period configuration unit is connected to the clock anomaly detection unit and is configured to store the mapping relationship between the difference between timestamps and a preset difference threshold, so that the clock anomaly detection unit can find the preset difference threshold corresponding to the difference between timestamps. The determination process of the mapping relationship can be as follows.

[0179] Please refer to Figure 9 , and the number of pulses corresponding to the first clock signal (expected count 2) can be calculated based on the time period T2 between two timestamps. Then, pulse counting is performed on the first clock signal, which facilitates comparing count 1 with the expected count 2 to determine whether there is a clock anomaly.

[0180] Figure 9 shows an application scenario for determining the expected count 2 based on the clock frequency of the first clock signal. In addition, the expected count 2 can also be determined at a preset clock frequency, such as when the preset clock frequency is different from the clock frequency of the first clock signal. At this time, the expected count 2 can be determined by calibration or calculation, etc. Through the above methods, the preset difference threshold corresponding to the difference between timestamps can be determined.

[0181] In a specific embodiment, a TSN network timestamp parsing unit is added beside the original RC circuit. The TSN network can be used as a time-sensitive network in vehicles, and the timestamps in the transmitted data can be used for the time synchronization of radars.

[0182] The second reference time period configuration unit is configured to store the legal maximum and minimum values of the corresponding clock counter when using the RC oscillation circuit as the reference count value, and the legal maximum and minimum values of the corresponding clock counter when using the TSN network timestamp as the reference time period.

[0183] The time unpacking unit is configured to parse the timestamp information from the TSN network packet. The timestamp contains accurate time information, and the timestamp information is transmitted to the second reference time period configuration unit and the count value comparison unit. Since there is an accurate time difference between every two timestamps, the legal maximum and minimum values of the corresponding legal clock counter when using the TSN timestamp can be configured as the judgment criteria for whether the clock is normal.

[0184] Either the RC oscillation circuit or the TSN network can be used as a time reference to measure the clock generated by the clock generation unit.

[0185] In some embodiments, the first reference time period determination circuit and the second reference time period determination circuit can also be used in cooperation. For example, when the result of the abnormal detection of the first clock signal based on the first reference time period determination circuit is that the clock is abnormal, the abnormal detection of the first clock signal can be further performed based on the second reference time period determination circuit to verify the detection result based on the first reference time period determination circuit. Another example is that if the weights of the detection results determined by the first reference time period determination circuit and the second reference time period determination circuit are W1 and W2 respectively, the weighted sum of the respective abnormal scores can be performed based on the two weights to improve the accuracy of the detection result.

[0186] It should be noted that each of the first preset difference threshold and the second preset difference threshold can include multiple levels: low-quality threshold level, abnormal threshold level, etc. Among them, when the clock frequency of the first clock is greater than the abnormal threshold level and less than the low-quality threshold level, a reset signal can be output. The quality of the clock is improved through the reset signal. It should be noted that the above conditions for outputting the reset signal are only for illustrative purposes and should not be construed as a limitation of the present application. Specifically, the reset signal will reset the main circuit and clear the key information. When the clock frequency of the first clock is greater than the abnormal threshold level and greater than the low-quality threshold level, an interrupt signal can be output.

[0187] It should be noted that the conditions for the above output interruption signal are only for illustrative purposes and should not be construed as a limitation of this application. The potential risks brought by the abnormal clock to the user can be reduced through the interruption signal. Specifically, the interruption signal can be sent to the central processing unit (CPU), enabling the CPU to respond to the interruption signal and perform corresponding processing according to the type of interruption, such as destroying important information, restarting, shutting down the first clock generation unit, etc. In addition, other processing methods can be introduced in addition to reset and interruption processing, such as replacing the clock generation unit channel, alarming, etc., which are not limited herein.

[0188] Figure 14 It is a timing diagram of a circuit for detecting clock anomalies shown in an embodiment of the present application.

[0189] See Figure 14 , in the timing diagram, the power-on signal, the first clock signal, the enable signal, and the second clock signal are shown in sequence from bottom to top. After power-on, the circuit for detecting clock anomalies receives the first clock signal output from the first clock generation unit. The count control unit sends an enable signal to the first counter and the second counter. The length t1 of the high-level segment in the enable signal can be divided into two types: 1. The time length (T1 + T2 + T3 +... + Tn, n is the preset number of pulses) when the first counter counts up to the preset number of pulses; 2. A preset time length, where the preset time length can be set and is not limited herein. Since the clock frequency is very high (the count value may be very large), if the time length when the first counter counts up to the preset number of pulses is adopted, the risk of count overflow caused by an inappropriate preset time length can be effectively reduced, and the accuracy of anomaly detection can be improved.

[0190] Figure 14 The length of the time period T0 in [] can be determined by the count control unit, such as the time length of T0 is determined by the delay control circuit. Specifically, it can be calculated by formula (7). Figure 14 The first clock frequency of the first clock signal and the second clock frequency of the second clock signal shown in [] can be the same or different.

[0191] The circuit for detecting clock anomalies provided by the present application can be applied to multiple fields such as precise three-dimensional (3D) modeling, detection, home decoration, driverless, and drones.

[0192] The circuit for detecting clock anomalies provided by the present application can automatically detect whether the clock signal output by the clock generation unit has an illegal high-frequency or low-frequency signal, and after detection, send an interruption and reset signal to notify the system to protect and handle the main control chip.

[0193] On the other hand, the present application also provides a clock circuit.

[0194] The clock circuit may include a first clock generation unit and a circuit for detecting clock anomalies.

[0195] Among them, the first clock generation unit is configured to output a first clock signal. The circuit for detecting clock anomalies is as shown in the above related content. It is connected to the first clock generation unit and is configured to detect the first clock signal. For example, the first clock generation unit may include devices such as a quartz crystal oscillator.

[0196] In some embodiments, the above circuit for detecting clock anomalies may further include a multiplexer (abbreviated as MUX).

[0197] Among them, the multiplexer is connected to the clock anomaly detection unit and is configured to output the first clock signal when the clock of the first clock signal is normal, or output a second clock signal when the clock of the first clock signal is abnormal.

[0198] Figure 15 It is a schematic structural diagram of the multiplexer shown in the embodiments of the present application.

[0199] See Figure 15 , the multiplexer can be a two-way selector. It should be noted that in order to implement the path for replacing the clock signal, at least one of the following can also be used: a wiring switch, a Look-Up-Table (LUT) circuit, etc.

[0200] Specifically, the implementation logic of the two-way MUX can be as shown in Equation (8).

[0201]

[0202] Among them, Y is the signal output by the MUX, S is the control signal, is non-S, and A and B are the two signals input to the MUX.

[0203] Figure 15 In, the two-way selector is composed of an AND gate 151, a NOT gate 152, and an OR gate 153. It should be noted that Figure 15 The circuit shown is only an example, and more or fewer logic circuits can also be used to implement the multiplexer. The logic circuits include but are not limited to: "OR operation circuit", "AND operation circuit", "NOT operation circuit", "NOR operation circuit", "NAND operation circuit", "XOR operation circuit", etc.

[0204] The multiplexer provided in this embodiment is configured to switch the function circuit clock to the built-in reference clock when the current clock signal is illegal, so as to prevent the function circuit from operating on an illegal clock. When the clock signal is normal, the path corresponding to the first clock generation unit is adopted. Thus, the function based on the clock signal can be realized, and the personal safety and property safety of users can be improved accordingly.

[0205] On the other hand, this application also provides a chip. The chip may include the clock circuit as described above, and a function circuit that realizes specific functions based on the clock signal output by the clock circuit. The function circuit includes but is not limited to: a processor, a transmitter, a receiver, etc.

[0206] In a possible implementation manner, on the other hand, this application also provides a board card, which includes a storage device, an interface device, a control device, and the above-mentioned chip. Among them, the chip is respectively connected to the storage device, the control device, and the interface device. The storage device is configured to store data. The interface device is configured to realize data transmission between the artificial intelligence chip and external devices. The control device is configured to monitor the state of the artificial intelligence chip.

[0207] On the other hand, this application also provides a method for detecting clock anomalies.

[0208] Figure 16 It is a schematic flowchart of the method for detecting clock anomalies shown in an embodiment of this application.

[0209] See Figure 16 , the method for detecting clock anomalies may include operation S1610 to operation S1630.

[0210] In operation S1610, a reference quantity corresponding to the first clock signal is determined. Among them, the reference quantity is determined based on the second clock signal and / or the time stamp.

[0211] In operation S1620, the first clock frequency of the first clock signal is determined based on the reference quantity.

[0212] In operation S1630, the first clock signal is subjected to anomaly detection based on the reference quantity and the first clock frequency.

[0213] In some embodiments, the above-mentioned determination of the reference quantity corresponding to the first clock signal may include the following operations.

[0214] For example, determine the first reference time period when the number of pulses of the second clock signal reaches the first count value.

[0215] For example, determine the second reference time period, where the second reference time period is the time period between the time stamps of two data packets.

[0216] In some embodiments, determining a reference quantity corresponding to a first clock signal may include: determining a first reference time period, and / or determining a second reference time period, where the first reference time period is a time period during which the number of pulses of a second clock signal reaches a first count value, and the second reference time period is a time period between the timestamps of two respective data packets.

[0217] Specifically, in response to a first enable signal, the pulses of the second clock signal are counted until a preset first count value is reached, and a count completion signal is output. Meanwhile, in response to the first enable signal, the pulses of the first clock signal are counted until the count completion signal is received, obtaining a second count value. This second count value can be used to characterize the first clock frequency.

[0218] Accordingly, determining the first clock frequency of the first clock signal based on the reference quantity may include the following operations: For example, determining a second count value of the number of pulses of the first clock signal within the first reference time period. For example, determining a second count value of the number of pulses of the first clock signal within the second reference time period.

[0219] Among them, determining the second count value of the number of pulses of the first clock signal within the second reference time period may include the following operations. First, in response to obtaining a first timestamp, a first time count value corresponding to the first timestamp is obtained. Then, in response to obtaining a second timestamp, a second time count value corresponding to the second timestamp is obtained. Next, the difference between the second time count value and the first time count value is used as the second count value.

[0220] In some embodiments, the above-mentioned abnormal detection of the first clock signal based on the first clock frequency and the reference time period may include: If the difference between the first count value and the second count value is within a difference threshold range, it is determined that the first clock signal is normal. The difference threshold range includes a first difference threshold and a second difference threshold, and the second difference threshold is greater than the first difference threshold. Specifically, the count difference can be compared with a first preset difference threshold, and / or the count difference can be compared with a second preset difference threshold to perform abnormal detection on the first clock signal, where the count difference is the difference between the first count value and the second count value, and the first preset difference threshold and the second preset difference threshold are different.

[0221] In some embodiments, the above method may further include the following operation: When the abnormal detection result for the first clock signal is abnormal, the second clock signal is used as the clock signal of the functional circuit.

[0222] In some embodiments, the above-mentioned determination of the second count value of the pulses of the first clock signal within the second time period may include the following operations: parsing the data packets from the first network to obtain timestamps, where the data packets transmitted by the first network have timestamps, so as to sort the received multiple data packets based on the chronological order of the timestamps.

[0223] In some embodiments, the above method may further include at least one of the following operations: outputting an interrupt signal when the first clock signal is abnormal, or outputting a reset signal when the first clock signal is abnormal.

[0224] Another aspect of the present application further provides a device for detecting clock anomalies.

[0225] Figure 17 It is a schematic structural diagram of a device for detecting clock anomalies shown in an embodiment of the present application.

[0226] See Figure 17 , the device 1700 for detecting clock anomalies may include a first clock frequency determination module 1710, a reference quantity determination module 1720, and an anomaly detection module 1730.

[0227] The first clock frequency determination module 1710 is configured to determine the first clock frequency of the received first clock signal.

[0228] The reference quantity determination module 1720 is configured to determine a reference quantity corresponding to the first clock signal; wherein, the reference quantity is determined based on the second clock signal and / or timestamps.

[0229] The anomaly detection module 1730 is configured to perform anomaly detection on the first clock signal based on the first clock frequency and the reference quantity.

[0230] Regarding the device in the above embodiments, the specific manners in which each module performs operations have been described in detail in the embodiments related to the method, and will not be elaborated here.

[0231] Another aspect of the present application further provides a radar. The radar may include the chip or board as described above.

[0232] Figure 18 It is a schematic structural diagram of a radar shown in an embodiment of the present application.

[0233] See Figure 18, the radar 1800 may include the chips or boards as shown above, and the chips and / or boards may include the clock circuit as described above. Specifically, the clock circuit may include the circuit for detecting clock anomalies as shown above. The clock circuit may be provided on the board 1810, and multiple chips such as a central control chip may be provided on the board 1810. The board 1810 may be provided in the housing 1820.

[0234] The radar may be a lidar, millimeter wave radar, ultrasonic radar, etc. The radar may be a scanning radar or a non-scanning radar.

[0235] The following takes a scanning lidar as an example for illustration.

[0236] For example, the MEMS lidar can dynamically adjust its scanning mode to focus on special objects, collect detailed information of farther and smaller objects and identify them. The inertial torque of the MEMS lidar is not large and it can move quickly, fast enough to track a 2D scanning mode in less than one second.

[0237] For example, the Flash lidar can quickly record the entire scene, avoiding various troubles caused by the movement of the target or the lidar during the scanning process. The radar system will use a micro sensor array to collect the laser beams reflected from different directions.

[0238] For example, a row of transmitters carried by the phased array lidar can change the emission direction of the laser beam by adjusting the relative phase of the signals.

[0239] For example, the mechanical rotary lidar is a lidar with an earlier development. At present, the technology is relatively mature, but the mechanical rotary lidar system structure is very complex, and the prices of its core components are also quite expensive, which mainly include lasers, scanners, optical components, photodetectors, receiving ICs, and position and navigation devices, etc.

[0240] Taking the MEMS solid-state lidar as an example, since the MEMS solid-state lidar scans through the simple harmonic vibration of the galvanometer mirror, its scanning path can be, for example, a scanning field of view where the slow axis moves from top to bottom and the fast axis reciprocates from left to right in terms of spatial order. Therefore, the detection range of the MEMS solid-state lidar is usually divided by the field of view angle corresponding to the slow axis. For example, the vertical field of view angle corresponding to the slow axis of the MEMS solid-state lidar is from 13° to 13°.

[0241] Taking the mechanical lidar in a scanning sensor as an example, since the mechanical lidar realizes scanning by driving an optical system to rotate 360 degrees through a mechanical driving device, it has a cylindrical detection area centered on the lidar. Therefore, the detection range corresponding to the 360° rotation of the mechanical lidar is the detection range corresponding to detecting one frame of data. So, the division of the detection range of the mechanical lidar in one cycle is generally based on the division of the rotation degrees.

[0242] For non-scanning lidars, they process the image through the internal photosensitive component circuit and control component and convert it into a digital signal that can be recognized by a computer. Then, it is input into the computer through a parallel port or USB connection and the image is restored by software.

[0243] On the other hand, the present application also provides an electronic device, which includes the above-mentioned artificial intelligence chip. The electronic device includes a data processing device, a robot, a radar, a computer, a printer, a scanner, a tablet computer, a smart terminal, a mobile phone, a driving recorder, a navigator, a sensor, a camera, a server, a cloud server, a camera, a video camera, a projector, a watch, headphones, a mobile storage device, a wearable device, a vehicle, household appliances, and / or medical devices. The vehicle includes an airplane, a ship, and / or a vehicle. The household appliances include a television, an air conditioner, a microwave oven, a refrigerator, a rice cooker, a humidifier, a washing machine, a light, a gas stove, and an oil fume extractor. The medical devices include a nuclear magnetic resonance instrument, a B-ultrasound instrument, and / or an electrocardiogram instrument.

[0244] Figure 19 It is a schematic structural diagram of the electronic device shown in the embodiments of the present application.

[0245] See Figure 19 , the electronic device 1900 may include a memory 1910 and a processor 1920. In addition, at least one of a clock generation circuit, a circuit for detecting clock anomalies, or a radar may also be provided on the electronic device 1900.

[0246] The processor 1920 may be a central processing unit (CPU), or may also be other general-purpose processors, digital signal processors (DSPs), application specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor or the processor may also be any conventional processor, etc.

[0247] The memory 1910 may include various types of storage units, such as system memory, read-only memory (ROM), and permanent storage devices. Among them, the ROM may store static data or instructions required by the processor 1920 or other modules of the computer. The permanent storage device may be a readable and writable storage device. The permanent storage device may be a non-volatile storage device that does not lose the stored instructions and data even when the computer is powered off. In some embodiments, the permanent storage device employs a mass storage device (such as a magnetic or optical disk, flash memory) as the permanent storage device. In some other embodiments, the permanent storage device may be a removable storage device (such as a floppy disk, optical drive). The system memory may be a readable and writable storage device or a volatile readable and writable storage device, such as dynamic random access memory. The system memory may store some or all of the instructions and data required by the processor during operation. In addition, the memory 1910 may include any combination of computer-readable storage media, including various types of semiconductor storage chips (such as DRAM, SRAM, SDRAM, flash memory, programmable read-only memory), and magnetic disks and / or optical disks may also be used. In some embodiments, the memory 1910 may include a removable storage device that is readable and / or writable, such as a compact disc (CD), read-only digital versatile disc (such as DVD-ROM, dual-layer DVD-ROM), read-only Blu-ray disc, super density disc, flash memory card (such as SD card, min SD card, Micro-SD card, etc.), magnetic floppy disk, etc. Computer-readable storage media do not include carrier waves and instantaneous electronic signals transmitted wirelessly or by wire.

[0248] Executable code is stored on the memory 1910, and when the executable code is processed by the processor 1920, it may cause the processor 1920 to execute some or all of the methods described above.

[0249] In addition, the method according to the present application may also be implemented as a computer program or a computer program product, which includes computer program code instructions for executing some or all of the steps of the above method according to the present application.

[0250] Alternatively, the present application may also be implemented as a computer-readable storage medium (or a non-transitory machine-readable storage medium or a machine-readable storage medium), on which executable code (or a computer program or computer instruction code) is stored. When the executable code (or the computer program or computer instruction code) is executed by a processor of an electronic device (or a server, etc.), it causes the processor to execute some or all of the steps of the above method according to the present application.

[0251] The embodiments of the present application have been described above. The above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and variations are obvious to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The choice of terms used herein is intended to best explain the principles of the embodiments, practical applications, or improvements to technologies in the market, or to enable other ordinary skilled persons in the art to understand the embodiments disclosed herein.

Claims

1. A circuit for detecting clock anomalies, characterized in that, Comprising: A first clock frequency determination unit configured to determine a first clock frequency of a received first clock signal; A reference quantity determination unit configured to determine a reference quantity corresponding to the first clock signal, the reference quantity being determined based on a second clock signal and / or a time stamp; A clock anomaly detection unit connected to the first clock frequency determination unit and the reference quantity determination unit respectively, and configured to perform anomaly detection on the first clock signal based on the first clock frequency and the reference quantity; The reference quantity determination unit includes: a first reference time period determination circuit configured to determine a first reference time period, the first reference time period being a time period during which the number of pulses of the second clock signal reaches a first count value; The first clock frequency determination unit includes a first counter connected to the clock anomaly detection unit, and is configured to perform pulse counting on the first clock signal during the first reference time period to obtain a second count value, and transmit the second count value to the clock anomaly detection unit; The first reference time period determination circuit includes: A second counter connected to the clock anomaly detection unit, and configured to perform pulse counting on the second clock signal in response to a first enable signal until reaching a preset first count value, and transmit the first count value to the clock anomaly detection unit, and output a count completion signal; A count control unit connected to the first counter and the second counter respectively, and specifically configured to output the first enable signal to the first counter and the second counter; and in response to the count completion signal, output a termination counting instruction to the first counter, and send a second enable signal to the clock anomaly detection unit.

2. The circuit according to claim 1, wherein The reference quantity determination unit includes a second reference time period determination circuit configured to determine a second reference time period, wherein the second reference time period is a time period between time stamps of two data packets.

3. The circuit according to claim 1, characterized in that: The count control unit includes a delay control circuit; and / or The clock anomaly detection unit includes a first count value comparator configured to compare a count difference with a first preset difference threshold, and / or compare the count difference with a second preset difference threshold to perform anomaly detection on the first clock signal, wherein the count difference is a difference between the first count value and the second count value, and the first preset difference threshold and the second preset difference threshold are different.

4. The circuit according to claim 3, characterized in that, Further comprising: A first reference time period configuration unit connected to the first count value comparator, and configured to store the first preset difference threshold and / or the second preset difference threshold, and transmit the first preset difference threshold and / or the second preset difference threshold to the first count value comparator.

5. The circuit according to claim 1, wherein The first reference time period determination circuit further includes: a second clock generation unit connected to the second counter, and configured to output the second clock signal to the second counter.

6. The circuit according to claim 2, wherein The second reference time period determination circuit includes: A time unpacking unit, connected to the first network, is configured to parse the data packet from the first network to obtain the time stamp, and the data packet transmitted by the first network has the time stamp.

7. The circuit according to claim 6, wherein The clock anomaly detection unit includes a second count value comparator, and the second count value comparator includes a buffer unit. The buffer unit is configured to store a second count value in response to the second count value comparator receiving the time stamp, and the second count value is from the first counter.

8. The circuit according to claim 6, wherein Further included: A second reference time period configuration unit, connected to the clock anomaly detection unit, is configured to store a mapping relationship between the difference between time stamps and a preset difference threshold, so that the clock anomaly detection unit can find the preset difference threshold corresponding to the difference between the time stamps.

9. A clock circuit, characterized in that, Including: A first clock generation unit, configured to output a first clock signal; The circuit for detecting clock anomaly according to any one of claims 1 to 8, connected to the first clock generation unit, is configured to detect the first clock signal.

10. The clock circuit according to claim 9, wherein Further included: A multiplexer, connected to the clock anomaly detection unit, is configured to output the first clock signal when the clock of the first clock signal is normal, or output a second clock signal when the clock of the first clock signal is abnormal.

11. A chip, characterized in that, Including: The circuit for detecting clock anomaly according to any one of claims 1 to 8, or the clock circuit according to claim 9 or 10; A functional circuit, configured to implement a specific function based on the first clock signal or the second clock signal.

12. A radar, including the circuit for detecting clock anomaly according to any one of claims 1 to 8, or the clock circuit according to claim 9 or 10, or the chip according to claim 11.

13. A method for detecting clock anomalies, characterized in that, Including: Determine a reference quantity corresponding to the first clock signal; Determine a first clock frequency of the first clock signal based on the reference quantity; Perform anomaly detection on the first clock signal based on the reference quantity and the first clock frequency; Wherein, the reference quantity is determined based on a second clock signal and / or a time stamp; Perform clock anomaly detection by the circuit for detecting clock anomaly according to any one of claims 1 to 8.

14. The method according to claim 13, characterized in that, The reference quantity includes a reference time period; The determining the reference quantity corresponding to the first clock signal includes: Determine a first reference time period, and / or determine a second reference time period. The first reference time period is the time period when the number of pulses of the second clock signal reaches a first count value, and the second reference time period is the time period between the time stamps of two data packets; The determining the first clock frequency of the first clock signal based on the reference quantity includes: Determine a second count value of the number of pulses of the first clock signal within the first reference time period; and / or Determine a second count value of the number of pulses of the first clock signal within the second reference time period.

15. The method according to claim 14, characterized in that, The determining the second count value of the number of pulses of the first clock signal within the second reference time period includes: In response to obtaining a first time stamp, obtain a first time count value corresponding to the first time stamp; In response to obtaining the second timestamp, obtain a second time count value corresponding to the second timestamp; Use the difference between the second time count value and the first time count value as the second count value.

16. The method according to claim 14 or 15, characterized in that, The anomaly detection of the first clock signal based on the reference quantity and the first clock frequency includes: If the difference between the first count value and the second count value is within the difference threshold range, determine that the first clock signal is normal. The difference threshold range includes a first difference threshold and a second difference threshold, and the second difference threshold is greater than the first difference threshold.

17. An electronic device, characterized in that, Includes: A processor; And A memory storing executable code that, when executed by the processor, causes the processor to execute the method according to any one of claims 13 to 16.

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