A circuit and method for reducing integer boundary spurs in a phase-locked loop

Abstract

The present invention discloses a circuit and control method for reducing integer boundary spurs in a phase-locked loop (PLL). When the PLL setting value N1 approaches the integer N2, the CPU forcibly changes the setting value N1 to the integer N2, and the FPGA sends the parameter value to the PLL. Since N2 is an integer, the PLL will not generate integer spurs. The frequency N2 generated by the PLL has a frequency error of |N2-N1|. The analog-to-digital converter data collected by the FPGA has a frequency of N2 and an error of |N2-N1|. The data collected by the FPGA is down-converted, and the frequency conversion parameter is changed from N1 to |N1+(N2-N1)|=N2. The data after down-conversion remains zero intermediate frequency data, and subsequent data processing is performed. The present invention is used to reduce integer spurs in the PLL, can solve the PLL integer spurs, and can achieve better circuit performance without incurring additional hardware costs.

Description

Technical Field

[0001] The present invention relates to the field of circuit electronic technology, and in particular to a circuit for reducing integer boundary spurs in a phase-locked loop. Background Art

[0002] PLL is actually a phase-locked loop, or PLL for short. For many electronic devices to work properly, they usually need to synchronize the external input signal with the internal oscillation signal, and this can be achieved using a PLL.

[0003] Integer boundary spurs (IBS) are spurs that occur at frequency offsets that are integer multiples of the reference frequency. For example, if the PLL reference frequency is 100 MHz, then spurs at frequency offsets of 200 MHz, 300 MHz, 400 MHz, and so on are all IBS. IBS are highest near integer multiples of the output frequency. The IBS power then decreases as the carrier moves away from an integer boundary until the carrier approaches the next integer boundary. If the target output frequency is an integer multiple of the reference frequency, the spurs are very low. Summary of the Invention

[0004] The object of the present invention is to provide a circuit for reducing integer boundary spurs in a phase-locked loop.

[0005] The technical solution adopted in the present invention is:

[0006] A circuit for reducing integer boundary spurs in a phase-locked loop (PLL), comprising a CPU, an FPGA, a phase-locked loop (PLL), a voltage-controlled oscillator (VCO), and an analog-to-digital converter (ADC); the CPU determines whether boundary compensation is required based on a frequency set by a user, calculates a compensation value for the boundary error, and transmits the result to the FPGA; the phase-locked loop (PLL) and the VCO are used to generate corresponding compensation signals; the analog-to-digital converter (ADC) is used to convert an intermediate frequency analog signal into an intermediate frequency digital signal; the FPGA is used to reduce integer boundary spurs and down-convert the intermediate frequency signal into a zero-frequency signal; the output end of the phase-locked loop is electrically connected to the input end of the voltage-controlled oscillator, the output end of the voltage-controlled oscillator is electrically connected to the input end of the analog-to-digital converter, the output end of the analog-to-digital converter is electrically connected to the input end of the FPGA, the input end of the FPGA is electrically connected to the output end of the CPU, and the output end of the FPGA is electrically connected to the phase-locked loop control end; when a phase-locked loop setting value N1 approaches an integer frequency division N2, the CPU forcibly changes the setting value N1 to the integer frequency division N2;

[0007] Furthermore, the output end of the CPU is also connected to a display screen.

[0008] A control method for a circuit for reducing integer boundary spurs in a phase-locked loop comprises the following steps:

[0009] Step 1, obtain the phase-locked loop setting value N1 and the integer frequency division N2;

[0010] Step 2: Determine whether the difference between the phase-locked loop setting value N1 and the integer frequency division N2 is less than a set threshold; if so, the CPU forcibly changes the setting value N1 to the integer frequency division N2 and executes step 3; otherwise, terminate data processing;

[0011] Step 3: The FPGA sends the parameter value to the phase-locked loop, so that the phase-locked loop uses N2 as the parameter and obtains the resulting frequency error as |N2-N1|.

[0012] Step 4: Down-convert the data collected by FPGA to obtain zero intermediate frequency data. The frequency conversion parameter changes from N1 to |N1+(N2-N1)|=N2;

[0013] Step 5: The zero-IF data undergoes subsequent data processing.

[0014] Furthermore, a threshold is set to determine whether the phase-locked loop setting value N1 is close to the integer frequency division N2.

[0015] Furthermore, the zero intermediate frequency data is subjected to detection processing to obtain detection data, and the detection data is sent to a display screen for display.

[0016] The present invention employs the above technical solution. When the phase-locked loop (PLL) setting value N1 approaches the integer N2, the PLL will generate integer boundary spurs due to N1's proximity to the integer frequency division N2. The CPU forcibly changes the setting value N1 to the integer N2, and the FPGA sends the parameter value to the PLL. Since N2 is an integer, the PLL will not generate integer spurs. When the setting value changes from N1 to N2, the frequency N2 generated by the PLL will have a frequency error of |N2-N1|. The analog-to-digital converter data collected by the FPGA has a frequency of N2, and the error is |N2-N1|. The data collected by the FPGA is down-converted, and the conversion parameter is changed from N1 to |N1+(N2-N1)|=N2. After down-conversion, the data remains zero intermediate frequency data, allowing for subsequent data processing. The present invention is used to reduce integer spurs in the PLL, solving the problem without incurring additional hardware costs, thereby achieving better circuit performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments;

[0018] Figure 1 The present invention is a schematic structural diagram of a circuit for reducing integer boundary spurs in a phase-locked loop. DETAILED DESCRIPTION

[0019] In order to make the purpose, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application.

[0020] like Figure 1 As shown, the present invention discloses a circuit for reducing integer boundary spurs of a phase-locked loop, which includes a CPU, an FPGA, a phase-locked loop (PLL), a voltage-controlled oscillator (VCO), and an analog-to-digital converter (ADC); the CPU determines whether boundary compensation is required based on a frequency set by a user and calculates a compensation value for the boundary error and sends it to the FPGA; the phase-locked loop (PLL) and the VCO are used to generate corresponding compensation signals; the analog-to-digital converter (ADC) is used to convert an intermediate frequency analog signal into an intermediate frequency digital signal; the FPGA is used to implement integer boundary spurs and down-convert the intermediate frequency signal into a zero-frequency signal; the output end of the phase-locked loop is electrically connected to the input end of the voltage-controlled oscillator, the output end of the voltage-controlled oscillator is electrically connected to the input end of the analog-to-digital converter, the output end of the analog-to-digital converter is electrically connected to the input end of the FPGA, the input end of the FPGA is electrically connected to the output end of the CPU, and the output end of the FPGA is electrically connected to the phase-locked loop control end; when the phase-locked loop setting value N1 is close to the integer frequency division N2, the CPU forcibly changes the setting value N1 to the integer frequency division N2;

[0021] Furthermore, the output end of the CPU is also connected to a display screen.

[0022] A control method for a circuit for reducing integer boundary spurs in a phase-locked loop comprises the following steps:

[0023] Step 1, obtain the phase-locked loop setting value N1 and the integer frequency division N2;

[0024] Step 2: Determine whether the difference between the phase-locked loop setting value N1 and the integer frequency division N2 is less than a set threshold; if so, the CPU forcibly changes the setting value N1 to the integer frequency division N2 and executes step 3; otherwise, terminate data processing;

[0025] Step 3: The FPGA sends the parameter value to the phase-locked loop, so that the phase-locked loop uses N2 as the parameter and obtains the resulting frequency error as |N2-N1|.

[0026] Step 4: Down-convert the data collected by FPGA to obtain zero intermediate frequency data. The frequency conversion parameter changes from N1 to |N1+(N2-N1)|=N2;

[0027] Step 5: The zero-IF data undergoes subsequent data processing.

[0028] Furthermore, a threshold is set to determine whether the phase-locked loop setting value N1 is close to the integer frequency division N2.

[0029] Furthermore, the zero intermediate frequency data is subjected to detection processing to obtain detection data, and the detection data is sent to a display screen for display.

[0030] The present invention employs the above technical solution. When the phase-locked loop (PLL) setting value N1 approaches the integer N2, the PLL will generate integer boundary spurs due to N1's proximity to the integer frequency division N2. The CPU forcibly changes the setting value N1 to the integer N2, and the FPGA sends the parameter value to the PLL. Since N2 is an integer, the PLL will not generate integer spurs. When the setting value changes from N1 to N2, the frequency N2 generated by the PLL will have a frequency error of |N2-N1|. The analog-to-digital converter data collected by the FPGA has a frequency of N2, and the error is |N2-N1|. The data collected by the FPGA is down-converted, and the conversion parameter is changed from N1 to |N1+(N2-N1)|=N2. After down-conversion, the data remains zero intermediate frequency data, allowing for subsequent data processing. The present invention is used to reduce integer spurs in the PLL, solving the problem without incurring additional hardware costs, thereby achieving better circuit performance.

[0031] Obviously, the described embodiments are part of the embodiments of the present application, rather than all of the embodiments. In the absence of conflict, the embodiments in the present application and the features in the embodiments can be combined with each other. The components of the embodiments of the present application generally described and shown in the drawings here can be arranged and designed in various different configurations. Therefore, the detailed description of the embodiments of the present application is not intended to limit the scope of the application for protection, but merely represents the selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

Claims

1. A circuit for reducing integer boundary spurs in a phase-locked loop, characterized in that: It includes a CPU, FPGA, phase-locked loop (PLL), voltage-controlled oscillator (VCO), and analog-to-digital converter (ADC). The CPU determines whether boundary compensation is required based on the frequency set by the user and calculates the compensation value of the boundary error and sends it to the FPGA. The phase-locked loop (PLL) and VCO are used to generate the corresponding compensation signal. The analog-to-digital converter (ADC) is used to convert the intermediate frequency analog signal into an intermediate frequency digital signal. The FPGA is used to implement integer boundary spurious and down-convert the intermediate frequency signal to a zero-frequency signal. The output end of the phase-locked loop is electrically connected to the input end of the voltage-controlled oscillator, the output end of the voltage-controlled oscillator is electrically connected to the input end of the analog-to-digital converter, the output end of the analog-to-digital converter is electrically connected to the input end of the FPGA, the input end of the FPGA is electrically connected to the output end of the CPU, and the output end of the FPGA is electrically connected to the phase-locked loop control end; when the phase-locked loop setting value N1 is close to the integer division frequency N2, the CPU forcibly changes the setting value N1 to the integer division frequency N2.

2. The circuit for reducing integer boundary spurs in a phase-locked loop according to claim 1, wherein: The output end of the CPU is also connected to a display screen.

3. A control method for a circuit for reducing integer boundary spurs in a phase-locked loop, comprising: It includes the following steps: Step 1, obtain the phase-locked loop setting value N1 and the integer frequency division N2; Step 2: Determine whether the difference between the phase-locked loop setting value N1 and the integer frequency division N2 is less than a set threshold; if so, the CPU forcibly changes the setting value N1 to the integer frequency division N2 and executes step 3; otherwise, terminate data processing; Step 3: The FPGA sends the parameter value to the phase-locked loop, so that the phase-locked loop uses N2 as the parameter and obtains the resulting frequency error as |N2-N1|. Step 4: Down-convert the data collected by FPGA to obtain zero intermediate frequency data. The frequency conversion parameter changes from N1 to |N1+(N2-N1)|=N2; Step 5: The zero-IF data undergoes subsequent data processing.

4. The control method for reducing integer boundary spurs in a phase-locked loop according to claim 3, wherein: A threshold is set to determine whether the phase-locked loop setting value N1 is close to the integer frequency division N2.

5. The control method for a circuit for reducing integer boundary spurs in a phase-locked loop according to claim 3, wherein: The zero intermediate frequency data is processed by demodulation to obtain detection data, which is then sent to the display screen for display.

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