Frame decoding circuit and method for performing frame decoding

Abstract

The present invention provides a frame decoding circuit and a method for performing frame decoding. A frame synchronizer receives an input clock signal and an input frame signal in a serial format to provide an output clock signal. When the detected code is sampled at the center point of every two bits of the input frame signal and is not of the correct type, the phase shift of the output clock signal is adjusted according to the detected code. The input clock signal is divided by the phase shift to provide an output clock signal. A deserializer unit receives an input frame signal, input data, an output clock signal from a frame synchronizer, and a delay locked loop clock signal to deserialize and convert the input frame signal and input data and then output them.

Description

Technical Field

[0001] The present invention relates to an interface between two integrated circuit (IC) chips for data communication, and more particularly, to a frame decoding circuit and a method for performing frame decoding. Background Art

[0002] Digital electronic devices based on semiconductor integrated circuits, such as mobile phones, digital cameras, personal digital assistants (PDAs), etc., are designed to have more powerful functions to adapt to various applications in the modern digital world. However, with the trend of semiconductor manufacturing, digital electronic devices are intended to be smaller and lighter, with improved functionality and higher performance. Semiconductor devices can be packaged into 2.5D semiconductor devices, in which several circuit chips can be integrated into a larger integrated circuit, in which contact components, inserts or redistribution layers (RDL) are used for connections between chips.

[0003] The present invention proposes an integrated fan-out (InFO) and chip-on-wafer-on-substrate (CoWoS) packaging technology to package multiple chips assembled side by side.

[0004] Regarding the entire electronic circuit, the main circuit can be manufactured based on 2.5D packaging technology. In addition, multiple application-specific integrated circuit (ASIC) chips and serializer / deserializer (SerDes) chips can be additionally placed on the main circuit and connected to each other through a connection interface involving a parallel bus.

[0005] The interfaces of the two chips to be connected usually include contact component patterns for connecting to each other. The contact component pattern of the chip includes multiple contact components for connecting to the contact components of the other chip. As a result, in data communication, a parallel bus is effectively established between the two IC chips, in which the contact components of the transmission components of one chip are connected to the contact components of the receiving components of the other IC chip.

[0006] However, each contact component between two IC chips in communication can speed up data transmission through serial data signals. In this case, the serialized data received by the IC chip at the receiving side is to be deserialized and converted into parallel data. How to ensure that the received data in the serial format is properly deserialized with appropriate clock timing is still a problem in development. Summary of the invention

[0007] The present invention provides a frame decoding circuit and a method for performing frame decoding. An input frame signal with coding is verified in an interface of an IC chip at a receiving side. The input frame signal allows a clock signal to have an appropriate timing, which can be used to effectively and correctly deserialize the input data in this serial format.

[0008] In one embodiment, the present invention provides a frame decoding circuit implemented in an integrated circuit (IC) chip. The IC chip converts the received input data in a serial format into output data in a deserialized format. The frame decoding circuit includes a frame synchronizer, which receives an input clock signal and an input frame signal in a serial format to provide an output clock signal. The input frame signal is sampled at the falling edge of the input clock signal to adjust the phase shift of the output clock signal according to the detected code. The input clock signal has also been divided by the phase shift to provide the output clock signal. In addition, the deserializer unit receives the input frame signal, the input data, the output clock signal from the frame synchronizer, and the delay-locked-loop (DLL) clock signal to deserialize the input frame signal and the input data to output the frame code and the deserialized data.

[0009] In one embodiment, the present invention also provides a method for performing frame decoding used in an integrated circuit chip, wherein the IC chip converts the received input data in a serial format into output data in a deserialized format. The method for performing frame decoding includes providing a frame synchronizer, which is used to receive an input clock signal and an input frame signal in a serial format to provide an output clock signal. The input frame signal is sampled at the falling edge or the rising edge of the input clock signal, and the phase shift of the output clock signal is adjusted according to the detected code. The input clock signal is phase shifted and divided to provide an output clock signal. The method also includes providing a deserializer unit, which is used to receive an input frame signal, input data, an output clock signal from a frame synchronizer, and a delay locked loop (DLL) clock signal to deserialize the input frame signal and input data to output a frame code and deserialized data.

[0010] In order to make the foregoing content more easily understood, several embodiments accompanied by drawings are described in detail below. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The accompanying drawings are included to provide a further understanding of the present disclosure, and are incorporated in and constitute a part of this specification. The accompanying drawings illustrate exemplary embodiments of the present disclosure and together with the embodiments serve to explain the principles of the present disclosure.

[0012] Figure 1is a schematic diagram schematically showing a cross-sectional stack structure of a 2.5D semiconductor device with an interface according to an embodiment of the present invention;

[0013] Figure 2 is a schematic diagram schematically illustrating an interface for connecting a chip to a plurality of other chips through an interface according to an embodiment of the present invention;

[0014] Figure 3 is a schematic diagram schematically illustrating an interface for connection between a plurality of processor chips according to an embodiment of the present invention;

[0015] Figure 4 is a schematic diagram schematically illustrating communication between two chips based on an interface having an interposer or a redistribution layer according to an embodiment of the present invention;

[0016] Figure 5 is a schematic diagram schematically showing the structure of a contact component pattern according to an embodiment of the present invention;

[0017] Figure 6 is a schematic diagram schematically illustrating a mechanism for defining data based on a clock for a frame signal according to an embodiment of the present invention;

[0018] Figure 7 is a schematic diagram schematically showing a circuit structure of a frame decoding circuit according to an embodiment of the present invention;

[0019] Figure 8 is a schematic diagram schematically showing a circuit structure of a frame synchronizer according to an embodiment of the present invention;

[0020] Fig. 9 is a diagram schematically showing a mechanism for phase shifting of an output clock.

[0021] Description of Figure Numbers

[0022] 50: Platform

[0023] 100: Substrate

[0024] 102: Through hole

[0025] 104: Bottom solder ball

[0026] 106: Top contact assembly

[0027] 110: Insert or redistribution layer

[0028] 112: Silicon via

[0029] 114: Interconnection wiring

[0030] 116: Contact components

[0031] 120: SerDes chip

[0032] 130: ASIC chip

[0033] 200: IC chip

[0034] 200': Processor

[0035] 202: Chip

[0036] 204: Interface

[0037] 300: Contact component pattern

[0038] 310. DCK: clock signal

[0039] 312: Frame signal

[0040] 314: Data signal

[0041] 350: Delay Locked Loop (DLL) Unit

[0042] 450: Sampling Circuit

[0043] 452: Trigger

[0044] 454: Judgment Logic

[0045] 456: Reset Circuit

[0046] 458: Clock Divider

[0047] 500: frame decoding circuit

[0048] 502: Alignment and effective detection circuit

[0049] 504: Deserializer

[0050] 506: Frame synchronizer and clock divider

[0051] 508: External Circuit

[0052] ALNERR: Alignment error output signal

[0053] C[0], C[1], C[2], C[3], C[4], C[5], C[6], C[7]: Clock period

[0054] CLKP: Output clock signal

[0055] CLKS: DLL clock

[0056] D[0], D[1], D[2], D[3], D[4], D[5], D[6], D[7]: bit data

[0057] F[0], F[1], F[2], F[3], F[4], F[5], F[6], F[7]: bit

[0058] RSTN: reset signal DETAILED DESCRIPTION

[0059] The present invention relates to an interface between two integrated circuit (IC) chips for data communication, wherein a frame decoding circuit and a method for performing frame decoding are further provided to correctly deserialize input data based on at least an encoded frame signal.

[0060] For semiconductor manufacturing, an interface of a 2.5D semiconductor device can be used, in which the chip is placed on an interposer or a redistribution layer. The contact component pattern of the chip is configured to have a geometrically symmetrical relationship. The chip is connected more freely through the interface. The wiring length between the contact components in the wiring can also be set more equally and shorter.

[0061] In communication through an interface, parallel data at the transmitting chip is usually serialized into a bit string in a serial format. Various signals containing the bit string are transmitted to another chip as a receiving chip through the interface. The interface provides a parallel bus for transmitting signals in a serial format. Subsequently, the receiving chip needs to correctly deserialize the input data signal to correctly obtain the transmitted communication data.

[0062] Several embodiments are provided below to describe the present invention, but the present invention is not limited to the embodiments.

[0063] The entire integrated circuit can be manufactured into a semiconductor device through a semiconductor manufacturing process, and the semiconductor device can be manufactured based on a stacked structure of a 2.5D semiconductor device. The interface of the chip for receiving data may include a frame decoding circuit associated with a deserialization circuit. In one embodiment, the interface in the semiconductor structure is integrated into the circuit of the entire chip.

[0064] First, semiconductor manufacturing will be described. Figure 1 FIG. 1 is a schematic diagram schematically showing a cross-sectional stack structure of a 2.5D semiconductor device having an interface according to an embodiment of the present invention. Figure 1In another application, a CoWoS or InFO platform 50 having a desired IC structure is formed based on 2.5D packaging technology. The CoWoS or InFO platform 50 may include a package substrate 100 having a bottom solder ball 104 and a top contactor component 106. A through hole 102 may be used to connect from the bottom solder ball 104 to the top contactor component 106. In addition, an interposer or a redistribution layer 110 may be further formed on the substrate 100, which is connected to the contact component 106. The interposer or the redistribution layer 110 may also include a through-silicon via (TSV) 112, an interconnect wiring 114, and a contact component 116.

[0065] In practical applications, additional chips (e.g., ASIC chip 130 and SerDes chip 120) may also be used to implement the CoWoS or InFO platform 50. The ASIC chip 130 and the SerDes chip 120 are connected via wiring 114 and contact components 116. One ASIC chip 130 may be connected to multiple SerDes chips 120 for various peripheral communications.

[0066] Figure 2 is a schematic diagram schematically illustrating an interface for connecting a chip to a plurality of other chips through an interface according to an embodiment of the present invention. Figure 2 , an IC chip 200 (e.g., a processor or an ASIC chip) can be connected to multiple chips 202 through an interface 204 to communicate between the chip 200 and the chip 202 using a parallel bus. The interface 204 may include wiring and contact components in a contact component pattern so that the chip 200 can be connected to the chip 202.

[0067] Figure 3 FIG. 1 is a schematic diagram schematically illustrating an interface for connection between a plurality of processor chips according to an embodiment of the present invention. Figure 3 In another application, multiple processors 200 ′ can be connected together to form a large processor with more powerful functions. In this case, these processors 200 ′ are also connected via the interface 204 .

[0068] As described above, the 2.5D packaging process can be applied to stack various chips side by side without substantially further consuming device area. However, in order to allow the chips to be connected more freely, the contact components in the interface 204 need to be properly arranged in a compact manner and further symmetrical for receiving and transmitting signals. The communication between the two chips 200 to the chip 202 can be easily arranged in the peripheral area. Here, the interface 204 can also refer to the Glink interface provided on the market.

[0069] Figure 4FIG. 1 is a schematic diagram schematically illustrating communication between two chips based on an interface having an interposer or a rewiring layer according to an embodiment of the present invention. Figure 4 In one example, the ASIC chip 130 and the SerDes chip 120 communicate through the interposer or the redistribution layer 110. The contact components of the ASIC chip 130 and the SerDes chip 120 for contacting the interposer or the redistribution layer 110 are appropriately arranged. Each contact component can transmit a specific signal at the same time. Therefore, a parallel bus is established based on the contact components. The signal at each contact component is in a serial format, such as a bit string.

[0070] Figure 5 FIG. 1 is a schematic diagram schematically showing the structure of a contact component pattern according to an embodiment of the present invention. Figure 5 , the total number of contact components involved in the interface can be one number, and signals are communicated in parallel for transmission and reception.

[0071] The total number of contact components involved in the interface can be a larger number. Signals communicate in parallel between chips for transmission and reception. Depending on the data size in a bus, a 32-bit data size with operating voltage and other functional signals is set as a tile, also referred to as a contact component pattern 300. The contact component pattern 300 can be replicated in a certain number (e.g., 8) to accommodate the total data size in parallel communication. In one example, the data corresponds to 32 bits with a sequence of R_D0 to R_D31 and T_D0 to T_D31, in which T represents a contact component for transmission and R represents a contact component for reception. In addition, the contact component pattern 300 also includes a plurality of low voltage signals VSS and a plurality of high voltages VDDP. In addition, various functional signals are also included, including FRAM T / R_FR, clock T / R_DCK_P / N, flow control T / R_FC[1:0], DBI T / R_DBI[3:0], parity T / R_PAR, and lane repair T / R_LR[1:0]. However, the contact components for the functional signals are not limited to the embodiments described above.

[0072] Table 1 is an example of defining the contact components of a transmission (T) group or a reception (R) group. The transmission group and the reception group have the same number of contact components.

[0073] Table 1

[0074]

[0075] Based on the above-described interposer or redistribution layer 110, various signals are communicated between the two chips. However, in one example, a set of parallel signals in communication can be converted into a serial format to be transmitted / received through a wiring having a contact component. Once the data signal in the serial format is received by the IC chip, the IC chip deserializes the data signal and converts it into a parallel format.

[0076] In one embodiment, in order to ensure that the data signal in the serial format is correctly deserialized, a frame signal is provided to define the N-bit data in each group. In one example, N is 8, but the present invention is not limited to 8. The parameter N is determined according to the actual data transmission algorithm. Here, 8 bits of data form a byte. The following examples use 8-bit signals as examples for description.

[0077] Figure 6 FIG. 1 is a schematic diagram schematically illustrating a mechanism for defining data based on a clock for a frame signal according to an embodiment of the present invention. Figure 6 In one embodiment, the clock signal 310, the frame signal 312, and the data signal 314 are transmitted separately and in parallel from the three contact components of the IC chip at the transmission side. Then, the IC chip at the receiving side receives the signals separately and in parallel. As indicated, the clock signal 310, the frame signal 312, and the data signal 314 are in serial format and need to be deserialized and converted into parallel data.

[0078] The clock signal 310 is continuously received by the IC chip at the receiving side to serve as a time reference for sampling various signals. For example, the clock signal 310 includes clock periods C[0], C[1], C[2], C[3], C[4], C[5], C[6], and C[7] corresponding to the data signal 314. The data signal 314 is also continuously received by the IC chip. However, the data signal is a packet of N bits of data transmitted each time, such as an 8-bit data packet. Here, N is not limited to 8. However, in an example, the following description uses 8 bits of data as the packet to be transmitted.

[0079] N-bit data, for example, 8-bit data is D[0], D[1], D[2], D[3], D[4], D[5], D[6] and D[7], each of which corresponds to one bit. In order to identify this 8-bit data, a frame signal 312 is also transmitted and then received. The size of the frame signal 312 is also N bits, for example 8 bits, so that the 8-bit data can be framed.

[0080] The frame signal 312 is generated with 8 bits so that the waveform extends over four clock cycles in a double data rate (DDR) format. In other words, the size of the frame signal 312 will define the N-bit data in a serial format.

[0081] In one example, the waveform of the frame signal 312 has a rule to be established. The rule requires that the frame signal 312 has only a "1" state at the leading portion and a "0" state at the ending portion. In addition, for the leading portion, at least two continuous positions have a "1" state, and for the ending portion, at least two continuous positions have a "0" state. In one example, the first four positions F[0] to F[3] are "1111", and the last four positions F[4] to F[7] are "0000". In one embodiment, the frame signal 312 may require that every two adjacent positions have the same state of "1" or "0". This also means that the first two positions can be "11" of the correct type and are not expected to be "00", "01" and "10".

[0082] The frame signal 312 is used to adjust the clock phase of the output clock signal, wherein the frame signal 312 also correctly defines the N-bit data. The data signal 314 represents various signals in a serial format, wherein the content of the data signal 314 needs to be deserialized and converted into a parallel format.

[0083] Figure 7 FIG. 1 is a schematic diagram schematically showing a circuit structure of a frame decoding circuit according to an embodiment of the present invention. Figure 7 , the frame decoding circuit 500 is implemented in the interface of the IC chip to receive the clock signal 310, the frame signal 312, and the data signal 314. In one embodiment, the frame decoding circuit 500 includes the DLL unit 350, the frame synchronizer and clock divider 506, the deserializer 504, and the alignment and validity detection circuit 502. The output of the frame decoding circuit 500 is provided to the external circuit 508 (e.g., Physical Medium Attachment Digital (PMAD) / Physical Coding Sublayer (PCS)) for further application.

[0084] The input clock signal 310 serves as a clock reference for various operations. In one embodiment, the DLL unit 350 receives the clock signal 310 to adjust to a delay locked loop (DLL) clock CLKS, which is further input to the alignment and valid detection circuit 502 and the deserializer 504. In addition, the frame synchronizer and clock divider 506 also receives the clock signal 310 to adjust the clock phase used in the IC chip.

[0085] like Figure 6 As stated in , the frame signal 312 is used to define N-bit data transmitted in a serial format, and the timing of the frame signal 312 needs to be synchronized with the output clock signal CLKP actually used in the operation. The frame synchronizer and clock divider 506 are described as follows.

[0086] Figure 8FIG. 1 is a schematic diagram schematically showing a circuit structure of a frame synchronizer according to an embodiment of the present invention. Figure 7 and Figure 8 , usually, the frame synchronizer and clock divider 506 receives the clock signal 310 and the frame signal 312 in serial format to provide the output clock signal CLKP. Through the sampling circuit 450 for sampling the input frame signal at the falling edge of the input clock signal 310, the frame synchronizer and clock divider 506 can adjust the phase shift of the clock signal 310 according to the code detected by the sampling circuit 450. However, the sampling circuit 450 can also use the rising edge instead of the falling edge without specific restrictions. When the detected code is not of the correct type, the frame synchronizer and clock divider 506 can perform the phase shift of the clock signal 310, wherein the relevant judgment is detailed in the relevant description of the judgment logic 454 described later. The clock signal 310 is also divided by the clock divider 458 with phase shift for outputting the output clock signal CLKP. In actual operation, the clock divider 458 is reset by the reset signal RSTN. The reset circuit 456 generates the reset signal RSTN according to the phase shift determined by the judgment logic 454.

[0087] The sampling circuit 450 is a flip-flop circuit including a plurality of flip-flops (FF) 452. In one example, the frame signal 312 is 8-bit data, and then eight flip-flops 452 are used to sample the frame signal 312 at the falling edge of the clock signal 310. However, the AND gate (logic AND) receives the clock signal DCK and an enable signal, so that the clock signal DCK and the frame signal 312 can be actually captured.

[0088] like Figure 6 As stated in , 8-bit data involves four clock cycles, wherein four falling edges are used to sample the frame signal 312 into four-bit data, which is also deserialized and converted into 4-bit data for use by the judgment logic 454. The judgment logic 454 judges whether the 4-bit data is of the correct type. If the 4-bit data is not of the correct type, the clock signal DCK is phase-shifted.

[0089] For 4-bit data, the correct type has two types of "1xx0" or "0000" as the code detected by the sampling circuit 450, where the bit indicated by "X" is an omitted bit. This means that the value of this bit is ignored without judgment. Here, the frame signal 312 carries 8 bits. However, the frame signal 312 is N-bit data, not limited to 8-bit data.

[0090] Types other than "1xx0" or "0000" are not correct types, and this means that the waveform of the frame signal 312 does not conform to the definition. As noted, the type of "1xx0" means that at least two leading bits are in the "1" state, and the last two bits are in the "0" state, indicating that the waveform of the frame signal 312 is correct. The type of "0000" means that no data is transmitted. If the first bit of the 4-bit data in the judgment logic 454 is "0", then this means that the frame signal 312 does not start from "1".

[0091] The output clock signal CLKP is output to the deserializer 504 and is used as a clock signal for actual operation in the deserializer 504. In addition, the output clock signal CLKP is also controlled and enabled by another AND gate (logic AND). The output clock signal CLKP requires a proper phase to be able to sample the input data signal 314 at a proper time.

[0092] Fig. 9 is a diagram schematically showing a mechanism for phase shifting of an output clock. Fig. 9 The phase shift of the output clock signal CLKP is as follows. When the code detected by the judgment logic 454 is not of the correct type, the phase of the output clock signal CLKP will shift in the next clock cycle. The phase shift can be performed until it is detected that the frame signal 312 has the correct type.

[0093] Return to reference Figure 7 , further describing the deserializer 504. The deserializer 504 deserializes the frame signal 312 and the data signal 314 in a serial format based on the output clock signal CLKP with phase adjustment. In addition, the deserializer 504 also receives the DLL clock CLKS to actually deserialize the serial signal. The circuit of the deserializer 504 can be a circuit known in the art without specific limitations. The description is omitted here. The deserializer 504 will output the frame signal 312 or the data signal 314 in a parallel format to the external circuit 508.

[0094] The alignment and validity detection circuit 502 further detects the frame signal to determine whether a clock error or a frame error occurs. A set of conditions for determining whether to discard input data includes:

[0095] (1) The leading bit of the input frame signal is not "1";

[0096] (2) The input frame signal is zero; and

[0097] (3) A "1" bit is additionally detected within the input frame signal, but a "0" bit is also detected before the "1" bit, although the leading bit of the input frame signal is "1".

[0098] If the frame signal 312 does not fall into the above conditions (1), (2) and (3), the input data is judged as correct data and used for subsequent use. Otherwise, the data is discarded due to an error, and an error count can be performed at this time. In one example, when condition (1) occurs, an alignment error in the input frame signal is determined, wherein the count of the alignment error is increased by one. In addition, when condition (3) occurs, a frame error in the input frame signal is determined, wherein the count of the frame error is increased by one.

[0099] Condition (1) means that the frame signal cannot obtain the "frame rising edge" at the expected position, and obtains "1" within 8 bits after the expected position, where the expected position is the leading bit. Condition (1) means that the leading bit of the frame signal is not "1" and this bit "1" is shifted to another bit position. In this way, the alignment and validity detection circuit 502 will generate an alignment error output signal ALNERR under condition (1). Condition (2) means that the frame signal cannot obtain the "frame rising edge" at the expected position, and obtains all "0" within 8 bits after the expected position. This means that there is no data being transmitted at present. Any data received under this condition is not actual data and should be discarded. Condition (3) means that the frame signal obtains the "frame rising edge" at the expected position, but obtains an unexpected frame code, and the unexpected frame code does not satisfy the conditions previously described in Figure 6 The rules for setting the frame signal described in . Condition (2) means that there is no data transmitted and the frame signal is invalid. When the alignment and validity detection circuit 502 meets condition (3), it will generate an output signal VALID, and the output signal VALID is used to indicate whether the frame signal is an illegal frame signal.

[0100] In terms of a method for performing frame decoding, in one example, the present invention also provides a method for performing frame decoding used in an integrated circuit (IC) chip, wherein the IC chip converts received input data in a serial format into output data in a deserialized format. The method for performing frame decoding includes providing a frame synchronizer, which is used to receive an input clock signal and an input frame signal in a serial format to provide an output clock signal. The phase shift of the output clock signal is adjusted according to the detected code by sampling the input frame signal at the falling edge of the input clock signal, and when the detected code is not of the correct type, the phase shift of the input clock signal is performed. The input clock signal has also been divided by the phase shift to provide an output clock signal. The method also includes providing a deserializer unit, which is used to receive an input frame signal, input data, an output clock signal from a frame synchronizer, and a delay locked loop (DLL) clock signal to deserialize the input frame signal and the input data to output a frame code and deserialized data. An alignment-validity detection circuit is provided, which is used to receive an input frame signal, a DLL clock, and an output clock signal from a frame synchronizer to output a valid signal for determining whether the input frame signal is valid and an alignment signal for determining whether the input frame signal is aligned.

[0101] It will be apparent to those skilled in the art that various modifications and variations may be made to the disclosed embodiments without departing from the scope or spirit of the present disclosure. In view of the foregoing, it is intended that the present disclosure encompass modifications and variations as long as they fall within the scope of the appended claims and their equivalents.

Claims

1. A frame decoding circuit, arranged in an integrated circuit chip, wherein the integrated circuit chip converts received input data in a serial format into output data in a deserialized format, the frame decoding circuit comprising: A frame synchronizer receives an input clock signal and an input frame signal in serial format to provide an output clock signal, wherein the phase shift of the output clock signal is adjusted according to the detected code by sampling the input frame signal, wherein the input clock signal is also divided by the phase shift to provide the output clock signal; as well as A deserializer unit receives the input frame signal, the input data, the output clock signal from the frame synchronizer and a delay locked loop clock signal to deserialize the input frame signal and the input data to output a frame code and the deserialized data. 2 . The frame decoding circuit according to claim 1 , wherein the input frame signal defines the N-bit data of the input data to be deserialized and converted into the serial format of parallel N-bit data.

3. The frame decoding circuit according to claim 1, wherein the integrated circuit chip as the first chip receives the input clock signal and the input frame signal from an external transmission integrated circuit chip as the second chip through a parallel bus between the first chip and the second chip. 4 . The frame decoding circuit according to claim 1 , wherein the input frame signal is N-bit data in a serial format. 5 . The frame decoding circuit according to claim 4 , wherein the N-bit data of the input frame signal is 8-bit frame data.

6. The frame decoding circuit according to claim 4, wherein when the detected code has a leading bit of "1" and an ending bit of "0" or the detected code is zero, the phase of the detected code having N / 2 bits of the input frame signal is correct, otherwise the phase of the input frame signal is incorrect.

7. The frame decoding circuit according to claim 6, wherein the phase of the detected code is correct when the bit string is 1x...x0, wherein the bits indicated by "x...x" are omitted bits. 8 . The frame decoding circuit according to claim 7 , wherein the N-bit data is 8-bit data and the detected code is 1xx0.

9. The frame decoding circuit according to claim 7, wherein the detected code having the bit string of 1x...x0 corresponds to the following condition: at least two start bits of the input frame signal are consecutive with 1 and at least two end bits of the input frame signal are consecutive with 0.

10. A frame decoding circuit according to claim 6, wherein when it is determined that the phase of the detected code having N / 2 bits of the input frame signal is correct, the output clock signal from the frame synchronizer remains in phase without adjustment, but the clock frequency is reduced and the output clock signal is set.

11. The frame decoding circuit of claim 1, wherein the phase shift of the input clock signal is performed when the detected code is not of a correct type.

12. The frame decoding circuit according to claim 11, wherein the frame synchronizer comprises: A first flip-flop circuit, comprising a plurality of first flip-flop units, the first flip-flop circuit receiving the input frame signal and the input clock signal, and configured to sample the input frame signal at a falling edge of the input clock signal and deserialize and convert the sampled data into N / 2-bit data; A judging circuit, used for judging whether the sampled data is of the correct type, so as to determine whether to perform the phase shift of the input clock signal; A second trigger circuit, comprising a plurality of second trigger units, wherein the second trigger circuit is configured to receive the output of the judgment circuit to generate a clock reset signal; a clock divider, receiving the reset signal to generate a phase-adjusted clock signal; A first AND gate, receiving the input clock signal and an enable signal to enable the input clock to enter the first flip-flop circuit; as well as A second AND gate receives the enable signal and the phase-adjusted clock signal as feedback from the clock divider to enable deserialization of the input frame signal.

13. The frame decoding circuit according to claim 1, wherein the phase shift is to shift the phase of the output clock signal relative to a current clock cycle to a rising edge of a next clock cycle of the input clock signal.

14. The frame decoding circuit according to claim 1 further includes an alignment-validity detection circuit, which receives the input frame signal, the delay-locked loop clock, and the output clock signal from the frame synchronizer to output a valid signal for determining whether the input frame signal is valid and output an alignment signal for determining whether the input frame signal is aligned. 15 . The frame decoding circuit according to claim 14 , wherein the alignment-validity detection circuit acquires the input frame signal having N-bit data, and determines whether to adopt or discard the deserialized input data.

16. The frame decoding circuit according to claim 15, wherein a set of conditions for determining whether to discard the input data comprises: (1) The leading bit of the input frame signal is not "1"; (2) The input frame signal is zero; as well as (3) A "1" bit is additionally detected within the input frame signal, but a "0" bit is also detected before the "1" bit, although the leading bit of the input frame signal is "1".

17. The frame decoding circuit according to claim 16, wherein when the condition (1) occurs, an alignment error in the input frame signal is determined, wherein a count of the alignment errors is increased by one.

18. The frame decoding circuit according to claim 16, wherein when the condition (3) occurs, a frame error in the input frame signal is determined, wherein a count of frame errors is increased by one.

19. The frame decoding circuit according to claim 1, wherein every two adjacent bits in a sequence within the input frame signal having correct encoding have the same voltage level.

20. The frame decoding circuit according to claim 1, wherein a correct code of the input frame signal including only a "1" bit string and a "0" bit string is sequentially formed within the input frame signal.

21. A method for performing frame decoding, used in an integrated circuit chip, wherein the integrated circuit chip converts received input data in a serial format into output data in a deserialized format, the method for performing frame decoding comprising: providing a frame synchronizer for receiving an input clock signal and an input frame signal in a serial format to provide an output clock signal, wherein the phase shift of the output clock signal is adjusted according to the detected code by sampling the input frame signal at the falling edge or the rising edge of the input clock signal, wherein the input clock signal has also been divided by the phase shift to provide the output clock signal; as well as A deserializer unit is provided for receiving the input frame signal, the input data, the output clock signal from the frame synchronizer, and a delay locked loop clock signal to deserialize the input frame signal and the input data to output a frame code and the deserialized data.

22. The method of performing frame decoding according to claim 21, further comprising: An alignment-validity detection circuit is provided for receiving the input frame signal, the delay-locked loop clock and the output clock signal from the frame synchronizer to output a valid signal for determining whether the input frame signal is valid and an alignment signal for determining whether the input frame signal is aligned.

23. The method of performing frame decoding of claim 21, further comprising performing a phase shift of the input clock signal when the detected code is not of the correct type.

24. The method for performing frame decoding according to claim 23, wherein the frame synchronizer provided comprises: a first flip-flop circuit, comprising a plurality of first flip-flop units, the first flip-flop circuit receiving the input frame signal and the input clock signal, and configured to sample the input frame signal at a falling edge of the input clock signal and deserialize the sampled data into N / 2-bit data; A judging circuit, used for judging whether the sampled data is of the correct type, so as to determine whether to perform the phase shift of the input clock signal; A second trigger circuit, comprising a plurality of second trigger units, wherein the second trigger circuit is configured to receive the output of the judgment circuit to generate a clock reset signal; a clock divider, receiving the reset signal to generate a phase-adjusted clock signal; A first AND gate, receiving the input clock signal and an enable signal to enable the input clock to enter the first flip-flop circuit; as well as A second AND gate receives the enable signal and the phase-adjusted clock signal as feedback from the clock divider to enable deserialization of the input frame signal.

25. The method for performing frame decoding according to claim 22, wherein the provided alignment-valid detection circuit obtains the input frame signal having N-bit data, and determines whether to adopt or discard the deserialized input data.

26. The method for performing frame decoding according to claim 25, characterized in that: A set of conditions for determining to discard the input data includes: (1) The leading bit of the input frame signal is not "1"; (2) the input frame signal is zero; and (3) A "1" bit is additionally detected within the input frame signal, but a "0" bit is also detected before the "1" bit, although the leading bit of the input frame signal is "1".

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