Analog-digital hybrid memory device for secure storage and computation and operating method thereof

Abstract

A hybrid digital-analog memory device for secure storage and computation and an operating method thereof are disclosed. A nonvolatile memory device according to an embodiment includes a plurality of memory cells arranged in a matrix form; a plurality of word lines extending in a first direction, wherein each memory cell is connected with one of the plurality of word lines; a plurality of bit lines extending in a second direction different from the first direction, wherein each memory cell is connected with one of the plurality of bit lines; a word line control circuit connected with the word lines and configured to control the word lines; a first bit line control circuit configured to control the bit lines, wherein the first bit line control circuit is connected with a first end of each bit line; and a second bit line control circuit configured to control the bit lines, wherein the second bit line control circuit is connected with a second end of each bit line, the second end being opposite to the first end.

Description

[0001] This application is a divisional application of patent application No. 202080012609.4, filed on May 21, 2020, entitled "Mixed-Signal Storage Device and Circuit for Secure Storage and Computation".

[0002] Cross-references to related applications

[0003] This application claims priority to U.S. Application No. 16 / 876,616, filed May 18, 2020, entitled "Mixed-Signal Storage Device and Circuit for Secure Storage and Computation" and U.S. Provisional Application No. 62 / 851,936, filed May 23, 2019, entitled "Mixed-Signal Storage Device and Circuit for Secure Storage and Computation". U.S. Application No. 16 / 876,616 claims priority and benefit to U.S. Provisional Application No. 62 / 851,936. The contents of both applications are incorporated herein by reference in their entirety. Technical Field

[0004] This invention relates generally to storage devices and methods for achieving storage and computation purposes using storage devices, and more particularly to mixed-signal storage devices and methods for achieving storage and computation purposes using mixed-signal storage devices. Background Technology

[0005] Many electronic devices, such as mobile phones, computers, automobiles, and monitors, contain storage devices. These devices are used to store data for various purposes. Depending on whether the stored data is retained or erased after power is turned off, storage devices generally fall into two categories. For volatile storage devices, the data is erased whenever the power is turned off. However, for non-volatile storage devices, the stored data is retained even when the power is off.

[0006] Non-volatile storage devices typically comprise memory arrays containing tens of thousands of memory cells for storing data. Non-volatile storage devices are already used in neural networks for generating mathematical models for machine learning and artificial intelligence (AI) applications. Well-trained neural networks can contain weight data, which is a valuable data asset in terms of the time / resources required for training. Well-trained neural networks can also contain unique training datasets and models. Such datasets and models can be stored within one or more neural network chips containing non-volatile storage devices.

[0007] However, driven by self-interest, hackers may attempt to corrupt the data stored in neural network chips and try to replicate the neural network. Once deployed in the field, adversaries will go to great lengths to attack the neural network model and weight data and reverse engineer it. For example, hackers might generate training sets by simulating inputs / outputs or directly probe the weight data stored in the storage device. One particularly damaging scenario is that the weight data generated at great expense of resources and time can ultimately be easily probed and seized by hackers. Summary of the Invention

[0008] One aspect of the present invention relates to a non-volatile memory device. The non-volatile memory device includes a plurality of memory cells arranged in a matrix and a plurality of word lines extending along a row direction. Each memory cell is connected to one of the word lines. The non-volatile memory device also includes a plurality of bit lines extending along a column direction. Each memory cell is connected to one of the bit lines. The non-volatile memory device further includes: word line control circuitry connected to the word lines and for controlling the word lines; a first bit line control circuitry for controlling the bit lines and sensing the memory cells in digital mode; and a second bit line control circuitry for biasing the bit lines and sensing the memory cells in analog mode. The first bit line control circuitry is connected to a first end of each bit line. The second bit line control circuitry is connected to a second end of each bit line. The second end is opposite to the first end.

[0009] In some embodiments, the non-volatile memory device further includes multiple source lines extending along the row direction. Each source line is connected to one row of memory cells. In some embodiments, each source line may be connected to two rows of memory cells. In some embodiments, the non-volatile memory device may include multiple source lines extending along the column direction, such that each source line is connected to one column of memory cells.

[0010] In some implementations, a first portion of the memory cell is biased and sensed in digital mode, and a second portion of the memory cell is biased and sensed in analog mode.

[0011] In some embodiments, the non-volatile memory device further includes a memory device control circuit connected to the word line control circuit, the first bit line control circuit, and the second bit line control circuit. This memory device control circuit is used to read or write to a first portion and a second portion of the memory cells during different operating cycles.

[0012] In some embodiments, the non-volatile memory device further includes a memory device control circuit connected to the word line control circuit, the first bit line control circuit, and the second bit line control circuit. This memory device control circuit is used to read or write a first portion and a second portion of the memory cells within the same operating cycle.

[0013] In some embodiments, a pre-generated public key is stored in a first portion of the memory cell. The non-volatile memory device further includes memory device control circuitry configured to, upon receiving data to be stored in the non-volatile memory device,: read the pre-generated public key from the first portion of the memory cell; encrypt the data with the pre-generated public key; and store the encrypted data in one of the first portion of the memory cell and a second portion of the memory cell.

[0014] In some embodiments, the non-volatile memory device may include a memory device control circuit connected to the word line control circuit, the first bit line control circuit, and the second bit line control circuit. This memory device control circuit is used to store data having M bits. N bits, which are the most significant bits, are stored in a first portion of the memory cell, and (MN) bits, which are the least significant bits, are stored in a second portion of the memory cell.

[0015] In some embodiments, the storage device control circuitry is configured to enable the first bit line control circuitry to read the N bits as the most significant bits in digital mode, and to enable the second bit line control circuitry to read the (MN) bits as the least significant bits in analog mode.

[0016] In some implementations, each memory cell includes a resistance-changing element or a charge storage element.

[0017] In some embodiments, the storage device control circuitry is configured to perform neural network computation by: storing weights in corresponding memory cells in analog or digital mode; controlling the word line control circuitry to provide an input voltage to the word lines; and obtaining a current response from the first bit line control circuitry when the weight values ​​are stored in the corresponding memory cells in digital mode, or obtaining a current response from the second bit line control circuitry when the weight values ​​are stored in the corresponding memory cells in analog mode.

[0018] Another aspect of the present invention relates to a method for operating a mixed-signal memory device. The mixed-signal memory device includes a plurality of memory cells arranged in a matrix and a plurality of word lines extending along a row direction. Each memory cell is connected to one of the word lines. The non-volatile memory device also includes a plurality of bit lines extending along a column direction. Each memory cell is connected to one of the bit lines. The non-volatile memory device further includes: a word line control circuit connected to the word lines and for controlling the word lines; a first bit line control circuit connected to a first end of each bit line; and a second bit line control circuit connected to a second end of each bit line. The second end is opposite to the first end. The method includes: biasing and sensing a first portion of the memory cell using the first bit line control circuit in digital mode; and biasing and sensing a second portion of the memory cell using the second bit line control circuit in analog mode.

[0019] In some embodiments, the method further includes reading or writing a first portion and a second portion of the memory cells during different operating cycles. In some embodiments, the method further includes reading or writing a first portion and a second portion of the memory cells during the same operating cycle.

[0020] In some embodiments, the method further includes: storing a pre-generated public key in a first portion of the memory cell; receiving data to be stored in the non-volatile memory; reading the pre-generated public key from the first portion of the memory cell; encrypting the data with the pre-generated public key; and storing the encrypted data in one of the first portion of the memory cell and a second portion of the memory cell.

[0021] In some embodiments, the method further includes: receiving data having M bits; storing N bits of the M bits as the most significant bits into a first portion of the memory unit; and storing (MN) bits of the M bits as the least significant bits into a second portion of the memory unit.

[0022] In some embodiments, the method further includes: storing weight values ​​in corresponding memory cells in analog or digital modes; controlling the word line control circuit to provide an input voltage to the word line; and obtaining a current response from the first bit line control circuit when the weight values ​​are stored in the corresponding memory cells in digital mode, or obtaining a current response from the second bit line control circuit when the weight values ​​are stored in the corresponding memory cells in analog mode.

[0023] Another aspect of the present invention relates to a data storage method. The data is stored in a first mixed-signal memory array in analog mode to generate a first variation of the data. Subsequently, a first correction value is calculated to compensate for the first variation of the data, and the first correction value is stored in the first mixed-signal memory array in digital mode. Furthermore, the data is also stored in a second mixed-signal memory array in analog mode to generate a second variation of the data. Subsequently, a second correction value is calculated to compensate for the second variation of the data. This second correction value is different from the first correction value. This second correction value is stored in the second mixed-signal memory array in digital mode.

[0024] The above and other features of the various devices, systems, and methods of the present invention, as well as the functions of their operating methods and related structural elements, will become more readily understood when viewed in conjunction with the accompanying drawings, all of which form part of this specification. However, it should be clearly understood that the drawings are for illustrative and descriptive purposes only and are not intended to define the scope of the invention. It should be understood that both the foregoing summary and the following detailed description are illustrative and explanatory only and do not limit the scope of the claimed invention. Attached Figure Description

[0025] The non-limiting embodiments of the present invention can be more easily understood by referring to the following figures.

[0026] Figure 1 This is a schematic diagram of a non-volatile storage device according to an exemplary embodiment.

[0027] Figure 2 This is a schematic diagram of another non-volatile storage device according to an exemplary embodiment.

[0028] Figure 3 This is a schematic diagram of yet another non-volatile storage device according to an exemplary embodiment.

[0029] Figure 4 This is a schematic diagram of yet another non-volatile storage device according to an exemplary embodiment.

[0030] Figure 5 This is a schematic diagram of yet another non-volatile storage device according to an exemplary embodiment.

[0031] Figure 6 This is a schematic diagram of yet another non-volatile storage device according to an exemplary embodiment.

[0032] Figure 7 This is a flowchart illustrating a method for operating a non-volatile storage device according to an exemplary embodiment.

[0033] Figure 8 This is a flowchart of another non-volatile storage device operation method according to an exemplary embodiment.

[0034] Figure 9 This is a flowchart illustrating a method for operating a non-volatile storage device according to an exemplary embodiment.

[0035] Figure 10 This is a flowchart illustrating a method for using a mixed-signal non-volatile storage device to improve data storage security according to an exemplary embodiment.

[0036] Figure 11 This is a flowchart illustrating a method for using a mixed-signal non-volatile storage device for data storage according to an exemplary embodiment.

[0037] Figure 12 This is a flowchart illustrating a method for using a mixed-signal nonvolatile storage device for computational purposes according to an exemplary embodiment.

[0038] Figure 13 This is a schematic diagram of a non-volatile storage device for neural network computation according to an exemplary embodiment.

[0039] Figure 14 This is a schematic diagram of another non-volatile storage device used for neural network computation according to an exemplary embodiment.

[0040] Figure 15 This is a flowchart illustrating a method for achieving secure storage in a mixed-signal non-volatile storage device according to an exemplary embodiment.

[0041] Figures 16A to 16C This is a block diagram of a memory cell structure including a resistance-changing element according to various embodiments.

[0042] Figure 17A and Figure 17B This is a block diagram of a memory cell structure including a charge storage element according to various embodiments. Detailed Implementation

[0043] Hereinafter, non-limiting embodiments of the present invention are described with reference to the accompanying drawings. It should be understood that specific features and aspects of any embodiment of the present invention may be used and / or combined with specific features and aspects of any other embodiment of the present invention. It should also be understood that such embodiments are exemplary and only a small subset of embodiments within the scope of the present invention are illustrated. Various changes and modifications readily understood by those skilled in the art to which this invention pertains are considered to fall within the spirit, scope, and concept of the invention as further defined by the claims.

[0044] The present invention provides mixed-signal memory arrays and devices, as well as various applications of such arrays and devices. Furthermore, methods of operating the mixed-signal memory arrays and devices are also disclosed.

[0045] Hereinafter, various embodiments will be described with reference to the accompanying drawings. First, referring to... Figure 1 The figure is a schematic diagram of a non-volatile memory device 100 according to an exemplary embodiment. The non-volatile memory device 100 can be a resistive random access memory (RRAM) device. The non-volatile memory device 100 includes a plurality of memory cells 102 arranged in a matrix, a plurality of word lines 104 extending in the row direction, and a plurality of bit lines 106 extending in the column direction. The non-volatile memory device 100 also includes a word line control circuit 108 connected to the word lines 104 and used to control the word lines 104, a first bit line control circuit 110 for controlling the bit lines 106 and sensing the memory cells 102 in digital mode, and a second bit line control circuit 112 for biasing the bit lines 106 and sensing the memory cells 102 in analog mode. Each memory cell 102 is connected to one of the word lines 104 and one of the bit lines 106. The first bit line control circuit 110 is connected to a first terminal 106a of each bit line 106. The second bit line control circuit 112 is connected to the second end 106b of each bit line 106. The second end 106b of the bit line 106 is opposite to the first end 106a of the bit line 106.

[0046] The non-volatile memory device 100 also includes multiple source lines 120 extending along the row direction. Each source line 120 is connected to a row of memory cells 102. In some embodiments, each memory cell 102 may include a resistive element 102a and a transistor 102b. The gate of transistor 102b is connected to word line 104. The source of transistor 102b is connected to source line 120, and the drain of transistor 102b is connected to one end of resistive element 102a. The other end of resistive element 102a is connected to bit line 106. The resistive memory cell 102 receives read, reset, or set operations depending on the duration, magnitude, and polarity of a corresponding voltage pulse applied to the resistive memory cell 102 at the intersection of selected word line 104 and selected bit line 106. The resistive element 102a may be programmed to switch between two states to enable digital mode operation. The resistive element 102a can also be programmed to switch between more than two (e.g., three or four) states to achieve analog mode operation.

[0047] In some implementations, a first portion of the memory cell 102 is biased and sensed by a first bit line control circuit 110 in digital mode, and a second portion of the memory cell 102 is biased and sensed by a second bit line control circuit 112 in analog mode.

[0048] The non-volatile memory device 100 also includes a memory device control circuit 130 connected to a word line control circuit 108, a first bit line control circuit 110, and a second bit line control circuit 112. In some embodiments, the memory device control circuit 130 is configured to perform read or write operations on a first portion and a second portion of the memory cell 102 during different operating cycles. For example, during a first operating cycle, the memory device control circuit 130 enables the first bit line control circuit 110 to read or write the first portion of the memory cell 102 in digital mode, while the second portion of the memory cell is not subject to read or write operations. During a second cycle following the first operating cycle, the memory device control circuit 130 enables the second bit line control circuit 112 to read or write the second portion of the memory cell 102 in analog mode, while the first portion of the memory cell is not subject to read or write operations.

[0049] In some embodiments, the memory device control circuit 130 is configured to perform read or write operations on a first portion and a second portion of the memory cell 102 within the same operating cycle. For example, within one operating cycle, the memory device control circuit 130 first enables the first bit line control circuit 110 to read or write the first portion of the memory cell 102 in digital mode, and then enables the second bit line control circuit 112 to read or write the second portion of the memory cell 102 in analog mode; and vice versa.

[0050] In some embodiments, the first bit line control circuit 110 and the second bit line control circuit 112 can be independently controlled by the memory device control circuit 130. This allows for flexible operation control of the memory device 100. It should be understood that the number of memory cells 102, word lines 104, bit lines 106, and source lines 120 is not limited to... Figure 1 As shown in the diagram. Those skilled in the art can increase or decrease the number of such components according to application requirements.

[0051] Figure 2A schematic diagram of another non-volatile memory device 200 according to an exemplary embodiment is shown. The non-volatile memory device 200 may be RRAM. The non-volatile memory device 200 includes a plurality of memory cells 202 arranged in a matrix, a plurality of word lines 204 extending in the row direction, and a plurality of bit lines 206 extending in the column direction. The non-volatile memory device 200 also includes a word line control circuit 208 connected to the word lines 204 and for controlling the word lines 204, a first bit line control circuit 210 for controlling the bit lines 206 and sensing the memory cells 202 in digital mode, and a second bit line control circuit 212 for biasing the bit lines 206 and sensing the memory cells 202 in analog mode. Each memory cell 202 is connected to one word line 204 and one bit line 206 therein. The first bit line control circuit 210 is connected to a first terminal 206a of each bit line 206. The second bit line control circuit 212 is connected to a second terminal 206b of each bit line 206. The second end 206b of bit line 206 is opposite to the first end 206a of bit line 206.

[0052] The non-volatile memory device 200 also includes multiple source lines 220 extending along the column direction. Each source line 220 is connected to a column of memory cells 202. The non-volatile memory device 200 also includes a memory device control circuit 230 connected to and controlling the word line control circuit 208, the first bit line control circuit 210, and the second bit line control circuit 212. The structure and function of the non-volatile memory device 200 are similar to those of the other memory devices. Figure 1 The non-volatile storage device 100 is similar, except that the source line 220 is configured to extend along the column direction.

[0053] Figure 3 This is a schematic diagram of another non-volatile memory device 300 according to an exemplary embodiment. The non-volatile memory device 300 includes a plurality of memory cells 302 arranged in a matrix, a plurality of word lines 304 extending in a row direction, and a plurality of bit lines 306 extending in a column direction. The non-volatile memory device 300 also includes a word line control circuit 308 connected to and for controlling the word lines 304, a first bit line control circuit 310 for controlling the bit lines 306 and sensing the memory cells 302 in digital mode, and a second bit line control circuit 312 for biasing the bit lines 306 and sensing the memory cells 302 in analog mode. Each memory cell 302 is connected to one word line 304 and one bit line 306 therein. The first bit line control circuit 310 is connected to a first terminal 306a of each bit line 306. The second bit line control circuit 312 is connected to a second terminal 306b of each bit line 306. The second end 306b of bit line 306 is opposite to the first end 306a of bit line 306.

[0054] The non-volatile memory device 300 also includes multiple source lines 320 extending along the row direction. Each source line 320 is connected to a row of memory cells 302. The non-volatile memory device 300 also includes a memory device control circuit 330 connected to and controlling the word line control circuit 308, the first bit line control circuit 310, and the second bit line control circuit 312. The structure and function of the non-volatile memory device 300 are similar to those of the other memory devices. Figure 1 The non-volatile memory device 100 is similar, except that each memory cell 302 is composed of a charge storage element 302a. In some embodiments, the charge storage element 302a may include a transistor with a floating gate for storing charge. The charge storage element 302a may be controlled by word line 304, bit line 306, and source line 320 to change the charge stored therein. The charge storage element 302a may be programmed to switch between two charge states to achieve digital mode operation. The charge storage element 302a may also be programmed to switch between more than two (e.g., three or four) charge states to achieve analog mode operation.

[0055] Figure 4 This is a schematic diagram of another non-volatile memory device 400 according to an exemplary embodiment. The non-volatile memory device 400 includes a plurality of memory cells 402 arranged in a matrix, a plurality of word lines 404 extending in a row direction, and a plurality of bit lines 406 extending in a column direction. The non-volatile memory device 400 also includes a word line control circuit 408 connected to the word lines 404 and for controlling the word lines 404, a first bit line control circuit 410 for controlling the bit lines 406 and sensing the memory cells 402 in digital mode, and a second bit line control circuit 412 for biasing the bit lines 406 and sensing the memory cells 402 in analog mode. Each memory cell 402 is connected to one word line 404 and one bit line 406 therein. The first bit line control circuit 410 is connected to a first terminal 406a of each bit line 406. The second bit line control circuit 412 is connected to a second terminal 406b of each bit line 406. The second end 406b of bit line 406 is opposite to the first end 406a of bit line 406.

[0056] The non-volatile memory device 400 also includes multiple source lines 420 extending along the column direction. Each source line 420 is connected to a column of memory cells 402. The non-volatile memory device 400 also includes a memory device control circuit 430 connected to and controlling the word line control circuit 408, the first bit line control circuit 410, and the second bit line control circuit 412. The structure and function of the non-volatile memory device 400 are similar to those of the other memory devices. Figure 3 The non-volatile storage device 300 is similar, except that the source line 420 is configured to extend along the column direction.

[0057] Figure 5 This is a schematic diagram of a non-volatile memory device 500 according to an exemplary embodiment. The non-volatile memory device 500 may be RRAM. The non-volatile memory device 500 includes a plurality of memory cells 502 arranged in a matrix, a plurality of word lines 504 extending in the row direction, and a plurality of bit lines 506 extending in the column direction. The non-volatile memory device 500 also includes a word line control circuit 508 connected to the word lines 504 and for controlling the word lines 504, a first bit line control circuit 510 for controlling the bit lines 506 and sensing the memory cells 502 in digital mode, and a second bit line control circuit 512 for biasing the bit lines 506 and sensing the memory cells 502 in analog mode. Each memory cell 502 is connected to one word line 504 and one bit line 506 therein. The first bit line control circuit 510 is connected to a first terminal 506a of each bit line 506. The second bit line control circuit 512 is connected to a second terminal 506b of each bit line 506. The second end 506b of bit line 506 is opposite to the first end 506a of bit line 506. The non-volatile memory device 500 also includes multiple source lines 520 extending along the row direction. Each source line 520 is connected to two rows of memory cells 502. The non-volatile memory device 500 also includes a memory device control circuit 530 connected to and controlling the word line control circuit 508, the first bit line control circuit 510, and the second bit line control circuit 512. The structure and function of the non-volatile memory device 500 are similar to... Figure 1 The non-volatile storage device 100 is similar, except that each source line 520 is connected to two rows of memory cells 502.

[0058] Figure 6This is a schematic diagram of a non-volatile memory device 600 according to an exemplary embodiment. The non-volatile memory device 600 includes a plurality of memory cells 602 arranged in a matrix, a plurality of word lines 604 extending in a row direction, and a plurality of bit lines 606 extending in a column direction. The non-volatile memory device 600 also includes a word line control circuit 608 connected to and for controlling the word lines 604, a first bit line control circuit 610 for controlling the bit lines 606 and sensing the memory cells 602 in digital mode, and a second bit line control circuit 612 for biasing the bit lines 606 and sensing the memory cells 602 in analog mode. Each memory cell 602 is connected to one word line 604 and one bit line 606. The first bit line control circuit 610 is connected to a first terminal 606a of each bit line 606. The second bit line control circuit 612 is connected to a second terminal 606b of each bit line 606. The second end 606b of bit line 606 is opposite to the first end 606a of bit line 606. The non-volatile memory device 600 also includes multiple source lines 620 extending along the row direction. Each source line 620 is connected to two rows of memory cells 602. The non-volatile memory device 600 also includes a memory device control circuit 630 connected to and controlling the word line control circuit 608, the first bit line control circuit 610, and the second bit line control circuit 612. The structure and function of the non-volatile memory device 600 are similar to... Figure 3 The non-volatile storage device 300 is similar, except that each source line 620 is connected to two rows of memory cells 602.

[0059] The operation and application of non-volatile storage devices are further elaborated below. (References) Figure 7 The figure is a flowchart of a non-volatile storage device operation method 700 according to an exemplary embodiment. Method 700 can be executed by a storage device control circuit, such as storage device control circuit 130. Figure 1 ), 230 Figure 2 ), 330 Figure 3 ), 430 Figure 4 ), 530 Figure 5 ), 630 Figure 6Any of the following. The non-volatile memory device may be a mixed-signal memory device. In 702, the memory device control circuit begins executing the operation cycle of the non-volatile memory device. For example, the memory device control circuit may be instructed to begin executing a read, set, or write operation of the non-volatile memory device. Since the memory cells of the non-volatile memory device can operate in both digital mode (two switching states) and analog mode (more than two switching states), in 704, the memory device control circuit determines whether to perform the operation in digital mode (or analog mode). If the operation is to be performed in digital mode ("yes" in 704), then in 706, the memory device control circuit enables the bit line control circuit to have digital bias and sensing capabilities. In 708, the memory device control circuit performs memory array operations (read, set, reset, etc.) on the first portion of each memory cell in digital mode. For example, the memory device control circuit controls the word line control circuit and the digital mode bit line control circuit to apply signals to the first portion of each memory cell. In some embodiments, the memory device control circuit may acquire the output of this operation. In 710, the operation cycle ends. During this cycle, no analog mode operations were performed on any memory cells.

[0060] In the next operating cycle, method 700 returns to 702. If the operation is to be performed in analog mode ("No" in 704), then in 712, the memory device control circuit enables another bit line control circuit to have analog bias and sensing capabilities. In 714, the memory device control circuit performs memory array operations (read, set, reset, etc.) on the second portion of each memory cell in analog mode. For example, the memory device control circuit controls the word line control circuit and the analog mode bit line control circuit to apply signals to the second portion of each memory cell. In some embodiments, the memory device control circuit may also acquire the output of this operation. Subsequently, in 710, the operating cycle ends. During this cycle, no digital mode operation was performed on any memory cell. In this operating scheme, the memory device control circuit is used to read or write the first portion of the memory cell in digital mode and read or write the second portion of the memory cell in analog mode in different cycles.

[0061] Figure 8 This is a flowchart of a non-volatile memory device operation method 800 according to an exemplary embodiment. Method 800 may be executed, for example, by a memory device control circuit, such as memory device control circuit 130. Figure 1 ), 230 Figure 2 ), 330 Figure 3 ), 430 Figure 4 ), 530 Figure 5 ), 630 Figure 6Any of the following. The non-volatile memory device may be a mixed-signal memory device. In 802, the memory device control circuit begins executing a non-volatile memory device operation cycle. For example, the memory device control circuit may be instructed to begin executing a read, set, or write operation on the non-volatile memory device. In 804, the memory device control circuit enables the bit line control circuit to have digital bias and sensing capabilities. In 806, the memory device control circuit performs memory array operations (read, set, reset, etc.) on the first portion of each memory cell in digital mode. For example, the memory device control circuit controls the word line control circuit and the digital mode bit line control circuit to apply signals to the first portion of each memory cell during memory array operations. In some embodiments, the memory device control circuit may also acquire the output of the operation in 806.

[0062] In 808, the memory device control circuit enables another bit line control circuit to have analog bias and sensing functions. In 810, the memory device control circuit performs memory array operations (read, set, reset, etc.) on the second portion of each memory cell in analog mode. For example, the memory device control circuit controls the word line control circuit and the analog mode bit line control circuit to apply signals to the second portion of each memory cell. In some embodiments, the memory device control circuit may also acquire the output of the operation in 810. Subsequently, in 812, the operation cycle ends. In this operation scheme, the memory device control circuit is used to read or write the first portion of the memory cell in digital mode and read or write the second portion of the memory cell in analog mode within the same operation cycle. It should be understood that, although in Figure 8 In general, digital mode operation begins before analog mode operation, but in some implementations, analog mode operation may also be initiated before digital mode operation.

[0063] Figure 9 This is a flowchart illustrating a method 900 for operating a non-volatile memory device according to an exemplary embodiment. Method 900 may be executed, for example, by a memory device control circuit, such as memory device control circuit 130. Figure 1 ), 230 Figure 2 ), 330 Figure 3 ), 430 Figure 4 ), 530 Figure 5 ), 630 Figure 6 Any one of them. The non-volatile memory device is a mixed-signal memory device. In 902, the first part of the memory cell of the memory device is controlled by the first bit line circuit (such as...). Figure 1 The first bit line control circuit 110 in the memory device is programmed in digital mode. In 904, the second part of the memory cell of the memory device is programmed with the second bit line control circuit (such as...). Figure 1The second bit line control circuit 112 is programmed in analog mode. In 906, the first part and the second part of the memory cell receive array operations (such as read or write) in different operating cycles. As an additional or alternative, in 908, the first part and the second part of the memory cell receive array operations (such as read or write) in the same operating cycle.

[0064] Figure 10 This is a flowchart of a method 1000 for using a mixed-signal non-volatile storage device to improve data storage security according to an exemplary embodiment. Method 1000 may be executed, for example, by a storage device control circuit, such as storage device control circuit 130. Figure 1 ), 230 Figure 2 ), 330 Figure 3 ), 430 Figure 4 ), 530 Figure 5 ), 630 Figure 6 Any one of them. In 1002, the pre-generated public key is stored in the first part of the memory unit in digital mode. For example, to achieve data security, a pair of public and private keys is generated for the user. The public and private keys can be generated by a server or user equipment associated with the user. The pre-generated public key can be stored in any non-volatile storage device of the present invention. The pre-generated public key can be stored, in particular, in a memory unit programmed in digital mode. The user can store the private key in another secure location.

[0065] In step 1004, data to be stored in a non-volatile storage device is received. In step 1006, in response to an instruction to save the received data, the storage device control circuit reads / obtains a pre-generated public key from a first portion of the memory cell. In step 1008, the storage device control circuit encrypts the data using the pre-generated public key. In step 1010, the encrypted data is stored in the non-volatile storage device. In some embodiments, the encrypted data may be stored in the first portion of the memory cell in digital mode. In some embodiments, the encrypted data may be stored in the second portion of the memory cell in analog mode. This type of technology allows users to securely store data, for example, using a pre-generated key. Thus, even if the stored data is stolen, the data remains securely protected because only the owner / user possesses the private key capable of decrypting the encrypted data. This type of technology also provides a scheme for automatically encrypting data whenever it is stored in a non-volatile storage device containing a pre-generated key.

[0066] Figure 11This is a flowchart of a method 1100 for using a mixed-signal non-volatile memory device for data storage according to an exemplary embodiment. Method 1100 may be executed, for example, by a memory device control circuit, such as memory device control circuit 130. Figure 1 ), 230 Figure 2 ), 330 Figure 3 ), 430 Figure 4 ), 530 Figure 5 ), 630 Figure 6 In 1102, the memory device control circuit receives data containing M bits, where M ≥ 2. In 1104, N bits, which are the most significant bits among the M bits, are stored in digital mode in the first part of the memory cell of the non-volatile memory device. In 1106, (MN) bits, which are the least significant bits among the M bits, are stored in analog mode in the second part of the memory cell of the non-volatile memory device. In the illustrated embodiment, digital storage has better accuracy / reliability than analog storage, but requires a larger chip area. Therefore, mixed-signal non-volatile memory devices can be used to perform both digital and analog storage simultaneously to achieve high accuracy / reliability while saving chip area, thereby reducing storage costs.

[0067] For example, data requiring high accuracy / reliability can be stored in digital mode, while data requiring lower accuracy can be stored in analog mode. In some implementations, digital and / or analog storage can be used to store the weight values ​​of the neural network. Neural networks are inherently fault-tolerant, especially of the least significant bit (LSB). Taking advantage of this, in one implementation, the memory device control circuitry of a non-volatile memory device can store the most significant bit of the weight data in digital mode and the LSB of the weight data in analog mode. By storing the LSB of the weight data in analog mode, the chip size of the neural network integrated circuit chip can be reduced, saving costs. Although a small number of errors may occur when storing the LSB of the weight data, the neural network can still operate.

[0068] When using a neural network to obtain inference results based on an existing model, the following calculations can be used:

[0069] Y = WX,

[0070] X = [x1, x2, ..., xn] T ,

[0071] Y = [y1, y2, ..., ym] T ,

[0072] W=[w11,w12,…,w1n;….;wm1,…,wmn],

[0073] Where Y is the inference matrix, X is the input value, and W is the weight value of the neural network model. The hybrid analog-digital non-volatile storage device of this invention can be used to perform this inference calculation.

[0074] Figure 12 This is a flowchart of a method 1200 for using a mixed-signal nonvolatile memory device in a computing application according to an exemplary embodiment. Method 1200 may be executed, for example, by a memory device control circuit, such as memory device control circuit 130. Figure 1 ), 230 Figure 2 ), 330 Figure 3 ), 430 Figure 4 ), 530 Figure 5 ), 630 Figure 6 Any one of them. In 1202, the storage device control circuit stores the weight values ​​into the corresponding memory cells of the non-volatile storage device in either analog or digital mode. The weight values ​​of the neural network are first stored in the memory cells in digital and / or analog modes. Since the mixed-signal non-volatile storage device of the present invention can operate in both digital and / or analog modes, the weight values ​​can be stored in one mode or both modes simultaneously. In some embodiments, the weight values ​​of the neural network can be combined with the above. Figure 10 The described encryption method is securely stored in a memory unit. In some implementations, the weight value can be obtained by combining the above methods. Figure 11 The described mixed-signal storage mode is used.

[0075] In 1204, the memory device control circuit controls the word line control circuit to provide an input voltage to the word line. In the illustrated embodiment, the input value calculated by the neural network can be in the form of an input voltage applied to the word line of the non-volatile memory device. The input voltage can be presented in either digital or analog mode. For example, when simulating in digital mode, the input voltage includes two values ​​corresponding to 0 and 1, respectively. When simulating in analog mode, the input voltage can include more than two different values ​​corresponding to multiple input values ​​of the neural network.

[0076] In step 1206, when the weight value is stored in the corresponding memory cell in digital mode, the storage device control circuit obtains a current response from the first bit line control circuit. Alternatively, in step 1208, when the weight value is stored in the corresponding memory cell in analog mode, the storage device control circuit obtains a current response from the second bit line control circuit. In the illustrated embodiment, the neural network output can be obtained by reading the bit line output. In some embodiments, in step 1210, the calculation result is obtained based on the current response. For example, when calculating a patient's health data, the current response can be used to determine whether the patient suffers from a specific disease. This technique can be used to solve problems based on neural networks or machine learning schemes.

[0077] Figure 13 This is a schematic diagram of a non-volatile memory device 1300 for neural network computation according to an exemplary embodiment. The non-volatile memory device 1300 includes a plurality of memory cells 1302 arranged in a matrix, a plurality of word lines 1304 extending in a row direction, and a plurality of bit lines 1306 extending in a column direction. The non-volatile memory device 1300 also includes a word line control circuit 1308 connected to the word lines 1304 and for controlling the word lines 1304, a first bit line control circuit 1310 for controlling the bit lines 1306 and sensing the memory cells 1302 in digital mode, and a second bit line control circuit 1312 for biasing the bit lines 1306 and sensing the memory cells 1302 in analog mode. Each memory cell 1302 is connected to one word line 1304 and one bit line 1306 therein. The first bit line control circuit 1310 is connected to a first terminal 1306a of each bit line 1306. The second bit line control circuit 1312 is connected to the second end 1306b of each bit line 1306. The second end 1306b of the bit line 1306 is opposite to the first end 1306a of the bit line 1306.

[0078] The non-volatile memory device 1300 also includes multiple source lines 1320 extending along the row direction. Each source line 1320 is connected to a row of memory cells 1302. In some embodiments, each memory cell 1302 may include a resistive element 1302a and a transistor 1302b. Each memory cell 1302 is used to store the weight values ​​W(W) of the neural network in resistive form. ik W il W jk W jl (etc.). In some implementations, the weight value can be stored in the form of electric charge. The weight value W can be stored in memory cell 1302 in digital or analog mode. Word line 1304 is connected to the input voltage X. i , ..., X jThe input value is provided to the memory cell 1302 in the form of a current response. Furthermore, the input value can be provided to the memory cell 1302 in either digital or analog mode. The output Y includes a current response in the form of a current response. a and Y b The output Y can be read from bit line 1306. The output Y can be used to determine the result of the neural network.

[0079] Figure 14 This is a schematic diagram of another non-volatile memory device 1400 for neural network computation according to an exemplary embodiment. The non-volatile memory device 1400 includes a plurality of memory cells 1402 arranged in a matrix, a plurality of word lines 1404 extending in a row direction, and a plurality of bit lines 1406 extending in a column direction. The non-volatile memory device 1400 also includes a word line control circuit 1408 connected to the word lines 1404 and for controlling the word lines 1404, a first bit line control circuit 1410 for controlling the bit lines 1406 and sensing the memory cells 1402 in digital mode, and a second bit line control circuit 1412 for biasing the bit lines 1406 and sensing the memory cells 1402 in analog mode. Each memory cell 1402 is connected to one word line 1404 and one bit line 1406 therein. The first bit line control circuit 1410 is connected to a first terminal 1406a of each bit line 1406. The second bit line control circuit 1412 is connected to the second end 1406b of each bit line 1406. The second end 1406b of the bit line 1406 is opposite to the first end 1406a of the bit line 1406.

[0080] The non-volatile memory device 1400 also includes multiple source lines 1420 extending along the column direction. Each source line 1420 is connected to a column of memory cells 1402. In some embodiments, each memory cell 1402 may include a resistive element 1402a and a transistor 1402b. Each memory cell 1402 is used to store the weight values ​​W(W) of the neural network in resistive form. ik W il W jk W jl (etc.). In some implementations, the weight value can be stored in the form of electric charge. The weight value W can be stored in memory cell 1402 in digital or analog mode. Word line 1404 is connected to the input voltage X. i , ..., X j The input value is provided to the memory cell 1402 in the form of a current response. Furthermore, the input value can be provided to the memory cell 1402 in either digital or analog mode. a and Y b It can be read from bit line 1406 or source line 1420.

[0081] Figure 15This is a flowchart of a method 1500 for secure storage using a mixed-signal non-volatile memory device according to an exemplary embodiment. Method 1500 can be executed, for example, by a processor of a computing device such as a desktop computer, laptop computer, server system, mobile device, or handheld device. In 1502, the processor receives data to be stored. This data can be, for example, weight values ​​of a neural network. Other data may also be considered. In 1504, the processor stores the data in analog mode into a first mixed-signal memory array to form a first variation of the data. In some embodiments, this variation is formed because the performance of the memory cells in the first mixed-signal memory array varies. For example, inconsistencies in the manufacturing process of the first mixed-signal memory array can lead to variations in memory cell performance. Inconsistencies not only lead to variations in memory cell performance but also to variations in the performance of different memory arrays.

[0082] Because data may become distorted when stored in the first mixed-signal memory array, in step 1506, the processor calculates a first correction value to compensate for the changes in the first data form. In some embodiments, the operation in step 1506 may include retraining the neural network to determine the first correction value. Other correction methods, either known or future, are also considered. In some embodiments, the correction calculation may be performed on all bits or on the most significant bit selected from the data. In step 1508, the processor stores the first correction value in digital mode in the first mixed-signal memory array. While the first correction value can be used to correct weight values ​​that have become distorted during storage, it is safer to store the first correction value in another location within the first mixed-signal memory array. This complexity reduces the likelihood of a hacker obtaining the correct weight values ​​through reverse engineering. To retrieve the first correction value from the first mixed-signal memory array, the processor may generate a log / map for the neural network. During neural network computation, the first correction value is read first, and then used to correct the stored weight values ​​to obtain the correct weight values ​​for computation. In some implementations, to further enhance storage security, the first correction value may be encrypted before being stored in the first mixed-signal memory array.

[0083] In step 1510, the processor stores the data in analog mode into a second mixed-signal memory array to form a second variation of the data. Consistent with the description in step 1504, this variation is generally due to inconsistencies in the manufacturing process. In some embodiments, the second data variation differs from the first data variation in the first mixed-signal memory array. In step 1512, the processor calculates a second correction value to compensate for the second data variation. This second correction value may differ from the first correction value. In step 1514, the processor stores the second correction value in digital mode into the second mixed-signal memory array. To be able to retrieve the second correction value from the second mixed-signal memory array, the processor may generate a log / mapping for the neural network. During neural network computation, the second correction value is read first, and then used to correct the stored weight values ​​to obtain the correct weight values ​​for computation. In some embodiments, the second correction value may be encrypted before being stored in the second mixed-signal memory array.

[0084] The above operations create two seemingly different neural network memory arrays. This could make it difficult for hackers to obtain the correct neural network weights by reverse engineering the arrays, as the weights and correction values ​​stored in the two memory arrays differ. Furthermore, the correction values ​​can be stored in different locations within the memory arrays, further complicating the process and making it harder for hackers to obtain the correct weights. Additionally, the correction values ​​can be encrypted to increase the difficulty of obtaining the correct weights. Since these security measures can only be decrypted by the owner and authorized users, the neural network weights are securely protected.

[0085] In some implementations, in step 1516, the processor, which correctly knows the correction value, performs neural network computation using the same input value. In step 1518, the processor obtains the same computation result using weight values ​​obtained from two memory arrays.

[0086] As described in this invention, the memory cell may include a resistance variation element or a charge storage element that retains data after the memory cell is powered off. Figures 16A to 16C This is a block diagram of a memory cell structure including a resistance-changing element according to various embodiments. (Refer to...) Figure 16A The first memory cell structure 1610 includes a bottom electrode 1612, a top electrode 1614, and a resistance changing element 1616 disposed between the bottom electrode 1612 and the top electrode 1614. The resistance changing element 1616 can change the resistance between the top electrode 1614 and the bottom electrode 1612. The resistance changing mechanism can be based on the formation of oxygen vacancy filaments, conductive bridges, phase transitions, ferroelectric switching, or spin-transfer torque (STT) switching.

[0087] Figure 16BThe diagram shows a second memory cell structure 1620, including a bottom electrode 1622, a resistance changing element 1624 disposed on the bottom electrode 1622, a top columnar electrode 1626 disposed on the resistance changing element 1624, and a top electrode 1628 disposed on the top columnar electrode 1626. The top columnar electrode 1626 ensures good contact between the resistance changing element 1624 and the top electrode 1628, thereby reducing contact resistance.

[0088] Figure 16C The diagram shows a third memory cell structure 1630, including a bottom electrode 1631, a bottom columnar electrode 1632 disposed on the bottom electrode 1631, a resistance changing element 1633 disposed on the bottom columnar electrode 1632, a top columnar electrode 1634 disposed on the resistance changing element 1633, and a top electrode 1635 disposed on the top columnar electrode 1634. The top columnar electrode 1634 ensures good contact between the resistance changing element 1633 and the top electrode 1635, thereby reducing contact resistance. Similarly, the bottom columnar electrode 1632 ensures good contact between the resistance changing element 1633 and the bottom electrode 1631, thereby reducing contact resistance.

[0089] In some embodiments, the bottom electrode may include conductive materials such as TiN, TaN, W, or other suitable conductive materials. In some embodiments, the top electrode may include conductive materials such as TiN, TaN, Ru, and other suitable conductive materials. The resistance changing element may be a resistive layer containing a resistive material. For example, the resistance changing element may include Ta2O5, T... a O x One or more resistive metal oxides. In some embodiments, the resistance-changing element may include one or more films.

[0090] Charge storage elements can be used in mixed-signal non-volatile storage devices. These devices operate based on changes in the charge stored within the charge storage element. The charge storage element typically includes two or three terminals and a component capable of storing either positive or negative charge. The charge storage element can switch between two charge states (digital mode) or more than two different charge states (analog mode). Changes in charge state can be sensed as voltage or current at a specific terminal of the charge storage element.

[0091] Figure 17A and Figure 17B This is a block diagram of a memory cell structure including a charge storage element according to various embodiments. Figure 17A The diagram shows a memory cell structure 1710 including a transistor with three terminals 1711, 1712, 1713 and a floating gate 1714. The floating gate 1714 can be used to store charge. Figure 17BAnother memory cell structure 1720 is shown, including a transistor 1722 and a capacitor 1724. The capacitor 1724 is used to store charge in the memory cell structure 1720. In some embodiments, the digital portion of the mixed-signal memory array can be implemented using an SRAM device.

[0092] While examples and features of the principles of the invention have been described herein, modifications and alterations may be made without departing from the spirit and scope of the embodiments of the invention, and other implementations exist. Furthermore, the words “comprising,” “having,” “including,” “containing,” and other similar forms are intended to be equivalent in meaning and are open-ended terms, meaning that one or more items following any of these words are not intended to be an exhaustive list of these items, nor are they intended to be limited to only the listed one or more items. It must be noted that throughout this document and in the claims, unless the context clearly indicates otherwise, the unspecified number includes both singular and plural meanings.

[0093] The detailed description of the embodiments provided in this invention is sufficient to enable those skilled in the art to practice the disclosed technical solutions. In addition, other embodiments may be used, or other embodiments may be derived therefrom; therefore, structural and logical substitutions and changes may be made without departing from the scope of this disclosure. Therefore, this "Detailed Description" section should not be construed as limiting, and the scope of the various embodiments is defined only by the claims and all their equivalents.

Claims

1. A hybrid digital and analog nonvolatile memory device for digital storage and analog storage, comprising: comprising: a plurality of memory cells arranged in a matrix form; a plurality of word lines extending in a first direction, wherein each memory cell is connected with one of the plurality of word lines; a plurality of bit lines extending in a second direction different from the first direction, wherein each memory cell is connected with one of the plurality of bit lines; a word line control circuit connected with the word lines and configured to control the word lines; a first bit line control circuit configured to control the bit lines; and a second bit line control circuit configured to control the bit lines, wherein a first end of each bit line is connected with the first bit line control circuit and a second end of each bit line is connected with the second bit line control circuit, the second end being opposite to the first end, wherein a first portion of the plurality of memory cells is biased and sensed in a digital mode by the first bit line control circuit and a second portion of the plurality of memory cells is biased and sensed in an analog mode by the second bit line control circuit.

2. The nonvolatile memory device of claim 1, wherein, further comprising: a plurality of source lines extending in the first direction, wherein each source line is connected with a row of the memory cells.

3. The nonvolatile memory device of claim 1, wherein, further comprising: a plurality of source lines extending in the first direction, wherein each source line is connected with two rows of the memory cells.

4. The nonvolatile memory device of claim 1, wherein, further comprising: a plurality of source lines extending in the second direction, wherein each source line is connected with a column of the memory cells.

5. The nonvolatile memory device of claim 1, wherein, further comprising: a memory device control circuit connected with the word line control circuit, the first bit line control circuit and the second bit line control circuit, wherein the memory device control circuit is configured to read or write the first portion of the memory cells and the second portion of the memory cells in different operation periods.

6. The nonvolatile memory device of claim 1, wherein, further comprising: a memory device control circuit connected with the word line control circuit, the first bit line control circuit and the second bit line control circuit, wherein the memory device control circuit is configured to read or write the first portion of the memory cells and the second portion of the memory cells in a same operation period.

7. The non-volatile memory device of claim 1, wherein: the first portion of the memory cells stores a pre-generated public key; wherein the non-volatile memory device further comprises a memory device control circuit configured to, upon receiving data to be stored in the non-volatile memory device: read the pre-generated public key from the first portion of the memory cells; encrypt the data with the pre-generated public key; and store the encrypted data in one of the first portion of the memory cells and the second portion of the memory cells.

8. The nonvolatile memory device of claim 1, wherein, further comprising: a memory device control circuit connected to the word line control circuit, the first bit line control circuit, and the second bit line control circuit, wherein the memory device control circuit is configured to store data having M bits, wherein N bits of the M bits as most significant bits are stored in the first portion of the memory cells, and (M-N) bits of the M bits as least significant bits are stored in the second portion of the memory cells.

9. The non-volatile memory device of claim 8, wherein: the memory device control circuit is configured to enable the first bit line control circuit to read the N bits as the most significant bits in the digital mode, and to enable the second bit line control circuit to read the (M-N) bits as the least significant bits in the analog mode.

10. The non-volatile memory device of claim 1, wherein: each memory cell includes a resistance variable element or a charge storage element.

11. The nonvolatile memory device of claim 1, wherein, Further comprising: a memory device control circuit connected to the word line control circuit, the first bit line control circuit, and the second bit line control circuit, wherein the memory device control circuit is configured to perform neural network computation by: storing weight values in respective memory cells in the analog mode or the digital mode; controlling the word line control circuit to provide an input voltage to the word line; and when the weight values are stored in respective memory cells in the digital mode, obtaining a current response from the first bit line control circuit; or when the weight values are stored in respective memory cells in the analog mode, obtaining a current response from the second bit line control circuit.

12. A method of operating an analog-digital hybrid memory device, characterized by, The hybrid digital-analog memory device comprises: a plurality of memory cells arranged in a matrix form; a plurality of word lines extending in a first direction, wherein each memory cell is connected to one of the plurality of word lines; a plurality of bit lines extending in a second direction different from the first direction, wherein each memory cell is connected to one of the plurality of bit lines; a word line control circuit connected to the word lines and configured to control the word lines; a first bit line control circuit configured to control the bit lines; and a second bit line control circuit configured to control the bit lines, wherein a first end of each bit line is connected to the first bit line control circuit, and a second end of each bit line is connected to the second bit line control circuit, the second end being opposite to the first end, The method comprises: programming a first portion of the plurality of memory cells with the first bit line control circuit in a digital mode; and programming a second portion of the plurality of memory cells with the second bit line control circuit in an analog mode.

13. The method of claim 12, wherein, Further comprising: reading or writing the first portion of the memory cells and the second portion of the memory cells in different operation cycles.

14. The method of claim 12, wherein: reading or writing to the first portion of the memory cells and the second portion of the memory cells in the same operation cycle.

15. The method of claim 12, wherein, Further comprising: storing a pre-generated public key in the first portion of the memory cells; receiving data to be stored in the mixed-mode memory device; reading the pre-generated public key from the first portion of the memory cells; encrypting the data with the pre-generated public key; and storing the encrypted data in one of the first portion of the memory cells and the second portion of the memory cells. Further comprising:

16. The method of claim 12, wherein, receiving data having M bits; storing N bits of the M bits as most significant bits in the first portion of the memory cells; and storing (M-N) bits of the M bits as least significant bits in the second portion of the memory cells. Further comprising: storing a weight value in a corresponding memory cell in the analog mode or the digital mode; 17. The method of claim 12, wherein, controlling the word line control circuit to provide an input voltage to the word line; and obtaining a current response from the first bit line control circuit when the weight value is stored in the corresponding memory cell in the digital mode; or obtaining a current response from the second bit line control circuit when the weight value is stored in the corresponding memory cell in the analog mode. ​ ​ ​ ​

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