Integrated components

Abstract

Some embodiments include an integrated component having a memory array on a substrate. A first sense amplifier circuitry is associated with the substrate and includes a sense amplifier located directly beneath the memory array. A vertically extending digital line is associated with the memory array and coupled to the first sense amplifier circuitry. A second sense amplifier circuitry is associated with the substrate and offset from the first sense amplifier circuitry. A control circuitry is configured to selectively couple the digital line to a voltage supply terminal or the second sense amplifier circuitry.

Description

Technical Field

[0001] Integrated memory (e.g., DRAM). Background Technology

[0002] Memory is used to store data in modern computing architectures. One type of memory is Dynamic Random Access Memory (DRAM). Compared to alternative types of memory, DRAM offers advantages such as simple structure, low cost, and high speed.

[0003] DRAM can utilize memory cells with a capacitor coupled to a transistor (so-called 1T-1C memory cells), where the capacitor is coupled to the source / drain regions of the transistor.

[0004] Figure 1 illustrates an area of ​​an exemplary prior art DRAM configuration 10. Configuration 10 includes memory cells 14 (some of which are labeled) arranged in a three-dimensional memory array 16. The area adjacent to component 10 provides an x, y, z coordinate system to aid in describing the relative orientation of the various structures.

[0005] Each of the memory cells contains an access device 18 (only one of which is labeled) coupled to a capacitor 20 (only one of which is labeled).

[0006] In the case that each of the transistors includes a channel region 22 located between a pair of source / drain regions 24 and 26, the access device 18 corresponds to a horizontally extending transistor.

[0007] The channel region and the source / drain region may be formed in the semiconductor material 28. The semiconductor material 28 may contain any suitable composition; and in some embodiments, it may contain one or more of silicon, germanium, group III / V semiconductor materials (e.g., gallium phosphide), semiconductor oxides, etc., substantially composed of or composed of them; the term group III / V semiconductor material refers to a semiconductor material containing elements selected from groups III and V of the periodic table (where group III and V are old nomenclature and are now referred to as groups 13 and 15).

[0008] The source / drain regions 24 and 26 can correspond to the heavily doped regions formed within the semiconductor material 28.

[0009] In the illustrated embodiment, semiconductor material 28 extends to conductive plate 30. In some operating states, conductive plate 30 can be used to drain excess carriers (e.g., holes) from the body region (channel region) of transistor 18.

[0010] Vertically extending bit lines (bit lines, sensing lines) 32 run along the columns of memory array 16 and are coupled to source / drain regions 24.

[0011] The horizontally extending word lines (access lines) 34 extend along the rows of the memory array 16 and are operatively close to the channel region 22.

[0012] The word line 34 extends along the y-axis direction shown, and the digit line 32 extends along the z-axis direction shown. The vertically extending digit line 32 may be orthogonal to the word line 34, or at least substantially orthogonal to such word lines (wherein the term "substantially orthogonal" means orthogonal within reasonable tolerances for manufacturing and measurement). In some embodiments, the digit line 32 may extend along a direction within approximately 10° orthogonal to the word line 34.

[0013] Word line 34 can be considered to include a gated region operatively adjacent to channel region 22 of transistor 18, such that source / drain regions 24 and 26 of the respective transistors 18 are gate-coupled to each other. When the term "gate-coupled" is used herein, this can refer to controlled coupling / decoupling between source / drain regions 24 and 26, which may be caused by electrical activation / deactivation of word line 34.

[0014] The gated region along word line 34 is spaced from channel region 22 by gate dielectric material 36. The gate dielectric material may contain any suitable composition; and in some embodiments may contain silicon dioxide, be substantially composed of it, or be composed of it.

[0015] Word line 34 may extend to the word line driver circuitry (e.g., sub-word line driver cells (SWD cells)) outside the area shown in component 10. A stepped region may be laterally adjacent to memory array 16 and may be used to couple individual word lines to specific SWD cells.

[0016] The memory cell 14 can be considered to be arranged within a vertically stacked layer (level) 35.

[0017] Conductive nodes 38 (only one pair is labeled) are adjacent to source / drain regions 26 and couple such source / drain regions to memory element 20. In some embodiments, conductive nodes 38 may be considered as part of memory element 20.

[0018] In operation, word line 34 can be used to selectively couple capacitor 20 to bit line 32 during a READ / WRITE operation associated with memory cell 14. Each of the memory cells 14 can be considered uniquely addressable using a combination of one of the bit lines 32 and one of the word lines 34.

[0019] The digital line can be coupled to a sensing circuit system (e.g., a sensing amplifier circuit system). The sensing circuit system can be used to determine the memory state of the memory cell during a READ operation and can be used to assist in programming the memory cell during a WRITE operation.

[0020] The goal is to develop a sensing circuit system that can be highly integrated with the memory array 16 in an integrated component. Summary of the Invention

[0021] In one aspect, this disclosure relates to an integrated component comprising: a memory array situated on a substrate, the memory array comprising a three-dimensional arrangement of memory cells; a first sense amplifier circuitry system associated with the substrate and comprising a sense amplifier located directly beneath the memory array; vertically extending digital lines passing through the arrangement of the memory cells and coupled to the first sense amplifier circuitry system; a second sense amplifier circuitry system associated with the substrate and offset from the first sense amplifier circuitry system; and a control circuitry system configured to selectively couple the digital lines to a voltage supply terminal or to the second sense amplifier circuitry system.

[0022] In another aspect, this disclosure relates to an integrated component comprising: a memory array located on a substrate; a first sense amplifier circuit system associated with the substrate and including a sense amplifier located directly below the memory array; a vertically extending digit line associated with the memory array and coupled to the first sense amplifier circuit system; a second sense amplifier circuit system offset from the first sense amplifier circuit system; the first sense amplifier circuit system being configured for PRECHARGE operations; and the second sense amplifier circuit system being configured for READ / WRITE operations, but not for PRECHARGE operations.

[0023] In a further aspect, this disclosure relates to an integrated component comprising: a memory array situated on a substrate; vertically extending digit lines associated with the memory array; a sense amplifier situated below the memory array and coupled to the digit lines; and a wiring structure coupled to each of the digit lines and extending to a Mux component; the Mux component corresponding one-to-one with the digit lines; each of the Mux components comprising a first transistor and a second transistor; the first transistor having a first gate, a first source / drain region, and a second source / drain region; the first... The gates gate-couple the first and second source / drain regions to each other; the second transistor has a second gate, a third source / drain region, and a fourth source / drain region; the second gate gate-couples the third and fourth source / drain regions to each other; the wiring structure is coupled to the second and third source / drain regions; the first source / drain region is coupled to a second sense amplifier circuit system; the fourth source / drain region is coupled to a voltage source; the first and second gates are coupled to a Mux driver circuit system configured to selectively activate / deactivate the first and second gates. Attached Figure Description

[0024] Figure 1 is an illustrated three-dimensional view of a region of a prior art integrated component having a memory array extending through multiple vertically shifted layers.

[0025] Figure 2 It is a schematic cross-sectional side view of an area of ​​integrated components including an example arrangement of memory cells, digit lines, and sense amplifier circuitry.

[0026] Figure 3 This is a schematic view of an example arrangement of the memory, sense amplifier circuitry, and control circuitry during an example operation phase.

[0027] Figure 3A This is a schematic diagram of an example arrangement of an example sense amplifier configuration.

[0028] Figure 3B This is a diagram illustrating an example Mux configuration.

[0029] Figure 3B-1 It is possible to be with Figure 3B A schematic diagram of an example control circuit used in conjunction with the Mux configuration.

[0030] Figure 4 This is a schematic view of an example arrangement of the memory, sense amplifier circuitry, and control circuitry during an example operation phase.

[0031] Figure 4AThis is a schematic diagram of an example arrangement of an example sense amplifier configuration.

[0032] Figure 4A-1 It is possible to be with Figure 4A A schematic diagram of the region of an example balanced circuit used in conjunction with a sense amplifier configuration.

[0033] Figure 5 This is a schematic view of an example arrangement of the memory, sense amplifier circuitry, and control circuitry during an example operation phase.

[0034] Figure 5A This is a schematic diagram of an example arrangement of an example sense amplifier configuration.

[0035] Figure 5A-1 It is possible to be with Figure 5A A schematic diagram of the region of an example balanced circuit used in conjunction with a sense amplifier configuration.

[0036] Figure 6 During the example operation phase and Figure 5 A graphical view of the timing and relative signal strength associated with the various structures of the memory device. Detailed Implementation

[0037] Some embodiments include an integrated component having at least two different types of sense amplifier circuitry systems. These two different types may include a first sense amplifier circuitry system and a second sense amplifier circuitry system. The first sense amplifier circuitry system (also referred to as a local sense amplifier circuitry system) includes a sense amplifier located directly below a vertically extending digital line and is used for PRECHARGE operation, and may also be used to provide signal enhancement during READ / WRITE operation. The second sense amplifier circuitry system (also referred to as a global sense amplifier circuitry system) is used for READ / WRITE operation. Reference Figure 2-6 Example implementations are described.

[0038] Figure 3-6 Specific example operations that can be used relative to configurations having local sense amplifier circuitry and global sense amplifier circuitry are described. Before describing the specific operations, Figure 2 This will be used to generally describe the local sense amplifier circuit system and the global sense amplifier circuit system relative to the example memory array.

[0039] Figure 2 An area of ​​an integrated component 200 is shown, comprising a memory array 16 similar to that described above with reference to FIG1. ​​The memory array includes multiple vertically extending bit lines 32 and multiple horizontally extending word lines 34. Relative to Figure 2A cross-sectional view, with line 34 extending in and out of the page. Figure 2 The insulating material is not specifically shown; instead, its location is illustrated using intervals. Correspondingly, the gate dielectric material 36 in Figure 1... Figure 2 The spacing between word line 34 and the memory cell 14 below is illustrated.

[0040] Memory cell 14 (only one of them is labeled) extends horizontally along the illustrated x-axis, and the memory cell includes access device 18 (some of which are labeled) and capacitor 20. In the illustrated embodiment, laterally adjacent capacitors share plate electrode 40.

[0041] Memory array 16 can be considered as a three-dimensional arrangement comprising memory cells 14, wherein such arrangement has relative to Figure 2 The cross-section extends into and out of the page (i.e., along the y-axis shown in Figure 1) in rows and has columns extending along the z-axis shown. Therefore, word lines 34 can be considered to be associated with rows of the memory array, and bit lines (bit lines) 32 can be considered to be associated with columns of the memory array.

[0042] The illustrated area of ​​memory array 16 includes four vertically stacked layers 35 of memory cells 14. It should be understood that memory array 16 may contain any suitable number of layers 35. In some embodiments, memory array 16 may contain 4 vertically stacked layers (as shown), 8 vertically stacked layers, 16 vertically stacked layers, 32 vertically stacked layers, 64 vertically stacked layers, and so on.

[0043] The memory array 16 can be considered to be supported by the underlying substrate 12. The substrate 12 may contain semiconductor material; and may, for example, contain, substantially consist of, or be composed of single-crystal silicon. The substrate 12 may be referred to as a semiconductor substrate. The term "semi-conductive substrate" means any structure containing a semi-conductive material, including but not limited to bulk semi-conductive materials such as semi-conductive wafers (alone or as a component containing other materials) and layers of semi-conductive materials (alone or as a component containing other materials). The term "substrate" means any support structure, including but not limited to the semiconductor substrate described above. In some applications, the substrate 12 may correspond to a semiconductor substrate containing one or more materials associated with integrated circuit manufacturing. Such materials may include one or more of, for example, refractory metals, barrier materials, diffusion materials, insulating materials, etc.

[0044] The first sense amplifier circuit system 42 is associated with the substrate 12 and is subdivided into a plurality of local sense amplifiers (LSAs). The lateral boundaries of each LSA are illustrated using dashed lines. The boundaries are shown as ellipses, but can contain any suitable shape, including, for example, polygons, circles, etc. Each LSA can contain any suitable size.

[0045] Each LSA contains NMOS and PMOS transistors, as shown below relative to Figure 3A In a more detailed description, NMOS and PMOS transistors may be located within a CMOS supported by substrate 12. Such a CMOS may include regions extending into substrate 12 and / or may include regions located on substrate 12.

[0046] LSA regions 42 are located directly beneath memory array 16, and in the illustrated embodiment, each LSA region is located directly beneath a pair of bit lines 32. For example, one of the LSA regions is labeled 42a and is shown as being directly beneath a pair of bit lines labeled 32a and 32b. Bit lines 32a and 32b are shown as being electrically coupled to LSA region 42a. One of the bit lines 32a and 32b may be a “true” bit line (BL), while the other may be a complementary bit line (BL*). During some operations (e.g., PRECHARGE operation, REFRESH operation, etc.), the true bit line 32a and the complementary bit line 32b may be coupled to each other through LSA region 42a.

[0047] In some operations, complementary digital lines can be comparatively coupled to each other via a sense amplifier circuit system. For the purposes of understanding this disclosure and the following claims, the first digital line is "comparatively coupled" to the second digital line via the sense amplifier circuit system if the sense amplifier circuit system is configured to compare the electrical characteristics (e.g., voltage) of the first and second digital lines. Note that the terms "true" and "complementary" are arbitrary in their use to label digital lines and are used only to distinguish digital lines compared to each other via the sense amplifier circuit system.

[0048] Digit line 32 is shown coupled to control circuitry 44. Control circuitry 44 may be associated with substrate 12. Control circuitry 44 is configured to electrically connect the digit line to voltage supply terminal 43 (which provides voltage Q) or to a second sense amplifier circuitry 46. The second sense amplifier circuitry is shown corresponding to a global sense amplifier (GSA). GSA cells (also referred to herein as GSA regions, or simply GSA) 46 may be located offset (e.g., laterally offset) relative to the LSA region and not directly below memory array 16. References below... Figure 4 The example GSA unit is described in more detail.

[0049] Still referencing Figure 2 The control circuitry 44 is coupled to a control unit 48, which is configured to control access to the digital line pairs voltage supply terminals 43 and GSA 46. The control unit 48 can be located in any suitable position. For example, the control unit 48 can be associated with the substrate 12 and can be laterally offset from the control circuitry 44 and the memory array 16.

[0050] In practice, the local sensing amplifier 42 can be a relatively simple structure used for PRECHARGE operation, REFRESH operation, and also to provide signal enhancement during READ / WRITE operation. The global sensing amplifier 46 can be a more complex structure used for READ / WRITE operation, rather than for PRECHARGE and REFRESH operation.

[0051] An example PRECHARGE operation relative to digit line 32 can be described as follows. All word lines 34 can be turned off, and control unit 48 can be used to switch control circuitry 44 to voltage supply terminal 43. This couples digit line 32 to voltage Q at the voltage supply terminal and thus charges the digit line to voltage Q. Voltage Q can be any suitable voltage, and in some embodiments it can be approximately VCC / 2.

[0052] An example REFRESH operation relative to digit line 32 can be described relative to digit line 32a. After the PRECHARGE operation, both digit lines 32a and 32b will be at voltage Q. Subsequently, one of the word lines 34 (e.g., the word line labeled 34a) can be activated, and this places the contents from memory cell 14a onto digit line 32a. Digit lines 32a and 32b can then be comparatively coupled using LSA 42a, which causes the contents of memory cell 14a to be restored to a full charge / discharge level (i.e., full rail level). It is worth noting that the REFRESH operation can be performed simultaneously on all digit lines associated with the activated word line, and therefore the entire row of memory cells can be refreshed simultaneously.

[0053] An example READ operation relative to digit line 32 can be described relative to digit line 32a. After a PRECHARGE operation, word line 34a can be activated to transfer content from cell 14a to digit line 32a, and control unit 48 can be used to switch control circuitry 44a and 44b such that digit lines 32a and 32b are comparatively coupled to each other via GSA 46 to determine the memory state of cell 14a.

[0054] The WRITE operation is similar to the READ operation, except that data is transferred to a memory cell instead of being read from a memory cell.

[0055] The READ operation described above primarily utilizes GSA 46 to determine the contents of memory cell 14a. In other embodiments, LSA 42a may initially be used for initial pre-sensing ("soft" sensing) of the memory state of execution cell 14a and to amplify the signal from digit line 32a before utilizing GSA 46. Figure 5 and 6 The use of LSA 42 in pre-sensing operations is described in more detail.

[0056] refer to Figure 3 This illustrates an area of ​​the integrated component 200 used for the example PRECHARGE / REFRESH operation. This component includes a digit line 32 associated with the LSA area 42. An example memory layer 35 is shown as part of the memory array 16, and word lines 34 are shown extending along the layer of memory 16, where one of the word lines (34a) is activated during the REFRESH operation and is easily distinguishable from the other word lines because it is a solid line labeled LWL. The word line LWL and digit line 32a together address memory cell 14a (cell 1).

[0057] Each unit of the control circuit system 44 is shown as comprising a wiring structure 54 and two switches (transistors) 50 and 52, wherein the two units are labeled 44a and 44b. Transistors 50 and 52 are adjacent to each other and may be referred to as the first transistor and the second transistor, respectively.

[0058] Figure 3B One of the control circuit systems 44 is shown in more detail. A first transistor 50 has a first gate 51 and a first source / drain region 53 and a second source / drain region 55; and a second transistor 52 has a second gate 57 and a third source / drain region 59 and a fourth source / drain region 61. The first gate 51 gate-couples the first source / drain region 53 and the second source / drain region 55 to each other, and the second gate 57 gate-couples the third source / drain region 59 and the fourth source / drain region 61 to each other.

[0059] The gate 51 of the first transistor may contain a deactivation voltage of approximately VSS (Vss) and an activation voltage of approximately VEQ; and the gate 57 of the second transistor may contain a deactivation voltage of approximately VSS and an activation voltage of approximately VDD (Vdd). The voltage VDD may be substantially the same as the voltage VCC. The voltage VEQ may be greater than the voltage VDD, and correspondingly, the first transistor 51 may have a higher threshold voltage than the second transistor 57. In other embodiments, the first transistor 51 and the second transistor 57 may have substantially the same threshold voltage and may be activated using substantially the same activation voltage; wherein the term "substantially the same" means identical within reasonable tolerances of fabrication and measurement. The advantage of having a higher threshold voltage associated with transistor 51 is that it can be adapted to transmit high-voltage signals from digit line 32 to GSA circuit system 46. Conversely, the lower threshold voltage transistor 57 can be adapted for PRECHARGE / REFRESH operation associated with digit line 32.

[0060] The wiring structure 54 is coupled to the second source / drain region 55 and the third source / drain region 59, and extends from the second / third source / drain region to the digit line 32.

[0061] The first source / drain region 53 is coupled to the second sense amplifier circuit system 46 (GSA circuit system), and the fourth source / drain region 61 is coupled to the voltage supply terminal 43. The voltage supply terminal 43 is coupled to a voltage source at voltage level Q (e.g., VCC / 2).

[0062] The first gate 51 and the second gate 57 are coupled to the control unit 48. In some embodiments, the control circuit system 44 may be referred to as a Mux (multiplexer) circuit system (or Mux component), and the control unit 48 may be referred to as a Mux driver circuit system. The Mux driver circuit system 48 is configured to selectively activate / deactivate one or both of the first gate 51 and the second gate 57 during programming operations (e.g., during PRECHARGE, REFRESH, READ, WRITE, etc.). Figure 2 and 3 In the embodiment shown, the Mux component 44 corresponds one-to-one with the digit line 32.

[0063] Figure 3B The embodiments refer to the first gate 51 as associated with the selector (A) and the second gate 57 as associated with the bleeder (B). The terms selector and bleeder are used to convey example operational aspects of gates 51 and 57, wherein gate 51 is used to “select” the GSA circuit system 46 and gate 57 is used to “bleed” the voltage level Q into the digit line 32 during PRECHARGE operation.

[0064] Figure 3B-1 An example control circuit system that can be associated with the Mux driver circuit system 48 and the LSA 42 is illustrated in the diagram.

[0065] Figure 3A Example LSA 42 is illustrated. The LSA includes a pair of cross-coupled PMOS transistors (pull-up transistors) 56 and 58, and a pair of cross-coupled NMOS transistors (pull-down transistors) 60 and 62. PMOS transistors 56 and 58 can be collectively considered as PSA region 63 (pull-up region), and NMOS transistors 60 and 62 can be collectively considered as NSA region 65 (pull-down region). Signals from a pair of comparison-coupled bit lines (corresponding to BL and BL* of bit lines 32a and 32b, respectively) are shown associated with LSA 42. One signal will be higher than the other. LSA 42 is configured to reduce the lower signal to a fully discharged level and raise the higher signal to a fully charged level. As will be understood by those skilled in the art, the symbols ACT and RNL refer to voltage levels.

[0066] The NMOS and PMOS transistors of LSA 42 can be located within a CMOS supported by substrate 12.

[0067] Figure 3 The LSA 42 is a simple device that utilizes only four transistors (Tr). Such devices can be easily integrated into the above reference. Figure 2 and 3 In applications of the type described, the device is positioned directly below an adjacent digital line. LSA devices can remain relatively small, especially compared to GSA devices (an example GSA device will be described below).

[0068] Refer again Figure 3 The diagram illustrates component 200 in operation during a REFRESH operation associated with digit line 32a. First transistor 50 and second transistor 52 within Mux components 44a and 44b are deactivated (i.e., the gate voltage for such transistors is Vss), and digit lines 32a and 32b are correspondingly coupled to each other via LSA 42a. Notably, other digit lines remain in a PRECHARGE state, and specifically, the second transistor 52 associated with such digit lines is activated (i.e., the gate voltage is Vdd), such that the digit line is coupled to the PRECHARGE voltage Q.

[0069] Figure 4An example READ operation utilizing GSA 46 is illustrated. The first transistor 50 of Mux components 44a and 44b is activated (i.e., the gate voltage of such transistors is VEQ), the second transistor 52 of Mux components 44a and 44b is deactivated (i.e., the gate voltage of such transistors is Vss), and correspondingly, the digit lines 32a and 32b are comparatively coupled via GSA 46. The activated word line 34a (LWL) and digit line 32a together address memory cell 14a (cell 1), and... Figure 4 The contents of such cells are accessed during the READ operation.

[0070] Signals from digital lines 32a and 32b are transmitted to column selection circuit systems 64 and 66, and from the column selection circuit systems to GSA circuit system 46. Figure 4A Example GSA configuration 46 is illustrated in the diagram. This configuration includes local input / output (LIO) signals passed to column select circuit systems 64 and 66, as will be understood by those skilled in the art. Column select circuit systems 64 / 66 are used to address selected digit lines 32a and 32b, where such digit lines are... Figure 4A In Chinese, these are referred to as BL and BL*.

[0071] Figure 4A The GSA configuration contains 12 transistors, and therefore is more... Figure 3A The LSA configuration is much larger. Figure 4A The GSA configuration includes a pair of cross-coupled PMOS transistors (pull-up transistors) 72 and 74, and a pair of cross-coupled NMOS transistors (pull-down transistors) 76 and 78. The column select circuit system 64 / 66 includes a first transistor 71a laterally offset from a first side 73a of the region containing the pull-up and pull-down transistors; and includes a second transistor 71b laterally offset from a second side 73b of the region containing the pull-up and pull-down transistors, wherein the second side is opposite to the first side.

[0072] In some embodiments, with Figure 3A Compared to the LSA configuration, Figure 4A A GSA configuration can have a higher threshold voltage associated with it. The threshold voltage associated with the sense amplifier can be understood as being related to the threshold voltage associated with the transistors of the sense amplifier (e.g., PMOS transistors and NMOS transistors). It may be advantageous for the GSA to have a higher threshold voltage than the LSA because it may be desirable to configure the GSA and LSA to be suitable for handling (and generating) different load levels (i.e., different levels of signal strength).

[0073] Figure 4AThe GSA-configured NMOS and PMOS transistors can be located within the CMOS supported by substrate 12. In some embodiments, Figure 4A The CMOS circuitry configured in the GSA configuration can be referred to as a second CMOS circuitry system, in order to integrate it with... Figure 3A The first CMOS circuit system is distinguished from the LSA configuration.

[0074] Figure 4 The illustrated embodiment shows a GSA 46 associated with multiple LSAs 42. The illustrated embodiment shows three LSAs 42 associated with the GSA 46, but indicates that more than three LSAs may be associated with the GSA. In some embodiments, there may be at least approximately 10 local sense amplifiers (LSAs 42) associated with a single global sense amplifier (GSA 46), at least approximately 100 local sense amplifiers associated with a single global sense amplifier, at least approximately 500 local sense amplifiers associated with a single global sense amplifier, and so on.

[0075] Figure 4 The view can be considered to show slices of a three-dimensional configuration through a three-dimensional array 16 containing memory cells 14. There can be a large number of such slices (e.g., at least about 10 such slices, at least about 50 such slices, at least about 100 such slices, etc.), and each slice can contain a global sensing amplifier 46 associated with a large number of local sensing amplifiers. Accordingly, in some embodiments, there can be at least about 10 global sensing amplifiers, at least about 50 global sensing amplifiers, at least about 100 global sensing amplifiers, etc., associated with the three-dimensional memory array.

[0076] Figure 4A The sensing amplifier component can be balanced using any suitable balancing configuration. Figure 4A-1 An example configuration 67 is shown utilizing a pair of transistors 68 and 69 and a control unit 70 (equalizer) configured to control the activation / deactivation of transistors 68 and 69. Voltage levels Q, R, and S are shown at the source / drain regions of the transistors. Voltage level Q can be the PRECHARGE level described above, and levels R and S can be any suitable levels, as understood by one of ordinary skill in the art.

[0077] Figure 4 The configuration is described as utilizing GSA 46 for the READ operation. In other embodiments, GSA 46 may be used in conjunction with LSA 42 during the READ operation. For example, Figure 5 It shows a state similar to Figure 4The processing stage component 200, but in addition to GSA 46, LSA 42a is also used for read operations. Figure 5 The configuration is similar to Figure 4 The configuration, but Figure 5 The boundary of the LSA region is shown using a solid line, while Figure 4 The boundaries are shown using dashed lines to graphically indicate differences in the use of LSA areas. (Reference) Figure 5A and 5A-1 This can be further understood. Figure 5 Implementation examples and Figure 4 The differences between the embodiments. Specifically, Figure 5A The GSA configuration can now be an eight-transistor configuration, instead of... Figure 4A The configuration is 12 transistors. Figure 5A-1 It shows the relationship with Figure 4A-1 The equalizer circuit, or equivalent circuit, now utilizes signals (voltages) from bit lines 32a and 32b.

[0078] Figure 6 The diagram illustrates the interaction between the READ operation and the READ operation. Figure 5 The relative signal strength versus time relationship of various structures associated with component 200. In the early stage 80 of the READ operation, the difference in signal strength between bit lines 32a and 32b is shown as a quantity S1. In some embodiments, S1 may be less than or equal to about 200 mV (millivolts). At the subsequent stage 82, the difference in signal strength between bit lines 32a and 32b is amplified using LSA circuitry 42. During stage 84, as the signal on the bit lines is transmitted from LSA circuitry 42 to GSA circuitry 46, there may be a slight loss in the difference in signal strength between bit lines 32a and 32b, and then proceeding to stage 86, where GSA circuitry 46 is used to significantly amplify the difference in signal strength between bit lines 32a and 32b.

[0079] The components and structures discussed above can be utilized within integrated circuits (where the term "integrated circuit" refers to electronic circuits supported by a semiconductor substrate); and can be incorporated into electronic systems. Such electronic systems can be used in, for example, memory modules, device drivers, power supply modules, communication modems, processor modules, and special-purpose modules, and can include multi-layered, multi-chip modules. Electronic systems can be any of a variety of systems, such as, for example, cameras, wireless devices, displays, chipsets, set-top boxes, game consoles, lighting fixtures, vehicles, clocks, televisions, mobile phones, personal computers, automobiles, industrial control systems, aircraft, etc.

[0080] Unless otherwise stated, the various materials, substances, components, etc. described herein can be formed by any suitable method known or yet to be developed, including, for example, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), etc.

[0081] The terms “dielectric” and “insulating” can be used to describe materials having insulating electrical properties. In this disclosure, these terms are considered synonyms. In some instances, the use of the term “dielectric” and in others the use of the term “insulating” (or “electrically insulating”) may provide a linguistic variation in this disclosure to simplify the premises of the following claims and is not intended to indicate any significant chemical or electrical differences.

[0082] The terms "electrical connection" and "electrical coupling" are both used in this disclosure. The terms are considered synonyms. The use of one term in some cases and the use of another term in others may provide linguistic variation in this disclosure to simplify the presuppositions in the following claims.

[0083] The specific orientations of the various embodiments in the accompanying drawings are for illustrative purposes only, and in some applications, the embodiments may be rotated relative to the shown orientation. The description provided herein and the following claims relate to any structure having the described relationships between various features, regardless of whether the structure is in or rotated relative to the specific orientation of the drawings.

[0084] Unless otherwise indicated, the cross-sectional views in the accompanying drawings show only the features within the plane of the cross section and not the material outside the plane of the cross section, in order to simplify the drawings.

[0085] When a structure is described as being "above," "adjacent to," or "abutting" another structure, it can be directly above the other structure, or there may be an intermediate structure. Conversely, when a structure is described as being "directly above," "directly adjacent to," or "directly abutting" another structure, there is no intermediate structure. The terms "directly below," "directly above," etc., do not indicate direct physical contact (unless explicitly stated otherwise), but rather indicate upright alignment.

[0086] A structure (e.g., a layer, a material, etc.) may be described as “vertically extending” to indicate that the structure typically extends upward from an underlying substrate (e.g., a base plate). A vertically extending structure may extend substantially orthogonally to the upper surface of the substrate, or it may extend non-orthogonally.

[0087] Some embodiments include an integrated component having a memory array located on a substrate. The memory array has a three-dimensional arrangement of memory cells. A first sense amplifier circuitry is associated with the substrate and includes a sense amplifier located directly beneath the memory array. Vertically extending digital lines pass through the arrangement of memory cells and are coupled to the first sense amplifier circuitry. A second sense amplifier circuitry is associated with the substrate and is offset from the first sense amplifier circuitry. A control circuitry is configured to selectively couple the digital lines to either a voltage supply terminal or the second sense amplifier circuitry.

[0088] Some embodiments include an integrated component comprising a memory array located on a substrate. A first sense amplifier circuitry is associated with the substrate and includes a sense amplifier located directly beneath the memory array. Vertically extending digital lines are associated with the memory array and coupled to the first sense amplifier circuitry. A second sense amplifier circuitry is offset from the first sense amplifier circuitry. The first sense amplifier circuitry is configured for PRECHARGE operations. The second sense amplifier circuitry is configured for READ / WRITE operations, but not for PRECHARGE operations.

[0089] Some embodiments include an integrated component comprising a memory array located on a substrate. Vertically extending digit lines are associated with the memory array. Sensing amplifiers are located below the memory array and coupled to the digit lines. Wiring structures are coupled to each of the digit lines and extend to a Mux component. A Mux component corresponds one-to-one with a digit line. Each of the Mux components includes a first transistor and a second transistor. The first transistor has a first gate, a first source / drain region, and a second source / drain region. The first gate gate-couples the first and second source / drain regions to each other. The second transistor has a second gate, a third source / drain region, and a fourth source / drain region. The second gate gate-couples the third and fourth source / drain regions to each other. Wiring structures are coupled to the second and third source / drain regions.

[0090] The first source / drain region is coupled to the second sense amplifier circuitry. The fourth source / drain region is coupled to a voltage source. The first and second gates are coupled to a Mux driver circuitry configured to selectively activate / deactivate the first and second gates.

[0091] In accordance with regulations, the subject matter disclosed herein has been described in more or less specific language regarding structural and methodological features. However, it should be understood that the claims are not limited to the specific features shown and described, as the apparatus disclosed herein includes exemplary embodiments. Therefore, the claims should be provided for in their full literal sense and should be properly interpreted in accordance with the doctrine of equivalents.

Claims

1. An integrated assembly, comprising: a memory array on a substrate, the memory array comprising a three-dimensional arrangement of memory cells; first sense amplifier circuitry associated with the substrate and comprising a sense amplifier located directly below the memory array; vertically-extending digit lines passing through the arrangement of memory cells and coupled with the first sense amplifier circuitry; second sense amplifier circuitry associated with the substrate and offset from the first sense amplifier circuitry; and control circuitry configured to selectively couple the digit lines to a voltage supply terminal or to the second sense amplifier circuitry, wherein: the first sense amplifier circuitry comprises a first threshold voltage associated therewith; the second sense amplifier circuitry comprises a second threshold voltage associated therewith; and the second threshold voltage is greater than the first threshold voltage.

2. The integrated assembly of claim 1, wherein the second sense amplifier circuitry is not located directly below the memory array.

3. The integrated assembly of claim 1, wherein the control circuitry associated with each of the digit lines comprises: a wiring structure coupled with an associated one of the digit lines; a pair of adjacent transistors, wherein one of the transistors is a first transistor and the other is a second transistor; the first transistor having a first gate, a first source / drain region, and a second source / drain region; the first gate coupling the first and second source / drain regions to one another in a gated manner; the second transistor having a second gate, a third source / drain region, and a fourth source / drain region; the second gate coupling the third and fourth source / drain regions to one another in a gated manner; the wiring structure coupled with the second and third source / drain regions; the first source / drain region coupled with the second sense amplifier circuitry; the fourth source / drain region coupled with the voltage supply terminal; and the first and second gates coupled with Mux driver circuitry configured to selectively activate / deactivate one or both of the first and second gates.

4. The integrated assembly of claim 3, wherein the first transistor has a higher threshold voltage than the second transistor.

5. The integrated assembly of claim 3, wherein the first transistor has substantially the same threshold voltage as the second transistor.

6. The integrated assembly of claim 3, wherein activation of the first gate utilizes a first activation voltage and activation of the second gate utilizes a second activation voltage; and wherein the first and second activation voltages are substantially the same as one another. ​ ​ 7. The integrated assembly of claim 3, wherein activation of the first gate utilizes a first activation voltage, and activation of the second gate utilizes a second activation voltage; and wherein the first and second activation voltages are different from one another.

8. The integrated assembly of claim 7, wherein the first activation voltage is greater than the second activation voltage.

9. The integrated assembly of claim 1, wherein the voltage supply terminal is at a voltage of approximately Vcc / 2.

10. The integrated assembly of claim 1, wherein: the sense amplifier is a first sense amplifier; the second sense amplifier circuitry includes a second sense amplifier; the first sense amplifier is in a configuration having no more than 4 transistors; and the second sense amplifier is in a configuration having at least 8 transistors.

11. The integrated assembly of claim 10, wherein the second sense amplifier is in a configuration having at least 12 transistors.

12. The integrated assembly of claim 1, wherein the three-dimensional arrangement includes at least 8 vertically stacked layers of memory cells.

13. The integrated assembly of claim 1, wherein the three-dimensional arrangement includes at least 16 vertically stacked layers of memory cells.

14. The integrated assembly of claim 1, wherein the three-dimensional arrangement includes at least 64 vertically stacked layers of memory cells.

15. An integrated assembly, comprising: a memory array on a substrate; first sense amplifier circuitry associated with the substrate and including a sense amplifier located directly below the memory array; a vertically extending digit line associated with the memory array and coupled with the first sense amplifier circuitry; second sense amplifier circuitry offset from the first sense amplifier circuitry; the first sense amplifier circuitry configured for use in PRECHARGE operations; and the second sense amplifier circuitry configured for use in READ / WRITE operations, but not in PRECHARGE operations, wherein: the first sense amplifier circuitry includes a first threshold voltage associated therewith; the second sense amplifier circuitry includes a second threshold voltage associated therewith; and the second threshold voltage is greater than the first threshold voltage.

16. The integrated assembly of claim 15, including control circuitry laterally offset from the digit line and configured to selectively couple the digit line to a voltage supply terminal or to the second sense amplifier circuitry.

17. The integrated assembly of claim 15, wherein the first sense amplifier circuitry is configured for use in the READ / WRITE operations to boost a signal before sending the signal to the second sense amplifier circuitry. ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ 18. The integrated assembly of claim 15, wherein the sense amplifier is a first sense amplifier associated with the substrate and including first CMOS circuitry, and wherein the second sense amplifier circuit includes a second sense amplifier associated with the substrate and including second CMOS circuitry.

19. The integrated assembly of claim 18, wherein: the second CMOS circuitry includes a region including a pair of cross-coupled pull-up transistors and a pair of cross-coupled pull-down transistors; the region is proximate column select circuitry; and the column select circuitry includes a first transistor laterally offset from a first side of the region and includes a second transistor laterally offset from a second side of the region, wherein the second side is opposite the first side.

20. An integrated assembly, comprising: a memory array on a substrate; vertically-extending digit lines associated with the memory array; a first sense amplifier circuitry associated with the substrate and coupled with the digit line, the first sense amplifier circuitry including a sense amplifier located directly below the memory array; and a wiring structure coupled to each of the digit lines and extending to a Mux component; the Mux component corresponding one-to-one to the digit lines; each of the Mux components including a first transistor and a second transistor; the first transistor having a first gate, a first source / drain region, and a second source / drain region; the first gate coupling the first and second source / drain regions to one another in a gated manner; the second transistor having a second gate, a third source / drain region, and a fourth source / drain region; the second gate coupling the third and fourth source / drain regions to one another in a gated manner; the wiring structure coupled to the second and third source / drain regions; the first source / drain region coupled to second sense amplifier circuitry; the fourth source / drain region coupled to a voltage source; the first and second gates coupled to Mux driver circuitry configured to selectively activate / deactivate the first and second gates, wherein: the first sense amplifier circuitry includes a first threshold voltage associated therewith; the second sense amplifier circuitry includes a second threshold voltage associated therewith; and the second threshold voltage is greater than the first threshold voltage.

21. The integrated assembly of claim 20, wherein the Mux driver circuitry is associated with the substrate and laterally offset from the first and second sense amplifier circuitry.

22. The integrated assembly of claim 20, wherein the first transistor has a higher threshold voltage than the second transistor.

23. The integrated assembly of claim 20, wherein the first transistor has substantially the same threshold voltage as the second transistor.

24. The integrated assembly of claim 20, wherein: the sense amplifier is a first sense amplifier; the second sense amplifier circuitry includes a second sense amplifier; the first sense amplifier is in a configuration having no more than 4 transistors; and the second sense amplifier is in a configuration having no more than 4 transistors. The second sense amplifier is in a configuration having at least 8 transistors.

25. The integrated assembly of claim 24, wherein the second sense amplifier is in a configuration having at least 12 transistors.

26. The integrated assembly of claim 20, wherein the sense amplifiers are local sense amplifiers, wherein the second sense amplifier circuitry includes a global sense amplifier, and wherein at least 10 of the local sense amplifiers are associated with each of the global sense amplifiers.

27. The integrated assembly of claim 20, wherein the sense amplifiers are local sense amplifiers, wherein the second sense amplifier circuitry includes a global sense amplifier, and wherein at least 100 of the local sense amplifiers are associated with each of the global sense amplifiers.

28. The integrated assembly of claim 20, wherein the sense amplifiers are local sense amplifiers, wherein the second sense amplifier circuitry includes a global sense amplifier, and wherein at least 500 of the local sense amplifiers are associated with each of the global sense amplifiers.

Images