Semiconductor structure and method of manufacturing the same

Abstract

A semiconductor structure includes a first bottom electrode and a second bottom electrode disposed on a substrate. The first bottom electrode includes a first sidewall and a second sidewall, and the second bottom electrode includes a third sidewall and a fourth sidewall. The second sidewall faces the third sidewall. An upper support layer is disposed between the first bottom electrode and the second bottom electrode and contacts the second sidewall and the third sidewall. A cavity is disposed between the upper support layer and the substrate. A capacitor dielectric layer is disposed on the first bottom electrode and the second bottom electrode. A conductive material is disposed on the capacitor dielectric layer and fills the cavity. An upper portion of the first sidewall includes a ramp profile, and a lower end of the ramp profile is not lower than a lower surface of the upper support layer. The ramp profile improves uniformity of the capacitor dielectric layer and helps the conductive material fill the cavity.

Description

Technical Field

[0001] This invention relates to a semiconductor structure and a method for manufacturing the same, and more particularly to a semiconductor structure including a stacked capacitor and a method for manufacturing the same. Background Technology

[0002] Dynamic random access memory (DRAM) is a type of volatile memory that comprises an array area consisting of multiple memory cells and a peripheral area consisting of control circuitry. Each memory cell consists of a transistor and a capacitor electrically connected to the transistor. The transistor controls the storage and release of charge in the capacitor to achieve the purpose of storing data. The control circuitry addresses each memory cell and controls the access to data in each memory cell by using word lines (WL) and bit lines (BL) that span the array area and are electrically connected to each memory cell.

[0003] To reduce the size of memory cells and create chips with higher density, memory cell structures have evolved towards three-dimensional designs, such as using buried word lines and stacked capacitors. Stacked capacitors are vertically positioned above the substrate, saving substrate area and allowing for larger capacitances by increasing the height of the capacitor's electrode plates. However, as memory cell density increases, the arrangement of stacked capacitors becomes increasingly dense, increasing manufacturing difficulty and impacting capacitor reliability. Summary of the Invention

[0004] One of the objectives of this invention is to provide a semiconductor structure including a stacked capacitor and a method for manufacturing the same.

[0005] An embodiment of the present invention provides a semiconductor structure comprising a substrate, a first bottom electrode and a second bottom electrode disposed on the substrate, wherein the first bottom electrode includes a first sidewall and a second sidewall, and the second bottom electrode includes a third sidewall and a fourth sidewall, the second sidewall facing the third sidewall, and the upper portion of the first sidewall including a slop profile. An upper support layer is located between the first bottom electrode and the second bottom electrode and contacts the second sidewall and the third sidewall, wherein the upper support layer includes an upper surface and a lower surface, and the lower end of the slop profile is not lower than the lower surface of the upper support layer. A cavity is located between the substrate and the upper support layer. A capacitor dielectric layer is located on the first bottom electrode and the second bottom electrode. A conductive material is located on the capacitor dielectric layer and fills the cavity.

[0006] Another embodiment of the present invention provides a method for manufacturing a semiconductor structure, comprising the following steps: First, a substrate is provided, on which an upper sacrificial layer, an upper support layer, and a hard mask layer are disposed. Next, a plurality of bottom electrodes are formed, penetrating the upper sacrificial layer, the upper support layer, and the hard mask layer. Then, at least one opening is formed between the plurality of bottom electrodes, penetrating the hard mask layer and the upper support layer, to expose the upper sacrificial layer, wherein the portion of the plurality of bottom electrodes exposed from the opening includes a slop profile, the lower end of the slop profile being not lower than a lower surface of the upper support layer. Next, the upper sacrificial layer is removed from the opening to form a cavity between the upper support layer and the substrate. Then, a capacitor dielectric layer and a conductive material are formed to fill the cavity.

[0007] The invention is characterized by a sloping profile at the top of the bottom electrode around the opening. This helps the conductive material of the capacitor dielectric layer and the top electrode fill the cavity and improves the uniformity of the capacitor dielectric layer, thereby increasing the reliability of the capacitor. Furthermore, by controlling the lower end of the sloping profile to be no lower than the lower surface of the upper support layer, the invention reduces the electrical difference between the bottom electrode around the opening (with the sloping profile) and the bottom electrode outside the opening (without the sloping profile), resulting in a capacitor with more consistent electrical performance. Attached Figure Description

[0008] The accompanying drawings are provided to give a more in-depth understanding of this embodiment and are incorporated herein by reference as a whole. These drawings and descriptions are used to illustrate the principles of some embodiments. It should be noted that all drawings are schematic diagrams for illustrative and drafting purposes, and relative dimensions and scales have been adjusted. The same symbols represent corresponding or similar features in different embodiments.

[0009] Figures 1 to 6This is a schematic diagram illustrating the steps of a semiconductor structure manufacturing method according to an embodiment of the present invention, wherein... Figure 1 and Figure 3 This is a floor plan. Figure 2 , Figure 4 , Figure 5 and Figure 6 For along Figure 1 or Figure 3 The cross-sectional view of the tangent AA' shown.

[0010] Figure 7 This is a cross-sectional schematic diagram of a semiconductor structure according to another embodiment of the present invention.

[0011] Figure 8 This is a planar schematic diagram of a semiconductor structure according to another embodiment of the present invention. Figure 9 for Figure 8 A schematic cross-sectional view of one embodiment of the semiconductor structure along the AA' tangent. Figure 10 for Figure 8 Another embodiment of the semiconductor structure is shown in a cross-sectional view along the AA' tangent.

[0012] The reference numerals in the attached figures are explained as follows:

[0013] AA' tangent

[0014] 10 Substrates

[0015] 12 interlayer dielectric layer

[0016] 14 Storage Node Contact Pads

[0017] 16 Etching Stop Layer

[0018] 18 Lower Sacrificial Layer

[0019] 20 Lower support layer

[0020] 22 Upper Sacrificial Layer

[0021] 24 Upper support layer

[0022] 26 Hard mask layers

[0023] 29. Cavity

[0024] 30 bottom electrode

[0025] 32. Slope Profile

[0026] 34. Slope Profile

[0027] 42 Capacitor dielectric layer

[0028] 44 Conductive Materials

[0029] 24a Upper surface

[0030] 24b Lower surface

[0031] 30A First bottom electrode

[0032] 30B Second Bottom Electrode

[0033] 30C Third bottom electrode

[0034] 30D Fourth Bottom Electrode

[0035] OP opening

[0036] P1 lower end

[0037] P2 lower end

[0038] P3 top

[0039] P4 Top

[0040] S1 First sidewall

[0041] S2 Second Side Wall

[0042] S3 Third Side Wall

[0043] S4 Fourth Side Wall

[0044] S5 Fifth Side Wall

[0045] S6 Sixth Side Wall Detailed Implementation

[0046] To enable those skilled in the art to further understand this invention, preferred embodiments are described below, along with accompanying drawings, to explain in detail the composition and desired effects of the invention. It should be understood that the features described below can be substituted, rearranged, or combined with other embodiments without departing from the spirit of the invention.

[0047] Figures 1 to 6 This diagram illustrates the steps of a method for manufacturing a semiconductor structure according to an embodiment of the present invention. Please refer to... Figure 1 and Figure 2 First, a substrate 10 is provided. Then, an interlayer dielectric layer 12 and a memory node contact pad 14 located in the interlayer dielectric layer 12 are formed on the substrate 10. Next, a stacked structure is formed on the interlayer dielectric layer 12, which may include, from bottom to top, an etch stop layer 16, a lower sacrificial layer 18, a lower support layer 20, an upper sacrificial layer 22, an upper support layer 24, and a hard mask layer 26. Then, a plurality of bottom electrodes 30 are formed on the substrate 10, penetrating the stacked structure and respectively in direct contact with a memory node contact pad 14.

[0048] Substrate 10 may include a silicon substrate, epitaxial silicon substrate, silicon-germanium substrate, silicon carbide substrate, or silicon-on-insulator (SOI) substrate, but is not limited thereto. Semiconductor devices and circuit structures, such as transistors, embedded word lines, bit lines, and conductive plugs, may be disposed in substrate 10, but are not shown in the figures for simplicity. Interlayer dielectric layer 12 is composed of a dielectric material, suitable dielectric materials may include silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide nitride (SiCN), high-k dielectric materials, or combinations thereof, but is not limited thereto. According to one embodiment of the present invention, interlayer dielectric layer 12 mainly includes silicon nitride (SiN). Storage node contact pads 14 are composed of a conductive material, suitable conductive materials may include metals, such as tungsten (W), copper (Cu), aluminum (Al), titanium (Ti), tantalum (Ta), or compounds, alloys, and / or composite layers of the aforementioned metal materials, but are not limited thereto. According to one embodiment of the present invention, the storage node contact pad 14 primarily comprises tungsten (W). The etch stop layer 16, lower sacrificial layer 18, lower support layer 20, upper sacrificial layer 22, upper support layer 24, and hard mask layer 26 of the stacked structure each comprise a dielectric material, and the lower sacrificial layer 18 and upper sacrificial layer 22 require the use of dielectric materials that can be easily and selectively etched away from the stacked structure subsequently to facilitate the formation of cavities exposing the sidewalls of the bottom electrode 30 (e.g., ...). Figure 5 Cavity 29). According to one embodiment of the invention, the lower sacrificial layer 18, the upper sacrificial layer 22, and the hard mask layer 26 may each comprise an oxide dielectric, such as silicon oxide (SiO2) or boron phosphorus-doped silicon glass (BPSG), but are not limited thereto. The etch stop layer 16, the lower support layer 20, and the upper support layer 24 may each comprise a nitride dielectric, such as silicon carbide nitride (SiCN) or silicon nitride (SiN), but are not limited thereto. In some embodiments, the hard mask layer 26 may comprise the same dielectric material (e.g., silicon oxide) as the lower sacrificial layer 18 and the upper sacrificial layer 22, so as to be removed together with the lower sacrificial layer 18 and the upper sacrificial layer 22 during a selective etching process. The total thickness of the stack determines the height of the bottom electrode 30. According to one embodiment of the invention, the height of the bottom electrode 30 (i.e., the total thickness of the stack) may be between 1600 angstroms and 5000 angstroms, but is not limited thereto. According to one embodiment of the present invention, the thickness of the lower sacrificial layer 18 and the upper sacrificial layer 22 is preferably more than 5 times the thickness of the lower support layer 20 and the upper support layer 24, for example, between 5 and 10 times, or more than 10 times, so that the cavity can expose more of the sidewalls of the bottom electrode 30 for subsequent contact with the conductive material (e.g., the conductive material subsequently filled into the cavity) Figure 6The conductive material 44) is capacitively coupled. The thickness of the hard mask layer 26 determines the height at which the bottom electrode 30 protrudes from the upper support layer 24. According to an embodiment of the present invention, the thickness of the hard mask layer 26 is preferably between 1 / 3 and 1 / 10 of the thickness of the upper sacrificial layer 22, but is not limited thereto. The bottom electrode 30 is arranged in an array corresponding to each memory node contact pad 14, and is electrically connected to the source / drain regions of the transistors of the memory cells in the substrate 10 through the memory node contact pads 14. The bottom electrode 30 is made of a conductive material, and suitable conductive materials may include metals, such as tungsten (W), copper (Cu), aluminum (Al), titanium (Ti), tantalum (Ta), or compounds, alloys, and / or composite layers of the aforementioned metal materials, but are not limited thereto. According to an embodiment of the present invention, the bottom electrode 30 mainly comprises titanium (Ti). In this embodiment, the bottom electrode 30 has a cylindrical structure. For ease of explanation of the features of the present invention, the following will also be used... Figure 1 The bottom electrodes 30 through which the tangent AA' passes are sequentially (along the tangent AA') named the third bottom electrode 30C, the first bottom electrode 30A, the second bottom electrode 30B, and the fourth bottom electrode 30D. For example... Figure 2 As shown, the first bottom electrode 30A is located between the second bottom electrode 30B and the third bottom electrode 30C. The fourth bottom electrode 30D is located on opposite sides of the first bottom electrode 30A.

[0049] Please refer to Figure 3 and Figure 4 Next, a mask layer 28 (e.g., a photoresist layer) is formed on the hard mask layer 26. Then, the stacked structure is etched using the mask layer 28 as an etching mask to form multiple openings OP that penetrate the hard mask layer 26 and the upper support layer 24 and expose the upper sacrificial layer 22. The openings OP are generally circular, located between three adjacent bottom electrodes 30, and partially overlap with the bottom electrodes 30, exposing part of the sidewalls of the bottom electrodes 30.

[0050] Please refer to Figure 5 Next, the mask layer 28 is removed, followed by a selective etching process (e.g., a wet etching process) to remove the upper sacrificial layer 22 and the lower sacrificial layer 18 of the stacked structure from the opening OP, thereby forming a laterally extending cavity 29 between the upper support layer 24 and the substrate 10, exposing the sidewalls of each bottom electrode 30. The lower support layer 20 is etched with openings during the selective etching process, allowing the etchant of the wet etching process to access and remove the lower sacrificial layer 18. According to one embodiment of the invention, the hard mask layer 26 can be removed together in the selective etching process, exposing the upper surface 24a of the upper support layer 24.

[0051] Please refer to Figure 6Next, a deposition process is performed to form a capacitor dielectric layer 42 on the top surface and sidewalls of the bottom electrode 30, as well as on the surfaces of the upper support layer 24, the lower support layer 20, and the etch stop layer 16. Then, a conductive material 44 is formed on the capacitor dielectric layer 42 to completely cover the bottom electrode 30 and fill the cavity 29, thus obtaining the semiconductor structure of this embodiment. The capacitor dielectric layer 42 is composed of a dielectric material, and suitable dielectric materials may include silicon oxide (SiO2), silicon nitride (SiN), or high-k dielectric materials, but are not limited thereto. The conductive material 44 may include metals, such as tungsten (W), copper (Cu), aluminum (Al), titanium (Ti), tantalum (Ta), or compounds, alloys, and / or composite layers of the aforementioned metal materials, but are not limited thereto. According to one embodiment of the present invention, the conductive material 44 mainly includes titanium (Ti). The conductive material 44 serves as the top electrode of the capacitor, and is separated from the bottom electrode 30 by the capacitor dielectric layer 42 without direct contact.

[0052] One feature of this invention is that the bottom electrode 30 surrounding the opening OP (the portion of the bottom electrode 30 exposed from the opening OP) is chamfered to have a slop profile during the etching process of fabricating the opening OP, for example, as indicated in... Figure 3 , Figure 4 and Figure 5 The first bottom electrode 30A has a ramp profile 32, and the third bottom electrode 30A has a ramp profile 34. Due to the presence of the ramp profile, the capacitor dielectric layer 42 and the conductive material 44 are less likely to accumulate on the top of the bottom electrode 30 and obstruct the path of deposited gas into the cavity 29. Therefore, the present invention can obtain improved uniformity and quality of the capacitor dielectric layer 42 and the conductive material 44, thereby improving the reliability of the product.

[0053] Furthermore, the present invention allows adjustment of the slope and height of the ramp profile via etching process parameters of the opening OP. Preferably, the lower end of the ramp profile (e.g., marked on...) Figure 4 and Figure 5 The lower ends P1 of the ramp profile 32 and P2 of the ramp profile 34 are controlled to be no lower than the lower surface 24b of the upper support layer 24. In this way, the bottom electrodes 30 with beveled corners around the opening OP (e.g., the first bottom electrode 30A, the third bottom electrode 30C, and the fourth bottom electrode 30D) and the bottom electrodes 30 without beveled corners (e.g., the second bottom electrode 30B) have a consistent straight sidewall profile below the lower surface 24b, so that the formed capacitor can have a more consistent electrical performance.

[0054] The semiconductor structure provided according to an embodiment of the present invention, such as Figure 5As shown, the substrate 10 has adjacent first bottom electrodes 30A and 30B disposed thereon. The first bottom electrode 30A includes a first sidewall S1 and a second sidewall S2. The second bottom electrode 30B includes a third sidewall S3 facing the second sidewall S2 and a fourth sidewall S4 away from the second sidewall S2. An upper support layer 24 is laterally connected between the first bottom electrodes 30A and 30B and directly contacts the second sidewall S2 and the third sidewall S3. The upper part of the first sidewall S1 includes a ramp profile 32, and the lower end P1 of the ramp profile 32 is higher than the upper surface 24a of the upper support layer 24. The upper parts of the second sidewall S2 and the third sidewall S3 may each include straight profiles perpendicular to the upper surface 24a of the upper support layer 24. A third bottom electrode 30C may also be disposed on the substrate 10, adjacent to the first bottom electrode 30A, and includes a fifth sidewall S5 facing the first sidewall S1 of the first bottom electrode 30A. The upper support layer 24 is not included between the fifth sidewall S5 and the first sidewall S1. The upper part of the fifth sidewall S5 includes another ramp profile 34, wherein the lower end P2 of the ramp profile 34 is higher than the upper surface 24a of the upper support layer 24 and can be approximately flush with the lower end P1 of the ramp profile 32. A fourth bottom electrode 30D may also be provided on the substrate 10, adjacent to the second bottom electrode 30B, including a sixth sidewall S6 and a fourth sidewall S4 facing the second bottom electrode 30B. The upper support layer 24 is also laterally connected between the fourth bottom electrode 30D and the second bottom electrode 30B, and directly contacts the sixth sidewall S6 and the fourth sidewall S4. The upper part of the sixth sidewall S6 includes a straight profile perpendicular to the upper surface 24a of the upper support layer 24. The first bottom electrode 30A, the second bottom electrode 30B, the third bottom electrode 30C, and the fourth bottom electrode 30D all have a cylindrical structure. A laterally extending cavity 29 may be included between the upper support layer 24 and the substrate 10, exposing the sidewalls of each bottom electrode 30. In some embodiments, the semiconductor structure may further include a lower support layer 20 disposed parallel to the upper support layer 24 and the substrate 10, in direct contact with the second sidewall S2, the third sidewall S3, the fourth sidewall S4, and the sixth sidewall S6. The lower support layer 20 is not included between the fifth sidewall S5 and the first sidewall S1. In some embodiments, such as Figure 6 As shown, the semiconductor structure also includes a capacitor dielectric layer 42, located on the top surface and sidewalls of the bottom electrode 30, as well as on the surfaces of the upper support layer 24, the lower support layer 20, and the etch stop layer 16. A conductive material 44 is located on the capacitor dielectric layer 42, completely covering the bottom electrode 30 and filling the cavity 29.

[0055] Figure 7 This is a schematic cross-sectional view of a semiconductor structure according to another embodiment of the present invention. For the purpose of simplifying the description and facilitating comparison between different embodiments, Figure 7 Use and Figure 5The same labels are used to identify the same components. As mentioned above, the slope and height of the ramp profile can be adjusted by the etching process parameters of the opening OP so that the lower end P1 of the ramp profile 32 and the lower end P2 of the ramp profile 34 are located between the upper surface 24a and the lower surface 24b of the upper support layer 24.

[0056] Figure 8 This is a planar schematic diagram of a semiconductor structure according to another embodiment of the present invention. Figure 9 for Figure 8 A schematic cross-sectional view of one embodiment of the semiconductor structure along the AA' tangent. Figure 10 for Figure 8 A schematic cross-sectional view along the tangent AA' of another embodiment of the semiconductor structure. For the sake of simplicity and ease of comparison between different embodiments, Figure 8 , Figure 9 and Figure 10 Use and Figure 3 and Figure 5 The same reference numerals are used to identify the same components. The bottom electrode 30 of this invention can be fabricated as a hollow cylindrical shape with an open or closed bottom, allowing the top electrode (i.e., the conductive material 44 subsequently filled into the cavity 29) to be filled into the inner cavity of the bottom electrode 30, increasing the capacitive coupling area between the top electrode and the bottom electrode 30 to meet the need for greater capacitance. For example... Figure 8 As shown, the bottom electrode 30 can appear as a ring in the plan view. Figure 9 In the illustrated embodiment, the bottom end of the bottom electrode 30 may be open, exposing the top surface of the storage node contact pad 14. Figure 10 In the illustrated embodiment, the bottom end of the bottom electrode 30 may be closed, having a U-shaped cross-sectional shape. The opening OP is located between three adjacent annular bottom electrodes 30, partially overlapping with the bottom electrodes 30. In some embodiments, when the area of ​​the opening OP partially overlaps with the inner cavity area of ​​the bottom electrode 30, the upper end of the ramp profile of the bottom electrode 30 will be lower than the upper end of the straight sidewall. For example, referring to a portion of the first bottom electrode 30A, its inner cavity may partially overlap with the opening OP area, and the upper end P3 of the ramp profile 32 (also the upper end of the first sidewall S1) will be lower than the upper end of the second sidewall S2. In some embodiments, when the opening OP is offset and not located in the exact center of the three bottom electrodes 30, the upper ends of the ramp profiles of the three bottom electrodes 30 may not be flush. For example, as... Figure 8 and Figure 9 (or Figure 10As shown in the figure, the opening OP between the first bottom electrode 30A and the third bottom electrode 30C is more biased towards the first electrode 30A. The upper end P3 of the slope profile 32 of the first bottom electrode 30A (which is also the upper end of the first sidewall S1) is lower than the upper end P4 of the slope profile 34 of the third bottom electrode 30C (which is also the upper end of the fifth sidewall S5).

[0057] In summary, this invention forms a ramp profile on the top of the bottom electrode around the opening, which helps the conductive material of the capacitor dielectric layer and the top electrode fill the cavity and improves the uniformity of the capacitor dielectric layer, thereby increasing the reliability of the capacitor. Furthermore, by controlling the lower end of the ramp profile to be no lower than the lower surface of the upper support layer, this invention reduces the electrical difference between the bottom electrode around the opening (with the ramp profile) and the bottom electrode outside the opening (without the ramp profile), resulting in a more consistent electrical performance of the formed capacitor. It should be noted that the semiconductor structure with two support layers described herein is merely an example. In other embodiments, the number of stacked layers can be adjusted according to design requirements. For example, three support layers (e.g., upper, middle, and lower support layers) can be used to provide more robust structural support, or a single support layer (e.g., upper or middle support layer) can be used to provide structural support to simplify the manufacturing process; both are within the scope of this invention.

[0058] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A semiconductor structure, characterized in that, include: A substrate; A first bottom electrode and a second bottom electrode are disposed on the substrate, wherein the first bottom electrode includes a first sidewall and a second sidewall, the second bottom electrode includes a third sidewall and a fourth sidewall, the second sidewall faces the third sidewall, and the upper part of the first sidewall includes a ramp profile. A third bottom electrode is disposed on the substrate, the third bottom electrode including a fifth sidewall facing the first sidewall, the upper part of the fifth sidewall including another ramp profile, wherein the highest vertex of the fifth sidewall is higher than the highest vertex of the first sidewall; An upper support layer is located between the first bottom electrode and the second bottom electrode and contacts the second sidewall and the third sidewall, wherein the upper support layer includes an upper surface and a lower surface, and the lower end of the ramp profile is not lower than the lower surface of the upper support layer; A cavity is located between the substrate and the upper support layer; A capacitor dielectric layer is located on the first bottom electrode and the second bottom electrode; and A conductive material is located on the capacitor dielectric layer and fills the cavity.

2. The semiconductor structure as described in claim 1, characterized in that, The lower end of the slope profile is located between the upper surface and the lower surface of the upper support layer.

3. The semiconductor structure as described in claim 1, characterized in that, The lower end of the slope profile is higher than the upper surface of the upper support layer.

4. The semiconductor structure as described in claim 1, characterized in that, The upper portions of the second sidewall and the third sidewall each include a straight profile perpendicular to the upper surface of the upper support layer.

5. The semiconductor structure as described in claim 1, characterized in that, Also includes: A third bottom electrode is disposed on the substrate, including a fifth sidewall facing the first sidewall of the first bottom electrode, wherein the upper support layer is not included between the fifth sidewall and the first sidewall, and the upper part of the fifth sidewall includes another ramp profile, the lower end of the other ramp profile being flush with the lower end of the ramp profile.

6. The semiconductor structure as described in claim 5, characterized in that, The upper end of the other slope profile is not flush with the upper end of the slope profile.

7. The semiconductor structure as described in claim 1, characterized in that, Also includes: A fourth bottom electrode is disposed on the substrate, including a sixth sidewall facing the second bottom electrode. The upper support layer is also located between the second bottom electrode and the fourth bottom electrode and contacts the fourth sidewall and the sixth sidewall. The upper part of the sixth sidewall includes another straight profile perpendicular to the upper surface of the upper support layer.

8. The semiconductor structure as described in claim 1, characterized in that, The first bottom electrode and the second bottom electrode include cylindrical structures.

9. The semiconductor structure as described in claim 1, characterized in that, The first bottom electrode and the second bottom electrode comprise hollow cylindrical structures.

10. The semiconductor structure as claimed in claim 1, characterized in that, It also includes a lower support layer located between the upper support layer and the substrate, and in contact with the second sidewall and the third sidewall.

11. A method for manufacturing a semiconductor structure, characterized in that, include: A substrate is provided, on which an upper sacrificial layer, an upper support layer and a hard mask layer are disposed; Multiple bottom electrodes are formed, penetrating the upper sacrificial layer, the upper support layer, and the hard mask layer; At least one opening is formed between the plurality of bottom electrodes, penetrating the hard mask layer and the upper support layer to expose the upper sacrificial layer. The portion of the plurality of bottom electrodes exposed from the opening includes a ramp profile, the lower end of which is not lower than the lower surface of the upper support layer. The opening also includes another ramp profile, and the fifth sidewall of the second ramp profile faces the first sidewall of the ramp profile. The highest point of the fifth sidewall is higher than the highest point of the first sidewall. The upper sacrificial layer is removed from the opening to form a cavity between the upper support layer and the substrate; as well as A capacitor dielectric layer is formed and a conductive material fills the cavity.

12. The method for manufacturing a semiconductor structure as described in claim 11, characterized in that, The top surfaces of the plurality of bottom electrodes are flush with one upper surface of the hard mask layer.

13. The method for manufacturing a semiconductor structure as described in claim 11, characterized in that, The hard mask layer is removed simultaneously when the upper sacrificial layer is removed.

14. The method for manufacturing a semiconductor structure as described in claim 13, characterized in that, The lower end of the slope profile is located between an upper surface and a lower surface of the upper support layer.

15. The method for manufacturing a semiconductor structure as described in claim 13, characterized in that, The lower end of the slope profile is higher than an upper surface of the upper support layer.

16. The method for manufacturing a semiconductor structure as described in claim 11, characterized in that, The plurality of bottom electrodes and the conductive material are separated by the capacitor dielectric layer and do not come into direct contact.

17. The method for manufacturing a semiconductor structure as described in claim 11, characterized in that, The plurality of bottom electrodes each comprises a cylindrical structure.

18. The method for manufacturing a semiconductor structure as described in claim 11, characterized in that, The plurality of bottom electrodes each comprises a hollow cylindrical structure.

19. The method for manufacturing a semiconductor structure as described in claim 11, characterized in that, Also includes: A lower sacrificial layer is formed on the substrate; A lower support layer is formed on the lower sacrificial layer; as well as The upper sacrificial layer, the upper support layer, and the hard mask layer are formed on the lower support layer.

20. The method for manufacturing a semiconductor structure as described in claim 19, characterized in that, Also includes: Remove the lower sacrificial layer to form another cavity between the lower support layer and the substrate; as well as The capacitor dielectric layer is formed and the conductive material fills the other cavity.

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