Semiconductor device having memory cell

Abstract

The present disclosure generally relates to semiconductor devices, and more particularly to semiconductor devices having memory cells for multi-bit programming and methods for forming the same. The present disclosure also relates to methods for forming such semiconductor devices. The disclosed semiconductor devices can achieve smaller cell sizes than conventional devices, thereby increasing the packaging density of the disclosed devices.

Description

Technical Field

[0001] The disclosed subject matter relates generally to semiconductor devices and, more particularly, to semiconductor devices having memory cells for multi-bit programming and methods of forming the same. Background Art

[0002] Semiconductor devices and integrated circuit (IC) chips have found numerous applications in physics, chemistry, biology, computing, and memory devices. One example of a memory device is a non-volatile (NV) memory device. NV memory devices are programmable and widely used in electronic products due to their ability to retain data for extended periods of time.

[0003] NV memory devices can be categorized based on their read / write mechanisms. Exemplary categories of NV memory can include resistive random access memory (ReRAM), erasable programmable read-only memory (EPROM), flash memory, ferroelectric random access memory (FeRAM), and magnetoresistive random access memory (MRAM). NV memory devices can be constructed using device components such as transistors (e.g., fin field-effect transistors (FinFETs), ferroelectric field-effect transistors (FeFETs), complementary metal-oxide-semiconductor (CMOS) transistors) and capacitors (e.g., metal-insulator-metal (MIM) capacitors).

[0004] NV memory devices can be constructed in the form of memory cells, each of which stores a binary bit of information and can be operated via bit lines, word lines, and / or source lines. These devices can also be programmed using one-time programmable (OTP) or multi-time programmable (MTP) technologies. However, devices programmed using OTP / MTP technologies have been found to have large cell sizes, which can be disadvantageous because large cell sizes reduce the packing density of device components in IC chips. Summary of the Invention

[0005] In one aspect of the present disclosure, a semiconductor device is provided, comprising an isolation region located on a substrate; a first row of gates and diffusion blocks located on the isolation region. Each gate is arranged between two diffusion blocks and includes a dielectric layer conforming to the sides and bottom of the gate structure, wherein the dielectric layer contacts the two diffusion blocks in the first row. The semiconductor device also includes a first diffusion structure and a second diffusion structure located on the isolation region, the first diffusion structure and the second diffusion structure extending along the length of the isolation region, wherein the first row of gates and diffusion blocks are arranged between the first diffusion structure and the second diffusion structure, and the dielectric layer of each gate contacts the first diffusion structure and the second diffusion structure.

[0006] In another aspect of the present disclosure, a semiconductor device is provided, comprising an isolation region located on a substrate; and a gate located on the isolation region. The gate includes a dielectric layer conforming to the sides and bottom of the gate structure. The semiconductor device also includes two diffusion blocks and two diffusion structures located on the isolation region, wherein the gate is arranged between the two diffusion structures and the two diffusion blocks, and wherein the dielectric layer of the gate contacts each of the two diffusion structures and each of the two diffusion blocks.

[0007] In another aspect of the present disclosure, a method for forming a semiconductor device is provided by forming an isolation region on a substrate; forming a first row of gates and diffusion blocks on the isolation region, wherein each gate is formed between two diffusion blocks and includes a dielectric layer that conforms to the sides and bottom of the gate structure. The dielectric layer contacts the two diffusion blocks in the first row. The method also includes forming a first diffusion structure and a second diffusion structure on the isolation region, the first diffusion structure and the second diffusion structure extending along the length of the isolation region, wherein the first row of gates and diffusion blocks are formed between the first diffusion structure and the second diffusion structure, and the dielectric layer of each gate contacts the first diffusion structure and the second diffusion structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The present disclosure may be understood by referring to the following description taken in conjunction with the accompanying drawings.

[0009] For simplicity and clarity of illustration, the drawings illustrate general construction methods, and specific descriptions and details of well-known features and technologies may be omitted to avoid unnecessarily obscuring the discussion of the embodiments of the present disclosure described. In addition, the elements in the drawings are not necessarily drawn to scale. For example, the dimensions of some elements in the drawings may be exaggerated relative to other elements to help improve understanding of the embodiments of the present disclosure. The same reference numerals in different figures represent the same elements, and similar reference numerals may, but do not necessarily, represent similar elements.

[0010] Figure 1A is a top view of an example of a semiconductor device.

[0011] Figure 1B It is along Figure 1A 2 is a cross-sectional view of an example semiconductor device taken along line XX′ in FIG.

[0012] Figure 1C It is along Figure 1A 1 is a cross-sectional view of the example semiconductor device taken along line YY′ in FIG.

[0013] Figure 1D Yes Figure 1A A circuit diagram of an example semiconductor device is shown.

[0014] Figure 2 yes Figures 1A to 1D A perspective view of an example semiconductor device is shown.

[0015] Figures 3A to 3D is a top view illustrating an example arrangement of gate and diffusion structures within a memory cell of the semiconductor device shown in FIG. 1 .

[0016] Figure 4A is a top view of another example of a semiconductor device.

[0017] Figure 4B It is along Figure 4A 2 is a cross-sectional view of an example semiconductor device taken along line XX′ in FIG.

[0018] Figure 4C It is along Figure 4A A cross-sectional view of the example semiconductor device taken along line YY' in FIG.

[0019] Figures 5A to 9B The structure of a semiconductor device at various stages of forming the semiconductor device is shown.

[0020] Figure 5A and Figure 5B 1 and 2 are a top view and a cross-sectional view respectively showing a device structure for forming a semiconductor device. Figure 5B It is along Figure 5A A cross-sectional view taken along section line Y-Y'.

[0021] Figure 6A and Figure 6B They are shown respectively Figure 5A and Figure 5B Top and cross-sectional views of the patterning of the dielectric region of the device structure are shown. Figure 6B It is along Figure 6A Cross-sectional view taken along section line Y-Y'.

[0022] Figure 7A and Figure 7B They are shown in Figure 6A and Figure 6B Top and cross-sectional views showing the formation of conductive material in patterned dielectric regions. Figure 7B It is along Figure 7A A cross-sectional view taken along section line Y-Y'.

[0023] Figure 8A and Figure 8B They are shown respectively Figure 7A and Figure 7B Top and cross-sectional views of the patterning of the conductive material are shown. Figure 8B It is along Figure 8A A cross-sectional view taken along section line Y-Y'.

[0024] Figure 9A and Figure 9B It is shown in Figure 8A and Figure 8B A top view and a cross-sectional view of a gate formed in an opening formed in a patterned conductive material are shown. Figure 9B It is along Figure 9A A cross-sectional view taken along section line Y-Y'.

[0025] Figure 10 is a cross-sectional view illustrating an exemplary arrangement of components in a gate according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0026] Various illustrative embodiments of the present disclosure are described below. The embodiments disclosed herein are exemplary and are not intended to be exhaustive or limiting of the present disclosure.

[0027] refer to Figure 1A 、 Figure 1B and Figure 1C , an exemplary semiconductor device 100 is shown. Figure 1A is a simplified top view showing an example configuration of the exemplary semiconductor device 100. Line XX' indicates a cut-away Figure 1B The section line along which the view is taken in the figure is shown, and the line Y-Y' indicates the section taken. Figure 1C The section line along which the view in follows. Figure 1A In the simplified view of FIG, the isolation region 104 and the substrate 102 are not shown, however, it should be understood that Figure 1A The configuration in is placed on the isolation region 104.

[0028] like Figure 1A 、 Figure 1B and Figure 1C As shown, the device 100 may include a substrate 102, an isolation region 104 disposed on the substrate 102, and a dielectric region 106 disposed on the isolation region 104. The gates 120a, 120b, 120c and the diffusion blocks 109a, 109b, 109c, 109d of a first row 130 and the gates 122a, 122b, 122c and the diffusion blocks 111a, 111b, 111c, 111d of a second row 132 may be located on the isolation region 104. The gates and the diffusion blocks in the first row 130 and the second row 132 may be arranged along the length of the isolation region 104.

[0029] The gates and diffusion blocks in the first row 130 and the second row 132 may be arranged alternately. Specifically, each gate 120a, 120b, 120c in the first row 130 may be arranged between two diffusion blocks (respectively, 109a and 109b, 109b and 109c, and 109c and 109d) in the first row 130, and each gate 122a, 122b, 122c in the second row 132 may be arranged between two diffusion blocks (respectively, 111a and 111b, 111b and 111c, and 111c and 111d) in the second row 132. For example, in the first row 130, the gate 120a is located between the two diffusion blocks 109a and 109b, the gate 120b is located between the two diffusion blocks 109b and 109c, and the gate 120c is located between the two diffusion blocks 109c and 109d.

[0030] Each gate 120a, 120b, 120c in the first row 130 and each gate 122a, 122b, 122c in the second row 132 may include a dielectric layer 112, 114 that conforms to the sides and bottom of the gate structures 116, 118. The dielectric layer 112a, 112b, 112c of each gate (120a, 120b, 120c, respectively) in the first row 130 may contact two diffusion blocks in the first row 130. Similarly, the dielectric layer 114a, 114b, 114c of each gate (122a, 122b, 122c, respectively) in the second row 132 may contact two diffusion blocks in the second row 132. For example, in the first row 130, dielectric layer 112a contacts two diffusion blocks 109a and 109b, dielectric layer 112b contacts two diffusion blocks 109b and 109c, and dielectric layer 112c contacts two diffusion blocks 109c and 109d.

[0031] A first diffusion structure 108a, a second diffusion structure 108b, a third diffusion structure 110a, and a fourth diffusion structure 110b are disposed on the isolation region 104. The first, second, third, and fourth diffusion structures (108a, 108b, 110a, 110b, respectively) may extend along the length of the isolation region 104. The gates 120a, 120b, 120c and the diffusion blocks 109a, 109b, 109c, 109d of the first row 130 may be disposed between the first diffusion structure 108a and the second diffusion structure 108b. The dielectric layer 112a, 112b, 112c of each gate (120a, 120b, 120c, respectively) in the first row 130 may contact the first diffusion structure 108a and the second diffusion structure 108b. Similarly, the gates 122a, 122b, 122c and the diffusion blocks 111a, 111b, 111c, 111d of the second row 130 may be arranged between the third diffusion structure 110a and the fourth diffusion structure 110b. The dielectric layer 114a, 114b, 114c of each gate (122a, 122b, 122c, respectively) in the second row 132 may contact the third diffusion structure 110a and the fourth diffusion structure 110b.

[0032] Each diffusion structure 108a, 108b, 110a, 110b, each diffusion block 109a, 109b, 109c, 109d, 111a, 111b, 111c, 111d, and each gate 120a, 120b, 120c, 122a, 122b, 122c, 122d located on the isolation region 104 can be connected to a conductive line. The conductive line can be made of copper, aluminum, cobalt, or alloys thereof. The conductive lines connected to the diffusion structures, diffusion blocks, and gates can be configured as source lines, word lines, and bit lines. The terms "source line," "bit line," and "word line" as used herein refer to electrical terminal connections that connect memory cells in a device circuit.

[0033] As described above, each gate 120a, 120b, 120c in the first row 130 and each gate 122a, 122b, 122c in the second row 132 can be arranged between two diffusion blocks. The two diffusion blocks that contact the corresponding dielectric layer of each gate 120a, 120b, 120c in the first row 130 and each gate 122a, 122b, 122c in the second row 132 can be connected to different conductive lines. For example, in the first row 130, gate 120a is arranged between two diffusion blocks 109a and 109b. Diffusion block 109a can be connected to source line SL2, while diffusion block 109b can be connected to source line SL3. Alternatively, gate 120b is arranged between two diffusion blocks 109b and 109c. Diffusion block 109b can be connected to source line SL3, while diffusion block 109c can be connected to source line SL2.

[0034] The conductive lines may connect one of the gates 120a, 120b, 120c in the first row 130 and one of the gates 122a, 122b, 122c in the second row 132. For example, word line WL1 may connect gates 120a in the first row 130 and gates 122a in the second row 132, word line WL2 may connect gates 120b in the first row 130 and gates 122b in the second row 132, and word line WL3 may connect gates 120c in the first row 130 and gates 122c in the second row 132.

[0035] The first, second, third, and fourth diffusion structures 108a, 108b, 108c, and 108d may each be connected to a conductive line. The conductive lines connecting the first, second, third, and fourth diffusion structures (108a, 108b, 110a, and 110b, respectively) may be different from the conductive lines connecting the diffusion blocks 109 in the first row 130 and the diffusion blocks 111 in the second row 132.

[0036] refer to Figure 1A In the example shown in FIG1 , source line SL1 may be connected to the first diffusion structure 108a, source line SL2 may be connected to the first diffusion block (e.g., diffusion blocks 109a and 109c) of the two diffusion blocks in the first row 130, source line SL3 may be connected to the second diffusion block (e.g., diffusion blocks 109b and 109d) of the two diffusion blocks in the first row 130, and source line SL4 may be connected to the second diffusion structure 108b. Similarly, source line SL5 may be connected to the third diffusion structure 110a, source line SL6 may be connected to the first diffusion block (e.g., diffusion blocks 111a and 111c) of the two diffusion blocks in the second row 132, source line SL7 may be connected to the second diffusion block (e.g., diffusion blocks 111b and 111d) of the two diffusion blocks in the second row 132, and source line SL8 may be connected to the fourth diffusion structure 110b.

[0037] Although not shown in the figures, it should be noted that alternative ways of configuring the terminal connections (e.g., source lines, word lines, bit lines) to the diffusion structures and gates are contemplated within the scope of the present disclosure. For example, the diffusion structures 108, 110 and the diffusion blocks 109, 111 may alternatively be connected to word lines or bit lines, while the gates 120, 122 may be connected to source lines or bit lines.

[0038] Figure 1A130 and 132. Each gate 120a, 120b, 120c in the first row 130 and each gate 122a, 122b, 122c in the second row 132 can be electrically coupled to two diffusion structures and two diffusion blocks. The two diffusion structures and two diffusion blocks coupled to each gate 120a, 120b, 120c in the first row 130, and the two diffusion structures and two diffusion blocks coupled to each gate 122a, 122b, 122c in the second row 132 can be connected to different source lines. Each gate 120a, 120b, 120c in the first row 130 can be connected to the same word line as the corresponding gate 122a, 122b, 122c in the second row 132.

[0039] Each gate 120a, 120b, 120c in the first row 130 and each gate 122a, 122b, 122c in the second row 132 can be configured to receive a voltage to control an electrical characteristic (e.g., conductance) of at least one of the diffusion structure and the diffusion block in contact with the dielectric layer of each gate. As an illustrative example, gate 120a can be configured to be connected to word line WL1. Dielectric layer 112a has resistive properties and electrically insulates gate structure 116a from diffusion structures 108a, 108b and diffusion blocks 109a, 109b. A voltage can be applied to gate structure 116a, and an electric field can be generated across dielectric layer 112a. The generated electric field can enable gate structure 116a to modulate the conductance of diffusion structures 108a, 108b and diffusion blocks 109a, 109b. The resistance value of the dielectric layer 112a and the voltage supplied to the gate structure 116a may be optimized or adjusted to control the electrical characteristics of the diffusion structures 108a, 108b and the diffusion blocks 109a, 109b.

[0040] Advantageously, the devices of the present disclosure can achieve smaller cell sizes compared to conventional devices. Figure 1A As shown, a configuration of a single gate electrically coupled to at least two diffusion structures and two diffusion blocks can provide a memory cell having at least four bits, which can reduce the size of each cell in the device (e.g., each cell can be less than 38F). 2 ) and increase the packaging density of device components in IC chips, resulting in improved chip performance (e.g., faster processing speeds).

[0041] Furthermore, by alternately arranging the gates 120, 122 and the diffusion blocks 109, 111 in the first row 130 and the second row 132, for example, by arranging a gate between every two diffusion structures in the first row 130 and the second row 132, the packing density of the device components in the IC chip can be further increased. Therefore, the configuration of alternating gates and diffusion blocks in the first row 130 and the second row 132 can enable the device to be manufactured with multiple memory cells, each cell having at least four bits.

[0042] The substrate 102 can be made of any semiconductor material, such as silicon, germanium, silicon-germanium (SiGe), silicon carbide, and semiconductor materials consisting essentially of III-V compound semiconductors (e.g., GaAs) or II-VI compound semiconductors (e.g., ZnSe). The substrate 102 can also be a semiconductor-on-insulator substrate or a bulk semiconductor substrate. Examples of semiconductor-on-insulator substrates include, but are not limited to, organic semiconductors or stacked semiconductors, such as Si / SiGe, silicon-on-insulator (SOI), germanium-on-insulator (GOI), or SiGe-on-insulator. A portion or the entire semiconductor substrate 102 can be amorphous, polycrystalline, or single crystalline.

[0043] The isolation regions 104 may comprise an oxide material such as silicon dioxide. A plurality of isolation regions 104 may be formed on the substrate 102. The isolation regions 104 may be shallow trench isolation regions or deep trench isolation regions. Although not shown in the figures, other IC components such as bipolar junction transistors (BJTs) and / or field effect transistors (FETs) may also be constructed on the substrate 102 and separated by the isolation regions 104.

[0044] The dielectric region 106 may be embedded with the diffusion structures 108a, 108b, 110a, 110b, the diffusion blocks 109a, 109b, 109c, 109d, 111a, 111b, 111c, 111d, the gates 120, 122, and other interconnect features (e.g., conductive lines). For example, the dielectric region 106 may be an intermetallic dielectric (IMD) layer or "metallization layer" and may serve as an electrical insulator to prevent electrical shorts between the diffusion structures 108a, 108b, 110a, 110b and the diffusion blocks 109a, 109b, 109c, 109d, 111a, 111b, 111c, 111d. The dielectric region 106 may include a dielectric material such as, but not limited to, silicon dioxide, tetraethyl orthosilicate (TEOS), or a material having the chemical composition SiC. x O y H z A material wherein x, y and z are in stoichiometric ratios.

[0045] The diffusion structures 108a, 108b, 110a, 110b and the diffusion blocks 109a, 109b, 109c, 109d, 111a, 111b, 111c, 111d located on the isolation region 104 can serve as channels or paths for current flow (i.e., diffusion of electrons or charges) and can be made of conductive materials. Exemplary conductive materials for the diffusion structures and diffusion blocks include, but are not limited to, crystalline materials such as polycrystalline silicon, amorphous silicon, polycrystalline germanium, amorphous germanium, polycrystalline silicon germanium, or amorphous silicon germanium, or metallic materials such as tungsten, cobalt, nickel, copper, aluminum, or alloys thereof. In some embodiments, the diffusion structures 108a, 108b, 110a, 110b and the diffusion blocks 109a, 109b, 109c, 109d, 111a, 111b, 111c, 111d can be referred to as "poly lines."

[0046] As described above, each gate 120, 122 may include a dielectric layer 112, 114 and a gate structure 116, 118. In some embodiments, each gate structure 116, 118 in the corresponding gate 120, 122 may be surrounded by the corresponding dielectric layer 112, 114. The dielectric layers 112, 114 may include an oxide-containing dielectric material. The oxide-containing dielectric material may be made of a high-K dielectric material or silicon dioxide (SiO2).

[0047] As used herein, the term "high K" refers to a material having a dielectric constant (i.e., K value) greater than 5, preferably between 25 and 30. High K dielectric materials may include, but are not limited to, tantalum pentoxide (Ta2O5), magnesium oxide (MgO), hafnium oxide (HfO2), zirconium oxide (ZrO2), lanthanum oxide (La2O3), aluminum oxide (Al2O3), titanium oxide (TiO2), strontium titanium oxide (SrTiO3), lanthanum aluminum oxide (LaAlO3), yttrium oxide (Y2O3), hafnium oxynitride (HfO x N y ), zirconium oxynitride (ZrO x N y ), lanthanum oxynitride (La2O x N y ), aluminum oxynitride (Al2O x N y ), titanium oxynitride (TiO x N y ), strontium titanium oxynitride (SrTiO x N y ), lanthanum aluminum oxynitride (LaAlO x N y ), yttrium oxynitride (Y2O x N y), silicates thereof, and alloys thereof. Each value of x is independently from 0.5 to 3 and each value of y is independently from 0 to 2. The dielectric layers 112, 114 may have a thickness in a range of about 1 nm to about 20 nm, preferably about 5 nm to about 10 nm.

[0048] The gate structures 116 and 118 may also include metal electrodes and work function material (WFM) components. The metal electrodes may be made of conductive materials. Examples of conductive materials for the metal electrodes may include, but are not limited to, tungsten, cobalt, nickel, copper, and aluminum.

[0049] The WFM component may include any metal compound or combination of metal compounds that can modify the work function characteristics of the gate. Examples of metal compounds may include, but are not limited to, Hf, Ti, Zr, Cd, La, Tl, Yb, Al, Ce, Eu, Li, Pb, Tb, Bi, In, Lu, Nb, Sm, V, Zr, Ga, Mg, Gd, Y, TiAl, TaN, Pt, Rh, Ir, Ru, Cu, Os, Be, Co, Pd, Te, Cr, Ni, stacks thereof, conductive oxides thereof, conductive nitrides thereof, alloys thereof, and combinations thereof.

[0050] refer to Figure 1D , which shows Figures 1A to 1C 2. A circuit diagram 200 of electrical connections in an exemplary semiconductor device 100 is shown. The circuit diagram 200 may include a first row 230 having gate structures 216a, 216b, 216c and a second row 232 having gate structures 218a, 218b, 218c. Each gate structure 216a, 216b, 216c in the first row 230 and each gate 218a, 218b, 218c in the second row 232 is connected to four resistors R1, R2, R3, R4. The gate structures 216, 218 in the circuit diagram 200 may correspond to Figure 1A The implementation of the gate structure in each gate of the device 100 shown. The four resistors R1, R2, R3, R4 connected to each gate structure may correspond to Figure 1A The implementation of the dielectric layer in each gate of the device 100 is shown.

[0051] The circuit diagram 200 may include at least one memory cell. For example, the memory cell 228 in the circuit diagram 200 may include a gate structure (e.g., 216a) coupled to four resistors (e.g., R1, R2, R3, R4). Each memory cell may be connected to and operated by four source lines and one word line. Figure 1DAs shown, each resistor R1, R2, R3, and R4 of the memory cell can be connected to a source line. Specifically, in the first row 230, the source line SL1 can be connected to the resistor R3 of each memory cell, the source line SL2 can be connected to the resistor R1 of each memory cell, the source line SL3 can be connected to the resistor R4 of each memory cell, and the source line SL4 can be connected to the resistor R2 of each memory cell. In the second row 232, the source line SL5 can be connected to the resistor R3 of each memory cell, the source line SL6 can be connected to the resistor R1 of each memory cell, the source line SL7 can be connected to the resistor R4 of each memory cell, and the source line SL8 can be connected to the resistor R2 of each memory cell.

[0052] Each gate structure of a memory cell can be connected to a word line. Specifically, a first word line WL1 can connect gate structure 216a in the first row 230 and gate structure 218a in the second row 232. A second word line WL2 can connect gate structure 216b in the first row 230 and gate structure 218b in the second row 232. A third word line WL3 can connect gate structure 216c in the first row 230 and gate structure 218c in the second row 232.

[0053] Each memory cell in the device can be programmed using either OTP or MTP technology. In addition, in multi-level cell applications, each memory cell can be programmed as a single bit or multiple bits, depending on the control level.

[0054] For example, memory cell 228 can be programmed to have at least four bits. The first bit can include the connection between gate structure 216a, resistor R1, and source line SL2. The second bit can include the connection between gate structure 216a, resistor R2, and source line SL4. The third bit can include the connection between gate structure 216a, resistor R3, and source line SL1. The fourth bit can include the connection between gate structure 216a, resistor R4, and source line SL3.

[0055] To operate the first bit in the memory cell 228 of the circuit diagram 200, an "operation" voltage can be provided to the gate structure 216a via the first word line WL1, with the source line SL2 acting as a ground terminal (i.e., zero volts). The second and third word lines (WL2, WL3, respectively) and the other source lines SL1, SL3, SL4, SL5, SL6, SL7, SL8 can provide an "inhibit" voltage. The inhibit voltage can be 50% lower than the operation voltage to effect a change in the resistance state of the resistor R1 (e.g., from a high resistance state to a low resistance state, or from a low resistance state to a high resistance state). For an MTP memory cell, the resistance state of R1 can change between the low resistance state and the high resistance state multiple times, while for an OTP memory cell, the resistance state of R1 can change between the low resistance state and the high resistance state only once.

[0056] Similarly, to operate the second bit in memory cell 228, an operating voltage can be provided to gate structure 216a via first word line WL1, with source line SL3 acting as a ground terminal. The second and third word lines (WL2, WL3, respectively) and other source lines SL1, SL2, SL4, SL5, SL6, SL7, SL8 can provide an inhibit voltage, which enables the resistance state of resistor R2 to change. Similarly, other memory cells in first row 230 or second row 232 can operate in the same manner as memory cell 228 described herein.

[0057] Advantageously, it has been found that this configuration enables the use of a single gate to control the transmission of electrical signals to at least four source lines. Also advantageously, the disclosed device can enable multi-bit programming of memory cells with significantly reduced cell size.

[0058] Figure 2 Shown Figures 1A to 1C A perspective view of an exemplary semiconductor device is shown. As shown, an interconnect structure can be formed over the device structure to provide routing for electrical signals to and from the gate, diffusion block, and diffusion structure. The interconnect structure can be made of a metal material such as copper, cobalt, aluminum, or alloys thereof.

[0059] like Figure 2As shown, the interconnect structure may include interconnect vias 150 and conductive lines 152a, 152b, 152c, 152d, 152e, 152f, 152g, 152h, 154a, 154b, 154c. Conductive lines 152a, 152b, 152c, 152d, 152e, 152f, 152g, 152h, 154a, 154b, 154c may function as source lines, word lines, or bit lines. Specifically, conductive lines 154a, 154b, 154c may be configured as word lines connected to gate structures 116, 118 through interconnect vias 150. The conductive lines 152 a , 152 b , 152 c , 152 d , 152 e , 152 f , 152 h may be configured as source lines and connected to the diffusion structures 108 , 110 and the diffusion blocks 109 , 111 through the interconnection vias 150 .

[0060] exist Figure 2 In the embodiment shown, conductive lines (e.g., source lines) 152b, 152c, 152f, 152g connected to the diffusion structures in the first row 130 and the second row 132 can be formed above (e.g., at a higher metallization level than) the conductive lines 152a, 152d, 152e, 152h, 154a, 154b, 154c. The conductive lines (e.g., word lines) 154a, 154b, 154c can extend vertically across the gates and diffusion blocks of the first row 130 and the gates and diffusion blocks of the second row 132.

[0061] refer to Figure 3A 、 Figure 3B 、 Figure 3C and Figure 3D , shows an example of a memory cell 128 in a device of the present disclosure. As described herein, the memory cell 128 may include a gate 120 and at least two diffusion structures 108a, 108b, and two diffusion blocks 109a, 109b disposed on the isolation region 104. The gate 120 may be disposed between adjacent diffusion structures 108a, 108b and diffusion blocks 109a, 109b, and the dielectric layer 112 of the gate 120 may contact each of the diffusion structures 108a, 108b and diffusion blocks 109a, 109b.

[0062] The dielectric layer 112 of the gate 120 may conform to the side surfaces of the gate structure 116. The side surfaces of the gate structure 116 may provide at least four contact points (e.g., surfaces, facets, and / or edges) for contacting the adjacent diffusion structures 108a, 108b and diffusion blocks 109a, 109b. Figure 3A and Figure 1AIn the embodiment, the side surface of the gate structure 116 may provide at least four facets for contacting the adjacent diffusion structures 108a, 108b and the diffusion blocks 109a, 109b. Figure 3B In the example shown, the side surfaces of the gate structure 116 may provide at least four edges for contacting the adjacent diffusion structures 108a, 108b and the diffusion blocks 109a, 109b. Figure 3C In the example shown, the side surface of the gate structure 116 may provide at least two facets and at least two edges for contacting the adjacent diffusion structures 108a, 108b and the diffusion blocks 109a, 109b. Figure 3D As shown, the side surfaces of the gate structure 116 may form circumferential surfaces for contacting the adjacent diffusion structures 108 a , 108 b and the diffusion blocks 109 a , 109 b .

[0063] refer to Figure 4A 、 Figure 4B and Figure 4C , another exemplary semiconductor device 100 ′ is shown. Figure 4A is a simplified top view showing an example configuration of an exemplary semiconductor device 100 ′. Line XX′ indicates a cutaway view. Figure 4B The section line along which the view is taken in the figure is shown, and the line Y-Y' indicates the section taken. Figure 4C The section line along which the view in follows. Figure 4A In the simplified view of FIG, the isolation region 104 and the substrate 102 are not shown, however, it should be understood that Figure 4A The configuration in is located on the isolation region 104 .

[0064] Figure 4A 、 Figure 4B and Figure 4C The structures shown are similar to Figure 1A 、 Figure 1B and Figure 1C The structure shown, but in Figure 4A 、 Figure 4B and Figure 4CIn the embodiment, the first diffusion structure 108a, the second diffusion structure 108b, the third diffusion structure 110a, the fourth diffusion structure 110b, each diffusion block 109a, 109b, 109c, 109d in the first row 130, and each diffusion block 111a, 111b, 111c, 111d in the second row 132 may include at least one doped region 134. The doped region 134 of each diffusion structure 108a, 108b and each diffusion block 109a, 109b, 109c, 109d may contact the dielectric layer of each corresponding gate 122a, 122b, 122c in the first row 130. Similarly, the doped region 134 of each diffusion structure 110 a , 110 b and each diffusion block 111 a , 111 b , 111 c , 111 d may contact the dielectric layer of each corresponding gate 122 a , 122 b , 122 c in the second row 132 .

[0065] Doped region 134 may have N-type or P-type conductivity. Exemplary dopants for N-type conductivity doping include, but are not limited to, arsenic, phosphorus, or antimony. Exemplary dopants for P-type conductivity doping include, but are not limited to, boron, aluminum, or gallium. Advantageously, doped region 134 may enable selective control of electrical signal transmission between word lines WL1, WL2, and WL3 and source lines SL1, SL2, SL3, SL4, SL5, SL6, SL7, and SL8.

[0066] Figures 5A to 9B Example structures are shown in association with steps that may be used to create a semiconductor device as described above.

[0067] As used herein, "deposition technique" refers to a process by which a material is applied to another material (or substrate). Exemplary deposition techniques include, but are not limited to, spin coating, sputtering, chemical vapor deposition (CVD), physical vapor deposition (PVD), molecular beam deposition (MBD), pulsed laser deposition (PLD), liquid source mist chemical deposition (LSMCD), and atomic layer deposition (ALD).

[0068] Furthermore, "patterning techniques" include depositing, patterning, exposing, developing, etching, cleaning, and / or removing materials or photoresists as needed to form the described patterns, structures, or openings. Examples of techniques for patterning include, but are not limited to, wet etch lithography, dry etch lithography, or direct patterning.

[0069] Figure 5A shows a top view of the device structure, Figure 5B Shows the intersection along line Y-Y' Figure 5A Reference Figure 5A and Figure 5B, which shows a device structure for forming a semiconductor device of the present disclosure. The device structure may include a substrate 102 , an isolation region 104 formed on the substrate 102 , and a dielectric region 106 formed on the isolation region 104 .

[0070] refer to Figure 6A and Figure 6B ( Figure 6A Continue Figure 5A The embodiment shown, Figure 6B Continue Figure 5B In the illustrated embodiment, the dielectric region 106 may be patterned using the patterning techniques described herein to form trench openings 124 in the dielectric region 106 .

[0071] refer to Figure 7A and Figure 7B ( Figure 7A Continue Figure 6A The embodiment shown, Figure 7B Continue Figure 6B ), a conductive material 142 may be formed in the patterned dielectric region 106. For example, a conductive material (eg, polysilicon) may be deposited to fill the trench opening 124 using the deposition techniques described herein.

[0072] refer to Figure 8A and Figure 8B ( Figure 8A Continue Figure 7A The embodiment shown, Figure 8B Continue Figure 7B In the embodiment shown, the conductive material 142 may be patterned using the patterning techniques described herein. For example, the conductive material 142 may be patterned by etching using a dry etchant. The patterning of the conductive material 142 may form a first group of diffusion blocks 109a, 109b, 109c, 109d and a second group of diffusion blocks 110a, 110b, 110c, 110d. The first and second groups of diffusion blocks may be formed along the length of the isolation region 104.

[0073] The patterning of the conductive material 142 may also form a gate opening 126 above the isolation region 104. The gate opening 126 may separate adjacent diffusion blocks. For example, a gate opening 126 may be formed between each two diffusion blocks in the first group of diffusion blocks 109a, 109b, 109c, 109d and the second group of diffusion blocks 110a, 110b, 110c, 110d.

[0074] The patterning of the conductive material 142 may also simultaneously form diffusion structures 108a, 108b, 110a, 110b extending along the length of the isolation region 104. A first set of diffusion blocks 109a, 109b, 109c, 109d may be formed between the first diffusion structure 108a and the second diffusion structure 108b, and a second set of diffusion blocks 110a, 110b, 110c, 110d may be formed between the third diffusion structure 110a and the fourth diffusion structure 110b.

[0075] To manufacture Figures 4A to 4C The device structure shown in FIG. 1 can form doped regions ( Figure 8A and Figure 8B Various doping techniques may be used to form the doped regions, such as an ion implantation process using a mask and dopants of the conductivity type described herein.

[0076] refer to Figure 9A and Figure 9B ( Figure 9A Continue Figure 8A The embodiment shown, Figure 9B Continue Figure 8B In the embodiment shown, gates 120a, 120b, 120c, 122a, 122b, 122c are formed in gate openings 126. Specifically, dielectric layers 112a, 112b, 112c, 114a, 114b, 114c can be deposited in each gate opening 126 using the deposition techniques described herein, and preferably using a conformal deposition process, such as an ALD process or a highly conformal CVD process. The dielectric layer deposited in each gate opening 126 can contact adjacent diffusion structures and diffusion blocks. For example, dielectric layer 116a contacts diffusion structures 108a, 109a and diffusion blocks 109b, 108b.

[0077] The gate structures 116a, 116b, 116c, 118a, 118b, 118c may be formed on the respective dielectric layers 112a, 112b, 112c, 114a, 114b, 114c using techniques employed in a replacement metal gate (RMG) process. Figure 9A As shown, the gate structures 116a, 116b, 116c, 118a, 118b, 118c may be surrounded at their periphery by each corresponding dielectric layer 112a, 112b, 112c, 114a, 114b, 114c. Figure 9B As shown, the dielectric layers 112a, 112b, 112c may conform to the sides and bottom of the corresponding gate structures 116a, 116b, 116c.

[0078] It should be understood that the RMG process is described at this point in the sequence as an example. The RMG process will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the present disclosure.

[0079] Thus, gates 120a, 120b, 120c and diffusion blocks 109a, 109b, 109c, 109d are formed in a first row 130, and gates 122a, 122b, 122c and diffusion blocks 111b, 111b, 111d are formed in a second row 132. In the first and second rows 130, 132, the gates and diffusion blocks can be formed along the length of the isolation region 104, and each gate can be arranged between two diffusion blocks. The first row 130 can be formed between the first and second diffusion structures 108a, 108b, and the second row 132 can be formed between the third and fourth diffusion structures 110a, 110b.

[0080] In order to form Figure 2 As shown, interconnect structures such as conductive lines and interconnect vias may be formed to connect to gates 120, 122, diffusion blocks 109, 111, and diffusion structures 108, 110. The interconnect structures may be formed using a semiconductor process such as a damascene process.

[0081] As described herein, the gate structure 116 may include metal electrodes and WFM features. Figure 10 An exemplary arrangement of metal electrodes 148 and WFM components 146 in gate structure 116 is shown. WFM components 146 may be formed on dielectric layer 112. Metal electrodes 148 may be formed on WFM components 146. Formation of metal electrodes 148 and WFM components 146 may be performed using deposition techniques described herein.

[0082] It should be understood that the following disclosure is not limited to any particular type of semiconductor device. The devices and methods disclosed herein can be applied to any type of semiconductor device architecture, such as tri-gate field effect transistor (FET) devices, fin FET (FinFET) devices, or planar metal oxide semiconductor FET (MOSFET) devices.

[0083] Throughout this disclosure, it should be understood that if a method is described herein as comprising a series of steps, the order of such steps presented herein is not necessarily the only order in which the steps may be performed, specific ones of the steps may be omitted, and / or additional specific steps not described herein may be added to the method. Furthermore, the terms "comprises," "comprising," "having," and any variations thereof are intended to cover non-exclusive inclusions, such that a process, method, article, or device that comprises a series of elements is not necessarily limited to those elements, but may include other elements not expressly listed or inherent to those processes, methods, articles, or devices. The appearances of the phrase "in an embodiment" herein do not necessarily all refer to the same embodiment.

[0084] The description of the various embodiments of the present disclosure is provided for illustrative purposes, but is not intended to be exhaustive or limited to the disclosed embodiments. Modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terms used herein are selected to best explain the principles of the embodiments, practical applications, or technical improvements to technologies found in the market, or to enable those of ordinary skill in the art to understand the embodiments disclosed herein. Furthermore, no intention is to be bound by any theory presented in the foregoing background or the following detailed description.

[0085] Furthermore, the various tasks and processes described herein may be combined into more comprehensive programs or processes having additional functionality not described in detail herein.

[0086] References herein to terms modified by approximating language, such as "about," "approximately," and "substantially," are not limited to the precise value specified. Approximate language may correspond to the precision of the instrument used to measure the value and, unless otherwise relied upon, may represent + / - 10% of the stated value.

[0087] It will be apparent to those skilled in the art after fully reading this application that the disclosed semiconductor devices and methods of forming the same can be used to manufacture a variety of different integrated circuit products, including but not limited to memory cells, NV memory devices, FinFET transistor devices, CMOS devices, etc.

Claims

1. A semiconductor device comprising: an isolation region located on the substrate; a first row of gates and diffusion blocks located on the isolation region, wherein each gate is arranged between two diffusion blocks in a row direction and includes a dielectric layer conforming to a side and a bottom of the gate structure, and wherein the dielectric layer contacts the two diffusion blocks in the first row; as well as A first diffusion structure and a second diffusion structure are located on the isolation region, the first diffusion structure and the second diffusion structure extend along the row direction, wherein the gates and diffusion blocks of the first row are arranged between the first diffusion structure and the second diffusion structure, and wherein the dielectric layer of each gate contacts the first diffusion structure and the second diffusion structure. 2 . The device of claim 1 , wherein the first diffusion structure, the second diffusion structure, and each diffusion block in the first row include at least one doped region in contact with the dielectric layer of each gate in the first row. 3 . The device of claim 1 , wherein the two diffusion blocks of the dielectric layer contacting each gate in the first row are connected to different conductive lines.

4. The device according to claim 3, further comprising: a first source line connected to the first diffusion structure; a second source line connected to a first diffusion block of the two diffusion blocks in the first row; a third source line connected to a second diffusion block of the two diffusion blocks in the first row; as well as A fourth source line is connected to the second diffusion structure.

5. The device of claim 4, wherein each gate in the first row is connected to a word line and configured to receive a voltage to control an electrical characteristic of at least one of the diffusion structure and the diffusion block in contact with the dielectric layer of each gate.

6. The device according to claim 3, further comprising: a second row of gates and diffusion blocks located on the isolation region, wherein each gate is arranged between two diffusion blocks in the row direction and includes a dielectric layer conforming to a side and a bottom of the gate structure, and wherein the dielectric layer contacts the two diffusion blocks in the second row; a third diffusion structure and a fourth diffusion structure located on the isolation region and extending along the row direction, wherein the gates and diffusion blocks of the second row are arranged between the third diffusion structure and the fourth diffusion structure, and wherein the dielectric layer of each gate in the second row contacts the third diffusion structure and the fourth diffusion structure; as well as A conductive line connects one of the gates in the first row and one of the gates in the second row.

7. The device according to claim 6, further comprising: a first source line connected to the first diffusion structure; a second source line connected to a first diffusion block of the two diffusion blocks in the first row; a third source line connected to a second diffusion block of the two diffusion blocks in the first row; a fourth source line connected to the second diffusion structure; a fifth source line connected to the third diffusion structure; a sixth source line connected to a first diffusion block of the two diffusion blocks in the second row; a seventh source line connected to a second diffusion block of the two diffusion blocks in the second row; an eighth source line connected to the fourth diffusion structure; as well as A word line is connected to one of the gates in the first row and one of the gates in the second row. 8 . The device of claim 7 , wherein the word line extends vertically across the first row and the second row.

9. A semiconductor device comprising: an isolation region located on the substrate; a gate located on the isolation region, the gate comprising a dielectric layer conforming to sides and a bottom of the gate structure; as well as Two diffusion blocks and two diffusion structures are located on the isolation region, wherein the gate is arranged between the two diffusion blocks in a row direction and between the two diffusion structures extending along the row direction, and wherein the dielectric layer contacts the diffusion structures and the diffusion blocks.

10. The device of claim 9, wherein the diffusion structure and the diffusion block are connected to different conductive lines, and the gate is configured to receive a voltage to control electrical characteristics of at least one of the diffusion structure and the diffusion block in contact with the dielectric layer of the gate. 11 . The device of claim 9 , wherein the gate is connected to a word line, and the diffusion structure and the diffusion block are connected to different source lines. 12 . The device of claim 9 , wherein the gate is connected to a source line, and the diffusion structure and the diffusion block are connected to different word lines. 13 . The device of claim 9 , wherein each diffusion structure and each diffusion block comprises at least one doped region in contact with the dielectric layer of the gate. The device according to claim 9 , wherein the gate structure is surrounded at its periphery by the dielectric layer.

15. The device of claim 14, wherein the side of the gate structure provides at least 4 facets. The device of claim 14 , wherein the side surface of the gate structure provides at least four edges.

17. The device of claim 14, wherein the side of the gate structure provides at least 2 facets and at least 2 edges. The device according to claim 14 , wherein the side surface of the gate structure forms a circumferential surface.

19. A method of forming a semiconductor device, comprising: forming an isolation region on the substrate; forming a first row of gates and diffusion blocks on the isolation region, wherein each gate is formed between two diffusion blocks in a row direction and includes a dielectric layer conforming to a side and a bottom of the gate structure, and wherein the dielectric layer contacts the two diffusion blocks in the first row; A first diffusion structure and a second diffusion structure are formed on the isolation region, wherein the first diffusion structure and the second diffusion structure extend along the row direction, wherein the gate and the diffusion block of the first row are formed between the first diffusion structure and the second diffusion structure, and the dielectric layer of each gate contacts the first diffusion structure and the second diffusion structure.

20. The method of claim 19, further comprising forming at least one doped region in the first diffusion structure, the second diffusion structure, and each diffusion block in the first row, wherein the doped region contacts the dielectric layer of each gate in the first row.

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