Ultrawideband High-Efficiency Inverse Class-F Power Amplifier Based on Elliptic Low-Pass Filter Matching Network

Abstract

This invention discloses an ultrawide, high-efficiency inverse Class-F power amplifier based on an elliptic low-pass filter matching network. The gate DC bias network provides the gate bias voltage required for the power amplifier transistor to operate; the drain DC bias network provides the drain bias voltage required for the power amplifier transistor to operate; the input impedance matching network includes a microstrip line, a DC blocking capacitor, and an RC parallel circuit; the output impedance matching network includes a harmonic control network and an elliptic low-pass filter matching network. The harmonic control network selects two frequency points outside the passband for second harmonic control; the elliptic low-pass filter matching network is based on an improved sixth-order Chebyshev low-pass filter, generating two transmission zeros outside the operating frequency band to achieve the conversion from fundamental impedance to second harmonic impedance. This invention enables the power amplifier to achieve high efficiency and high gain within a bandwidth exceeding five harmonics.

Description

Technical Field

[0001] This invention belongs to the field of wireless communication technology, and specifically relates to an ultrawide high-efficiency inverse Class-F power amplifier based on an elliptic low-pass filter matching network. Background Technology

[0002] In today's era, with the rapid development of mobile communications, we have now entered the 5G era, and all industries are placing high demands on the technological development of the communications industry. As a core module in communication systems, power amplifiers bear the heavy responsibility of technological development. In addition, the advocacy for environmental protection and energy conservation in recent years has led power amplifiers to develop towards higher efficiency, larger bandwidth, and higher gain.

[0003] However, in practice, it has been found that large bandwidths are often accompanied by reduced efficiency. Therefore, the operating bandwidth of most traditional power amplifiers does not exceed one octave. Although some research has achieved power amplifiers with large bandwidths, the slow transition of impedance between the high end of the fundamental frequency band and the low end of the second harmonic frequency band also causes a certain degree of efficiency reduction.

[0004] Therefore, in view of the shortcomings of the current technology, it is necessary to conduct further research to realize a power amplifier that can maintain high efficiency and high gain while having an operating bandwidth of more than several octaves and covering 5G commercial frequency bands. Summary of the Invention

[0005] To overcome the problems existing in the above-mentioned technologies, this invention provides an ultra-wideband, high-efficiency inverse Class-F power amplifier based on an elliptic low-pass filter matching network. Compared with existing power amplifiers of the same type, this invention expands the optimal fundamental impedance point in the traditional power amplifier design process into an impedance design space composed of a series of points, thereby greatly increasing the design range of the fundamental and harmonic impedances and thus increasing the possibility of widening the operating bandwidth.

[0006] To achieve the above objectives, this invention provides an ultrawideband, high-efficiency inverse Class-F power amplifier based on an elliptic low-pass filter matching network, comprising a gate DC bias network, a drain DC bias network, an input impedance matching network, a power amplifier transistor, and an output impedance matching network, wherein...

[0007] The gate DC bias network is used to provide the gate bias voltage required for the power amplifier transistor to operate;

[0008] The drain DC bias network is used to provide the drain bias voltage required for the power amplifier transistor to operate;

[0009] The input impedance matching network includes a microstrip line, a DC blocking capacitor, and an RC parallel circuit.

[0010] The output impedance matching network includes a harmonic control network and an elliptic low-pass filter matching network. The harmonic control network selects two frequency points outside the passband for second harmonic control. The elliptic low-pass filter matching network is based on an improved sixth-order Chebyshev low-pass filter, which generates two transmission zeros outside the operating frequency band to realize the conversion from fundamental impedance to second harmonic impedance.

[0011] Preferably, the gate DC bias network includes a microstrip line TL8 and a first decoupling capacitor, wherein one end of the microstrip line TL8 is connected to the input impedance matching network, the other end of the microstrip line TL8 is connected to one end of the first decoupling capacitor, and the other end of the first decoupling capacitor is grounded.

[0012] Preferably, the input impedance matching network includes microstrip lines T1, T2, T3, T4, T6, T7, T9, a DC blocking capacitor C1, and an RC parallel circuit. One end of microstrip line TL1 serves as the signal input port. The other end of microstrip line TL1 is connected to one end of the DC blocking capacitor C1. The other end of the DC blocking capacitor C1 is connected to one end of microstrip line TL2. The other end of microstrip line TL2 is connected to one end of microstrip lines TL3 and TL4. The other end of microstrip line TL3 remains open. The other end of microstrip line TL4 is connected to one end of microstrip lines TL5 and TL6. The other end of microstrip line TL5 remains open. The other end of microstrip line TL6 is connected to one end of the RC parallel circuit. The other end of the RC parallel circuit is connected to one end of microstrip lines TL7 and TL9. The other end of microstrip line TL7 remains open. The other end of microstrip line TL9 is connected to the gate of the power amplifier transistor. The input signal enters the gate of the power amplifier transistor through the aforementioned input impedance matching network.

[0013] Preferably, the drain DC bias network includes microstrip lines T11 and T12 and a second decoupling capacitor, wherein one end of microstrip line T11 is connected to the harmonic control network and is connected in parallel in the harmonic control network, the other end of microstrip line T11 is connected to one end of microstrip line T12, and the other end of microstrip line T12 is connected to the second decoupling capacitor.

[0014] Preferably, the harmonic control network includes microstrip lines TL10, TL13, TL14 and TL15, wherein one end of microstrip line TL10 is connected to the drain of the power amplifier transistor as the input terminal of the output impedance matching network, the other end of TL10 is connected to one end of microstrip line TL13, the other end of microstrip line TL13 is connected to one end of microstrip lines TL14 and TL15, and the other ends of microstrip lines TL14 and TL15 are kept open.

[0015] Preferably, the elliptic low-pass filter matching network includes microstrip lines TL16, TL17, TL18, TL19, TL20, TL21, TL22, TL23, TL24 and a DC blocking capacitor C3. One end of microstrip line TL16 serves as the input of the elliptic low-pass filter matching network and is connected to the output of the harmonic control network. The other end of microstrip line TL16 is connected to one end of microstrip lines TL17 and TL19, and the other end of microstrip line TL17 is connected to one end of microstrip line TL18. The other end of the microstrip line TL18 is kept open. The other end of the microstrip line TL19 is connected to one end of the microstrip lines TL20 and TL22. The other end of the microstrip line TL20 is connected to one end of the microstrip line TL21. The other end of the microstrip line TL21 is kept open. The other end of the microstrip line TL22 is connected to one end of the microstrip line TL23. The other end of the microstrip line TL23 is connected to one end of the DC blocking capacitor C3. The other end of the DC blocking capacitor C3 is connected to the microstrip line TL24 with a characteristic impedance of 50 ohms. The signal is output from here.

[0016] Preferably, the power amplifier transistor is a GaN HEMT CGH40010F transistor.

[0017] The beneficial effects of this invention include at least the following: By expanding the optimal fundamental impedance point in the traditional power amplifier design process into an impedance design space composed of a series of points, this invention significantly increases the design range of the fundamental and harmonic impedances, thereby increasing the possibility of broadening the operating bandwidth. The operating bandwidth of this invention is 0.7-3.7GHz (136%), covering the 3.3-3.6GHz 5G commercial frequency band, with a drain efficiency between 60.7-73.4%, a saturated output power greater than 41dBm, and a gain between 11-12.7dB, demonstrating excellent performance indicators. Attached Figure Description

[0018] To make the objectives, technical solutions, and beneficial effects of this invention clearer, the following figures are provided for illustration:

[0019] Figure 1 This is a schematic diagram of the structure of an ultrawide high-efficiency inverse Class-F power amplifier based on an elliptic low-pass filter matching network according to an embodiment of the present invention;

[0020] Figure 2 This is a topology diagram of the gate DC bias network and the input impedance matching network in an ultrawide high-efficiency inverse Class F power amplifier based on an elliptic low-pass filter matching network according to an embodiment of the present invention.

[0021] Figure 3 This is a topology diagram of the drain DC bias network and the output impedance matching network in an ultrawide high-efficiency inverse Class F power amplifier based on an elliptic low-pass filter matching network according to an embodiment of the present invention.

[0022] Figure 4 This is a modular schematic diagram of the output impedance matching network in an ultrawide high-efficiency inverse Class F power amplifier based on an elliptic low-pass filter matching network according to an embodiment of the present invention.

[0023] Figure 5 This invention relates to the sixth-order Chebyshev low-pass filter and the improved elliptic low-pass filter based on the elliptic low-pass filter matching network in the ultrawide high-efficiency inverse Class-F power amplifier.

[0024] Figure 6 This is the impedance design space of the ultrawide high-efficiency inverse Class-F power amplifier based on an elliptic low-pass filter matching network in this embodiment of the invention.

[0025] Figure 7 This is a schematic diagram of the impedance trajectory simulation results of the output impedance matching network of the ultrawide high-efficiency inverse Class F power amplifier based on an elliptic low-pass filter matching network according to an embodiment of the present invention.

[0026] Figure 8 This is the overall circuit diagram of the ultrawide high-efficiency inverse Class-F power amplifier based on an elliptic low-pass filter matching network according to an embodiment of the present invention.

[0027] Figure 9 The output power, drain efficiency, and gain simulation results of the ultrawide high-efficiency inverse Class F power amplifier based on an elliptic low-pass filter matching network according to an embodiment of the present invention are obtained through simulation and physical measurement. Detailed Implementation

[0028] The preferred embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0029] See Figure 1 The diagram shows a schematic of an ultrawideband, high-efficiency inverse Class-F power amplifier based on an elliptic low-pass filter matching network according to an embodiment of the present invention. It includes a gate DC bias network 10, a drain DC bias network 20, an input impedance matching network 30, a power amplifier transistor 40, and an output impedance matching network 50. The gate DC bias network 10 provides the gate bias voltage required for the power amplifier transistor 40 to operate; the drain DC bias network 20 provides the drain bias voltage required for the power amplifier transistor 40 to operate; the input impedance matching network 30 includes a microstrip line, a DC blocking capacitor, and an RC parallel circuit; the output impedance matching network 50 includes a harmonic control network 51 and an elliptic low-pass filter matching network 52. The harmonic control network 51 selects two frequency points outside the passband for second harmonic control; the elliptic low-pass filter matching network 52 is an improvement on a sixth-order Chebyshev low-pass filter, generating two transmission zeros outside the operating frequency band to achieve the conversion from fundamental impedance to second harmonic impedance.

[0030] See Figure 2 The diagram shows the topology of the gate DC bias network 10 and the input impedance matching network 30 in this invention. The gate DC bias network 10 includes a microstrip line TL8 and a first decoupling capacitor C. bypass One end of the microstrip line TL8 is connected to the input impedance matching network 30, and the other end of the microstrip line TL8 is connected to the first decoupling capacitor C. bypass One end is connected to the C of the first decoupling capacitor. bypass The other end is grounded.

[0031] The input signal enters the gate of the power amplifier transistor 40 through the input impedance matching network 30. Furthermore, the 50-ohm input impedance is matched to the optimal source impedance of the power amplifier transistor 40 gate through the input impedance matching network 30, thereby improving the overall circuit efficiency. The input impedance matching network 30 consists of microstrip lines TL1, TL2, TL3, TL4, TL5, TL6, TL7, TL9 and a DC blocking capacitor C1. One end of microstrip line TL1 serves as the signal input port. The other end of microstrip line TL1 is connected to one end of DC blocking capacitor C1. The other end of DC blocking capacitor C1 is connected to one end of microstrip line TL2. The other end of microstrip line TL2 is connected to one end of microstrip lines TL3 and TL4. The other end of microstrip line TL3 remains open. The other end of microstrip line TL4 is connected to one end of microstrip lines TL5 and TL6. The other end of microstrip line TL5 remains open. The other end of microstrip line TL6 is connected to one end of an RC parallel circuit. The other end of the RC parallel circuit is connected to one end of microstrip lines TL7 and TL9. The other end of microstrip line TL7 remains open. The other end of microstrip line TL9 is connected to the gate of power amplifier transistor 40. The input signal enters the gate of power amplifier transistor 40 through the aforementioned input impedance matching network 30. Furthermore, the input impedance is matched to the optimal source impedance of the power amplifier transistor gate through the input impedance matching network 30, thereby improving the overall circuit performance.

[0032] See Figure 3 The diagram shows the topology of the drain DC bias network 20 and the output impedance matching network 50 in this invention. The drain DC bias network 20 includes microstrip lines T11 and T12 and a second decoupling capacitor C. bypass One end of microstrip line T11 is connected to harmonic control network 51 and is connected in parallel within harmonic control network 51. The other end of microstrip line T11 is connected to one end of microstrip line T12, and the other end of microstrip line T12 is connected to the second decoupling capacitor C. bypass connect.

[0033] The harmonic control network 51 includes microstrip lines TL10, TL13, TL14 and TL15. One end of microstrip line TL10 is connected to the drain of power amplifier transistor 40 as the input terminal of the output impedance matching network 50. The other end of TL10 is connected to one end of microstrip line TL13. The other end of microstrip line TL13 is connected to one end of microstrip lines TL14 and TL15. The other ends of microstrip lines TL14 and TL15 are kept open.

[0034] The elliptic low-pass filter matching network 52 includes microstrip lines TL16, TL17, TL18, TL19, TL20, TL21, TL22, TL23, TL24 and a DC blocking capacitor C3. One end of microstrip line TL16 serves as the input of the elliptic low-pass filter matching network 52 and is connected to the output of the harmonic control network 51. The other end of microstrip line TL16 is connected to one end of microstrip lines TL17 and TL19, and the other end of microstrip line TL17 is connected to one end of microstrip line TL18. The other end of the microstrip line TL18 is kept open. The other end of the microstrip line TL19 is connected to one end of the microstrip lines TL20 and TL22. The other end of the microstrip line TL20 is connected to one end of the microstrip line TL21. The other end of the microstrip line TL21 is kept open. The other end of the microstrip line TL22 is connected to one end of the microstrip line TL23. The other end of the microstrip line TL23 is connected to one end of the DC blocking capacitor C3. The other end of the DC blocking capacitor C3 is connected to the microstrip line TL24 with a characteristic impedance of 50 ohms. The signal is output from here.

[0035] See Figure 4 The diagram shows a modular schematic of the output impedance matching network 50 in this invention, which consists of a harmonic control network 51 and an elliptic low-pass filter matching network 52. The harmonic control network 51 consists of microstrip lines TL10, TL13, TL14, and TL15. One end of TL10 serves as the input terminal of the output impedance matching network 50 and is connected to the drain of the power amplifier transistor 40. The other end of TL10 is connected to one end of microstrip line TL13, and the other end of microstrip line TL13 is connected to one end of microstrip lines TL14 and TL15. The other ends of microstrip lines TL14 and TL15 remain open. The electrical lengths of microstrip lines TL14 and TL15 are λ / 4, and they suppress signals at two selected second harmonic frequencies. The input impedance Z of the harmonic control network 51 is... OMN The calculation formula is:

[0036]

[0037]

[0038] Z 10 Z 13 Z 14 and Z15 The characteristic impedances of microstrip lines TL10, TL13, TL14, and TL15 are θ, respectively. 10 θ 13 θ 14 and θ 15 These are the electrical lengths of microstrip lines TL10, TL13, TL14, and TL15, respectively, while Z... LPR Let Z be the input impedance of the elliptic low-pass filter matching network 52, and its value is equal to the real part of the optimal fundamental impedance. The optimal load impedance Z can be determined through load pulling. OMN The value is 23 + j * 10.6 ohms.

[0039] In addition, the design steps of the elliptic low-pass filter matching network 52 are as follows: First, design the network according to the required impedance transformation ratio, such as... Figure 5 The sixth-order Chebyshev low-pass filter shown converts capacitors C1 and C2 into a series circuit of capacitor and inductor, thereby generating two transmission zeros near the operating frequency band. The formulas for calculating the converted capacitors C4 and C5 and inductors L7 and L8 are shown below:

[0040]

[0041]

[0042]

[0043]

[0044] Where f TZ1 and f TZ2 The frequency points corresponding to the two selected transmission zeros, f H This is the cutoff frequency. We now have an improved elliptic low-pass filter matching network 52. This network not only provides a rapid impedance transition from the high end of the fundamental frequency band to the low end of the second harmonic band, but also transforms a 50-ohm load impedance to the real part of the optimal fundamental impedance. Finally, we replace the capacitor and inductor with a microstrip line. The characteristic impedance and electrical length of the microstrip line can be calculated using the following formula:

[0045]

[0046]

[0047] Among them l L and l C Z represents the length of the microstrip line replacing the inductor and capacitor, respectively. L and Z C Let β and v represent the characteristic impedances of the microstrip lines replacing the inductor and capacitor, respectively. pLet L and C represent the propagation constant and phase velocity of the microstrip line, respectively, and L and C represent the inductance and capacitance values ​​of the replacement lines, respectively.

[0048] See Figure 6 The diagram shows the impedance design space of the power amplifier according to this invention. This invention expands the impedance design space by introducing more free design factors into the voltage and current waveform expressions, as shown below:

[0049]

[0050]

[0051] Where v DC i represents the drain bias voltage of the power amplifier. MAX This represents the maximum drain current of the transistor. A, B, δ, and γ are introduced free design factors. The expressions for the fundamental, second harmonic, and third harmonic admittances can be obtained from the extended voltage and current waveform expressions:

[0052]

[0053] Y2=δ(AB)+jγ(δ-AB) (12)

[0054] Y3=∞ (13)

[0055] See Figure 7 The figure shows a schematic diagram of the impedance trajectory simulation results of the output impedance matching network 50 of the present invention. It can be seen from the figure that the simulation results are consistent with... Figure 6 The demonstrated impedance theory design space is consistent with the expected goals.

[0056] See Figure 8 This is the overall circuit diagram of an ultra-wideband high-efficiency inverse Class-F power amplifier of the present invention, and... Figure 2 and Figure 3 The positions and connections of the microstrip lines, capacitors, and resistors are shown in the diagram, and will not be repeated here.

[0057] See Figure 9 The figure shows the simulation and measurement results of the drain efficiency, output power, and gain of an ultra-wideband high-efficiency inverse Class-F power amplifier based on an elliptic low-pass filter matching network 52 according to the present invention. The results show that the designed power amplifier has an operating bandwidth of 0.7-3.7GHz (136%), covering the 5G commercial frequency band of 3.3-3.6GHz, a drain efficiency between 60.7-73.4%, a saturated output power greater than 41dBm, and a gain between 11-12.7dB, demonstrating excellent performance indicators.

[0058] Finally, it should be noted that the above preferred embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail through the above preferred embodiments, those skilled in the art should understand that various changes can be made to it in form and detail without departing from the scope defined by the claims of the present invention.

Claims

1. An ultrawide high-efficiency inverse Class-F power amplifier based on an elliptic low-pass filter matching network, characterized in that, This includes a gate DC bias network, a drain DC bias network, an input impedance matching network, a power amplifier transistor, and an output impedance matching network. The gate DC bias network is used to provide the gate bias voltage required for the power amplifier transistor to operate; The drain DC bias network is used to provide the drain bias voltage required for the power amplifier transistor to operate; The input impedance matching network includes a microstrip line, a DC blocking capacitor, and an RC parallel circuit. The output impedance matching network includes a harmonic control network and an elliptic low-pass filter matching network. The harmonic control network selects two frequency points outside the passband for second harmonic control. The elliptic low-pass filter matching network is based on an improved sixth-order Chebyshev low-pass filter, which generates two transmission zeros outside the operating frequency band to realize the conversion from fundamental impedance to second harmonic impedance. The harmonic control network includes microstrip lines TL10, TL13, TL14 and TL15. One end of microstrip line TL10 is connected to the drain of the power amplifier transistor as the input terminal of the output impedance matching network. The other end of TL10 is connected to one end of microstrip line TL13. The other end of microstrip line TL13 is connected to one end of microstrip lines TL14 and TL15. The other ends of microstrip lines TL14 and TL15 are kept open. The elliptic low-pass filter matching network includes microstrip lines TL16, TL17, TL18, TL19, TL20, TL21, TL22, TL23, TL24 and a DC blocking capacitor C3. One end of microstrip line TL16 serves as the input of the elliptic low-pass filter matching network and is connected to the output of the harmonic control network. The other end of microstrip line TL16 is connected to one end of microstrip lines TL17 and TL19, and the other end of microstrip line TL17 is connected to one end of microstrip line TL18. The other end of TL18 remains open. The other end of microstrip line TL19 is connected to one end of microstrip lines TL20 and TL22. The other end of microstrip line TL20 is connected to one end of microstrip line TL21. The other end of microstrip line TL21 remains open. The other end of microstrip line TL22 is connected to one end of microstrip line TL23. The other end of microstrip line TL23 is connected to one end of DC blocking capacitor C3. The other end of DC blocking capacitor C3 is connected to microstrip line TL24 with a characteristic impedance of 50 ohms. The signal is output from here. The power amplifier transistor is a GaN HEMT CGH40010F transistor.

2. The ultrawide high-efficiency inverse Class-F power amplifier based on an elliptic low-pass filter matching network according to claim 1, characterized in that, The gate DC bias network includes a microstrip line TL8 and a first decoupling capacitor. One end of the microstrip line TL8 is connected to the input impedance matching network, and the other end of the microstrip line TL8 is connected to one end of the first decoupling capacitor, which is grounded.

3. The ultrawide high-efficiency inverse Class-F power amplifier based on an elliptic low-pass filter matching network according to claim 2, characterized in that, The input impedance matching network includes microstrip lines T1, T2, T3, T4, T6, T7, T9, a DC blocking capacitor C1, and an RC parallel circuit. One end of microstrip line TL1 serves as the signal input port. The other end of microstrip line TL1 is connected to one end of the DC blocking capacitor C1. The other end of the DC blocking capacitor C1 is connected to one end of microstrip line TL2. The other end of microstrip line TL2 is connected to one end of microstrip lines TL3 and TL4. The other end of microstrip line TL3 remains open. The other end of microstrip line TL4 is connected to one end of microstrip lines TL5 and TL6. The other end of microstrip line TL5 remains open. The other end of microstrip line TL6 is connected to one end of the RC parallel circuit. The other end of the RC parallel circuit is connected to one end of microstrip lines TL7 and TL9. The other end of microstrip line TL7 remains open. The other end of microstrip line TL9 is connected to the gate of the power amplifier transistor. The input signal enters the gate of the power amplifier transistor through the aforementioned input impedance matching network.

4. The ultrawide high-efficiency inverse Class-F power amplifier based on an elliptic low-pass filter matching network according to claim 3, characterized in that, The drain DC bias network includes microstrip lines T11 and T12 and a second decoupling capacitor. One end of microstrip line T11 is connected to the harmonic control network and is connected in parallel in the harmonic control network. The other end of microstrip line T11 is connected to one end of microstrip line T12, and the other end of microstrip line T12 is connected to the second decoupling capacitor.

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