Display substrate, preparation method thereof and display panel

Abstract

A display substrate, a manufacturing method thereof and a display panel. The display substrate comprises a substrate (1), a pixel definition layer (2) arranged on the substrate (1), and a display area (101), a non-display area (102) and a light transmission area (103), wherein the display area (101) and the non-display area (102) at least partially surround the light transmission area (103); the pixel definition layer (2) extends from the display area (101) to the non-display area (102); the pixel definition layer (2) is provided with a first opening (21), the first opening (21) comprises a plurality of first sub-openings (211) and a plurality of second sub-openings (212); the plurality of first sub-openings (211) are distributed in the display area (101), and the plurality of second sub-openings (212) are distributed in the non-display area (102); and the second sub-opening (212) is closer to the light transmission area (103) than the first sub-opening (211).

Description

Technical Field

[0001] This disclosure pertains to the field of display technology, specifically relating to a display substrate, its fabrication method, and a display panel. Background Technology

[0002] OLED display panels, manufactured using Organic Light-Emitting Display (OLED) technology, have become the mainstream development direction in the display technology field due to their advantages such as self-illumination, high brightness, good image quality, and low energy consumption. This emerging technology allows for more design possibilities to meet people's needs, and punch-hole technology in the display area is one such direction in current screen development. Summary of the Invention

[0003] This disclosure provides a display substrate, a method for fabricating the same, and a display panel.

[0004] In a first aspect, embodiments of this disclosure provide a display substrate, comprising:

[0005] substrate;

[0006] A pixel defining layer disposed on the substrate;

[0007] The display substrate further includes a display area, a non-display area, and a light-transmitting area, wherein the display area and the non-display area at least partially surround the light-transmitting area;

[0008] The pixel-defining layer extends from the display area to the non-display area;

[0009] The pixel defining layer has a first opening, which includes a plurality of first sub-openings and a plurality of second sub-openings; the plurality of first sub-openings are distributed in the display area, and the plurality of second sub-openings are distributed in the non-display area; and the second sub-openings are closer to the light-transmitting area than the first sub-openings.

[0010] In some embodiments, a first electrode layer and a light-emitting functional layer are disposed in the first sub-opening;

[0011] The substrate includes a pixel circuit, the pixel circuit includes a driving transistor, and the driving transistor is electrically connected to the first electrode layer.

[0012] The first electrode layer and the light-emitting functional layer are stacked in a direction away from the substrate;

[0013] The light-emitting functional layer is provided in the second sub-opening;

[0014] The display substrate further includes a second electrode layer, which is disposed on the side of the pixel defining layer opposite to the substrate, and the second electrode layer covers the first sub-opening and the second sub-opening;

[0015] The orthographic projection of the driving transistor on the substrate does not overlap with the orthographic projection of the second sub-opening on the substrate.

[0016] In some embodiments, the display substrate further includes signal lines disposed on the side of the pixel defining layer near the substrate, the signal lines extending from the display area to the non-display area, and the signal lines including arc portions in the non-display area;

[0017] The arc portion is at least partially disposed around the light-transmitting area, and the arc portion at least partially overlaps with the orthographic projection of the second sub-opening on the substrate.

[0018] In some embodiments, the signal line includes a data line.

[0019] In some embodiments, along the radial direction of the light-transmitting area, the width of the distribution area of ​​the second sub-opening ranges from 2 to 8 times the radial width of the second sub-opening.

[0020] In some embodiments, the display substrate further includes a dike located in the non-display area and at least partially surrounding the light-transmitting area;

[0021] The cofferdam surrounds the edge of the light-transmitting area, and the second sub-openings are distributed around the cofferdam on the side of the cofferdam away from the light-transmitting area;

[0022] The shortest interval between the cofferdam and the distribution area of ​​the second sub-opening is greater than 0 and less than 300 micrometers.

[0023] In some embodiments, a touch film layer is further included, the touch film layer being disposed on the side of the second electrode layer opposite to the substrate;

[0024] The touch film layer includes touch electrodes; the touch electrodes are in a grid shape; the pixel defining layer is in a grid shape; the orthographic projection of the touch electrodes on the substrate and the orthographic projection area of ​​the pixel defining layer on the substrate at least partially overlap.

[0025] In some embodiments, the orthographic projection of the touch electrode on the substrate and the orthographic projection of the pixel defining layer between the second sub-opening on the substrate at least partially overlap.

[0026] In some embodiments, the size difference between the first sub-opening and the second sub-opening is less than a set threshold.

[0027] In some embodiments, the second sub-opening includes a first-shaped opening, a second-shaped opening, and a third-shaped opening;

[0028] The first shaped opening, the second shaped opening, and the third shaped opening have different shapes and sizes;

[0029] Two first-shaped openings, one second-shaped opening, and one third-shaped opening constitute an opening cycle; multiple opening cycles are distributed within the non-display area.

[0030] In some embodiments, during the opening period, the spacing between two first-shaped openings ranges from 6 to 27 μm;

[0031] The distance between the first shaped opening and the second shaped opening is in the range of 15–30 μm;

[0032] The distance between the second shaped opening and the third shaped opening is in the range of 15 to 30 μm;

[0033] The distance between the first shaped opening and the third shaped opening is in the range of 50 to 80 μm.

[0034] In some embodiments, the distance between the first shaped opening and the third shaped opening is 1.5 to 2.5 times the distance between the first shaped opening and the second shaped opening;

[0035] The distance between the first shaped opening and the second shaped opening is 0.8 to 1.2 times the distance between the second shaped opening and the third shaped opening;

[0036] The spacing between the two first-shaped openings is 0.6 to 1 times the spacing between the first-shaped opening and the second-shaped opening.

[0037] In some embodiments, the first sub-opening and the second sub-opening have the same uniformity of arrangement.

[0038] In some embodiments, the display area surrounds the periphery of the non-display area;

[0039] Alternatively, the non-display area may be located in a corner of the display area;

[0040] Alternatively, the non-display area may be located at one edge of the display area.

[0041] In some embodiments, a planarization layer is further included, the planarization layer being disposed on the side of the pixel defining layer near the substrate;

[0042] The substrate further includes a base, the pixel circuit is disposed on the base, and a via is formed in the planarization layer. The first electrode layer is connected to the driving transistor in the pixel circuit through the via.

[0043] Secondly, embodiments of this disclosure also provide a display panel, including the aforementioned display substrate.

[0044] Thirdly, embodiments of this disclosure also provide a method for preparing a display substrate, comprising:

[0045] Preparing a substrate;

[0046] A pixel defining layer is fabricated on the substrate;

[0047] The display substrate further includes a display area, a non-display area, and a light-transmitting area, wherein the display area and the non-display area at least partially surround the light-transmitting area; the pixel defining layer extends from the display area to the non-display area.

[0048] Preparing the pixel-defining layer includes: forming a pattern of the pixel-defining layer and opening a first opening in the pixel-defining layer;

[0049] The first opening includes a plurality of first sub-openings and a plurality of second sub-openings; the plurality of first sub-openings are distributed in the display area, and the plurality of second sub-openings are distributed in the non-display area; and the second sub-openings are closer to the light-transmitting area than the first sub-openings.

[0050] In some embodiments, the pattern of the pixel-defining layer and the pattern of the first opening are formed through a single patterning process. Attached Figure Description

[0051] The accompanying drawings are provided to further illustrate the embodiments of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the disclosure and do not constitute a limitation thereof. The above and other features and advantages will become more apparent to those skilled in the art from the detailed description of exemplary embodiments with reference to the accompanying drawings, in which:

[0052] Figure 1 This is a partial cross-sectional view of an opening in the pixel-defining layer within the display area of ​​an OLED display panel in the disclosed technology.

[0053] Figure 2 This is a top view of the structure of the OLED screen display area with perforations in the publicly disclosed technology;

[0054] Figure 3 A top view of the structure for setting the touch electrode pattern when drilling holes in the display area of ​​an OLED screen in the disclosed technology;

[0055] Figure 4A top view of the structure in the publicly disclosed technology where the touch electrode pattern extends outward from the display area when a hole is punched in the display area of ​​an OLED screen;

[0056] Figure 5 This is a top view of the display substrate structure in an embodiment of this disclosure;

[0057] Figure 6 for Figure 5 Cross-sectional view of the display substrate along section line AA;

[0058] Figure 7 This is a partial structural cross-sectional view of the display area of ​​the display substrate in an embodiment of this disclosure;

[0059] Figure 8 This is a partial cross-sectional view of the display substrate from the display area to the non-display area in an embodiment of this disclosure;

[0060] Figure 9 This is a top view schematic diagram of the structure of the arc portion of the signal line in the substrate according to an embodiment of the present disclosure;

[0061] Figure 10 for Figure 5 A top-view enlarged schematic diagram of the structure of part C of the display substrate;

[0062] Figure 11 This is a schematic cross-sectional view of the structure of the isolation pillars in the display substrate according to an embodiment of the present disclosure;

[0063] Figure 12 This is a top view of the display substrate with a touch film layer provided in this embodiment of the present disclosure;

[0064] Figure 13 for Figure 7 Cross-sectional view of the display substrate along the BB section line;

[0065] Figure 14 This is a schematic diagram illustrating another distribution of the display area and non-display area on the display substrate in an embodiment of this disclosure;

[0066] Figure 15 This is another schematic diagram showing the distribution of the display area and non-display area on the display substrate in an embodiment of this disclosure;

[0067] Figure 16 This is another schematic diagram showing the distribution of the display area and non-display area on the display substrate in an embodiment of this disclosure;

[0068] Figure 17 This is a top view of the structure of the second sub-opening in the non-display area of ​​the display substrate according to another embodiment of the present disclosure;

[0069] Figure 18 for Figure 5 A top-view enlarged schematic diagram of another structure of part C of the display substrate.

[0070] The attached figures are labeled as follows:

[0071] 1. Substrate; 11. Base; 12. Pixel circuit; 2. Pixel limiting layer; 21. First opening; 211. First sub-opening; 212. Second sub-opening; 23. First groove; 24. Dike; 101. Display area; 102. Non-display area; 103. Light-transmitting area; 100. Boundary; 3. First electrode layer; 4. Light-emitting functional layer; 5. Second electrode layer; 6. Touch film layer; 61. Insulating layer; 611. First inorganic encapsulation layer; 612. Organic encapsulation layer; 613. Second inorganic encapsulation layer; 614. Inorganic buffer layer; 62. Touch electrode; 620. Bridge structure; 621. First insulating layer; 622. Touch electrode pattern; 7. Planarization layer 70. Via; 71. First planarization layer; 72. Second planarization layer; 8. Hole; 9. Sub-pixel aperture; 10. Touch electrode pattern; 13. Groove; 14. Opening; 15. Signal line; 150. Data line; 151. Scan line; 16. Isolation pillar; 17. Buffer layer; 18. Active layer; 19. First gate insulating layer; 20. Gate; 25. First scan line; 26. Second gate insulating layer; 27. Second scan line; 28. Intermediate dielectric layer; 29. ​​Source; 30. Drain; 31. Passivation layer; 32. Conductive layer; 33. Support layer; 34. First shaped opening; 35. Second shaped opening; 36. Third shaped opening; 37. Opening period. Detailed Implementation

[0072] To enable those skilled in the art to better understand the technical solutions of the embodiments of this disclosure, the following describes in further detail a display substrate, its preparation method, and a display panel provided by the embodiments of this disclosure, in conjunction with the accompanying drawings and specific implementation methods.

[0073] Embodiments of this disclosure will be described more fully below with reference to the accompanying drawings; however, the embodiments shown may be embodied in different forms and should not be construed as limited to the embodiments set forth in this disclosure. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will enable those skilled in the art to fully understand the scope of this disclosure.

[0074] This disclosure is not limited to the embodiments shown in the accompanying drawings, but includes modifications to the configuration based on the manufacturing process. Therefore, the areas illustrated in the drawings are schematic, and the shapes of the areas shown illustrate specific shapes of the areas, but are not intended to be limiting.

[0075] Organic Light-Emitting Display (OLED) technology has made OLED display panels the mainstream development direction in the field of display technology due to their advantages such as self-illumination, high brightness, good image quality, and low energy consumption.

[0076] The openings defined by the pixel confinement layer in an OLED display panel serve to define the deposition area for each sub-pixel. Simultaneously, the pixel confinement layer acts as a planarizer, preparing for the deposition of subsequent film layers. Typically, an opening is created in the pixel confinement layer of the display area of ​​the OLED display panel. The subsequently deposited red, green, and blue sub-pixel luminescent materials are formed on the anode at the opening. The anode and cathode located on the upper and lower sides of the luminescent material layer respectively provide electrons and holes for recombination and light emission within the luminescent material layer. The cross-section of the opening 14 in the pixel confinement layer 2 within the display area is shown below. Figure 1 As shown, the layers below the pixel limiting layer 2 are the various film layers of the OLED display panel backplane.

[0077] This newly developing OLED display technology allows for more design possibilities to meet people's needs. One such technology is the punch-hole display area, which is a current trend in screen development. Punch-hole displays are used to house under-display detection devices such as cameras. Figure 2 As shown, one problem with this screen display area 101 punch-hole technology is that, since the sub-pixel opening 9 is only opened in the pixel limiting layer 2 of the display area 101, the size of the sub-pixel opening 9 at the junction of the non-display area 102 and the display area 101 where the punch-hole 8 is located is uneven, affecting the screen display effect. For screens with integrated touch film layers, another problem with this screen display area punch-hole technology is that the integrity of the touch electrode pattern 10 at the punch-hole 8 location cannot be guaranteed. Figure 3 As shown, the four touch electrode patterns 10 around the punch hole 8 are clearly incomplete. To improve the integrity of the touch electrode patterns 10 around the punch hole 8, as follows: Figure 4As shown, one solution is to extend the boundary of the touch electrode pattern 10 beyond the punch hole 8 area at the junction 100 of the display area 101 and the non-display area 102. This requires the underlying film layer of the touch electrode traces in the punch hole 8 area to be relatively flat to avoid defects in the touch electrode traces. However, in order to form the encapsulation dam 24 in the punch hole 8 area, a groove 13 needs to be cut in the pixel limiting layer (and the flat layer below the pixel limiting layer) in the punch hole 8 area. This groove 13 makes the pixel limiting layer uneven. To ensure good touch electrode traces, the groove 13 in the pixel limiting layer (and the flat layer below the pixel limiting layer) should be as far away from the display area 101 as possible to ensure that the touch electrode traces are not above the groove 13 in the pixel limiting layer. When the notch in the pixel-defining layer is far from the display area, the pixel-defining layer area between the notch and the display area boundary is relatively large. Since gases are released from the internal film layers during and after the display panel manufacturing process, the large pixel-defining layer area between the notch and the display area boundary can prevent the released gases from the notch opening of the pixel-defining layer from being released in time. As a result, the released gases can push open some of the internal film layers, forming small gaps or cavities. This can cause the film layers to easily absorb moisture during the production process, resulting in defects.

[0078] To address the series of problems caused by the aforementioned screen display area punching technology, this disclosure provides a display substrate, its preparation method, and a display panel.

[0079] This disclosure provides a display substrate, such as... Figure 5 and Figure 6 As shown, the display includes: a substrate 1; a pixel defining layer 2 disposed on the substrate 1; the display substrate further includes a display area 101, a non-display area 102 and a light-transmitting area 103, the display area 101 and the non-display area 102 at least partially surrounding the light-transmitting area 103; the pixel defining layer 2 extends from the display area 101 to the non-display area 102; a first opening 21 is formed in the pixel defining layer 2, the first opening 21 includes a plurality of first sub-openings 211 and a plurality of second sub-openings 212; the plurality of first sub-openings 211 are distributed in the display area 101, the plurality of second sub-openings 212 are distributed in the non-display area 102; and the second sub-openings 212 are closer to the light-transmitting area 103 than the first sub-openings 211.

[0080] The first sub-opening 211 in the display area 101 is used to house sub-pixels. The light-transmitting area 103 corresponds to an opening in the display substrate, which is used to house under-display detection devices, such as cameras and fingerprint sensors. The positional relationship between the display area 101 and the non-display area 102 can be: the display area 101 surrounds the periphery of the non-display area 102; or, the non-display area 102 is located at a corner of the display area 101; or, the non-display area 102 is located at one edge of the display area 101, etc.

[0081] The display substrate has a first opening in the pixel limiting layer 2, and multiple first sub-openings 211 are distributed in the display area 101, while multiple second sub-openings 212 are distributed in the non-display area 102. The second sub-openings 212 are closer to the light-transmitting area 103 than the first sub-openings 211. Compared with the disclosed technology where sub-pixel openings are only opened in the pixel limiting layer of the display area, this embodiment opens multiple second sub-openings 212 in the portion of the pixel limiting layer 2 extending into the non-display area 102. This allows the openings in the pixel limiting layer 2 to extend to the area at the boundary 100 between the non-display area 102 and the display area 101, thereby ensuring that the size of the first sub-openings 211 at the boundary 100 between the display area 101 and the non-display area 102 is uniform, that is, the size of the first sub-openings 211 at the boundary 100 is the same as the size of the first sub-openings 211 in the display area 101, thus ensuring the display effect of the display substrate.

[0082] In some embodiments, a first electrode layer 3 and a light-emitting functional layer 4 are disposed in the first sub-opening 211; the substrate 1 includes a pixel circuit 12, the pixel circuit 12 includes a driving transistor, the driving transistor is electrically connected to the first electrode layer 3; the first electrode layer 3 and the light-emitting functional layer 4 are stacked in a direction away from the substrate 1; the light-emitting functional layer 4 is disposed in the second sub-opening 212; the display substrate further includes a second electrode layer 5, the second electrode layer 5 is disposed on the side of the pixel limiting layer 2 away from the substrate 1, and the second electrode layer 5 covers the first sub-opening 211 and the second sub-opening 212; the orthographic projection of the driving transistor on the substrate 1 and the orthographic projection of the second sub-opening 212 on the substrate 1 do not overlap. In this sub-pixel, the first electrode layer 3, the light-emitting functional layer 4, and the second electrode layer 5 disposed on the pixel limiting layer 2 in the first sub-opening 211 of the display area 101 are stacked together to form a sub-pixel. Under the drive of the pixel circuit 12, the first electrode layer 3 and the second electrode layer 5 can provide holes and electrons respectively. The holes and electrons recombine to emit light in the light-emitting functional layer 4, that is, the sub-pixel in the first sub-opening 211 can emit light normally for display. However, in the second sub-opening 212 of the non-display area 102, only the light-emitting functional layer 4 is disposed, and the second electrode layer 5 is covered on top of the light-emitting functional layer 4. Since the first electrode layer 3 is missing in the second sub-opening 212 of the non-display area 102, the area of ​​the second sub-opening 212 of the non-display area 102 will not emit light, thus satisfying the requirement that the area of ​​the second sub-opening 212 in the non-display area 102 does not emit light.

[0083] In some embodiments, the light-emitting functional layer 4 distributed in the second sub-opening 212 of the non-display area 102 may have the same film structure as the light-emitting functional layer 4 distributed in the first sub-opening 211 of the display area 101. The light-emitting functional layer 4 distributed in the second sub-opening 212 of the non-display area 102 may also be a part of the film layer of the light-emitting functional layer 4 distributed in the first sub-opening 211 of the display area 101. For example, the light-emitting functional layer 4 distributed in the first sub-opening 211 of the display area 101 may include a hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer, and an electron injection layer. The light-emitting functional layer distributed in the second sub-opening 212 of the non-display area 102 may include only two (such as the light-emitting layer and the hole injection layer), three, or four of these five film layers.

[0084] In some embodiments, the display substrate further includes a planarization layer 7, which is disposed on the side of the pixel defining layer 2 near the substrate 1; the substrate 1 further includes a substrate 11, on which the pixel circuit 12 is disposed, and through-holes 70 are formed in the planarization layer 7, through which the first electrode layer 3 is connected to the driving transistor in the pixel circuit 12.

[0085] In some embodiments, such as Figure 7 and Figure 8 As shown, the pixel circuit includes a buffer layer 17 and a transistor circuit stacked sequentially on a substrate 11. The transistor circuit includes multiple transistors (including a driving transistor), a memory 1, and multiple signal lines connected to the transistors. The transistor circuit includes a transistor active layer 18, a first gate insulating layer 19, a gate 20 and a first scan line 25, a second gate insulating layer 26, a second scan line 27, an intermediate dielectric layer 28, a source 29 and a drain 30, and a passivation layer 31, all stacked sequentially on the buffer layer 17. The source 29 and drain 30 are located at opposite ends of the active layer 18, and are connected to the active layer 18 vias formed in the intermediate dielectric layer 28, the second gate insulating layer 26, and the first gate insulating layer 19, respectively.

[0086] In some embodiments, the planarization layer 7 includes two layers: a first planarization layer 71 and a second planarization layer 72. The first planarization layer 71 and the second planarization layer 72 are stacked sequentially on the passivation layer 31. A conductive layer 32 may also be disposed between the first planarization layer 71 and the second planarization layer 72. The first electrode layer 3 is connected to the conductive layer 32 through vias formed in the second planarization layer 72. The conductive layer 32 is then connected to the drain 30 of the transistor through vias formed in the first planarization layer 71 and the passivation layer 31. The first scan line 25 is a gate line, and the second scan line 27 is a light emission control signal line.

[0087] In some embodiments, the pixel circuit can be a 2T1C driving circuit or a 7T1C driving circuit, etc.

[0088] In some embodiments, an insulating layer 61 is further provided on the side of the second electrode layer 5 facing away from the substrate. The insulating layer 61 includes a first inorganic encapsulation layer 611, an organic encapsulation layer 612, a second inorganic encapsulation layer 613, and an inorganic buffer layer 614 stacked sequentially. The insulating layer 61 encapsulates the first sub-opening 211 and the second sub-opening 212.

[0089] In some embodiments, each film layer on the display substrate corresponding to the area where the light-transmitting area 103 is located is hollowed out, that is, the light-transmitting area 103 on the display substrate is opened as a through hole; or, only the substrate 11 is retained in the area on the display substrate corresponding to the light-transmitting area 103, and all other film layers in this area are hollowed out; or, all the opaque metal film layers in the area on the display substrate corresponding to the light-transmitting area 103 are hollowed out, and the remaining light-transmitting film layers are retained.

[0090] In some embodiments, such as Figure 9 and Figure 10 As shown, the display substrate also includes signal lines 15, which are disposed on the side of the pixel limiting layer near the substrate. The signal lines 15 extend from the display area 101 to the non-display area 102. In the non-display area 102, the signal lines 15 include an arc portion. The arc portion at least partially surrounds the light-transmitting area 103, and the arc portion at least partially overlaps with the orthographic projection of the second sub-opening 212 on the substrate. Due to the arrangement of the light-transmitting area 103, some signal lines 15 in the substrate cannot extend in their original direction. Around the light-transmitting area 103, some signal lines 15 passing through it need to be wound around it, thus forming the arc portion of the signal lines 15. At least some signal lines 15 pass below the orthographic projection of the second sub-opening 212. Since the area of ​​the second sub-opening 212 does not emit light, the signal lines 15 passing below it will not affect the second sub-opening 212. No signal lines pass below the orthographic projection of the first sub-opening 211 located in the display area 101.

[0091] In some embodiments, the signal line 15 includes a data line 150. Due to the presence of the light-transmitting area 103, some of the data lines 150 in the substrate cannot extend normally in the vertical direction. Around the light-transmitting area 103, some of the data lines 150 passing through the light-transmitting area 103 need to be wrapped around the second opening 22, thus forming an arc portion of the data line 150. This arc portion of the data line 150 at least partially passes below the orthographic projection of the second sub-opening 211.

[0092] In some embodiments, the signal line 15 further includes scan lines 151 such as gate lines, light emission control signal lines, and reset lines. These scan lines 151 originally extend horizontally, but the portion of the scan lines 151 passing through the light-transmitting area 103 needs to be surrounded by lines around the light-transmitting area 103, thereby forming an arc portion of the scan line 151. This arc portion of the scan line 151 passes at least partially below the orthographic projection of the second sub-opening 211.

[0093] In some embodiments, such as Figure 8 As shown, below the distribution area of ​​the second sub-opening 212, there are correspondingly distributed arc-shaped portions of multiple signal lines 15. These arc-shaped portions of the signal lines 15 may include arc-shaped portions of data lines 150. The arc-shaped portions of the data lines 150 are distributed in two layers: one layer is co-layered with the source 29 and drain 30, and the other layer is co-layered with the conductive layer 32. This two-layer distribution of the arc-shaped portions of the data lines 150 saves on the display substrate bezel. The arc-shaped portions of the data lines 150 can also be distributed in multiple layers, with each data line 150 in each layer being fabricated using the same material as the metal conductive film layer in the same layer through a single process. Alternatively, when the display substrate has other metal layer structures, such as the gate layer and transition layer of oxide transistors in an LTPO panel, or other transition metal layers in the display panel, a multi-layer winding structure of the signal lines can be used to save on the display substrate bezel. The arc-shaped portions of the signal lines 15 may also include arc-shaped portions of scan lines 151. The arc-shaped portions of the scan lines 151 can also be distributed in two or more layers, such as... Figure 8 In this design, the arc portion of scan line 151 is distributed in two layers: one layer is the arc portion of the gate line on the same layer as the gate 20 and the first scan line 25, and the other layer is the light-emitting control signal line winding on the same layer as the second scan line 27. The arc portion of scan line 151 employs a multi-layer winding structure, saving on the display substrate bezel. The arc portion of scan line 151 can also be distributed in multiple layers, with each scan line 151 in each layer being fabricated using the same material as the metal conductive film layer in the same layer through a single process.

[0094] It should be noted that when the scan line 151 adopts the bilateral drive mode, the scan line 151 does not need to be wound at the light-transmitting area 103, that is, there is no need to set the arc part.

[0095] In some embodiments, such as Figure 5 and Figure 6As shown, along the radial direction of the light-transmitting area 103, the width L of the distribution area of ​​the second sub-opening 212 ranges from 2 to 8 times the radial width of the second sub-opening 212. The radial width of the second sub-opening 212 refers to the maximum opening size of the second sub-opening 212 along the radial direction of the light-transmitting area 103. For example, when the second sub-opening 212 is circular, the radial width of the second sub-opening 212 is the diameter of the circle; when the second sub-opening 212 is rectangular, the radial width of the second sub-opening 212 is the length of the wide side of the rectangle, that is, the wide side of the second sub-opening 212 extends along the radial direction of the light-transmitting area 103; the same applies when the second sub-opening 212 is any other arbitrary shape. The second sub-openings 212 are distributed around the light-transmitting area 103. The distribution area of ​​the second sub-openings 212 refers to the annular region around the light-transmitting area 103 where the second sub-openings 212 are distributed. The width L of the distribution area of ​​the second sub-openings 212 refers to the distance between the inner and outer rings of the annular region along the radial direction of the light-transmitting area 103. In some embodiments, the radial width of the second sub-opening 212 ranges from 5 to 40 μm, such as 7 to 8 μm, 20 to 30 μm, etc., and the width of the distribution area of ​​the second sub-openings 212 ranges from 10 to 320 μm. In some embodiments, the size difference between the first sub-opening 211 and the second sub-opening 212 is less than a set threshold. This set threshold can be 0 or a value close to 0. That is, the sizes of the first sub-opening 211 and the second sub-opening 212 are approximately identical. In some embodiments, the uniformity of the arrangement of the first sub-opening 211 and the second sub-opening 212 is the same. The uniformity of the arrangement of the first sub-opening 21 refers to the distribution density of the first sub-opening 21 within the display area 101, that is, the density of the distribution of the first sub-opening 21 within the display area 101; the uniformity of the arrangement of the second sub-opening 212 refers to the distribution density of the second sub-opening 212 within the annular region surrounding the light-transmitting area 103, that is, the density of the distribution of the second sub-opening 212 within the annular region surrounding the light-transmitting area 103. This arrangement effectively ensures that the size of the first sub-opening 211 at the boundary 100 between the display area 101 and the non-display area 102 is uniform, thereby effectively ensuring the display effect of the display substrate.

[0096] In some embodiments, the display substrate further includes a dam 24 located in the non-display area 102 and at least partially surrounding the light-transmitting area 103. The dam 24 surrounds the edge of the light-transmitting area 103, and a second sub-opening 212 is distributed around the dam 24 on the side of the dam 24 facing away from the light-transmitting area 103. The shortest interval M between the dam 24 and the distribution area of ​​the second sub-opening 212 is greater than 0 and less than 300 micrometers. The dam 24 is formed by forming a first groove 23 in a portion of the insulating layer (such as a planarization layer, pixel defining layer, or support layer) at the edge of the light-transmitting area 103. The width E of the portion of the first groove 23 near the second sub-opening 212 ranges from 40 μm to 80 μm. Therefore, the distance F between the edge of the first groove 23 near the second sub-opening 212 and the distribution area of ​​the second sub-opening 212 is greater than 0 and less than 260 μm; or, the distance F between the edge of the first groove 23 near the second sub-opening 212 and the distribution area of ​​the second sub-opening 212 is greater than 0 and less than 220 μm. The distribution area of ​​the second sub-opening 212 refers to the annular area surrounding the second sub-opening 212 of the light-transmitting area 103. The shortest interval between the dike 24 and the distribution area of ​​the second sub-opening 212 refers to the distance between the outer edge of the dike 24 away from the light-transmitting area 103 and the inner edge of the annular distribution area of ​​the second sub-opening 212 near the light-transmitting area 103. Compared with the case in the disclosed technology where sub-pixel openings are only opened in the pixel limiting layer of the display area, this interval distance M is much smaller than the distance between the sub-pixel opening area and the groove in the pixel limiting layer in the disclosed technology. That is, the pixel limiting layer area retained between the dike 24 and the distribution area of ​​the second sub-opening 212 is smaller, so that the gas released from the internal film layer of the display substrate during and after the process can be released in time through the first groove 23 and the second sub-opening 212, thereby avoiding the released gas from pushing open some internal film layers to form small gaps or cavities, and thus avoiding defects caused by the film layers absorbing moisture through small gaps or cavities during the production process.

[0097] In some embodiments, such as Figure 8 As shown, the dike 24 typically consists of at least two organic layers, such as a planarization layer, a pixel-defining layer, and a support layer 33, but is not limited to this structure. As long as the dike 24 has a sufficient height to block the overflow of the organic encapsulation layer 612, it is acceptable. The dike 24 can have one or two rings. If the dike 24 has two rings, the shortest interval between the dike 24 and the distribution area of ​​the second sub-opening 212 refers to the distance between the outer edge of the dike 24 closest to the distribution area of ​​the second sub-opening 212 away from the light-transmitting area 103 and the inner edge of the annular distribution area of ​​the second sub-opening 212 near the light-transmitting area 103. The support layer 33 and the spacer in the display area 101 are formed using the same material in a single process. Alternatively, the support layer 33 can also be formed using an organic resin material alone in a single process.

[0098] In some embodiments, the dike 24 is used to encapsulate the substrate area surrounding the light-transmitting area 103. Specifically, when encapsulating the substrate area surrounding the light-transmitting area 103, the encapsulation film layer is pressed against the dike 24 to encapsulate the substrate area surrounding the light-transmitting area 103.

[0099] In some embodiments, such as Figure 10 Viewed from above, the display substrate shows that an isolation pillar 16 is provided between the dam 24 and the arcuate portion of the signal line 15. Additionally, an isolation pillar 16 is provided on the side of the dam 24 furthest from the arcuate portion of the signal line 15 (i.e., the side of the dam 24 closer to the light-transmitting area 103). The isolation pillar 16 is used to cut off the conductive film layer (such as the second electrode layer) located on the side of the pixel defining layer facing away from the substrate.

[0100] In some embodiments, the isolation column 16 may be as follows: Figure 8 The isolation groove structure shown is illustrated. In some embodiments, the isolation post 16 may also be as shown in the figure. Figure 11 The isolation protrusion structure shown can actually be an I-shaped isolation pillar formed by the source / drain metal layer on the substrate side.

[0101] In some embodiments, such as Figure 12 and Figure 13As shown, the display substrate also includes a touch film layer 6, which is disposed on the side of the second electrode layer 5 away from the substrate 1. The touch film layer 6 includes touch electrodes 62. The touch electrodes 62 are in a grid shape. The pixel limiting layer 2 is in a grid shape. The orthographic projection of the touch electrodes 62 on the substrate 1 and the orthographic projection area of ​​the pixel limiting layer 2 on the substrate 1 at least partially overlap. Since the second sub-opening 212 in the pixel limiting layer 2 is located in the non-display area 102 near the boundary 100 between the display area 101 and the non-display area 102, the distance between the first groove 23 in the pixel limiting layer 2 and the boundary 100 can be set sufficiently large, ensuring that the size of the light-transmitting area 103 is large enough to accommodate the under-display detection device. This allows the touch electrode 62 to extend from the display area 101 to cover the edge of the first groove 23 in the non-display area 102 away from the light-transmitting area 103. Furthermore, the pixel limiting layer below the covered area of ​​the touch electrode 62 is relatively flat. This not only prevents poor traces on the touch electrode 62 but also improves the effect of the light-transmitting area 103 on the integrity of the touch electrode 62 pattern within the non-display area 102. Simultaneously, since the second sub-opening 212 in the pixel limiting layer 2 is located in the non-display area 102 near the boundary 100 between the display area 101 and the non-display area 102, the distance between the first groove 23 in the pixel limiting layer 2 and the boundary 100 can be set sufficiently large, allowing the touch electrode 62 to extend from the display area 101 to cover the edge of the first groove 23 in the non-display area 102 away from the light-transmitting area 103. The area near the boundary 100 between the display area 101 and the non-display area 102 within region 102 results in a smaller pixel-defining layer 2 area between the distribution areas of the first groove 23 and the second sub-opening 212. Therefore, gases released from the internal film layers during and after the manufacturing process can be released promptly through the first groove 23 and the first opening 21, preventing the released gases from creating small gaps or cavities between some internal film layers. This avoids defects caused by moisture absorption through these gaps or cavities during production. In this embodiment, the distribution of the second sub-opening 212 in the pixel-defining layer 2 within the non-display area 102 ensures that the extension of the touch electrode 62 from the display area 101 to the first groove 23 in the non-display area 102 does not lead to defects caused by moisture absorption in the internal film layers of the display substrate during production. Furthermore, the grid-like design of the touch electrode 62 improves the etching uniformity during its fabrication and enhances its capacitance compensation effect.

[0102] In some embodiments, such as Figure 7 and Figure 8 As shown, the touch electrode 62 is disposed on the side of the insulating layer 61 facing away from the substrate 1. The touch electrode 62 includes a bridge structure 620 disposed on the inorganic buffer layer 614, a first insulating layer 621, and a touch electrode pattern 622 (including a driving electrode and a sensing electrode). The driving electrode or sensing electrode in the touch electrode pattern 622 is connected to the bridge structure 620 through a via formed in the first insulating layer 621.

[0103] In some embodiments, the orthographic projection of the touch electrode 62 on the substrate and the orthographic projection of the pixel defining layer 2 between the second sub-opening 212 on the substrate at least partially overlap.

[0104] In some embodiments, the orthographic projection of the light-transmitting area 103 onto the substrate 1 includes a circle, a rectangle, or a regular hexagon. Of course, the shape of the light-transmitting area 103 can also be other shapes.

[0105] In some embodiments, the positional relationship between the display area 101 and the non-display area 102 may also be such that the display area 101 surrounds the periphery of the non-display area 102, such as... Figure 5 As shown; or, the non-display area 102 is located in a corner of the display area 101, as shown. Figure 14 As shown; or, the non-display area 102 is located at one edge of the display area 101; for example, the non-display area 102 is located in the middle region of one edge of the substrate 1, and the display area 101 surrounds the non-display area 102, such as... Figure 15 As shown.

[0106] In some embodiments, such as Figure 16 As shown, the display area 101 can also be located in the central region of the substrate 1, and the non-display area 102 surrounds the display area 101.

[0107] Based on the above-described structure of the display substrate, this disclosure also provides a method for preparing a display substrate, comprising: preparing a substrate.

[0108] A pixel-defining layer is fabricated on the substrate.

[0109] The display substrate also includes a display area, a non-display area, and a light-transmitting area, with the display area and the non-display area at least partially surrounding the light-transmitting area; the pixel defining layer extends from the display area to the non-display area.

[0110] Preparing a pixel-defining layer includes: forming a pattern of the pixel-defining layer and opening a first opening in the pixel-defining layer.

[0111] The first opening includes multiple first sub-openings and multiple second sub-openings; the multiple first sub-openings are distributed in the display area, and the multiple second sub-openings are distributed in the non-display area; and the second sub-openings are closer to the light-transmitting area than the first sub-openings.

[0112] In some embodiments, the pattern of the pixel-defining layer and the pattern of the first opening are formed through a single patterning process.

[0113] In this embodiment, the other film layer structures in the display substrate are prepared using traditional preparation processes, which will not be described in detail here.

[0114] The display substrate provided in this embodiment has a first opening in the pixel limiting layer, and multiple first sub-openings distributed in the display area and multiple second sub-openings distributed in the non-display area. The second sub-openings are closer to the light-transmitting area than the first sub-openings. Compared to the disclosed technology where sub-pixel openings are only opened in the pixel limiting layer of the display area, this embodiment opens multiple second sub-openings in the portion of the pixel limiting layer extending into the non-display area. This allows the openings in the pixel limiting layer to extend to the boundary between the non-display area and the display area, ensuring that the size of the first sub-openings at the boundary between the display area and the non-display area is uniform, i.e., the size of the first sub-openings at the boundary is the same as the size of the first sub-openings in the display area, thus ensuring the display effect of the display substrate. Simultaneously, by making the second sub-openings closer to the light-transmitting area... The openings are distributed in the non-display area, which shortens the distance between the cofferdam and the distribution area of ​​the second sub-opening. This allows the gas released from the internal film layers of the display substrate during and after the process to be released in a timely manner through the first groove and the second sub-opening. This prevents the released gas from pushing open some internal film layers to form small gaps or cavities, thereby preventing the film layers from absorbing moisture and causing defects during the production process. In addition, by distributing the second sub-opening in the non-display area, the touch electrode can extend from the display area to cover the edge of the first groove in the non-display area. The pixel limiting layer below the coverage area of ​​the touch electrode is relatively flat. This not only prevents defects in the touch electrode layer wiring, but also improves the impact of the setting of the light-transmitting area in the non-display area on the integrity of the touch electrode pattern.

[0115] This disclosure also provides a display substrate, such as... Figure 17 and Figure 18 As shown, based on the display substrate in the above embodiment, in this embodiment, the second sub-opening 212 includes a first shaped opening 34, a second shaped opening 35, and a third shaped opening 36; the first shaped opening 34, the second shaped opening 35, and the third shaped opening 36 have different shapes and sizes; two first shaped openings 34, one second shaped opening 35, and one third shaped opening 36 form an opening cycle 37; multiple opening cycles 37 are distributed in the non-display area.

[0116] In some embodiments, the first shaped opening 34 is pentagonal, the second shaped opening 35 is hexagonal, and the third shaped opening 36 is hexagonal, wherein the hexagonal shapes of the second shaped opening 35 and the third shaped opening 36 are different. Of course, the shapes of the first shaped opening 34, the second shaped opening 35, and the third shaped opening 36 are not limited to the shapes described above.

[0117] In some embodiments, within the same opening period 37, two first-shaped openings 34 are mirror-symmetrical about the horizontal X-axis; the first-shaped openings 34, the second-shaped openings 35, and the third-shaped openings 36 are arranged alternately along the X-axis. Of course, the arrangement of the openings within the opening period 37 is not limited to the above arrangement.

[0118] In some embodiments, the arrangement and shape of the first sub-opening 211 within the display area are exactly the same as those of the second sub-opening 212. Specifically, the first shaped opening 34 is used to accommodate green sub-pixels, the second shaped opening 35 is used to accommodate blue sub-pixels, and the third shaped opening 36 is used to accommodate red sub-pixels.

[0119] In some embodiments, within the opening period 37, the distance T between the two first-shaped openings 34 ranges from 6 to 27 μm; the distance P between the first-shaped opening 34 and the second-shaped opening 35 ranges from 15 to 30 μm; the distance Q between the second-shaped opening 35 and the third-shaped opening 36 ranges from 15 to 30 μm; and the distance Z between the first-shaped opening 34 and the third-shaped opening 36 ranges from 50 to 80 μm. Wherein, the distance T between the two first-shaped openings 34 is the shortest straight-line distance between two adjacent sides of the two first-shaped openings 34 that are parallel to the X-axis and mirror-symmetrical about the X-axis direction. The distance P between the first-shaped opening 34 and the second-shaped opening 35, the distance Q between the second-shaped opening 35 and the third-shaped opening 36, and the distance Z between the first-shaped opening 34 and the third-shaped opening 36 are all the shortest straight-line distances between two adjacent sides of the two openings along the Y-axis direction perpendicular to the X-axis.

[0120] In some embodiments, within the opening period 37, the distance T between the two first shape openings 34 is 16.5 μm; the distance P between the first shape opening 34 and the second shape opening 35 is 26 μm; the distance Q between the second shape opening 35 and the third shape opening 36 is 26 μm; and the distance Z between the first shape opening 34 and the third shape opening 36 is 72 μm.

[0121] In some embodiments, within the opening period 37, the width 'a' of the first shaped opening 34 along the X-axis ranges from 15 to 30 μm; optionally, for example, the width 'a' of the first shaped opening 34 along the X-axis is 20 μm. The width 'b' of the second shaped opening 35 along the X-axis ranges from 15 to 30 μm; optionally, the width 'b' of the second shaped opening 35 along the X-axis is 22 μm. The width 'd' of the third shaped opening 36 along the X-axis ranges from 6 to 15 μm; optionally, the width 'd' of the third shaped opening 36 along the X-axis is 10 μm. Wherein, the width of each shaped opening along the X-axis is the maximum dimension of each shaped opening along the X-axis.

[0122] In some embodiments, within the opening period 37, the width a of the first shaped opening 34 is 1 to 1.2 times the width b of the second shaped opening 35; and the width b of the second shaped opening 35 is 1.5 to 2 times the width d of the third shaped opening 36.

[0123] In some embodiments, within the opening period 37, the length e of the first shaped opening 34 along the Y-axis ranges from 5 to 25 μm; optionally, for example, the length e of the first shaped opening 34 along the Y-axis is 16 μm. The length f of the second shaped opening 35 along the Y-axis ranges from 10 to 50 μm; optionally, the length f of the second shaped opening 35 along the Y-axis is 35 μm. The length g of the third shaped opening 36 along the Y-axis ranges from 15 to 60 μm; optionally, the length g of the third shaped opening 36 along the Y-axis is 45 μm. Wherein, the length of each shaped opening along the Y-axis is the maximum dimension of each shaped opening along the Y-axis.

[0124] In some embodiments, within the opening period 37, the length e of the first shaped opening 34 is 0.5 to 0.7 times the length f of the second shaped opening 35; and the length f of the second shaped opening 35 is 0.8 to 1 times the length g of the third shaped opening 36.

[0125] In some embodiments, within the opening period 37, the area of ​​the first shaped opening 34 is 0.5 to 0.7 times the area of ​​the second shaped opening 35; the area of ​​the second shaped opening 35 is 1.5 to 2 times the area of ​​the third shaped opening 36. Here, the area of ​​each shaped opening refers to the orthographic projection area of ​​each shaped opening onto the substrate.

[0126] In some embodiments, the opening areas of shapes that are the same in the non-display area and the display area are identical.

[0127] In some embodiments, the area of ​​each shaped opening in the non-display area is 1.1 to 1.5 times the area of ​​each shaped opening with the same shape in the display area.

[0128] In some embodiments, the area of ​​each shaped opening in the non-display area is 0.6 to 0.9 times the area of ​​each shaped opening with the same shape in the display area.

[0129] The area ratio settings of the openings of the same shape in the non-display area and the display area ensure that the size of the first sub-opening at the junction of the display area and the non-display area is uniform. At the same time, it also allows the gas released from the internal film layer of the display substrate during and after the process to be released in a timely manner through the first groove and the second sub-opening. This prevents the released gas from pushing open some internal film layers to form small gaps or cavities, thereby preventing each film layer from absorbing moisture through small gaps or cavities during the production process and causing defects.

[0130] The other structures and fabrication methods of the display substrate in this embodiment are the same as those in the above embodiments, and will not be repeated here.

[0131] This disclosure also provides a display panel, including the above-described display substrate.

[0132] By using the aforementioned display substrate, the display effect of the display panel can be improved, while also preventing poor water absorption during the production process.

[0133] The display panel provided in this embodiment can be any product or component with display function, such as an OLED panel, OLED TV, monitor, mobile phone, or navigator.

[0134] It is understood that the above embodiments are merely exemplary embodiments used to illustrate the principles of this disclosure, and this disclosure is not limited thereto. For those skilled in the art, various modifications and improvements can be made without departing from the spirit and substance of this disclosure, and these modifications and improvements are also considered to be within the scope of protection of this disclosure.

[0135] This invention is based on PCT international patent application No. PCT / CN2020 / 114589 filed on September 10, 2020, and claims priority in accordance with the relevant provisions of the Patent Law. The entire contents of that application are incorporated herein by reference.

Claims

1. A display substrate, characterized in that, include: substrate; A pixel defining layer disposed on the substrate; The display substrate further includes a display area, a non-display area, and a light-transmitting area, wherein the display area and the non-display area at least partially surround the light-transmitting area; The pixel-defining layer extends from the display area to the non-display area; The pixel definition layer has a first opening, which includes a plurality of first sub-openings and a plurality of second sub-openings; the plurality of first sub-openings are distributed in the display area, and the plurality of second sub-openings are distributed in the non-display area; Furthermore, the second sub-opening is closer to the light-transmitting area than the first sub-opening; It also includes a planarization layer disposed on the side of the pixel defining layer near the substrate; The flat layer extends from the display area to the non-display area; A first groove is formed in the pixel defining layer and the planarization layer. The first groove is located in the non-display area and surrounds the light-transmitting area. The display substrate further includes signal lines, which are disposed on the side of the pixel defining layer near the substrate. The signal lines extend from the display area to the non-display area, and the signal lines include arc portions in the non-display area. The arc portion is at least partially disposed around the light-transmitting area, and the arc portion at least partially overlaps with the orthographic projection of the second sub-opening on the substrate; A first electrode layer and a light-emitting functional layer are disposed in the first sub-opening; the first electrode layer and the light-emitting functional layer are stacked in a direction away from the substrate; The light-emitting functional layer is provided in the second sub-opening; The display substrate further includes a second electrode layer, which is disposed on the side of the pixel defining layer opposite to the substrate, and the second electrode layer covers the first sub-opening and the second sub-opening; The orthographic projections of the first sub-opening and the second sub-opening on the substrate are located within the orthographic projection of the planarization layer on the substrate; The orthographic projection of the first sub-opening on the substrate is located within the orthographic projection of the first electrode layer on the substrate, and the orthographic projection of the first electrode layer on the substrate does not overlap with the orthographic projection of the second sub-opening on the substrate; The orthographic projection of the first groove on the substrate is located on the side of the orthographic projection of the second sub-opening on the substrate away from the display area, and the orthographic projection portions of the first groove, the planarization layer and the pixel defining layer on the substrate overlap.

2. The display substrate according to claim 1, characterized in that, The substrate includes a pixel circuit, the pixel circuit includes a driving transistor, and the driving transistor is electrically connected to the first electrode layer. The orthographic projection of the driving transistor on the substrate does not overlap with the orthographic projection of the second sub-opening on the substrate.

3. The display substrate according to claim 1, characterized in that, The signal lines include data lines.

4. The display substrate according to claim 2, characterized in that, Along the radial direction of the light-transmitting area, the width of the distribution area of ​​the second sub-opening ranges from 2 to 8 times the radial width of the second sub-opening.

5. The display substrate according to claim 1, characterized in that, The display substrate further includes a dike located in the non-display area and at least partially surrounding the light-transmitting area; The cofferdam surrounds the edge of the light-transmitting area, and the second sub-openings are distributed around the cofferdam on the side of the cofferdam away from the light-transmitting area; The shortest interval between the cofferdam and the distribution area of ​​the second sub-opening is greater than 0 and less than 300 micrometers.

6. The display substrate according to claim 2, characterized in that, It also includes a touch film layer, which is disposed on the side of the second electrode layer opposite to the substrate; The touch film layer includes touch electrodes; the touch electrodes are in a grid shape; the orthographic projection of the touch electrodes on the substrate at least partially overlaps with the orthographic projection area of ​​the pixel defining layer on the substrate.

7. The display substrate according to claim 6, characterized in that, The orthographic projection of the touch electrode on the substrate and the orthographic projection of the pixel defining layer on the substrate between the second sub-opening at least partially overlap.

8. The display substrate according to claim 1, characterized in that, The size difference between the first sub-opening and the second sub-opening is less than a set threshold.

9. The display substrate according to claim 1, characterized in that, The second sub-opening includes a first-shaped opening, a second-shaped opening, and a third-shaped opening; The first shaped opening, the second shaped opening, and the third shaped opening are of different sizes; Two first-shaped openings, one second-shaped opening, and one third-shaped opening constitute an opening cycle; multiple opening cycles are distributed within the non-display area.

10. The display substrate according to claim 9, characterized in that, During the opening period, the spacing between the two first-shaped openings ranges from 6 to 27 µm. The distance between the first shaped opening and the second shaped opening ranges from 15 to 30 µm; The distance between the second shaped opening and the third shaped opening is in the range of 15 to 30 µm; The distance between the first shaped opening and the third shaped opening is in the range of 50 to 80 µm.

11. The display substrate according to claim 9, characterized in that, The distance between the first shaped opening and the third shaped opening is 1.5 to 2.5 times the distance between the first shaped opening and the second shaped opening; The distance between the first shaped opening and the second shaped opening is 0.8 to 1.2 times the distance between the second shaped opening and the third shaped opening; The spacing between the two first-shaped openings is 0.6 to 1 times the spacing between the first-shaped opening and the second-shaped opening.

12. The display substrate according to claim 1, characterized in that, The first sub-opening and the second sub-opening have the same uniformity of arrangement.

13. The display substrate according to claim 1, characterized in that, The display area surrounds the periphery of the non-display area; Alternatively, the non-display area may be located in a corner of the display area; Alternatively, the non-display area may be located at one edge of the display area.

14. The display substrate according to claim 2, characterized in that, The substrate further includes a base, the pixel circuit is disposed on the base, and a via is formed in the planarization layer. The first electrode layer is connected to the driving transistor in the pixel circuit through the via.

15. A display panel, characterized in that, Includes the display substrate as described in any one of claims 1-14.

16. A method for preparing a display substrate, characterized in that, include: Preparing a substrate; A planarization layer is prepared on the substrate; A pixel defining layer is fabricated on the substrate; The display substrate further includes a display area, a non-display area, and a light-transmitting area, wherein the display area and the non-display area at least partially surround the light-transmitting area; The flat layer extends from the display area to the non-display area; The pixel-defining layer extends from the display area to the non-display area; Preparing the planarization layer includes: forming a pattern of the planarization layer; Preparing the pixel-defining layer includes: forming a pattern of the pixel-defining layer and opening a first opening in the pixel-defining layer; The first opening includes a plurality of first sub-openings and a plurality of second sub-openings; the plurality of first sub-openings are distributed in the display area, and the plurality of second sub-openings are distributed in the non-display area; and the second sub-openings are closer to the light-transmitting area than the first sub-openings. Fabricating the pixel-defining layer and the planarization layer further includes forming a first groove in the pixel-defining layer and the planarization layer; A first electrode layer and a light-emitting functional layer are formed in the first sub-opening; the first electrode layer and the light-emitting functional layer are stacked in a direction away from the substrate; The light-emitting functional layer is formed in the second sub-opening; The fabrication method further includes fabricating a second electrode layer, the second electrode layer being disposed on the side of the pixel defining layer opposite to the substrate, and the second electrode layer covering the first sub-opening and the second sub-opening; The orthographic projections of the first sub-opening and the second sub-opening on the substrate are located within the orthographic projection of the planarization layer on the substrate; The orthographic projection of the first sub-opening on the substrate is located within the orthographic projection of the first electrode layer on the substrate, and the orthographic projection of the first electrode layer on the substrate does not overlap with the orthographic projection of the second sub-opening on the substrate; The orthographic projection of the first groove on the substrate is located on the side of the orthographic projection of the second sub-opening on the substrate away from the display area, and the orthographic projection portions of the first groove, the planarization layer and the pixel defining layer on the substrate overlap.

17. The method for preparing a display substrate according to claim 16, characterized in that, The pixel-defining layer and the first opening are formed through a single patterning process.

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