Majorana fermion quantum computing devices fabricated using ion implantation methods

Abstract

A quantum computing device is fabricated by forming a first resist pattern defining a device region and a sensing region within the device region on a superconducting layer (410). The superconducting layer within the sensing region is removed, thereby exposing a region of the underlying semiconductor layer (340) outside the device region. The exposed region of the semiconductor layer is implanted to form an isolation region (240) surrounding the device region. After implantation, an etching process is used to expose the sensing region and a portion of the device region of the superconducting layer adjacent to the isolation region. A tunnel junction gate (204) is formed by depositing a first metal layer within the sensing region. A sensing region gate (202) is formed by coupling the semiconductor layer to a second metal layer. A chemical potential gate (208, 210) is also formed. Nanorod contacts (206, 212) are formed within a portion of the device region outside the sensing region using the second metal.

Description

Technical Field

[0001] This invention generally relates to superconducting devices, manufacturing methods, and manufacturing systems for superconducting quantum devices. More specifically, this invention relates to devices, methods, and systems for manufacturing Majorana fermion quantum computing devices using ion implantation methods. Background Technology

[0002] In the following text, unless explicitly distinguished when used, the “Q” prefix in a word or phrase indicates a reference to that word or phrase in the context of quantum computing.

[0003] Molecules and subatomic particles obey the laws of quantum mechanics, the branch of physics that explores how the physical world works at a fundamental level. At this level, particles behave in strange ways, simultaneously existing in more than one state and interacting with other particles very far away. Quantum computing utilizes these quantum phenomena to process information.

[0004] The computers we use today are called traditional computers (also referred to in this article as "traditional" computers or traditional nodes, or "CN"). Traditional computers use traditional processors, which are manufactured using semiconductor materials and technologies, semiconductor memory, and magnetic or solid-state storage devices, a process known as the von Neumann architecture. In particular, the processors in traditional computers are binary processors, that is, they operate on binary data represented by 1s and 0s.

[0005] Quantum processors (q processors) utilize the odd-numbered property of entangled qubit devices (concisely referred to as "qubits" or multiple "qubits" in this paper) to perform computational tasks. In specific areas of quantum mechanics, matter particles can exist in multiple states, such as "on," "off," and simultaneously "on" and "off." Where binary computation using semiconductor processors is limited to using only the on and off states (equivalent to 1 and 0 in binary code), quantum processors leverage these quantum states of matter to output signals that can be used for data computation.

[0006] Traditional computers encode information using bits. Each bit can take the value 1 or 0, and these 1s and 0s serve as on / off switches that ultimately drive the computer's functions. Quantum computers, on the other hand, are based on qubits, which operate according to two key principles of quantum physics: superposition and entanglement. Superposition means that each qubit can represent both 1 and 0 simultaneously. Entanglement means that qubits in a superposition can be correlated with each other in a non-classical way; that is, the state of one (whether it is 1 or 0 or both) can depend on the state of the other, and more information can be determined when two qubits are entangled than when they are processed individually.

[0007] Using these two principles, qubits function as more sophisticated information processors, enabling quantum computers to solve problems that are difficult to handle with conventional computers. IBM has successfully built and demonstrated the operability of a quantum processor using superconducting qubits (IBM is a registered trademark of International Business Machines Corporation in the U.S. and other countries).

[0008] In the superconducting state, the material firstly provides no resistance to the passage of electric current. When the resistance drops to zero, the current can circulate within the material without any energy dissipation. Secondly, the material exhibits the Meissne refractory effect, meaning that external magnetic fields will not penetrate the superconductor, but will remain on its surface, provided they are weak enough. When a material no longer exhibits one or both of these properties, it is said to be in the normal state and no longer superconducting.

[0009] The critical temperature of a superconducting material is the temperature at which the material begins to exhibit superconducting characteristics. Superconducting materials exhibit very low or zero resistivity to electric current. The critical magnetic field is the highest magnetic field at a given temperature at which the material remains superconducting.

[0010] Superconductors are generally classified into one of two types. Type I superconductors exhibit a single transition at the critical magnetic field. When the critical magnetic field is reached, a Type I superconductor transitions from a non-superconducting state to a superconducting state. Type II superconductors involve two critical magnetic fields and two transitions. At or below the lower critical magnetic field, a Type II superconductor exhibits superconductivity. Above the upper critical magnetic field, a Type II superconductor does not exhibit superconductivity. Between the upper and lower critical magnetic fields, a Type II superconductor exhibits a mixed state. In the mixed state, a Type II superconductor exhibits an incomplete Meissner effect, i.e., the external magnetic field penetrates the superconducting material within a quantized packet at a specific location.

[0011] Information processed by qubits is carried or transmitted as microwave signals / photons in the microwave frequency range. These microwave signals are captured, processed, and analyzed to decipher the quantum information encoded within them. A readout circuit, coupled to the qubit, is used to capture, read, and measure the quantum state of the qubit. The output of the readout circuit is information that can be used by a q-processor to perform computations.

[0012] Superconducting qubits possess two quantum states – |0> and |1>. These two states can be the two energy states of an atom, for example, the ground state (|g>) and the first excited state (|e>) of a superconducting artificial atom (superconducting qubit). Other examples include spin-up and spin-down of the nuclear or electron spin, the two locations of crystal defects, and the two states of a quantum dot. Due to the quantum nature of the system, any combination of the two states is permissible and valid.

[0013] In known semiconductor manufacturing techniques, superconducting devices such as qubits are fabricated using superconducting and semiconductor materials. Superconducting devices typically use one or more layers of different materials to achieve device performance and functionality. Material layers can be superconducting, conductive, semiconducting, insulating, resistive, inductive, capacitive, or possess any number of other properties. Different methods may be necessary to form different material layers, taking into account the properties of the materials, their shape, size, or arrangement, other materials adjacent to them, and many other considerations.

[0014] Software tools used to design semiconductor and superconducting devices are manufactured, operated, or otherwise integrated with electrical layouts and device assemblies on a very small scale. Some components that such tools can manipulate, when formed in a suitable substrate, may only be a few nanometers wide.

[0015] Layout includes shape, the shape and position of which are selected in the tooling according to the target of the device. Once the design layout for a device or a group of devices has been completed, also simply referred to as layout, the design is converted into a set of masks or reticles. A set of masks or reticles consists of one or more masks or reticles. During manufacturing, a semiconductor wafer is exposed to light or radiation through a mask to form microscopic components including structures. This process is called photolithography. Masks can be used to fabricate or print the contents of a mask onto a wafer. During the photolithography printing process, radiation is focused through the mask at a specific desired radiation intensity. This intensity of radiation, combined with any material used for radiation deposition, is often referred to as the "dose." The focus and dose of radiation are controlled to achieve the desired shape and electrical properties of the structure on the wafer.

[0016] Fabrication processes for semiconductor or superconducting devices include not only dosing but also other methods of depositing and / or removing materials with various electrical and / or mechanical properties. For example, an ion beam can be used to deposit a conductive material; hard insulators can be dissolved using chemicals or etched using mechanical means. Examples of operations in these fabrication processes are not limiting. Based on this disclosure, those skilled in the art will be able to conceive of many other operations that can be used in fabrication processes for manufacturing devices according to illustrative embodiments, and these operations can be envisioned within the scope of the illustrative embodiments.

[0017] Superconducting devices are typically planar, meaning that the superconducting structure is fabricated on a plane. Non-planar devices are three-dimensional (3D) devices, where some parts of the structure are formed above or below a given fabrication plane.

[0018] Quantum gates perform operations on qubits. Quantum gates are analogous to basic operations in classical computing, such as AND, OR, and NOT gates, and are often used as building blocks for more complex operations on qubits. Topological quantum computing is a method of quantum computing where quantum gates are generated by weaving together anyons, which are a specific type of topological quantum object. Devices implementing topological quantum computing offer the possibility of longer coherence times than conventional quantum computing devices, and therefore provide greater fault tolerance while possessing computational capabilities similar to conventional quantum computing devices.

[0019] One implementation of anyon suitable for topological quantum computing is the Majorana quasiparticle, also known as Majorana zero-mode (MZM) or Majorana fermion. Therefore, topological quantum computing involves manipulating MZMs and measuring their states, and Majorana fermion quantum computing devices realize MZM manipulation and state measurement. Summary of the Invention

[0020] Illustrative embodiments provide quantum computing devices. Embodiments include a device region on a superconducting layer above a semiconductor layer. Embodiments include a sensing region within the device region, the sensing region including a portion of the device region in which the superconducting layer has been removed. Embodiments include a tunnel junction gate within the sensing region comprising a first metal. Embodiments include a chemical potential gate comprising a dielectric and the first metal within a portion of the device region outside the sensing region. Embodiments include a sensing region gate comprising a second metal coupled to the semiconductor layer within the sensing region. Embodiments include a nanorod contact comprising a second metal coupled to the superconducting layer within a portion of the device region outside the sensing region.

[0021] The embodiments include a method for manufacturing a quantum computing device. The embodiments include a manufacturing system for manufacturing a quantum computing device. Attached Figure Description

[0022] The appended claims set forth novel features that are considered characteristic of the invention. However, the invention itself, its preferred modes of use, further objects and advantages will be best understood by referring to the following detailed description of illustrative embodiments taken in conjunction with the accompanying drawings, in which:

[0023] Figure 1 A block diagram of a network that can implement the illustrative embodiments of the data processing system is depicted;

[0024] Figure 2 A Majorana fermion quantum computing device fabricated using an ion implantation method according to an illustrative embodiment is depicted;

[0025] Figure 3A block diagram depicts an example configuration achieved in the fabrication of a Majorana Fermi quantum computing device according to an illustrative embodiment;

[0026] Figure 4 A block diagram depicts an example configuration achieved in the fabrication of a Majorana Fermi quantum computing device according to an illustrative embodiment;

[0027] Figure 5 A block diagram depicts an example configuration achieved in the fabrication of a Majorana Fermi quantum computing device according to an illustrative embodiment;

[0028] Figure 6 A block diagram depicts an example configuration achieved in the fabrication of a Majorana Fermi quantum computing device according to an illustrative embodiment;

[0029] Figure 7 A block diagram depicts an example configuration achieved in the fabrication of a Majorana Fermi quantum computing device according to an illustrative embodiment;

[0030] Figure 8 A block diagram depicts an example configuration achieved in the fabrication of a Majorana Fermi quantum computing device according to an illustrative embodiment;

[0031] Figure 9 A block diagram depicts an example configuration achieved in the fabrication of a Majorana Fermi quantum computing device according to an illustrative embodiment;

[0032] Figure 10 A block diagram depicts an example configuration achieved in the fabrication of a Majorana Fermi quantum computing device according to an illustrative embodiment;

[0033] Figure 11 A block diagram depicts an example configuration achieved in the fabrication of a Majorana Fermi quantum computing device according to an illustrative embodiment;

[0034] Figure 12 A block diagram depicts an example configuration achieved in the fabrication of a Majorana Fermi quantum computing device according to an illustrative embodiment;

[0035] Figure 13 A block diagram depicts an example configuration achieved in the fabrication of a Majorana Fermi quantum computing device according to an illustrative embodiment;

[0036] Figure 14 A block diagram depicts an example configuration achieved in the fabrication of a Majorana Fermi quantum computing device according to an illustrative embodiment;

[0037] Figure 15 A block diagram depicts an example configuration achieved in the fabrication of a Majorana Fermi quantum computing device according to an illustrative embodiment;

[0038] Figure 16 A block diagram depicts an example configuration achieved in the fabrication of a Majorana Fermi quantum computing device according to an illustrative embodiment;

[0039] Figure 17 A block diagram depicts an example configuration achieved in the fabrication of a Majorana Fermi quantum computing device according to an illustrative embodiment;

[0040] Figure 18 A block diagram depicts an example configuration achieved in the fabrication of a Majorana Fermi quantum computing device according to an illustrative embodiment;

[0041] Figure 19 A block diagram depicts an example configuration achieved in the fabrication of a Majorana Fermi quantum computing device according to an illustrative embodiment;

[0042] Figure 20 A block diagram depicts an example configuration achieved in the fabrication of a Majorana Fermi quantum computing device according to an illustrative embodiment; and

[0043] Figure 21 A flowchart depicts an example process for fabricating a Majorana fermion quantum computing device according to an illustrative embodiment. Detailed Implementation

[0044] The illustrative embodiments recognize that while devices for realizing topological quantum computing are desirable, there are difficulties in fabricating such devices. For Majorana fermion quantum computing devices to function correctly, the films and interfaces between device layers must be above a specific high quality threshold; however, conventional device processing techniques such as reactive ion etching (RIE), cleaning processes, and air oxidation tend to damage film and layer surfaces, thereby reducing the quality below this threshold. Furthermore, if a dielectric film is used for the discrete structure, trapped charges in the dielectric film can generate quasiparticles, leading to uncontrolled electron densities that may quench qubit coherence. In addition, multiple structures, including semiconductor and superconductor components, regions for measuring MZM states, gates, contacts, and wires, must be integrated into a single device. Therefore, the illustrative embodiments recognize an unmet need to fabricate Majorana fermion quantum computing devices using techniques that produce sufficiently high-quality films and surfaces, avoid damaging RIE and cleaning processes, and avoid using dielectric films. Furthermore, the illustrative embodiments recognize that, for efficient fabrication, the process flow for manufacturing Majorana fermion quantum computing devices should have as few masking steps as possible.

[0045] The illustrative embodiments used to describe the present invention generally address and resolve the aforementioned problems or needs, as well as other related problems or needs, by providing Majorana fermion quantum computing devices fabricated using ion implantation methods. The illustrative embodiments also provide a novel method for fabricating Majorana fermion quantum computing devices fabricated using ion implantation methods. The illustrative embodiments further provide a system for fabricating Majorana fermion quantum computing devices fabricated using ion implantation methods. In particular, the illustrative embodiments provide in-situ growth of semiconductor and superconductor structures using known III-V quantum well epitaxial processes to produce high-quality films and interfaces between films. The illustrative embodiments provide the use of low-dose ion implantation to define circuit regions, thereby avoiding damage to the RIE and cleaning processes, and altering film conductivity, thereby avoiding the use of dielectric films. Furthermore, gentle wet etching is used to remove superconductors from desired regions, and gentle stripping patterning is used to form wiring structures.

[0046] Refer to the attached diagram, and specifically refer to... Figure 1 These figures are example diagrams of a data processing environment in which illustrative embodiments can be implemented. Figure 1 This is merely an example and is not intended to assert or imply any limitation regarding the environment in which different embodiments may be implemented. Specific implementations may make many modifications to the depicted environment based on the following description.

[0047] Figure 1 A block diagram of a network in which an illustrative embodiment of a data processing system may be implemented is described. Data processing environment 100 is a computer network in which the illustrative embodiment may be implemented. Data processing environment 100 includes network 102. Network 102 is a medium for providing communication links between various devices and computers connected together within data processing environment 100. Network 102 may include connections such as wired, wireless communication links, or fiber optic cables.

[0048] The client or server are merely example roles of certain data processing systems connected to network 102 and are not intended to exclude other configurations or roles of these data processing systems. Servers 104 and 106 are coupled to network 102 along with storage unit 108. Software applications can execute on any computer in the data processing environment 100. Clients 110, 112, and 114 are also coupled to network 102. Data processing systems such as server 104 or 106 or clients 110, 112, or 114 can contain data and can have software applications or software tools executing on them.

[0049] Device 132 is an example of a mobile computing device. For example, device 132 may take the form of a smartphone, tablet computer, laptop computer, client 110 in fixed or portable form, wearable computing device, or any other suitable device. Described as being in Figure 1 Any software application executing in another data processing system within the device can be configured to execute in a similar manner in device 132. Figure 1 Any data or information stored or generated in another data processing system can be configured to be stored or generated in device 132 in a similar manner.

[0050] Application 105 implements the embodiments described herein. Manufacturing system 107 is a software component of any suitable system for fabricating quantum devices. Typically, manufacturing systems for fabricating superconducting devices, including devices for quantum computing applications, are known. Application 105 provides instructions to such a known manufacturing system via manufacturing application 107 for assembling, in the manner described herein, a novel Majorana fermion quantum computing device fabricated using the ion implantation method considered in the illustrative embodiments.

[0051] The embodiments provide a Majorana fermion quantum computing device fabricated using an ion implantation method according to an illustrative embodiment. The device includes a superconducting layer above a semiconductor layer, a tunnel junction gate and a sensing region gate within a sensing region, a chemical potential gate, and nanorod contacts outside the sensing region. The device is surrounded by an isolation region.

[0052] The embodiments provide a novel design and fabrication method for Majorana fermion quantum computing devices fabricated using an ion implantation method according to illustrative embodiments. In this embodiment, a design / fabrication system designs and fabricates Majorana fermion quantum computing devices fabricated using an ion implantation method.

[0053] Another embodiment provides a method for fabricating Majorana fermionic quantum computing devices using an ion implantation method, such that the method can be implemented as a software application. Applications implementing this fabrication method embodiment can be configured to operate in conjunction with existing superconducting fabrication systems, such as photolithography systems.

[0054] For clarity of description, and without implying any limitation thereof, illustrative embodiments are described using an example number of Majorana fermion operation and measurement structures arranged on a substrate. Within the scope of the illustrative embodiments, embodiments may be implemented with different numbers of structures, different arrangements of structures, superconducting devices other than those used to form qubits, or other types of quantum computing devices, or some combination thereof.

[0055] Furthermore, simplified diagrams of the exemplary structures are used in the accompanying drawings and illustrative embodiments. In the actual fabrication of Majorana Fermi quantum computing devices, additional structures not shown or described herein, or structures different from those shown and described herein, may exist without departing from the scope of the illustrative embodiments. Similarly, within the scope of the illustrative embodiments, the structures shown or described in the exemplary devices may be fabricated differently to produce similar operation or results as described herein.

[0056] As described herein, the different shaded areas in the two-dimensional diagrams of the exemplary structures, layers, and formations are intended to represent different structures, layers, materials, and formations in exemplary fabrication. Different structures, layers, materials, and constructions can be fabricated using suitable materials known to those skilled in the art.

[0057] The specific shape, location, orientation, or size of the shapes described herein is not intended to limit the illustrative embodiments unless such features are explicitly described as characteristics of an embodiment. The shapes, locations, sizes, quantities, or combinations thereof have been chosen solely for clarity of the drawings and description and may have been exaggerated, minimized, or otherwise modified relative to the actual shapes, locations, or sizes that might be used in actual lithography to achieve the objectives according to the illustrative embodiments.

[0058] Furthermore, illustrative embodiments are described, by way of example only, with respect to specific real or hypothetical superconducting devices, such as currently feasible qubits. The steps described by the various illustrative embodiments can be adapted to fabricate various quantum computing devices in a similar manner, and such adaptations are contemplated within the scope of the illustrative embodiments.

[0059] When implemented in an application, the embodiments cause the manufacturing process to perform certain steps as described herein. The steps of the manufacturing process are illustrated in several figures. Not all steps are necessary in a particular manufacturing process. Some manufacturing processes may perform the steps in a different order, combine certain steps, remove or replace certain steps, or perform some combination of these and other steps without departing from the scope of the illustrative embodiments.

[0060] The illustrative embodiments are described by way of example only, relating to certain types of materials, electrical properties, thermal properties, structures, formations, shapes, layer orientations, directions, steps, operations, planes, dimensions, quantities, data processing systems, environments, components, and applications. Any particular manifestation of these and other similar human factors is not intended to limit the invention. Any suitable manifestation of these and other similar products may be chosen within the scope of the illustrative embodiments.

[0061] Illustrative embodiments have been described using specific designs, architectures, layouts, diagrams, and tools. These are merely examples and not intended to limit the scope of the illustrative embodiments. The illustrative embodiments may be used in conjunction with other equivalent or similar designs, architectures, layouts, diagrams, and tools for similar purposes.

[0062] The examples in this disclosure are for illustrative purposes only and are not intended to limit the scope of the illustrative embodiments. Any advantages listed herein are merely examples and are not intended to limit the illustrative embodiments. Additional or different advantages may be achieved through specific illustrative embodiments. Furthermore, specific illustrative embodiments may have some, all, or none of the advantages listed above.

[0063] refer to Figure 2 The figure depicts a Majorana fermion quantum computing device fabricated using an ion implantation method according to an illustrative embodiment.

[0064] In particular, Figure 2 Top-view and cross-sectional views of device 200 are depicted. Device 200 is a Majorana fermion quantum computing device fabricated using an ion implantation method according to an illustrative embodiment. Device 200 includes at least two nanorod structures 230 and 232 configured as a superconducting island surrounded by an isolation region 240. Both nanorod structures 230 and 232 are connected to a sensing region. In one embodiment, nanorod structures 230 and 232 are substantially parallel to each other, and one end of each of nanorod structures 230 and 232 is connected to the sensing region. In another embodiment, nanorod structures 230 and 232 are substantially perpendicular to each other. In yet another embodiment, nanorod structures 230 and 232 intersect at an angle.

[0065] Each nanorod structure includes a semiconductor portion of a semiconductor layer 340 whose surface is covered by a protective layer 350 and a superconducting portion of a superconducting layer 410. Below the semiconductor layer 340 are a protective layer 330, a buffer layer 320, and a substrate 310.

[0066] Each nanorod structure has dimensions suitable for enabling the nanowire to act as a one-dimensional topological superconductor, wherein the chemical potential and magnetic field are tuned such that when the metal in the superconducting portions of nanorod structures 230 and 232 is made superconducting, for example by lowering the temperature of the metal to a specified cryogenic temperature, the nanorods accommodate MZMs at each end, and device 200 is operable. Specifically, layers 330 and 350 help confine charge carriers within layer 340, which serves as a type of quantum well. In one embodiment, each nanorod structure is 200 nanometers wide and 1 micrometer long; however, smaller dimensions and different aspect ratios are also possible and considered within the scope of the illustrative embodiments.

[0067] Using MZMs in quantum computing devices requires the ability to perform parity measurements of MZM pairs. An illustrative embodiment uses a quantum dot-based measurement scheme to perform MZM parity measurements. Specifically, quantum dot 220, a portion of the sensing region of device 200, is a semiconductor line connected to one end of each of nanorod structures 230 and 232. A tunnel junction gate 204 is used to control the amplitude of electron tunneling between quantum dot 220 and the MZMs in nanorod structures 230 and 232, to which quantum dot 220 can be selectively coupled. When not measuring the MZM state, all coupling is turned off, leaving the MZM islands and quantum dots with a fixed charge. In the decoupled state, ambient noise coupled to the charge has no effect on the MZMs. Therefore, noise cannot measure the qubit state unless a measurement is in progress, and thus causes the qubit state to collapse. To measure the MZM state, the tunnel junction gate is activated, causing an energy shift observable using, for example, the quantum dot charge.

[0068] Sensing region gate 202 is coupled to quantum dot 220 and is used to sense the electron density in the quantum dot. Nanorod contacts 206 and 212 are coupled to the superconducting portion of nanorod structure 230 and are used to guide current through the superconducting portion of nanorod structure, thereby imparting superconductivity to the surface of the semiconductor portion of nanorod structure to enable device 200 to function. Chemical potential gates 208 and 210 are used to modulate the chemical potential of the nanorod, such that the nanorod accommodates MZM at each end. Tunnel junction gate 204 also includes a dielectric portion coupled to the superconducting portion and a metallic portion coupled to the dielectric portion, and is used to pinch off the conductivity of the nanorod during device operation. Sensing region gate 202, tunnel junction gate 204, and quantum dot 220 together constitute the sensing region of device 200.

[0069] refer to Figure 3 The figure depicts a block diagram of an example configuration achieved in the fabrication of a Majorana Fermi quantum computing device according to an illustrative embodiment. Figure 1 Application 105 interacts with manufacturing system 107 to produce or manipulate configuration 300 as described herein. Substrate 310, buffer layer 320, protective layer 330, semiconductor layer 340, and protective layer 350 are... Figure 2 The substrate 310, buffer layer 320, protective layer 330, semiconductor layer 340 and protective layer 350 are the same.

[0070] Substrate 310 comprises a material that, when operating in a low-temperature range, exhibits a residual resistivity (RRR) of at least 100 and a thermal conductivity greater than 1 W / (cm×K) at 4 Kelvin. RRR is the ratio of the resistivity of the material at room temperature to that at 0 K; since 0 K cannot be reached in practice, an approximation at 4 K is used. For example, substrate 310 may be formed using sapphire, silicon, quartz, gallium arsenide (GaAs), fused silica, amorphous silicon, indium phosphide (InP), or diamond to operate in a temperature range from 77 K to 0.01 K. These examples of substrate materials are not limiting. Based on this disclosure, those skilled in the art will be able to conceive of many other materials suitable for forming substrate 310, and such materials are contemplated within the scope of the illustrative embodiments.

[0071] The embodiments enable the fabrication system to epitaxially grow a buffer layer 320, an epitaxial semiconductor, on a substrate 310. The material used for the buffer layer 320 is selected based on the composition of the substrate 310 and the protective layer 330. In one embodiment, the buffer layer 320 is formed of indium aluminum arsenide (InAlAs) to match the lattice of the adjacent protective layer 330. In one embodiment, the buffer layer 320 has a gradually changing composition from the substrate 310 to the protective layer 330 to avoid the formation of crystal defects, such as dislocations, in the protective layer 330. In one embodiment, the gradual change in composition is linear. For example, if the substrate 310 comprises GaAs and the protective layer 330 comprises InAs, it is difficult to grow a sufficiently high-quality InAs layer directly on the GaAs of the substrate 310. Therefore, the buffer layer 320 begins with the substrate 310 having GaAs, and the gallium is gradually replaced by indium to eventually match the InAs of the protective layer 330. These examples of materials are not limiting. Based on this disclosure, those skilled in the art will be able to conceive of many other materials suitable for forming the buffer layer 320, and such materials can be envisioned within the scope of the illustrative embodiments.

[0072] The embodiments allow the manufacturing system to epitaxially grow a protective layer 330, an epitaxial semiconductor, on a buffer layer 320. The materials used for protective layers 330 and 350 are selected based on the composition of semiconductor layer 340 to provide crystal quality above a specific quality threshold. In embodiments using a 1:1 ratio of InAs to semiconductor layer 340, protective layers 330 and 350 use indium gallium arsenide (InGaAs) at a ratio of 0.8In:1Ga:0.2As. In embodiments using indium gallium arsenide (InGaAs), a ratio of 0.7In:1Ga:0.3As is used for semiconductor layer 340; and in embodiments using indium gallium arsenide (InGaAs), a ratio of 0.53In:1Ga:0.47As or 0.52In:1Ga:0.48As is used for protective layers 330 and 350. In embodiments using InSb for semiconductor layer 340, In0.80-0.90Al0.1-0.2Sb (using InAlSb with a ratio of 1In to 0.8-0.9Al to 0.1-0.2Sb) is used for protective layers 330 and 350. In embodiments using InP as the substrate, protective layer 330 is lattice-matched to the InP of substrate 310. However, protective layers 330 and 350 need not be formed of the same material. Furthermore, protective layer 350 is not required. These examples of materials are not limiting. From this disclosure, those skilled in the art will be able to conceive of many other materials suitable for forming protective layers 330 and 350, and such materials are contemplated within the scope of the illustrative embodiments. In one embodiment, protective layer 330 is approximately 4 nm thick; however, thicker or thinner layers are also possible and contemplated within the scope of the illustrative embodiments.

[0073] The embodiments allow the manufacturing system to epitaxially grow a semiconductor layer 340 on a protective layer 330. In these embodiments, the semiconductor layer 340 is formed of indium arsenide (InAs) using a 1:1 In:As ratio, indium gallium arsenide (InGaAs) using a 0.7In:1Ga:0.3As ratio, or indium antimony (InSb). These examples of substrate materials are not limiting. Based on this disclosure, those skilled in the art will be able to conceive of many other materials suitable for forming the substrate 310, and such materials are contemplated within the scope of the illustrative embodiments. In one embodiment, the semiconductor layer 340 is approximately 7 nm thick; however, thicker or thinner layers are also possible and are considered to be within the scope of the illustrative embodiments.

[0074] The embodiments allow the fabrication system to epitaxially grow a protective layer 350 on semiconductor layer 340, thus epitaxially growing the semiconductor. In one embodiment, protective layer 350 is approximately 5 nm thick; however, thicker or thinner layers are also possible and considered within the scope of the illustrative embodiments. Protective layers 330 and 350 protect the surface of semiconductor layer 340 from damage during fabrication. Damaged portions of semiconductor layer 340 can degrade device performance. Therefore, protective layer 350 may not be necessary on the quantum dot structure if the risk of damage during fabrication is sufficiently low. Furthermore, protective layers 330 and 350 need not be made of the same material.

[0075] refer to Figure 4 The figure depicts a block diagram of an example configuration achieved in the fabrication of a Majorana Fermi quantum computing device according to an illustrative embodiment. Figure 1 Application 105 interacts with manufacturing system 107 to produce or manipulate configuration 400 as described herein. Substrate 310, buffer layer 320, protective layer 330, semiconductor layer 340, and protective layer 350 are... Figure 3 The substrate 310, buffer layer 320, protective layer 330, semiconductor layer 340 and protective layer 350 are the same.

[0076] The embodiments employ a manufacturing system using physical vapor deposition (PVD), such as evaporation or sputtering, to deposit a superconducting layer 410 on a protective layer 350 (or a semiconductor layer 340, if a protective layer 350 is not used). The superconducting layer 410 is formed of a material that is superconducting in a low temperature range of 77 K to 0.01 K. Aluminum (Al), niobium, lead, tantalum nitride, titanium, titanium nitride, and vanadium are non-limiting examples of suitable materials for the superconducting layer 410; however, many other materials are suitable for forming the superconducting layer 410, and the same materials are contemplated within the scope of the exemplary embodiments. In the embodiments, the thickness of the superconducting layer 410 is between 5 and 50 nm, preferably between 20 and 30 nm; however, thicker or thinner layers are also possible and are considered to be within the scope of the illustrative embodiments.

[0077] refer to Figure 5 The figure depicts a block diagram of an example configuration achieved in the fabrication of a Majorana Fermi quantum computing device according to an illustrative embodiment. Figure 1 Application 105 interacts with manufacturing system 107 to produce or manipulate configuration 500 as described herein. Substrate 310, buffer layer 320, protective layer 330, semiconductor layer 340, protective layer 350, and superconductor layer 410... Figure 4 The substrate 310, buffer layer 320, protective layer 330, semiconductor layer 340, protective layer 350 and superconductor layer 410 are the same.

[0078] The embodiment allows the fabrication system to deposit a resist layer 510 formed with a resist pattern on the superconductor layer 410. The resist pattern protects the nanorod regions 520 and 530 and the sensing region 540 from upcoming device processing steps. The resist layer 510 can be formed from any resist material used in photolithography.

[0079] The description of the resist layer formed in the resist pattern and the description of the photolithography technique should not be construed as limiting the manner in which the structure described herein is formed. The described pattern is merely a simplified and generalized example. The described structure can be photolithographically shaped in many ways. For example, the structure is currently achieved by patterning the resist with photolithography (light) or electron beam lithography (electron beam), developing the resist, and then subtracting the deposited material from openings in the resist or depositing material in openings in the resist. Finally, the resist is removed. Manufacturing processes and techniques are constantly evolving, and other methods of forming the described structure are within the scope of consideration for the illustrative embodiments, provided that the resulting structure has the electrical, mechanical, thermal, and operational properties as described herein.

[0080] refer to Figure 6 The figure depicts a block diagram of an example configuration achieved in the fabrication of a Majorana Fermi quantum computing device according to an illustrative embodiment. Figure 1 Application 105 interacts with manufacturing system 107 to produce or manipulate configuration 600 as described herein. Substrate 310, buffer layer 320, protective layer 330, semiconductor layer 340, protective layer 350, superconductor layer 410, and resist layer 510... Figure 5 The substrate 310, buffer layer 320, protective layer 330, semiconductor layer 340, protective layer 350, superconductor layer 410 and resist layer 510 are the same.

[0081] The embodiment causes the manufacturing system to perform an etching process to remove portions of the superconductor layer 410 and expose the protective layer 350 in areas not protected by the resist layer 510. The etching process also creates etched regions 610, which are undercut regions within the superconductor layer 410 beneath the resist layer 510. The etching process is selected to minimize surface damage during manufacturing. In one embodiment, the etching process is a wet etching process, such as using tetramethylammonium hydroxide (TMAH).

[0082] refer to Figure 7 The figure depicts a block diagram of an example configuration achieved in the fabrication of a Majorana fermion quantum computing device according to an illustrative embodiment. Figure 1 Application 105 interacts with manufacturing system 107 to produce or manipulate configuration 700 as described herein. Substrate 310, buffer layer 320, protective layer 330, semiconductor layer 340, protective layer 350, superconductor layer 410, and resist layer 510... Figure 6The substrate 310, buffer layer 320, protective layer 330, semiconductor layer 340, protective layer 350, superconductor layer 410 and resist layer 510 are the same.

[0083] The embodiment enables the manufacturing system to perform an ion implantation process. The ion implantation process disrupts the crystal structure of exposed portions of the semiconductor layer 340, forming an implantation region 710. In the implantation region 710, the semiconductor layer 340 is non-conductive, thereby forming an isolation region surrounding the device being manufactured. The ion implantation process uses ions from any material suitable for forming the isolation region. Some non-limiting examples of suitable ion implantation materials include hydrogen, oxygen, helium, gallium, argon, and neon. Other ion implantation materials are also possible and are considered to be within the scope of the illustrative embodiment.

[0084] refer to Figure 8 The figure depicts a block diagram of an example configuration achieved in the fabrication of a Majorana Fermi quantum computing device according to an illustrative embodiment. Figure 1 Application 105 interacts with manufacturing system 107 to produce or manipulate configuration 800 as described herein. Substrate 310, buffer layer 320, protective layer 330, semiconductor layer 340, protective layer 350, superconductor layer 410, resist layer 510, and implantation region 710 are... Figure 7 The substrate 310, buffer layer 320, protective layer 330, semiconductor layer 340, protective layer 350, superconductor layer 410, resist layer 510 and implantation region 710 are the same.

[0085] The embodiment allows the manufacturing system to deposit a resist layer 810 patterned with resist onto a resist layer 510 and portions of the underlying surface exposed through openings in the resist layer 510. The resist pattern protects areas other than the resist openings 820 from upcoming device processing steps. The resist layer 810 can be formed from any resist material used in photolithography and can be the same or a different material from the resist layer 510.

[0086] refer to Figure 9 The figure depicts a block diagram of an example configuration achieved in the fabrication of a Majorana Fermi quantum computing device according to an illustrative embodiment. Figure 1 Application 105 interacts with manufacturing system 107 to produce or manipulate configuration 900 as described herein. Substrate 310, buffer layer 320, protective layer 330, semiconductor layer 340, protective layer 350, superconductor layer 410, resist layer 510, implantation region 710, resist layer 810, and resist opening 820 are... Figure 8The substrate 310, buffer layer 320, protective layer 330, semiconductor layer 340, protective layer 350, superconductor layer 410, resist layer 510, implantation region 710, resist layer 810 and resist opening 820 are the same.

[0087] The embodiment causes the manufacturing system to perform an etching process to remove the superconductor layer 410 to expose the protective layer 350 in areas not protected by the resist layer 810. The etching process also creates etched regions 910, i.e., undercut regions, within the superconductor layer 410 beneath the resist layers 510 and 810. The etching process is selected to minimize surface damage during manufacturing and can be the same as or different from the process used to form configuration 600. In one embodiment, the etching process is a wet etching process, such as using tetramethylammonium hydroxide (TMAH).

[0088] refer to Figure 10 The figure depicts a block diagram of an example configuration achieved in the fabrication of a Majorana Fermi quantum computing device according to an illustrative embodiment. Figure 1 Application 105 interacts with manufacturing system 107 to produce or manipulate configuration 1000 as described herein. Substrate 310, buffer layer 320, protective layer 330, semiconductor layer 340, protective layer 350, superconductor layer 410, and implantation region 710 are... Figure 9 The substrate 310, buffer layer 320, protective layer 330, semiconductor layer 340, protective layer 350, superconductor layer 410 and implantation region 710 are the same.

[0089] The embodiment performs a resist removal process on the manufacturing system to remove resist layers 510 and 810, exposing portions of the superconductor layer 410 and the protective layer 350. The embodiment uses any resist removal process used in photolithography. As a result, in configuration 1100, portions of the protective layer 350 are exposed in a region on one side of the superconductor layer 410.

[0090] refer to Figure 11 The figure depicts a block diagram of an example configuration achieved in the fabrication of a Majorana Fermi quantum computing device according to an illustrative embodiment. Figure 1 Application 105 interacts with manufacturing system 107 to produce or manipulate configuration 1100 as described herein. Substrate 310, buffer layer 320, protective layer 330, semiconductor layer 340, protective layer 350, superconductor layer 410, and implantation region 710 are... Figure 10 The substrate 310, buffer layer 320, protective layer 330, semiconductor layer 340, protective layer 350, superconductor layer 410 and implantation region 710 are the same.

[0091] Configuration 1100 is a mask appropriately configured in the resist layer 510 during the photolithography process, omitting the manufacturing steps described in reference configurations 800 and 900, and optionally from... Figure 7 Configuration 700 is an achievable configuration. In configuration 1100, a portion of the protective layer 350 is exposed in the region surrounding the superconductor layer 410. Configurations 1000 and 1100 are performed similarly; however, configuration 1100 is preferred because it uses fewer process steps than configuration 1000.

[0092] refer to Figure 12 The figure depicts a block diagram of an example configuration achieved in the fabrication of a Majorana Fermi quantum computing device according to an illustrative embodiment. Figure 1 Application 105 interacts with manufacturing system 107 to produce or manipulate configuration 1200 as described herein. Substrate 310, buffer layer 320, protective layer 330, semiconductor layer 340, protective layer 350, superconductor layer 410, and implantation region 710 are... Figure 11 The substrate 310, buffer layer 320, protective layer 330, semiconductor layer 340, protective layer 350, superconductor layer 410 and implantation region 710 are the same. Configuration 1200 is described as the result of operation configuration 1000, but it can also be the result of operation configuration 1100.

[0093] The embodiment allows the fabrication system to deposit a resist layer 1210, which includes an opening in an exposed region 1220, comprising portions of a protective layer 350 and a superconductor layer 410. Region 1220 is intended to be a sensing region of device 200. The resist layer 1210 can be formed from any resist material used in photolithography and can be the same as or different from resist layers 510 and 810.

[0094] refer to Figure 13 The figure depicts a block diagram of an example configuration achieved in the fabrication of a Majorana Fermi quantum computing device according to an illustrative embodiment. Figure 1 Application 105 interacts with manufacturing system 107 to produce or manipulate configuration 1300 as described herein. Substrate 310, buffer layer 320, protective layer 330, semiconductor layer 340, protective layer 350, superconductor layer 410, implantation region 710, and resist layer 1210 are... Figure 12 The substrate 310, buffer layer 320, protective layer 330, semiconductor layer 340, protective layer 350, superconductor layer 410, implantation region 710 and resist layer 1210 are the same.

[0095] The embodiment causes the manufacturing system to perform an etching process to remove the superconductor layer 410 to expose the protective layer 350 in region 1310, including the undercut region within the superconductor layer 410 beneath the resist layer 1210. The etching process is selected to minimize surface damage during manufacturing and may be the same as or different from the process used to form configuration 600. In one embodiment, the etching process is a wet etching process, such as using tetramethylammonium hydroxide (TMAH).

[0096] refer to Figure 14 The figure depicts a block diagram of an example configuration achieved in the fabrication of a Majorana Fermi quantum computing device according to an illustrative embodiment. Figure 1 Application 105 interacts with manufacturing system 107 to produce or manipulate configuration 1400 as described herein. Substrate 310, buffer layer 320, protective layer 330, semiconductor layer 340, protective layer 350, superconductor layer 410, and implantation region 710 are... Figure 13 The substrate 310, buffer layer 320, protective layer 330, semiconductor layer 340, protective layer 350, superconductor layer 410 and implantation region 710 are the same.

[0097] The embodiment enables the manufacturing system to perform a resist removal process, removing the resist layer 1210 and exposing portions of the superconductor layer 410 and the protective layer 350. The embodiment uses any resist removal process used in photolithography. Alternatively, the resist, etching, and resist removal steps described with reference to configurations 1200 and 1300 can be combined with a mask of appropriate configuration used in the photolithography process for resist layers 510 or 810.

[0098] refer to Figure 15 The figure depicts a block diagram of an example configuration achieved in the fabrication of a Majorana Fermi quantum computing device according to an illustrative embodiment. Figure 1 Application 105 interacts with manufacturing system 107 to produce or manipulate configuration 1500 as described herein. Substrate 310, buffer layer 320, protective layer 330, semiconductor layer 340, protective layer 350, superconductor layer 410, and implantation region 710 are... Figure 14 The substrate 310, buffer layer 320, protective layer 330, semiconductor layer 340, protective layer 350, superconductor layer 410, and implantation region 710 are identical. The tunnel junction gate 204 and chemical potential gates 208 and 210 are the same as those in the original text. Figure 2 The tunnel junction gate 204 and chemical potential gates 208 and 210 are the same.

[0099] The embodiment allows the manufacturing system to deposit a photoresist 1530 on configuration 1400, subsequently forming a dielectric 1520 on portions of configuration 1400 exposed by openings in the photoresist layer, and then forming a metal 1510 on the dielectric 1520. The photoresist 1530 can be formed from any photoresist material used in photolithography and can be the same or different from other photoresist layers described herein. In one embodiment, the dielectric 1520 is formed from a natural oxide on a superconducting layer 410 (e.g., if the superconducting layer 410 comprises aluminum, alumina), and the metal 1510 is deposited on top of the dielectric 1520 using any photolithography process for metal deposition. In another embodiment, the dielectric 1520 is formed by adding additional oxygen, nitrogen, or another material to the initial metal deposition, followed by additional metal deposition using any photolithography process without the additional oxygen, nitrogen, or another material. In yet another embodiment, the dielectric 1520 and the metal 1510 are independent of each other.

[0100] Metal 1510 includes materials having high electrical and thermal conductivity (above the threshold RRR and above the threshold thermal conductivity) in a low-temperature range for operation in a temperature range from 77 K to 0.01 K. While superconducting metals in the low-temperature range are preferred because they have very low thermal resistance, non-superconducting metals may also be used. Some non-limiting examples of materials for metal 1510 are gold, palladium, vanadium, aluminum, lead, tin, platinum, niobium, tantalum, tantalum nitride, titanium, and titanium nitride. Dielectric 1520 can be formed of any suitable material. Some non-limiting examples of materials for dielectric 1520 are alumina or another natural oxide on superconducting layer 410, silicon oxide, and zinc oxide. These examples of layer materials are not limiting. Based on this disclosure, those skilled in the art will be able to conceive of many other materials suitable for forming dielectric 1520 and metal 1510, and the same materials are conceived within the scope of the illustrative embodiments. The dielectric 1520 and metal 1510 on the protective layer 350 form a tunnel junction gate 204, which can be used to pinch off the conductivity of the nanorods during operation of the device being manufactured. Due to the presence of the protective layer 350, the dielectric 1520 is not necessary for the formation of the tunnel junction gate 204, but if present, the dielectric 1520 does not affect the operation of the gate. The dielectric 1520 and metal 1510 on the superconducting layer 410 form chemical potential gates 208 and 210, which can be used to control the chemical potential of the nanorods during operation of the device being manufactured, allowing the nanorods to accommodate MZMs at each end.

[0101] refer to Figure 16 The figure depicts a block diagram of an example configuration achieved in the fabrication of a Majorana Fermi quantum computing device according to an illustrative embodiment. Figure 1Application 105 interacts with manufacturing system 107 to produce or manipulate configuration 1600 as described herein. Substrate 310, buffer layer 320, protective layer 330, semiconductor layer 340, protective layer 350, superconductor layer 410, implantation region 710, metal 1510, dielectric 1520, and photoresist 1530 are... Figure 15 The substrate 310, buffer layer 320, protective layer 330, semiconductor layer 340, protective layer 350, superconductor layer 410, implantation region 710, metal 1510, dielectric 1520, and photoresist 1530 are the same. The tunnel junction gate 204 and chemical potential gates 208 and 210 are the same as those in the original text. Figure 2 The tunnel junction gate 204 and chemical potential gates 208 and 210 are the same.

[0102] Specifically, configuration 1600 is an alternative to configuration 1500, wherein the contact region 1610 extends beyond the chemical potential gates 208 and 210 on the superconductor layer 410. Because quasiparticles (electrons or electron pairs) can cause a loss of coherence if they enter the nanorod structure, the contact region 1610 reduces the likelihood of coherence loss by instead routing quasiparticles along the outer edge of the nanorod structure. In one embodiment, the contact region 1610 also extends into the isolation region 240.

[0103] refer to Figure 17 The figure depicts a block diagram of an example configuration achieved in the fabrication of a Majorana Fermi quantum computing device according to an illustrative embodiment. Figure 1 Application 105 interacts with manufacturing system 107 to produce or manipulate configuration 1700 as described herein. Substrate 310, buffer layer 320, protective layer 330, semiconductor layer 340, protective layer 350, superconductor layer 410, implantation region 710, tunnel junction gate 204, and chemical potential gates 208 and 210 are... Figure 16 The substrate 310, buffer layer 320, protective layer 330, semiconductor layer 340, protective layer 350, superconductor layer 410, implantation region 710, tunnel junction gate 204, and chemical potential gates 208 and 210 are the same.

[0104] The embodiment causes the manufacturing system to perform a resist removal process, thereby removing resist 1530 from configuration 1500 or 1600 (not shown) and exposing the underlying portion of configuration 1700. The embodiment uses any resist removal process used in photolithography.

[0105] refer to Figure 18 The figure depicts a block diagram of an example configuration achieved in the fabrication of a Majorana Fermi quantum computing device according to an illustrative embodiment. Figure 1Application 105 interacts with manufacturing system 107 to produce or manipulate configuration 1800 as described herein. Substrate 310, buffer layer 320, protective layer 330, semiconductor layer 340, protective layer 350, superconductor layer 410, and implantation region 710 are... Figure 17 The substrate 310, buffer layer 320, protective layer 330, semiconductor layer 340, protective layer 350, superconductor layer 410 and implantation region 710 are the same.

[0106] The embodiment allows the manufacturing system to deposit a photoresist 1810 on configuration 1700, with openings in the photoresist 1810 in regions 1820, 1830, and 1840, followed by the formation of metal 1510 on dielectric 1520. The photoresist 1810 can be formed from any photoresist material used in photolithography and can be the same as or different from other photoresist layers described herein.

[0107] refer to Figure 19 The figure depicts a block diagram of an example configuration achieved in the fabrication of a Majorana Fermi quantum computing device according to an illustrative embodiment. Figure 1 Application 105 interacts with manufacturing system 107 to produce or manipulate configuration 1900 as described herein. Substrate 310, buffer layer 320, protective layer 330, semiconductor layer 340, protective layer 350, superconductor layer 410, implantation region 710, and photoresist 1810 are... Figure 18 The substrate 310, buffer layer 320, protective layer 330, semiconductor layer 340, protective layer 350, superconductor layer 410, implantation region 710 and photoresist 1810 are the same.

[0108] The embodiment allows the manufacturing system to form metal 1910 on a portion of configuration 1800 exposed by openings in the resist 1810. Metal 1910 is deposited using any suitable metal deposition process and can be formed from any metal as described herein. Metal 1910 on the protective layer 350 forms the sensing region gate 202. Metal 1910 on the superconducting layer 410 forms nanorod contacts 206 and 212.

[0109] refer to Figure 20 The figure depicts a block diagram of an example configuration achieved in the fabrication of a Majorana Fermi quantum computing device according to an illustrative embodiment. Figure 1 Application 105 interacts with manufacturing system 107 to produce or manipulate configuration 2000 as described herein. Substrate 310, buffer layer 320, protective layer 330, semiconductor layer 340, protective layer 350, superconductor layer 410, implantation region 710, and photoresist 1810 are... Figure 19The substrate 310, buffer layer 320, protective layer 330, semiconductor layer 340, protective layer 350, superconductor layer 410, implantation region 710, and resist 1810 are identical. The sensing region gate 202, tunnel junction gate 204, nanorod contacts 206 and 212, chemical potential gates 208 and 210, quantum dot structure 220, nanorod structures 230 and 232, and isolation region 240 are also identical. Figure 2 The sensing region gate 202, tunnel junction gate 204, nanorod contacts 206 and 212, chemical potential gates 208 and 210, quantum dot structure 220, nanorod structures 230 and 232, and isolation region 240 are the same.

[0110] The embodiment causes the manufacturing system to perform a resist removal process, removing resist 1910 from configuration 1900 and exposing the underlying portion of configuration 1900. The embodiment uses any resist removal process used in photolithography. As a result, configuration 2000 is the complete form of device 200.

[0111] refer to Figure 21 The figure depicts a flowchart of an example process for fabricating a Majorana fermion quantum computing device according to an illustrative embodiment. In one or more embodiments, process 2100 is implemented in application 105, which enables, for example... Figure 1 The manufacturing system 107 in the document performs the operations described herein.

[0112] In block 2102, the application causes the fabrication system to sequentially form a buffer layer, a first protective layer, a semiconductor layer, and a superconductor layer on a substrate surface. In block 2104, the application causes the fabrication system to form a first resist pattern on the superconductor layer defining a device region and a sensing region within the device region. In block 2106, the application causes the fabrication system to use an etching process to remove the superconductor layer within the sensing region and expose a region of the underlying semiconductor layer outside the device region not protected by the first resist pattern. In block 2108, the application causes the fabrication system to implant the exposed region of the semiconductor layer to form an isolation region surrounding the device region. In block 2110, the application causes the fabrication system to use an etching process to expose portions of the device region of the superconductor layer adjacent to the sensing region and the isolation region. In block 2112, the application causes the fabrication system to form a tunnel junction gate within the sensing region and a chemical potential gate within a portion of the device region outside the transmitting region by depositing a dielectric layer and a metal layer. In block 2114, the application uses a fabrication system to form a sensing region gate within the sensing region and nanorod contacts within a portion of the device region outside the transmitting region by depositing a second metal layer. Then, process 2100 ends.

[0113] Various embodiments of the invention are described herein with reference to the accompanying drawings. Alternative embodiments may be devised without departing from the scope of the invention. Although various connections and positional relationships between elements (e.g., top, bottom, above / above, below / below, adjacent, etc.) are illustrated in the following description and drawings, those skilled in the art will recognize that many of the positional relationships described herein are orientation-independent, provided that the described functionality is maintained even if the orientation is changed. Unless otherwise stated, these connections and / or positional relationships may be direct or indirect, and the invention is not intended to be limited in this respect. Thus, coupling of entities may refer to direct or indirect coupling, and positional relationships between entities may be direct or indirect positional relationships. As an example of an indirect positional relationship, the reference in this specification to forming layer "A" above layer "B" includes cases where one or more intermediate layers (e.g., layer "C") are between layer "A" and layer "B," provided that the relevant characteristics and functions of layer "A" and layer "B" are substantially not altered by the intermediate layers.

[0114] The following definitions and abbreviations are used to interpret the claims and specification. As used herein, the terms “comprising,” “including,” “having,” “containing,” or any other variations thereof are intended to cover a non-exclusive inclusion. For example, a composition, mixture, process, method, article, or apparatus that comprises a list of elements is not necessarily limited to those elements, but may include other elements not explicitly listed or inherent to such composition, mixture, process, method, article, or apparatus.

[0115] Additionally, the term "illustrative" is used herein to mean "serving as an example, illustration, or description." Any embodiment or design described herein as "illustrative" is not necessarily to be construed as preferred or advantageous over other embodiments or designs. The terms "at least one" and "one or more" are understood to include any integer greater than or equal to one, i.e., one, two, three, four, etc. The term "multiple" should be understood to include any integer greater than or equal to two, i.e., two, three, four, five, etc. The term "connection" can include both indirect "connection" and direct "connection."

[0116] References to "an embodiment," "an embodiment," "an exemplary embodiment," etc., in this specification indicate that the described embodiment may include a particular feature, structure, or characteristic; however, each embodiment may or may not include that particular feature, structure, or characteristic. Furthermore, these phrases do not necessarily refer to the same embodiment. Additionally, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is believed that incorporating other embodiments to affect that feature, structure, or characteristic is within the knowledge of those skilled in the art, regardless of whether it is explicitly described.

[0117] The terms “about,” “substantially,” “approximately,” and variations thereof are intended to include a degree of error associated with a measurement of a specific quantity based on the equipment available at the time of filing this application. For example, “about” may include a range of ±8%, 5%, or 2% of a given value.

[0118] Various embodiments of the invention have been described for illustrative purposes, but are not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein has been chosen to best explain the principles of the embodiments, their practical application, or improvements to existing technologies on the market, or to enable others skilled in the art to understand the embodiments described herein.

Claims

1. A quantum computing device, comprising: The device region located on the superconductor layer above the semiconductor layer; A sensing region located within the device region, the sensing region including a portion of the device region excluding the superconductor layer; The tunnel junction gate includes a first metal within the sensing region; A chemical potential gate, comprising a dielectric and the first metal within a portion of the device region outside the sensing region; A sensing region gate includes a second metal coupled to the semiconductor layer within the sensing region; as well as The nanorod contact includes a second metal within the superconducting layer of the device region coupled to the outside of the sensing region.

2. The quantum computing device of claim 1, wherein the device region includes a first nanorod region, a second nanorod region substantially parallel to the first nanorod region, and the sensing region, the sensing region connecting the first nanorod region and the second nanorod region.

3. The quantum computing device according to claim 1 or 2, further comprising: A buffer layer formed on the first surface of the substrate; A first protective layer is formed on the buffer layer; as well as The semiconductor layer formed on the first protective layer.

4. The quantum computing device of claim 3, wherein the buffer layer comprises indium aluminum arsenide.

5. The quantum computing device of claim 3, wherein the first protective layer comprises indium gallium arsenide.

6. The quantum computing device according to claim 1 or 2, wherein the superconducting layer comprises aluminum.

7. The quantum computing device according to claim 1 or 2, further comprising: A second protective layer is formed between the semiconductor layer and the superconductor layer.

8. The quantum computing device according to claim 1 or 2, further comprising: An isolation region surrounding the device region, the isolation region including the area where the superconductor layer has been removed and the semiconductor layer has been implanted.

9. A computer-implemented method for fabricating a quantum computing device, the method comprising: A first resist pattern is formed on a superconductor layer, the first resist pattern defining a device region and a sensing region within the device region; The superconductor layer within the sensing region is removed using an etching process, the etching exposing a region of the underlying semiconductor layer outside the device region that is not protected by the first resist pattern; The implantation is performed on the exposed areas of the semiconductor layer, forming an isolation region surrounding the device region; Following the implantation, an etching process is used to expose the sensing region and a portion of the device region of the superconductor layer adjacent to the isolation region; A tunnel junction gate is formed by depositing a first metal layer within the sensing region; The sensing region gate is formed by coupling the semiconductor layer to the second metal layer; as well as Nanorod contacts are formed within the portion of the device region outside the sensing region using the second metal.

10. The computer-implemented method of claim 9, wherein the device region includes a first nanorod region, a second nanorod region substantially parallel to the first nanorod region, and the sensing region, the sensing region connecting the first nanorod region and the second nanorod region.

11. The computer-implemented method according to claim 9 or 10, further comprising: A buffer layer is formed on the first surface of the substrate; A first protective layer is formed on the buffer layer; The semiconductor layer is formed on the first protective layer; as well as The superconductor layer is formed on the semiconductor layer.

12. The computer-implemented method of claim 11, wherein the buffer layer comprises indium aluminum arsenide.

13. The computer-implemented method of claim 11, wherein the first protective layer comprises indium gallium arsenide.

14. The computer-implemented method according to claim 9 or 10, wherein the superconducting layer comprises aluminum.

15. The computer-implemented method according to claim 9 or 10, further comprising: A second protective layer is formed between the semiconductor layer and the superconductor layer.

16. The computer-implemented method according to claim 9 or 10, further comprising: The first resist pattern is removed before the first metal layer is deposited.

17. The computer-implemented method according to claim 9 or 10, further comprising: A chemical potential gate is formed by depositing a dielectric layer and the first metal layer within the portion of the device region outside the sensing region.

18. The computer-implemented method of claim 9 or 10, wherein the deposition of the first metal layer is performed in an area defined by a second resist pattern.

19. The computer-implemented method of claim 17, wherein the second metal layer is formed by depositing the second metal layer in a region defined by a third resist pattern, the third resist pattern protecting the tunnel junction gate and the chemical potential gate.

20. A superconductor fabrication system including photolithography components, the superconductor fabrication system performing operations including the following when operating on at least one bare die to fabricate a quantum computing device: A first resist pattern is formed on a superconductor layer, the first resist pattern defining a device region and a sensing region within the device region; The superconductor layer within the sensing region is removed using an etching process, the etching exposing a region of the underlying semiconductor layer outside the device region that is not protected by the first resist pattern; The implantation is performed on the exposed areas of the semiconductor layer, forming an isolation region surrounding the device region; Following the implantation, an etching process is used to expose the sensing region and a portion of the device region of the superconductor layer adjacent to the isolation region; A tunnel junction gate is formed by depositing a first metal layer within the sensing region; The sensing region gate is formed by coupling the semiconductor layer to the second metal layer; as well as Nanorod contacts are formed within the portion of the device region outside the sensing region using the second metal.

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