Circuit and method for maintaining gain of a continuous time linear equalizer

Abstract

The bias structure includes a reference voltage node connected to gate structures of the first and second NMOS transistors, a bias voltage node including a bias voltage, and a first operational amplifier having a first input connected to the reference voltage, a second input connected to a drain of the first NMOS transistor, and an output connected to gate structures of the first and second PMOS transistors. The bias structure also includes a second operational amplifier having a first input connected to the reference voltage, a second input connected to a drain of the second NMOS transistor, and an output connected to gate structures of the third NMOS transistor and the bias voltage node. The first NMOS transistor matches a transistor of a differential pair of the integrated circuit device.

Description

[0001] Cross-references to related applications

[0002] This application claims the benefit of U.S. Patent Application No. 17 / 099,183, filed November 16, 2020, and U.S. Provisional Patent Application No. 62 / 944,817, filed December 6, 2019, the disclosures of which are incorporated herein by reference in their entirety. Technical Field

[0003] This application generally relates to data receivers, and more specifically to data receivers with analog equalizers. Background Technology

[0004] Differential signal processing circuits, such as variable gain amplifiers (VGAs) and continuous-time linear equalizers (CTLEs), receive a specific frequency-dependent gain and apply it to the input differential signal to generate the output differential signal. Typically, the input differential signal is received at the control terminal (e.g., the gate) of the input transistor (e.g., a field-effect transistor (FET)), and the output differential signal is generated at other terminals (e.g., the drain) of the input transistor.

[0005] The effective DC voltage level of a differential signal is commonly referred to as the common-mode voltage. The common-mode voltage is generally the average voltage between the voltage levels of the positive and negative components of the differential signal. The common-mode voltage affects the operating point of the device to which the differential signal is applied. If the common-mode voltage changes, the operating point of the device will change, which can have adverse consequences.

[0006] In the context of differential signal processing circuitry, the input differential signal applied to the input transistor may have a common-mode voltage that varies due to various reasons. The gain applied to the input differential signal by the differential signal processing circuitry results in the output differential signal having a common-mode voltage that varies with the common-mode voltage of the input differential signal. Furthermore, process variations within the differential signal processing circuitry itself can also cause common-mode voltage variations. As a result, the input transistors experience varying common-mode voltage levels, which has the adverse effect of reduced gain and peak control in the differential signal processing circuitry. Additionally, the varying common-mode voltage of the output differential signal may adversely affect the operation of one or more devices downstream of the differential signal processing circuitry. Summary of the Invention

[0007] According to one implementation, the receiver circuit includes: an analog equalizer including a first transistor connected in series with a first resistor and a first current source; and a bias circuit including a second transistor connected in series with a second current source, the bias circuit further including a second resistor between the second current source and the third transistor, a first operational amplifier having a first input coupled to the gate of the second transistor and a second input coupled to the source of the third transistor, and a second operational amplifier having a third input coupled to the gate of the second transistor and a fourth input coupled to the drain of the second transistor, the output of the second operational amplifier providing a gate voltage to the first current source and to the second current source.

[0008] According to one implementation, a method for operating an equalizer circuit includes: maintaining the drain voltage of the first transistor and the drain voltage of the second transistor equal to the gate voltage of the first transistor at a first bias circuit having a first transistor and a second transistor arranged in a branch of a current mirror; generating a current from a first current source connected in series with the branch of the current mirror, wherein the gate voltage of the first current source is provided by a first operational amplifier (op amp) disposed between the gate of the first transistor and the drain of the second transistor; and applying the gate voltage to a second current source within the equalizer circuit.

[0009] According to another implementation, a semiconductor chip includes: a first bias circuit having a first transistor and a second transistor disposed in a first current mirror, the first bias circuit further having a first current source coupled to the first transistor and the second transistor, the first bias circuit further having a first operational amplifier coupled to the drain of the second transistor and the gate of the first transistor and coupled to output a first bias voltage to the gate of the first current source; a second bias circuit having a second operational amplifier coupled to output a second bias voltage to the gate of a third transistor; and an equalizer circuit having a fourth transistor and a fifth transistor disposed in a second current mirror, the fourth transistor being connected in series with the second current source, the second current mirror being coupled to a power rail via a sixth transistor, wherein the second current source is coupled to the first bias voltage, and wherein the sixth transistor is coupled to the second bias voltage.

[0010] According to another implementation, a data receiver in a semiconductor chip includes: a component for shaping a differential data signal, the shaping of the differential data signal including applying a gain to the differential data signal, wherein the gain is equal to the transconductance of a first transistor multiplied by a resistance; a component for adjusting the current through the first transistor, including a component for applying a bias voltage to a current source in the shaping component, wherein the bias voltage applying component includes: a second transistor and a third transistor arranged in a current mirror architecture; and a first operational amplifier coupled to the drain of the second transistor and the gate of the third transistor, and having a feedback loop configured to adjust the bias voltage; and a component for deserializing the differential data signal.

[0011] According to another implementation, the bias structure includes: a reference voltage node connected to the gate structure of a first NMOS transistor and a second NMOS transistor; a bias voltage node including a bias voltage; a first operational amplifier having: a first input connected to the reference voltage; a second input connected to the drain of the first NMOS transistor; and an output connected to the gate structure of the first PMOS transistor and the second PMOS transistor; and a second operational amplifier having: a first input connected to the reference voltage; a second input connected to the drain of the second NMOS transistor; and an output connected to the gate structure of a third NMOS transistor and the bias voltage node; wherein the first NMOS transistor is a transistor of a differential pair in an integrated circuit device. Attached Figure Description

[0012] Figure 1 This is a diagram of an example data transmission and receiving circuit based on one implementation.

[0013] Figure 2 This is a diagram based on an example chip-to-chip data transfer architecture, including, for example... Figure 1 Multiple data transmission and receiving circuits in the system.

[0014] Figure 3 This is a diagram of an example bias generator that can execute methods based on various implementations.

[0015] Figure 4 It is based on an implementation that can utilize from Figure 3 An example of the bias current of a bias current generator is illustrated in the diagram of a continuous-time linear equalizer.

[0016] Figure 5 It is based on an implementation that can be with Figure 4 An illustration of an example bias generator used in conjunction with an equalizer.

[0017] Figure 6The illustration shows an improvement based on an approach that achieves consistent gain at different PVT inflection points at different frequencies.

[0018] Figure 7 The illustration shows an improvement in consistent gain at different PVT inflection points based on one implementation.

[0019] Figure 8 It is based on an implementation of an operational equalizer (such as...) Figure 4 A diagram illustrating an example method for an equalizer. Detailed Implementation

[0020] Based on the principles described in this paper, improvements have been made to the continuous-time linear equalizer (CTLE) to improve the consistency of gain and common-mode voltage at various process, voltage, and temperature (PVT) inflection points. Integrated circuits are affected by variations in circuit operating conditions. For example, the manufacturing process may vary slightly during the fabrication of integrated circuits. Furthermore, circuits may sometimes operate within a range of voltages and temperatures. Each of these varying conditions can affect circuit performance. These extremes of process variation can be referred to as PVT inflection points. It is desirable for the circuit to perform well at different PVT inflection points (in other words, under different conditions).

[0021] The CTLE described in this paper can be used as part of a receiver, for example, a serial-to-deserializer (SerDes) circuit. The CTLE in a SerDes circuit acts to compensate for channel losses. For a specific channel, the loss may be constant for a specific frequency of interest. However, for some conventional CTLEs, the gain varies at the PVT inflection point at both low and high frequencies of interest (e.g., the Nyquist frequency) (e.g., 10 GHz for a 20-Gb / s data rate). Handling this gain variation can be costly and detrimental to circuit performance. A mechanism is needed to maintain a constant CTLE gain at different PVT inflection points.

[0022] Some methods utilize a constant transconductance multiplied by a resistance (gm*R) structure to generate the bias current for CTLE, ensuring that the gain gm*R at the PVT inflection point will be constant. However, due to non-ideal bias conditions and second-order effects at advanced technology nodes, it is difficult to keep the gain variation within a tolerable range at the PVT inflection point using this technique.

[0023] Based on the principles described herein, the bias circuit is designed to mimic the actual bias conditions of the CTLE circuit operation. Therefore, as the PVT conditions change, the bias voltage generated by the bias structure will change to maintain a substantially consistent gain across the PVT inflection point of the CTLE. Simultaneously, a common-mode feedback (CMFB) circuit is also used to maintain consistent output common-mode voltage. Although this specification describes a bias circuit for the CTLE circuit, it should be understood that such a bias circuit can also be applied to other integrated circuit components.

[0024] For example, in one instance, the bias circuit is implemented as a current mirror, where one branch of the current mirror includes a first transistor, and the other branch includes a second transistor and a resistor. The first and second transistors are replicas of the transistors in the equalizer circuit, and the resistor is a replica of the resistor in the equalizer circuit. For instance, the transistors in the bias circuit can be constructed to have the same size as the transistors in the equalizer circuit and be located on the same semiconductor chip as the equalizer circuit. The same applies to the resistors. Since the bias circuit and the equalizer are constructed on the same chip, it is expected that their different components (e.g., transistors, resistors, etc.) will likely undergo similar process variations.

[0025] Furthermore, it can be expected that during normal operation, the transistors and resistors of both the bias circuit and the equalizer circuit will experience the same voltage and temperature range. And since the different components are structurally identical or similar, the effects of voltage and temperature should be common among similar components.

[0026] A bias circuit can be constructed such that its gain (gm*R) is the same as the gain of the equalizer circuit to which it provides the bias voltage. In one implementation, this bias circuit maintains the DC operating point of its transistor over a range of voltages and temperatures, thus providing more precise bias control than a similar bias circuit that does not maintain the DC operating point. For example, this bias circuit can use operational amplifiers to maintain the drain voltage of its transistor at a stable reference voltage.

[0027] Continuing with the example of the bias circuit, it can provide a bias voltage to the current source in the equalizer circuit. By biasing the current source, the bias circuit maintains a constant gain for the equalizer, because the gain of the bias circuit itself is also constant.

[0028] Furthermore, various implementations include common-mode feedback circuits that operate to maintain the common-mode voltage within the equalizer circuitry. Specifically, some implementations include circuitry that biases transistors within the equalizer, where the bias of the transistors determines the transistors' resistance. The transistors' resistance can adjust the common-mode voltage across the PVT to maintain the common-mode voltage at a consistent level and at the same level experienced by the common-mode voltage within the common-mode feedback circuitry.

[0029] Various implementations can include advantages over other systems. For example, the bias circuit described herein can include improved accuracy due to its control over its DC operating level. Improved bias circuit accuracy can also lead to improved equalizer accuracy. Equalizer accuracy is desirable because it reduces the chance of data bits being misread by downstream sampling circuitry. Furthermore, various implementations can further improve accuracy by maintaining a constant common-mode voltage across the entire voltage and temperature range.

[0030] Figure 1 This is a diagram of an example data transmission and reception system 100 according to one implementation. System 100 includes a transmitter 110 having a termination impedance matched to the characteristic impedance of a transmission channel 120. Transmitter 110 receives high-speed serialized digital data (labeled "data") as a series of high and low voltage values ​​at its data input. In this example, the signal is a differential signal having two parts (n and p).

[0031] Transmission channel 120 provides a data link between transmitter 110 and receiver 131, and includes equalizer 130 and deserializer 135. Transmission channel 120 can be embodied in any suitable structure, such as a cable, metal traces on a printed circuit board, or metal wires connecting chips in a package. Figure 1 In this diagram, transmission channel 120 is shown as a transmission line to emphasize its similarity to a typical transmission line, including having characteristic impedance and a resistance-capacitance (RC) time constant.

[0032] Equalizer 130 receives the transmitted data signal from transmission channel 120 and shapes the received data signal, which may be distorted due to transmission line reflections, RC attenuation, or other phenomena. System 100 uses equalizer 130 to shape the digital signal so that it is output from equalizer 130 in a form that more closely matches the approximate square wave shape of the signal output from transmitter 110. After being shaped by equalizer 130, the signal enters deserializer 135, after which the serial high-speed data is converted into parallel low-speed output.

[0033] Digital circuitry 140 may include triggers or other data recovery circuitry to capture the value of the data signal when it appears at the data output port of receiver 131. Shaping the digital signal using equalizer circuitry 130, including applying appropriate gain, can reduce the risk of errors when capturing the data signal. As further explained below, equalizer 130 can provide substantially constant gain over a range of processes, voltages, and temperatures.

[0034] Figure 2 It is based on an implementation. Figure 1 and Figures 3 to 5 A diagram illustrating an example application of a signal transmission system. Figure 2 The diagram illustrates system 200, in which system-on-chip (SOC) 210 communicates with memory chip 220. SOC 210 communicates with memory chip 220 via transmission channel 215.

[0035] The SOC 210 includes multiple processing units (not shown) implemented in the chip. These processing units can include any suitable device, examples of which include mobile station modems, multi-core central processing units (CPUs), graphics processing units (GPUs), digital signal processors (DSPs), 802.11x modems, and / or the like. In some examples, the SOC 210 is specifically designed for mobile devices such as smartphones, such that the processing units are designed for low power consumption. However, the scope of implementation is not limited to any particular SOC architecture.

[0036] The memory chip 220 in this example includes any suitable memory chip for use in a computing device having a SOC 210. Examples include static random access memory (SRAM) chips, dynamic random access memory (DRAM) chips, synchronous dynamic random access memory (SDRAM) chips, and electrically erasable programmable read-only memory (flash memory) chips, but the scope of implementation is not limited to any particular memory chip. During a write operation, memory chip 220 receives data from SOC 210 via transmission channel 215, and then the memory controller at memory chip 220 stores the data in the memory cells of the memory chip. During a read operation, memory chip 220 receives a read request for specific data from SOC 210, and then the memory controller of memory chip 220 accesses the data from the individual memory cells of the memory chip and transmits these data bits to SOC 210 via transmission channel 215.

[0037] Figure 2 The system may include Figure 1 and Figures 3 to 5 The system implementation is shown below. In one example, Figure 2System 200 operates according to one or more DDR standards, wherein memory chip 220 is a DDR SDRAM chip. Memory chip 220 includes multiple receiver circuits configured to receive data via corresponding transmission channels 215. It is anticipated that a number of receivers and a number of transmitters will be present at memory chip 220; therefore, transmitters and receivers are uniformly shown at TX / RX circuit 224. Each receiver circuit in the receiver circuitry is as described above regarding... Figure 1 and Figures 3 to 5 To operate as described, including having, as about Figure 8 The equalizer operates as described in method 800. Each independent transmission channel in independent transmission channel 215 is associated with... Figure 1 The transmission channel 120 is the same as or similar to the transmission channel 120, including characteristic impedance and frequency response.

[0038] Similarly, the SOC 210 also has multiple receiver circuits configured to receive data via corresponding transmission channels 215. In this example, the transmitter and receiver of the SOC 210 are collectively represented as the TX / RX circuit 212. Each receiver circuit in the receiver circuitry is described above regarding... Figure 1 and Figures 3 to 5 To operate as described, including having, as about Figure 8 The equalizer operates as described in method 800. Although not described in detail herein, it should be understood that the transmitter circuit in each of the TX / RX circuits 212 and 224 can have the same characteristics as... Figure 1 The transmitter circuit 110 has a similar structure and operation.

[0039] Figure 3 The diagram illustrates a bias circuit 300 according to one implementation. According to this example, the structure includes a first operational amplifier 320 and a second operational amplifier 321. The first operational amplifier 320 receives a reference voltage Vref and a voltage v1 as inputs. Voltage v1 is applied to the drain of transistor 301 and the drain of transistor 303. Operational amplifier 320 outputs a voltage v0, which is applied to the gates of transistors 301 and 302. The inputs of operational amplifier 321 are the reference voltage Vref and a voltage v2 at the node where the drains of coupled transistors 302 and 304 are located. The source of transistor 304 is coupled to a resistor 306. Resistor 306 is located between the source of transistor 304 and the drain of transistor 305. The source of transistor 303 is also coupled to the drain of transistor 305.

[0040] The gate of transistor 305 is coupled to the output of operational amplifier 321, and its voltage is referred to as the bias voltage Vbias. In this example, transistor 305 is also referred to as a current source. The current from its source to its drain is equal to the current 310 plus 311, which depends on the gate voltage Vbias.

[0041] The bias circuit 300 forms a current mirror with two branches. Therefore, current 310 mirrors current 311, and thus currents 310 and 311 are approximately the same in this implementation. Operational amplifiers 320 and 321 are arranged such that voltages v1 and v2 are kept the same as Vref. As a result, the DC operating point of transistor 303 is kept constant over a range of voltages and temperatures. For example, the performance of transistors 303 and 304 may change as the voltage or temperature may change, and even the resistance of resistor 306 may change. However, voltages v1 and v2 are kept constant, and even though currents 310 and 311 may change with temperature and voltage, the transconductance of transistor 303 multiplied by the resistance of resistor 306 remains constant, as does the DC operating point of transistor 303.

[0042] Within this temperature and voltage range, the bias can be changed as currents 310 and 311 and the resistance of resistor 306 can be varied. As current 310 increases, current 311 also increases, and Vbias decreases due to feedback between the output of operational amplifier 320 and its input at v1, and between the output of operational amplifier 321 and its input at v2. Conversely—as currents 310 and 311 decrease, Vbias increases. Therefore, Vbias is used as feedback-based adaptive bias control to maintain... Figure 4 The gain of the equalizer circuit 400 is constant.

[0043] Transistor 303 was designed to mimic Figure 4 Transistor 403 in the example is explained in more detail below. The gate, source, and drain voltages of transistor 303 are biased by operational amplifiers 320 and 321 at the same values ​​as those of transistor 403. Vref is the target / design common-mode voltage, and it can be provided by a stable voltage source such as a bandgap generator. In this example, VDD includes the voltage from the power rail. Vref can be, for example, VDD-220mV, but the range of implementations is not limited to any particular value.

[0044] Using the proposed bias structure, the transconductance of transistor 303 multiplied by the resistance of resistor 306 is constant. A bias voltage Vbias is generated and applied to... Figure 5 The current source is 405. Its advantage is that the gain can be varied. Figure 4The equalizer circuit 400 is internally controlled within 1dB at the PVT inflection point, as explained in more detail below.

[0045] Figure 4 This is a diagram of an example continuous-time linear equalizer (CTLE) 400 adapted according to one implementation. The equalizer circuit 400 has a three-stage design, each stage (stages 1-3) being substantially the same. Therefore, inductors 427, 428, 437, and 438 are substantially the same as inductors 407 and 408; resistors 426, 429, 436, and 439 are substantially the same as resistors 406 and 409; transistors 423 and 433 are substantially the same as transistor 403; transistors 424 and 434 are substantially the same as transistor 404; and transistors 425, 422, 435, and 432 are substantially the same as transistors 405 and 412.

[0046] The differences between stages include the impedance between the sources of transistors 403 / 404, 423 / 424, and 433 / 434. For example, the sources of transistors 403 and 404 are coupled via an RC impedance consisting of an 80Ω resistor and a 5pF capacitor, while the other stages 2 and 3 have impedance components of different sizes with similar placement.

[0047] It should be noted that Figure 4 Specific values ​​for resistors, capacitors, inductors, currents, etc., are provided, and these values ​​are merely examples. Other implementations can appropriately use different values ​​to achieve the desired equalization. Furthermore, other implementations can use different numbers of stages in the equalizer, and any one or more stages can be adapted according to the principles described herein to provide stable gain on the PVT.

[0048] The equalizer circuit 400 receives the differential data signals Inn and Inp and outputs reshaped data signals Outn and Outp, which can then be deserialized and latched. The equalizer circuit 400 applies a gain to the signal, which at stage 1 is equal to the transconductance of transistor 403 multiplied by the resistance of resistor 406 (i.e., gm*R). Figure 3 The bias circuit provides a bias voltage Vbias, which operates to maintain gm*R constant over voltage and temperature. In fact, the other stages 2-3 have essentially the same bias conditions as stage 1, thus each state has a constant gain.

[0049] First, let's look at stage 1, which includes a current mirror with two branches. The first branch includes inductor 407, resistor 406, transistor 403, and transistor 405. The second branch includes inductor 408, resistor 409, transistor 404, and transistor 412. Current 410 mirrors current 411, and therefore the magnitudes of currents 410 and 412 are substantially equal in this implementation.

[0050] Transistor 303 is a copy of transistor 403. In other words, in this implementation, transistors 303 and 403 are built on the same semiconductor chip and have the same nominal characteristics. It is assumed that any process changes affecting transistor 403 will also affect transistor 303. Similarly, transistor 304 is a copy of transistor 404, transistor 305 is a copy of transistor 405 (both referred to herein as current sources), and resistor 306 is a copy of resistor 406. Due to this replication, Figure 3 The components of the bias circuit 300 are assumed to operate under the same or similar PVT conditions as the components in each stage of the equalizer circuit 400.

[0051] The bias voltage Vbias is adjusted upwards or downwards depending on the PVT variation within the bias circuit 300. Therefore, the adjusted Vbias is provided to current sources 405 and 412 in stage 1 to adjust currents 410 and 411. Adjusting currents 410 and 411 adjusts the transconductance of transistor 403 to maintain a constant gain across the range of PVT variation. Specifically, the transconductance of transistor 403 is adjusted such that the transconductance of transistor 403 multiplied by the resistance of resistor 406 (i.e., gm*R) is also kept constant, even though the resistance of resistor 406 may vary across the PVT. Similarly, the bias voltage is applied to current sources 414-417 in stages 2-3 to maintain gm*R in the same manner.

[0052] Figure 5 This is a diagram of another example of a bias circuit 500 according to one implementation. The bias circuit 500 is implemented according to... Figure 5 The feedback loop shown in the diagram adjusts the voltage Vbp to adjust. Figure 4 The resistor of transistor 413.

[0053] exist Figure 5 In the example, transistor 513 is Figure 4 A replica of transistor 413. Similarly, resistor 506 is a replica of resistor 406, transistor 503 is a replica of transistor 403, and current source 505 is a replica of current source 405. Voltage Vcom is a replica of the common-mode voltage of stage 1 of equalizer circuit 400. Specifically, in equalizer circuit 400, the common-mode voltage is equal to Vdd minus the product of current 410 and resistance of resistor 406. Any resistance from transistor 413 can be added to the resistance of resistor 406 to calculate the common-mode voltage of stage 1. Bias circuit 500 generates Vbp to adjust the resistance of transistor 413 so that the product of current 410 and resistance is constant.

[0054] Referring to bias circuit 500, operational amplifier 520 is arranged such that it receives Vref at one input and Vcom at the other input, thereby forcing Vcom equal to Vref. As temperature and voltage change during operation, the resistance value of resistor 506 can change, and the operating parameters of any of transistors 503, 505, and 513 can also be altered. As a result of this change, the feedback loop of bias circuit 500 changes the resistance value of transistor 513 to increase or decrease current 510. The feedback loop of bias circuit 500 changes the resistance value of transistor 513 by adjusting the gate voltage Vbp.

[0055] Voltage Vbp is applied to Figure 4 Transistor 413 is used to adjust its resistance in the same way as the resistance of transistor 513. The result is that, despite any process variations that could potentially affect bias circuits 300 and 500, and even over a certain range of voltage and temperature, the common-mode voltage of stage 1 of equalizer circuit 400 is maintained substantially constant. By keeping the common-mode voltage in stage 1 constant, bias circuit 500 ensures that the behavior of transistors 303 and 304 replicates that of transistors 403 and 404, thus maintaining Vbias adjustment constant gm*R.

[0056] Similarly, voltage Vbp is also applied to transistors 418 and 419 of equalizer circuit 400. Therefore, Vbp adjusts the common-mode voltage at stages 2 through 3 in the same way as stage 1, so that the gain remains constant across stages 1 through 3.

[0057] Figure 5 The implementation described herein offers advantages over other common-mode feedback (CMFB) designs. For example, a CMFB design can tune the bias current, multiplying it by a resistor to obtain the target common-mode voltage. However, because the transconductance is determined by the bias current, the gain can change even if a constant common-mode voltage is achieved. In contrast, the implementation described herein maintains both the common-mode voltage and the gain substantially constant. A different technique could include adding some bleed current at the drain of the differential pair. By tuning the bleed current, a constant common-mode voltage can be obtained without affecting the gain. However, this could consume more power and introduce more output parasitics compared to bias circuit 500. (Using the information in this paper...) Figures 3 to 5 The described principle can overcome these challenges, and the gain and common-mode voltage can remain essentially consistent at different PVT inflection points without increasing parasitic effects or wasting current due to discharge.

[0058] Figure 6The illustration shows the gain at various frequencies at various PVT inflection points according to an implemented CTLE device, which has a bias circuit 300 and an equalizer circuit 400 working together. Figure 6 Based on simulation. Figure 6 Each line in the graph represents the gain across different PVT inflection points. As can be seen, the variation between the lines is low and acceptable for some applications seeking to minimize gain variation across the PVT.

[0059] Figure 7 The illustration shows an implementation of gain across different voltages at two different frequencies, 1 MHz and 10 GHz, with bias circuit 300 and equalizer circuit 400 working together. Figure 7 Based on simulations, as can be seen, the gain variation is very low and acceptable for some applications seeking to minimize the gain variation on the PVT.

[0060] Figure 8 This is a diagram based on an implementation of a method 800 for operating an equalizer. For example, Figure 8 It can be by Figures 3 to 5 The circuit shown is used to perform this because bias circuits 300 and 500 maintain the gain of equalizer circuit 400 substantially constant over the PVT range.

[0061] Action 810 includes: maintaining the drain voltage of the first transistor and the drain voltage of the second transistor equal to the gate voltage of the first transistor within the bias circuit. Figure 3 An example is shown where operational amplifiers 320 and 321 are used to force the drain voltages of transistors 303 and 304 to the same voltage level. Furthermore, the drain voltages are forced to the same level as a reference voltage Vref. In some examples, Vref may be provided by a bandgap generator or other stabilizing voltage generator to remain constant over a range of voltages and temperatures. The value of Vref can be set such that the gate voltages of transistors 303 and 304 are expected to be maintained at appropriate levels, even if the transconductance of one or both of transistors 303 and 304 may vary over the operating voltage and temperature range.

[0062] exist Figure 3 In this example, transistors 303 and 304 are arranged in separate branches of the current mirror, each branch being connected in series with current source 305. At operation 820, the bias circuit generates current through the first current source connected in series with the branch of the current mirror. In this example, the gate voltage of the current source is provided by an operational amplifier positioned between the gate of the first transistor and the drain of the second transistor.

[0063] exist Figure 3In the example, current source 305 generates a current influenced by its gate voltage Vbias. Operational amplifier 321 has inputs at the gate of transistor 303 and the drain of transistor 304, and has an output that provides Vbias to the gate of current source 305. Figure 3 In the architecture, one of the operational amplifier inputs is coupled to the drain of transistor 304 to create a feedback loop, which causes Vbias to decrease as currents 310 and 311 increase, and to increase as currents 310 and 311 decrease.

[0064] At action 830, the bias circuit applies the gate voltage to another current source within the equalizer circuit. For example, in Figure 4 In the example, the bias voltage Vbias is provided to the current source 405, which is... Figure 3 The current source 305 is replicated. Vbias is also provided to another current source 412 in another current mirror branch of stage 1 of equalizer circuit 400. Similarly, Vbias is also provided to current sources 414 to 417 of stages 2 to 3 of equalizer circuit 400.

[0065] In example method 800, the arrangement of operational amplifiers 320, 321 maintains the transconductance of bias circuit 300 multiplied by resistance (gm*R) substantially constant across the operating voltage and temperature range. Since transistors 303, 304 and resistor 306 are built on the same chip as the equalizer circuit with transistors 403, 404 and resistor 406, similarity to process variations can be expected, and therefore a certain amount of process variation can be tolerated. The arrangement of operational amplifiers 320, 321 results in the bias voltage Vbias being able to adaptively change upward or downward in response to changes in currents 310, 311, to maintain gm*R constant in bias circuit 300 and in stages 1 through 3 of equalizer circuit 400.

[0066] The scope of implementation is not limited to Figure 8 Actions 810 to 830 are shown in the diagram. Conversely, various implementations may add, omit, modify, or rearrange one or more actions. For example, method 800 may also include actions attributed to... Figure 5 The operation of the bias circuit 500. Specifically, method 800 may further include adjusting an additional bias voltage to cause adjustment of resistive components (e.g., transistors 413, 418, 419) to maintain a constant common-mode voltage. For example, the bias circuit 500 may maintain the common-mode voltage of the equalizer at the same level as the common-mode voltage of the bias circuit 500. Figure 5In the example, the common-mode voltage is kept constant by an operational amplifier configured with a feedback loop to adjust its output. The output of the operational amplifier is used as another bias voltage. As a result, the equalizer can maintain gm*R constant more precisely than if the common-mode voltage variation were allowed.

[0067] As will now be understood by those skilled in the art, and depending on the specific application at hand, many modifications, substitutions, and variations can be made to the materials, apparatus, configurations, and methods of using the devices disclosed herein without departing from the spirit and scope of the invention. Therefore, the scope of this disclosure should not be limited to the specific implementations illustrated and described herein, as they are merely examples, but should be fully proportionate to the scope of the appended claims and their functional equivalents.

Claims

1. A receiver circuit, comprising: An analog equalizer, the analog equalizer including a first transistor connected in series with a first resistor and a first current source; as well as A bias circuit includes a second transistor connected in series with a second current source and a second resistor between the second current source and a third transistor, the gate of the third transistor being coupled to the gate of the second transistor. The bias circuit also includes a first operational amplifier having a first input coupled to the gate of the second transistor and a second input coupled to the drain of the third transistor, and a second operational amplifier having a third input coupled to the gate of the second transistor and a fourth input coupled to the drain of the second transistor. The first operational amplifier provides a gate voltage to the second current source, the output of the second current source is coupled to the first current source, and the output of the second operational amplifier provides a gate voltage to a transistor coupled to a power rail.

2. The receiver circuit according to claim 1 further includes: An additional bias circuit with a third operational amplifier, the third operational amplifier providing a gate voltage for a fourth transistor and receiving a reference voltage, and receiving a feedback voltage from the fourth transistor, wherein the gate voltage for the fourth transistor is provided to the gate of a fifth transistor coupled to a power rail in the analog equalizer.

3. The receiver circuit of claim 1, wherein the second transistor is a copy of the first transistor, and wherein the second current source is a copy of the first current source.

4. The receiver circuit of claim 1, wherein the second resistor comprises a replica of the first resistor.

5. The receiver circuit of claim 1, wherein the gate of the second transistor is coupled to the output of the bandgap voltage generator.

6. The receiver circuit of claim 1, wherein the first transistor includes a gate coupled to a data input from a transmission line.

7. The receiver circuit of claim 1, wherein the first transistor and the first current source are part of a first branch of a current mirror, the current mirror having a second branch, wherein the first branch is coupled to a first portion of a differential data signal, and wherein the second branch is coupled to a second portion of the differential data signal.

8. The receiver circuit of claim 1, wherein the first transistor is disposed between the first resistor and the first current source.

9. The receiver circuit of claim 1, wherein the first current source is disposed between the first transistor and ground.

10. The receiver circuit of claim 1, wherein the bias circuit includes a current mirror, and wherein the second transistor is disposed in a first branch of the current mirror and the third transistor and the second resistor are disposed in a second branch of the current mirror, further wherein the second current source is disposed between the second resistor and ground.

11. A method for operating an equalizer circuit, the method comprising: At a first bias circuit having a first transistor and a second transistor arranged in a branch of a current mirror, the drain voltage of the first transistor and the drain voltage of the second transistor are maintained equal to the gate voltage of the first transistor. A current is generated by a first current source connected in series with a branch of the current mirror, wherein the gate voltage of the first current source is provided by a first operational amplifier (op amp), which is disposed between the gate of the first transistor and the drain of the second transistor; as well as The gate voltage of the first current source is applied to the second current source within the equalizer circuit; Maintain the transconductance of the first bias circuit multiplied by the resistance (gm) within the range of process inflection point, operating voltage, and operating temperature. R) is constant; as well as Maintain the gm of the equalizer circuit R is equal to the gm of the first bias circuit. R.

12. The method of claim 11, further comprising: At the second bias circuit, a bias voltage is generated for the gate of the third transistor in the equalizer circuit, wherein generating the bias voltage includes maintaining the common-mode voltage of the equalizer circuit at the same level as the common-mode voltage of the second bias circuit.

13. A semiconductor chip, comprising: A first bias circuit has a first transistor and a second transistor arranged in a first current mirror. The first bias circuit also has a first current source coupled to the first transistor and the second transistor. The first bias circuit also has a first operational amplifier (op amp) having a first input coupled to the drain of the second transistor and a second input coupled to the gate of the first transistor, and a first output coupled to output a first bias voltage to the gate of the first current source. The gate of the first transistor is coupled to a reference voltage. The second bias circuit has a second operational amplifier, which has a third input for receiving a reference voltage and a fourth input for receiving a feedback voltage from a third transistor and is coupled to output a second bias voltage to the gate of the third transistor. as well as An equalizer circuit has a fourth transistor and a fifth transistor arranged in a second current mirror, the fourth transistor being connected in series with a second current source, the second current mirror being coupled to a power rail via a sixth transistor, wherein the second current source is coupled to a first bias voltage, and wherein the sixth transistor is coupled to a second bias voltage.

14. The semiconductor chip of claim 13, comprising a system-on-a-chip (SOC) having a multi-core processor configured to communicate with a memory chip via the equalizer circuitry.

15. The semiconductor chip of claim 13, comprising a memory chip configured to communicate with a system-on-a-chip (SoC) via the equalizer circuitry.

16. The semiconductor chip of claim 13, wherein the first transistor is a copy of the fourth transistor, and wherein the first current source is a copy of the second current source.

17. The semiconductor chip of claim 13, wherein the fourth transistor includes a gate coupled to a data input from a transmission line.

18. The semiconductor chip of claim 13, wherein the fourth transistor and the second current source are part of a first branch of the second current mirror, the second current mirror having a second branch, wherein the first branch is coupled to a first portion of the differential data signal, and wherein the second branch is coupled to a second portion of the differential data signal.

19. The semiconductor chip according to claim 13, further comprising: A first resistor is coupled between the fourth transistor and the sixth transistor; as well as A second resistor is coupled between the second transistor and the first current source, wherein the second resistor is a replica of the first resistor.

20. The semiconductor chip of claim 13, wherein the third transistor is a copy of the sixth transistor.

21. The semiconductor chip of claim 13, further comprising a deserializer coupled to the output of the equalizer circuit.

22. A data receiver in a semiconductor chip, the data receiver comprising: A component for shaping differential data signals, wherein shaping differential data signals includes applying a gain to the differential data signals, wherein the gain is equal to the transconductance of a first transistor in the component for shaping differential data signals multiplied by its resistance. The component for adjusting the current through the first transistor includes a component for applying a bias voltage to the current source in the shaping component, wherein the bias voltage applying component includes: The second and third transistors are arranged in a current mirror architecture; A first operational amplifier has a first input coupled to the drain of the second transistor and a second input coupled to the gate of the third transistor, and a first output coupled to output a first bias voltage to the gate of the current source; and The second operational amplifier has a third input coupled to the gate of the third transistor and a fourth input coupled to the drain of the third transistor, and is coupled to output a second bias voltage to the gate of the fourth transistor, the gate of the third transistor being coupled to a reference voltage; and A component used to deserialize differential data signals.

23. The data receiver according to claim 22, further comprising: A component used to adjust the resistance of the shaping component.

24. The data receiver of claim 23, wherein the resistance adjustment component comprises: A component used to maintain the common-mode voltage of the shaping component.

25. The data receiver of claim 22, wherein the third transistor is a copy of the first transistor.

26. The data receiver of claim 22, wherein the bias voltage application component further comprises a second operational amplifier coupled to the drain of the third transistor and coupled to the gate of the third transistor.

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