Method of data access using dynamic speed adjustment by means of a thermal control unit and related device

Abstract

A data access method using dynamic speed adjustment by means of a thermal control unit and related apparatus are provided. The data access method includes: monitoring temperature at a predetermined controller-in-location of a memory controller using a thermal control unit within the memory controller; in response to at least one access request from a host device, controlling a transmission interface circuit of the memory controller to perform data transmission between the host device and the memory controller at an original communication speed to access data in a non-volatile memory; in response to the temperature being greater than a first temperature threshold, detecting an increase amount of the temperature between a first start time point and a first end time point; determining a first communication speed according to the increase amount based on at least one first predetermined rule; and switching from the original communication speed to the first communication speed.

Description

Technical Field

[0001] The present invention relates to memory control, and more particularly to a data access method using dynamic speed adjustment by means of a thermal control unit and related apparatus such as a memory device, a memory controller of the memory device, and an electronic system having the memory device. Background Art

[0002] Advances in memory technology have enabled the widespread use of various portable and non-portable memory devices (e.g., memory cards conforming to SD / MMC, CF, MS, XD, or UFS specifications, solid-state drives (SSDs), and embedded storage devices conforming to UFS or EMMC specifications). Improving access control for these memory devices has long been a challenge in the field.

[0003] NAND flash memory can include single-level cell (SLC) and multiple-level cell (MLC) flash memory. In SLC flash memory, each transistor used as a memory cell can have either of two charge values ​​corresponding to logical values ​​0 and 1, respectively. In contrast, in MLC flash memory, the storage capacity of each transistor used as a memory cell can be fully utilized. The transistors in MLC flash memory can be driven by a higher voltage than the transistors in SLC flash memory, and different voltage levels can be used to record at least two bits of information (e.g., 00, 01, 11, or 10). Theoretically, the recording density of MLC flash memory can be at least twice that of SLC flash memory, and is therefore preferred by NAND flash memory manufacturers.

[0004] The low cost and large capacity of MLC flash memory mean it is more likely to be used in memory devices than SLC flash memory. However, MLC flash memory does have instability issues. To ensure that access control to the flash memory in a memory device meets the required specifications, the flash memory controller may be equipped with certain management mechanisms to properly manage data access.

[0005] However, even memory devices equipped with the aforementioned management mechanisms may have certain drawbacks. For example, during data access to the memory device, high-speed data transfer can lead to heat accumulation, which can degrade memory device performance or, in particular, cause memory device failure. Therefore, a novel method and related architecture are needed to improve memory device performance without or with minimal potential for adverse effects. Summary of the Invention

[0006] An object of the present invention is to provide a data access method using dynamic speed adjustment with the aid of a thermal control unit, and related apparatus such as a memory device, a memory controller of the memory device, and an electronic system having the memory device, to solve the above-mentioned problems.

[0007] Another object of the present invention is to provide a data access method using dynamic speed adjustment with the aid of a thermal control unit, and related apparatus such as a memory device, a memory controller of the memory device, and an electronic system having the memory device, so as to achieve optimal performance of the memory device.

[0008] At least one embodiment of the present invention discloses a data access method using dynamic speed adjustment with the aid of a thermal control unit. The data access method is applicable to a memory controller of a memory device, the memory device including the memory controller and non-volatile (NV) memory, the NV memory including at least one NV memory element. The data access method includes: monitoring temperature at a predetermined intra-controller location of the memory controller using the thermal control unit within the memory controller; controlling a transmission interface circuit of the memory controller to transmit data between the host device and the memory controller at an original communication speed in response to at least one access request from a host device to access data in the NV memory; and detecting an increase in the temperature between a first start time point and a first end time point in response to the temperature being greater than a first temperature threshold, wherein a first period from the first start time point to the first end time point is a time interval. The invention relates to a method for controlling the transmission interface circuit to switch from the original communication speed to the first communication speed so as to perform data transmission between the host device and the memory controller at the first communication speed. The method comprises the following steps:

[0009] In addition to the above method, the present invention also provides a memory controller for a memory device, the memory device comprising the memory controller and a non-volatile (NV) memory, the non-volatile memory comprising at least one NV memory element. The memory controller comprises a processing circuit, a transmission interface circuit, and a memory device protection circuit. The processing circuit is configured to control the memory controller based on a plurality of host commands from a host device, thereby allowing the host device to access the NV memory through the memory controller. The transmission interface circuit is coupled to the processing circuit and configured to communicate with the host device. The memory device protection circuit is coupled to the processing circuit and configured to protect the memory device, wherein the memory device protection circuit comprises a thermal control unit. The thermal control unit is configured to perform thermal control to trigger dynamic speed adjustment during data access. For example, the memory controller uses the thermal control unit to monitor the temperature at a predetermined location within the memory controller; in response to at least one access request from the host device, the memory controller controls the transmission interface circuit to perform data transmission between the host device and the memory controller at an original communication speed to access data in the non-volatile memory; in response to the temperature being greater than a first temperature threshold, the memory controller detects an increase in the temperature between a first starting time point and a first ending time point, wherein a first period from the first starting time point to the first ending time point corresponds to a first predetermined time difference; based on at least one first predetermined rule, the memory controller determines a first communication speed according to the increase; and the memory controller controls the transmission interface circuit to switch from the original communication speed to the first communication speed to perform data transmission between the host device and the memory controller at the first communication speed.

[0010] In addition to the above method, the present invention also provides the memory device comprising the above memory controller, wherein the non-volatile memory is configured to store information, and the memory controller is coupled to the non-volatile memory and configured to control the operation of the memory device.

[0011] The method and related apparatus of the present invention ensure that the memory device operates correctly under various conditions without encountering the problems of the related art. For example, the data access method provides multiple control schemes for access control. By utilizing the method and related apparatus of the present invention, the memory device is free from the existing problems of the related art, such as performance degradation and malfunction. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1is a schematic diagram of an electronic system according to an embodiment of the present invention, wherein the electronic system includes a host device and a memory device.

[0013] Figure 2 A temperature-aware speed control scheme for a data access method using dynamic speed adjustment with the aid of a thermal control unit according to one embodiment of the present invention is illustrated.

[0014] Figure 3 FIG. 1 is a diagram illustrating an embodiment of the present invention. Figure 2 Some implementation details of the timer of the temperature-aware speed control scheme are shown.

[0015] Figure 4 FIG. 1 is a diagram illustrating an embodiment of the present invention. Figure 2 Some implementation details of the thermal control unit of this temperature-aware speed control scheme are shown.

[0016] Figure 5 A deceleration control scheme of the data access method according to an embodiment of the present invention is illustrated.

[0017] Figure 6 FIG. 1 is a diagram illustrating an embodiment of the present invention. Figure 5 A workflow of the deceleration control scheme is shown.

[0018] Figure 7 An acceleration control scheme of the data access method according to an embodiment of the present invention is illustrated.

[0019] Figure 8 FIG. 1 is a diagram illustrating an embodiment of the present invention. Figure 7 A workflow of the acceleration control scheme is shown.

[0020] Figure 9 is a flow chart of the data access method using dynamic speed adjustment with the thermal control unit according to one embodiment of the present invention.

[0021]

Explanation of symbols

[0022] 10: Electronic Systems

[0023] 50: Host device

[0024] 52: Processor

[0025] 54: Power supply circuit

[0026] 100: Memory device

[0027] 110: Memory Controller

[0028] 112: Microprocessor

[0029] 112M: Read Only Memory (ROM)

[0030] 112C: Program code

[0031] 114: Control logic circuit

[0032] 114F: Flash memory controller

[0033] 114N: Non-Volatile Memory Express (NVMe) controller

[0034] 115: Error Correction Code (ECC) circuit

[0035] 116: Random Access Memory (RAM)

[0036] 118: Transmission interface circuit

[0037] 118M: PCIe Media Access Control (MAC) circuit

[0038] 118P: PCIe Physical Layer (PHY) circuit

[0039] 118R: Register circuit

[0040] 119: Memory Device Protection (MDP) circuit

[0041] 119TR: Timer

[0042] 119TC: Thermal control unit

[0043] 120: Non-Volatile (NV) memory

[0044] 122: Flash memory die

[0045] 122-1, 122-2~122-N: Non-Volatile (NV) memory elements

[0046] 310, 410, REG1, REG2: Register

[0047] 312, 412: Register value

[0048] 320, 420: Control unit

[0049] 322, 422: Logic circuit

[0050] 330: Counter

[0051] 430: Thermal sensor

[0052] PHASE(0): Preset speed phase

[0053] PHASE(1): deceleration phase

[0054] PHASE(2): Acceleration phase

[0055] S10~S19, S20~S29, S30, S31, S40~S42, S50~S52: Steps DETAILED DESCRIPTION

[0056] Figure 1 FIG1 is a schematic diagram of an electronic system 10 according to an embodiment of the present invention, wherein the electronic system 10 includes a host device 50 and a memory device 100. The host device 50 may include at least one processor (e.g., one or more processors), which may be collectively referred to as a processor 52, and may further include a power supply circuit 54 coupled to the processor 52. The processor 52 is configured to control the operation of the host device 50, and the power supply circuit 54 is configured to provide power to the processor 52 and the memory device 100, and output one or more driving voltages to the memory device 100. The memory device 100 may be configured to provide storage space for the host device 50 and to obtain one or more driving voltages from the host device 50 as a power source for the memory device 100. Examples of the host device 50 include, but are not limited to, a multi-function mobile phone, a wearable device, a tablet computer, and personal computers such as desktop computers and notebook computers. Examples of the memory device 100 may include, but are not limited to, a solid state drive (SSD) and an embedded storage device such as one that complies with the Universal Flash Storage (UFS) standard or the embedded MMC (eMMC) standard. According to this embodiment, the memory device 100 may include a memory controller 110 and a non-volatile (NV) memory 120. The memory controller 110 is configured to control the operation of the memory device 100 and access the NV memory 120, and the NV memory 120 is configured to store information. The NV memory 120 may include at least one NV memory element (e.g., one or more NV memory elements), such as a plurality of NV memory elements 122-1, 122-2, ..., and 122-N, where "N" may represent a positive integer greater than 1. For example, the NV memory 120 may be a flash memory, and the plurality of NV memory elements 122 - 1 , 122 - 2 , . . . , and 122 -N may be a plurality of flash memory chips or a plurality of flash memory dies, but the present invention is not limited thereto.

[0057] likeFigure 1 As shown, the memory controller 110 may include a processing circuit such as a microprocessor 112, a storage unit such as a read-only memory (ROM) 112M, a control logic circuit 114, an error correction code (ECC) circuit 115, a random access memory (RAM) 116, a transmission interface circuit 118, and a memory device protection (MDP) circuit 119 (in FIG. Figure 1 (labeled as "MDP circuit" for simplicity), wherein the above-listed elements can be coupled to each other via a bus. RAM 116 is implemented by a static RAM (SRAM), but the present invention is not limited to this. RAM 116 can be configured to provide internal storage space to memory controller 110. For example, RAM 116 can serve as a buffer memory for buffering data. In addition, ROM 112M of this embodiment is configured to store program code 112C, and microprocessor 112 is configured to execute program code 112C to control access to NV memory 120. It is worth noting that in some examples, program code 112C can be stored in RAM 116 or any type of memory. Furthermore, ECC circuit 115 can be used to protect data and / or perform error correction, wherein ECC circuit 115 can protect data and / or perform error correction. The transmission interface circuit 118 may conform to a specific communication standard (e.g., the UFS standard) and may communicate in accordance with the specific communication standard, for example, for the memory device 100 to communicate with the host device 50. The memory device protection circuit 119 may be used to perform memory device protection on the memory device 100. For example, the memory device protection circuit 119 may include a timer 119TR and a thermal control unit 119TC, wherein the timer 119TR may perform timing control and the thermal control unit 119TC may perform thermal control to trigger dynamic speed adjustment during data access. With the timing control of the timer 119TR and the thermal control of the thermal control unit 119TC, the memory controller 110 may perform dynamic speed adjustment during data access.

[0058] In this embodiment, the host device 50 may send a host command and a corresponding logical address to the memory controller 110 to access the memory device 100. The memory controller 110 receives the host command and the logical address, converts the host command into a memory operation command (hereinafter referred to as an operation command), and further uses the operation command to control the NV memory 120 to read, write, or program memory cells (e.g., data pages) with physical addresses within the NV memory 120, where the physical addresses may be associated with the logical addresses. When the memory controller 110 performs an erase operation on any NV memory element 122-n0 (where "n0" may represent any integer in the interval [1, N]) among the plurality of NV storage elements 122-1, 122-2, ..., and 122-N, at least one physical block of the plurality of physical blocks of the NV memory element 122-n0 may be erased, where each physical block of the plurality of physical blocks may include a plurality of physical pages (e.g., data pages), and an access operation (e.g., read or write) may be performed on one or more physical pages.

[0059] When a host device 50 accesses the memory device 100 (e.g., by accessing the NV memory 120 therein via the memory controller 110), an access request (e.g., a read request, a write request, etc.) from the host device 50 may include a logical address, and the logical address may include a logical block address (LBA) pointing to a logical block, and more specifically, a logical page address pointing to a logical page within the logical block. The memory device 100 (e.g., the memory controller 110) may store and update at least one logical-to-physical (L2P) address mapping table (e.g., one or more L2P address mapping tables) in the NV memory 120 to manage the mapping relationship between logical blocks and physical blocks according to a block-based mapping control scheme (e.g., on a block-by-block basis), and more specifically, to manage the mapping relationship between logical blocks and logical pages, and between physical blocks and physical pages, according to a page-based mapping control scheme (e.g., on a page-by-page basis).

[0060] According to some embodiments, the memory device 100 may be implemented as a memory card compliant with the SD / MMC, CF, MS, XD, or UFS standards, wherein the memory device 100 may be coupled to the host device 50 via an intermediate device such as a memory card reader, but the present invention is not limited thereto.

[0061] Figure 2 FIG. 1 shows a heat control unit (eg,Figure 1 The thermal control unit 119TC in the embodiment of the present invention is a temperature-aware speed control scheme using a data access method with dynamic speed adjustment. The data access method is applicable to Figure 1 The electronic system 10 shown, in particular, the memory device 100 and the memory controller 110 applicable therein. The plurality of NV memory elements 122-1, 122-2, ..., 122-N of this embodiment can be implemented as a group of flash memory dies 122 (labeled as "flash die" for simplicity). Figure 2 As shown, the control logic circuit 114 may include a flash memory controller 114F and a Non-Volatile Memory Express (NVMe) controller 114N, wherein the flash memory controller 114F may use memory operation instructions to control the NV memory 120 (e.g., the set of flash memory dies 122), and the NVMe controller 114N may operate according to the NVMe standard, so that the control logic circuit 114 can respond to NVMe instructions to control the NV memory 120 (e.g., the set of flash memory dies 122). In addition, the transmission interface circuit 118 can be configured to comply with the Peripheral Component Interconnect Express (PCIe) standard. Therefore, at least a portion (e.g., a portion or all) of the transmission interface circuit 118 can be regarded as a PCIe interface circuit of the memory controller 110, and a corresponding transmission interface circuit in the host device 50 can be configured to comply with the PCIe standard. Therefore, at least a portion (e.g., a portion or all) of the corresponding transmission interface circuit can be regarded as a PCIe interface circuit of the host device 50, such as Figure 2 The root complex of the host device 50 is shown. Furthermore, the PCIe interface circuit within the transmission interface circuit 118 may include a PCIe media access control (MAC) circuit 118M and a PCIe physical layer (PHY) circuit 118P for performing MAC and PHY operations, respectively. For example, the PCIe MAC circuit 118M may include a register circuit 118R to allow the microprocessor 112 to control the PCIe MAC circuit 118M to adjust data speed during data access. The register circuit 118R may include multiple registers, such as registers REG1 and REG2, and the microprocessor 112 may set register values ​​in registers REG1 and REG2, respectively.

[0062] The host device 50 and the memory controller 110 may be configured to establish a PCIe link via the respective PCIe interface circuits of the host device 50 and the memory controller 110 (labeled as "PCIe link via PCIe interface" for simplicity). For data transmission between the host device 50 and the memory controller 110, register REG1 may be used to trigger a speed change and thus may be considered a trigger-speed-change register (TSCR), and register REG2 may be used to set a target communication speed (e.g., a transmission rate, which for a PCIe interface is typically measured in gigatransfers / gigatransactions per second (GT / s)) and thus may be considered a target-speed register (TSR). Figure 2 As shown, the microprocessor 112 can control the timer 119TR using a predetermined counter value COUNT and a start count signal START, and the timer 119TR can start counting in response to the triggering of the start count signal START and count until the predetermined counter value COUNT is reached, thereby performing time control for the microprocessor 112. When the predetermined counter value COUNT is reached, the timer 119TR can send a timeout signal TIMEOUT (e.g., an interrupt such as a timeout interrupt) to notify the microprocessor 112 that a timeout has occurred (e.g., the predetermined counter value COUNT has been reached). In addition, the microprocessor 112 can use at least one threshold THRESHOLD such as a first temperature threshold δ H and a second temperature threshold δ L The thermal control unit 119TC can monitor the temperature T at a predetermined intra-controller location of the memory controller 110, send a temperature signal TEMPERATURE with the latest value of the temperature T to the microprocessor 112, and adjust the temperature according to the first temperature threshold δ. H and the second temperature threshold δ L One or more of the temperature T is subjected to temperature-related detection. For example, when the temperature T is greater than the first temperature threshold δ H When the temperature T increases, the thermal control unit 119TC may send an interrupt signal INTERRUPT (e.g., another interrupt) to the microprocessor 112 to transmit a first temperature-related detection result (e.g., the temperature T reaches a threshold THRESHOLD such as the first temperature threshold δ in the direction of increasing the temperature T). H) Notify the microprocessor 112. For example, when the temperature T is less than the second temperature threshold δ L When the thermal control unit 119TC sends an interrupt signal INTERRUPT to the microprocessor 112, the thermal control unit 119TC may send a second temperature-related detection result (for example, the temperature T reaches a threshold THRESHOLD such as the second temperature threshold δ in the direction of decreasing the temperature T). L ) notifies the microprocessor 112.

[0063] based on Figure 2 With the illustrated temperature-aware speed control scheme, the memory device 100 (eg, the memory controller 110 ) can dynamically adjust a PCIe link speed, such as the speed of the PCIe link between the host device 50 and the memory controller 110 , to control the temperature and power consumption of the memory controller 110 .

[0064] Figure 3 FIG. 1 is a diagram illustrating an embodiment of the present invention. Figure 2 Certain implementation details of the timer 119TR of the temperature-aware speed control scheme are shown. The timer 119TR may include at least one register (e.g., one or more registers) such as register 310, a control unit 320, and a counter 330. The control unit 320 may be implemented using logic circuit 322. The timer 119TR may utilize register 310 to store a predetermined counter value COUNT as its register value 312 (labeled "value" for simplicity). The control unit 320 may control the operation of the timer 119TR. For example, the control unit 320 may clear the register 310 by default. The microprocessor 112 may write the predetermined counter value COUNT to the register 310 and then send a start counting signal START. In response to the triggering of the start counting signal START, the control unit 320 may retrieve the predetermined counter value COUNT from the register 310 and control the counter 330 to begin counting until the counter value of the counter 330 reaches the predetermined counter value COUNT. For example, the predetermined counter value COUNT may correspond to a predetermined time difference. When the counter value of the counter 330 reaches the predetermined counter value COUNT, it may indicate that the predetermined time difference has expired, and the control unit 320 may send a timeout signal TIMEOUT to notify the microprocessor 112 of the timeout (eg, the counter value of the counter 330 reaches the predetermined counter value COUNT).

[0065] Figure 4 FIG. 1 is a diagram illustrating an embodiment of the present invention. Figure 2Detailed implementation details of the thermal control unit 119TC of the temperature-aware speed control scheme are shown. The thermal control unit 119TC may include at least one register (e.g., one or more registers) collectively referred to as register 410, and further include a control unit 420 and a thermal sensor 430, wherein the control unit 420 may be implemented using a logic circuit 422. The thermal control unit 119TC may utilize the register 410 to store a threshold value THRESHOLD, such as a first temperature threshold value δ H and the second temperature threshold δ L As its register value 412 (labeled as "value" for simplicity). The control unit 420 can control the operation of the thermal control unit 119TC. For example, the control unit 420 can preset to clear the register 410. The microprocessor 112 can set the threshold THRESHOLD such as the first temperature threshold δ H and the second temperature threshold δ L Write to the register 410. In addition, the control unit 420 can obtain the threshold THRESHOLD such as the first temperature threshold δ from the register 410. H and the second temperature threshold δ L , obtain the temperature T sensed by the thermal sensor 430, and determine whether the temperature T reaches the threshold THRESHOLD, in particular, determine whether the temperature T reaches the first temperature threshold δ H and the second temperature threshold δ L For example, when T>δ H When the control unit 420 sends an interrupt signal INTERRUPT to the microprocessor 112, the first temperature-related detection result (for example, the temperature T reaches the threshold THRESHOLD such as the first temperature threshold δ H ) notifies the microprocessor 112. For another example, when T<δ L When the second temperature-related detection result (for example, the temperature T reaches the threshold THRESHOLD such as the second temperature threshold δ) is detected, the control unit 420 may send an interrupt signal INTERRUPT to the microprocessor 112 to detect the second temperature-related detection result (for example, the temperature T reaches the threshold THRESHOLD such as the second temperature threshold δ L ) to notify the microprocessor 112. In addition, the control unit 420 may send a temperature signal TEMPERATURE with the latest value of the temperature T to the microprocessor 112 for reading by the microprocessor 112. Since the thermal control unit 119TC may be located at a predetermined location within the memory controller 110, the microprocessor 112 may use the thermal control unit 119TC to accurately monitor the temperature T at the predetermined location within the controller.

[0066] For example, the predetermined controller location may represent a predetermined sub-region of a chip region of an integrated circuit (IC) for implementing the memory controller 110, wherein the predetermined sub-region may correspond to the transmission interface circuit 118, and the temperature T may represent the temperature of the transmission interface circuit 118. For better understanding, the predetermined controller location may represent an adjacent location adjacent to the transmission interface circuit 118, or an intra-interface location within the transmission interface circuit 118, but the present invention is not limited thereto. In addition, the second temperature threshold δ L Typically less than a first temperature threshold δ H For better understanding, the first temperature threshold δ H The second temperature threshold δ may be equal to any first predetermined value among a plurality of first predetermined values ​​within a predetermined abnormal temperature range above a predetermined normal temperature range, and the second temperature threshold δ L It can be equal to any second predetermined value among a plurality of second predetermined values ​​within the predetermined normal temperature range. H = 80 (°C) and δ L = 50 (°C), but the present invention is not limited thereto. In some examples, the first temperature threshold δ H and / or the second temperature threshold δ L Can be changed if necessary.

[0067] Figure 5 A speed-down control scheme for the data access method according to one embodiment of the present invention is illustrated, wherein the power consumption POWER of the memory controller 110 (e.g., the transmission interface circuit 118) may vary over time and may be measured in Watts (W). For better understanding, the memory controller 110 (e.g., under the control of the microprocessor 112) may use various control schemes, such as a dynamic voltage and frequency scaling (DVFS) control scheme for the microprocessor 112 and the speed-down control scheme for the transmission interface circuit 118, to reduce the power consumption POWER. In particular, the memory controller 110 may reduce / lower the operating frequency of the microprocessor 112 and reduce / lower the communication speed (e.g., the transmission rate) of the transmission interface circuit 118, but the present invention is not limited thereto. For example, the memory controller 110 may only reduce / lower the communication speed (e.g., the transmission rate) of the transmission interface circuit 118 without adjusting the operating frequency of the microprocessor 112, in order to ensure overall system stability of the memory device 100.

[0068] like Figure 5As shown, the memory controller 110 may trigger the deceleration / reduction of data transmission between the host device 50 and the memory controller 110 according to the deceleration control scheme to switch from a higher speed to a lower speed, and related operations may include:

[0069] (1) With the help of the thermal control unit 119TC, the microprocessor 112 detects that the temperature T reaches the threshold THRESHOLD, for example, T>δ H ;

[0070] (2) The microprocessor 112 starts at a first starting time point t 11 Obtain a first temperature value T from the temperature signal TEMPERATURE 11 ;

[0071] (3) The microprocessor 112 is at a first end time point t 12 Obtain a second temperature value T from the temperature signal TEMPERATURE 12 ;

[0072] (4) The microprocessor 112 sets the target speed register, such as register REG2, to notify the transmission interface circuit 118 of the target communication speed, wherein the microprocessor 112 can set the target communication speed according to an increment ΔT1 (e.g., a positive value such as the second temperature value T 12 With the first temperature value T 11 The difference between (T 12 - T 11 )) determining the target communication speed, for example, based on at least one first predetermined rule (eg, one or more first predetermined rules); and

[0073] (5) The microprocessor 112 sets the trigger speed change register, such as register REG1, to cause the transmission interface circuit 118 to send a speed change request to the root complex, wherein the request indicates the target communication speed;

[0074] But the present invention is not limited to this.In some examples, the relevant operation of this deceleration control scheme can be changed when necessary.

[0075] Figure 6 FIG. 1 is a diagram illustrating an embodiment of the present invention. Figure 5 A workflow of the deceleration control scheme is shown.

[0076] In step S10, the thermal control unit 119TC may check whether the temperature T reaches a threshold value THRESHOLD such as a first temperature threshold value δ in the direction in which the temperature T increases. H (e.g. T≥δ H ), in particular, checking whether the temperature T is greater than a first temperature threshold δ HIf yes (e.g. T > δ H ), step S11 is entered; if no, step S10 is entered.

[0077] In step S11, when T > δ H , the microprocessor 112 can receive an interrupt signal INTERRUPT from the thermal control unit 119TC. For example, when T > δ H is detected, the thermal control unit 119TC can send the interrupt signal INTERRUPT to the microprocessor 112.

[0078] In step S12, after receiving the interrupt signal INTERRUPT, the microprocessor 112 can read the temperature signal TEMPERATURE to obtain a latest value of the temperature T at the first start time point t 11 , and record the latest value of the temperature T as a first temperature value T 11 corresponding to the first start time point t 11 .

[0079] In step S13, the microprocessor 112 can set a predetermined counter value COUNT (e.g. a first predetermined counter value corresponding to a first predetermined time difference) into the timer 119TR, and set a start counting signal START to make the timer 119TR (e.g. the counter 330 therein) start counting.

[0080] In step S14, when the counter value of the counter 330 reaches the predetermined counter value COUNT, the timer 119TR can send a timeout signal TIMEOUT to inform the microprocessor 112 of a timeout.

[0081] In step S15, after receiving the timeout signal TIMEOUT, the microprocessor 112 can read the temperature signal TEMPERATURE to obtain a latest value of the temperature T at the first end time point t 12 , and record the latest value of the temperature T as a second temperature value T 12 corresponding to the first end time point t 12 .

[0082] In step S16, the microprocessor 112 can calculate an increase amount ΔT1 such as a difference between the second temperature value T 12 and the first temperature value T 11 (T 12 - T 11 ).

[0083] In step S17, based on the at least one first predetermined rule, the microprocessor 112 can determine whether the increase amount ΔT lDetermining the target communication speed. For example, when an original communication speed (such as a higher speed) represents PCIe Generation (Gen) 4 Speed ​​Gen_4_Speed ​​(e.g., 16 GT / s), the microprocessor 112 may determine that the target communication speed TARGET_SPEED (such as a lower speed) is a first communication speed from a first set of predetermined communication speeds, such as one of PCIe Gen 1 Speed ​​Gen_1_Speed ​​(e.g., 2.5 GT / s), PCIe Gen 2 Speed ​​Gen_2_Speed ​​(e.g., 5 GT / s), and PCIe Gen 3 Speed ​​Gen_3_Speed ​​(e.g., 8 GT / s), which is less than PCIe Gen_4_Speed. The at least one first predetermined rule may include:

[0084] (1) If ΔT1>α1, TARGET_SPEED = Gen_1_Speed;

[0085] (2) If α1>ΔT1>β1, TARGET_SPEED = Gen_2_Speed; and

[0086] (3) If β1>ΔT1>γ1, TARGET_SPEED = Gen_3_Speed;

[0087] Where α1>β1>γ1, but the present invention is not limited thereto. In another example, the above rules can be rewritten as follows:

[0088] (1) If ΔT1≥ α1, TARGET_SPEED = Gen_1_Speed;

[0089] (2) If α1>ΔT1 ≥ β1, TARGET_SPEED = Gen_2_Speed; and

[0090] (3) If β1>ΔT1 ≥ γ1, TARGET_SPEED = Gen_3_Speed;

[0091] Where α1>β1>γ1>0. In some examples, the original communication speed (such as a higher speed) may represent any communication speed among the second generation PCIe speed Gen_2_Speed, the third generation PCIe speed Gen_3_Speed, the fourth generation PCIe speed Gen_4_Speed, and the fifth generation PCIe speed Gen_5_Speed ​​(e.g., 32 GT / s), and the target communication speed TARGET_SPEED (such as a lower speed) may represent one of another predetermined communication speeds that is lower than the any communication speed.

[0092] In step S18, the microprocessor 112 may set a register value corresponding to the target communication speed TARGET_SPEED determined in step S17 into the register REG2, so as to notify the transmission interface circuit 118 of the target communication speed TARGET_SPEED via the register REG2. The register value of the register REG2 indicates the target communication speed TARGET_SPEED determined in step S17.

[0093] In step S19, the microprocessor 112 may set a register value corresponding to a trigger state into the register REG1, so that the transmission interface circuit 118 sends a speed change request, such as a speed change request, to the host device 50 (e.g., the root complex), wherein the request indicates the target communication speed TARGET_SPEED determined in step S17.

[0094] For better understanding, the method can be used Figure 6 The workflow shown in the figure is used for illustration, but the present invention is not limited thereto. According to some embodiments, one or more steps may be added, deleted or modified in the workflow shown in the figure.

[0095] Figure 7 An acceleration control scheme for the data access method according to one embodiment of the present invention is illustrated. For better understanding, the memory controller 110 (e.g., under the control of the microprocessor 112) can utilize various control schemes, such as the DVFS control scheme for the microprocessor 112 and the acceleration control scheme for the transmission interface circuit 118, to enhance overall processing performance. Specifically, the operating frequency of the microprocessor 112 and the communication speed (e.g., the transmission rate) of the transmission interface circuit 118 can be increased, with corresponding increases in power consumption (POWER), but the present invention is not limited thereto. For example, the memory controller 110 can simply increase the communication speed (e.g., the transmission rate) of the transmission interface circuit 118 without adjusting the operating frequency of the microprocessor 112, to ensure overall system stability of the memory device 100.

[0096] likeFigure 7 As shown, the memory controller 110 may trigger acceleration of data transmission between the host device 50 and the memory controller 110 according to the acceleration control scheme to switch from a lower speed to a higher speed, and related operations may include:

[0097] (1) With the help of the thermal control unit 119TC, the microprocessor 112 detects that the temperature T reaches the threshold THRESHOLD, for example, T<δ L ;

[0098] (2) The microprocessor 112 starts at a second starting time point t 21 Obtain a first temperature value T from the temperature signal TEMPERATURE 21 ;

[0099] (3) The microprocessor 112 is at a second end time point t 22 Obtain a second temperature value T from the temperature signal TEMPERATURE 22 ;

[0100] (4) The microprocessor 112 sets the target speed register, such as register REG2, to notify the transmission interface circuit 118 of the target communication speed, wherein the microprocessor 112 can set the target communication speed according to a reduction amount ΔT2 (e.g., a positive value such as the first temperature value T 21 and the second temperature value T 22 The difference (T 21 - T 22 ), or if T 22 Subtract T 21 To calculate another difference (T 22 -T 21 ) absolute value|(T 22 - T 21 )|) determining the target communication speed, for example, based on at least one second predetermined rule (eg, one or more second predetermined rules); and

[0101] (5) The microprocessor 112 sets the trigger speed change register, such as register REG1, to cause the transmission interface circuit 118 to send a speed change request to the root complex, wherein the request indicates the target communication speed;

[0102] However, the present invention is not limited thereto. In some examples, the related operations of the acceleration control scheme may be changed when necessary.

[0103] Figure 8 FIG. 1 is a diagram illustrating an embodiment of the present invention. Figure 7 A workflow of the acceleration control scheme is shown.

[0104] In step S20, the thermal control unit 119TC may check whether the temperature T reaches a threshold value THRESHOLD such as a second temperature threshold value δ in a direction in which the temperature T decreases. L (e.g. T ≤ δ L ), in particular, checking whether the temperature T is less than a second temperature threshold δ L If (for example, T<δ L ), then go to step S21; if not, then go to step S20.

[0105] In step S21, when T<δ L When T<δ, the microprocessor 112 may receive an interrupt signal INTERRUPT from the thermal control unit 119TC. L When the thermal control unit 119TC is on, it may send an interrupt signal INTERRUPT to the microprocessor 112.

[0106] In step S22, after receiving the interrupt signal INTERRUPT, the microprocessor 112 can read the temperature signal TEMPERATURE to obtain the temperature at the second starting time t 21 The latest value of temperature T is recorded as the value corresponding to the second starting time point t 21 The first temperature value T 21 .

[0107] In step S23, the microprocessor 112 may set a predetermined counter value COUNT (e.g., a second predetermined counter value corresponding to a second predetermined time difference) into the timer 119TR and assert a start count signal START to cause the timer 119TR (e.g., the counter 330 therein) to begin counting. For example, the second predetermined counter value may be the same as the first predetermined counter value, and the second predetermined time difference may be the same as the first predetermined time difference. For another example, the second predetermined counter value may be different from the first predetermined counter value, and the second predetermined time difference may be different from the first predetermined time difference.

[0108] In step S24 , when the counter value of the counter 330 reaches a predetermined counter value COUNT, the timer 119TR may send a timeout signal TIMEOUT to notify the microprocessor 112 of timeout.

[0109] In step S25, after receiving the timeout signal TIMEOUT, the microprocessor 112 can read the temperature signal TEMPERATURE to obtain the temperature at the second end time t 22 The latest value of temperature T is recorded as the value corresponding to the second end time point t 22 The second temperature value T22 .

[0110] In step S26, the microprocessor 112 may calculate the reduction amount ΔT2 such as the first temperature value T 21 and the second temperature value T 22 The difference between (T 21 - T 22 ).

[0111] In step S27, based on the at least one second predetermined rule, the microprocessor 112 may determine the target communication speed according to the reduction ΔT2. For example, when the first communication speed (e.g., the lower speed) represents the first generation PCIe speed Gen_1_Speed, the microprocessor 112 may determine that the target communication speed TARGET_SPEED (e.g., the higher speed) is a second communication speed from a second set of predetermined communication speeds, such as one of the fourth generation PCIe speed Gen_4_Speed, the third generation PCIe speed Gen_3_Speed, and the second generation PCIe speed Gen_2_Speed, which is greater than the first generation PCIe speed Gen_1_Speed. The at least one second predetermined rule may include:

[0112] (1) If ΔT2>α2, TARGET_SPEED = Gen_4_Speed;

[0113] (2) If α2>ΔT2>β2, TARGET_SPEED = Gen_3_Speed; and

[0114] (3) If β2>ΔT2>γ2, TARGET_SPEED = Gen_2_Speed;

[0115] Where α2>β2>γ2, but the present invention is not limited thereto. In another example, the above rules can be rewritten as:

[0116] (1) If ΔT2≥ α2, TARGET_SPEED = Gen_4_Speed;

[0117] (2) If α2>ΔT2 ≥ β2, TARGET_SPEED = Gen_3_Speed; and

[0118] (3) If β2>ΔT2 ≥ γ2, TARGET_SPEED = Gen_2_Speed;

[0119] Where α2>β2>γ2>0. In some examples, the first communication speed (such as a lower speed) may represent any communication speed among the first generation PCIe speed Gen_1_Speed, the second generation PCIe speed Gen_2_Speed, the third generation PCIe speed Gen_3_Speed, the fourth generation PCIe speed Gen_4_Speed, the fifth generation PCIe speed Gen_5_Speed, etc., except for the highest available communication speed (for example, the sixth generation PCIe speed Gen_6_Speed ​​such as 64 GT / s), and the target communication speed TARGET_SPEED (such as a higher speed) may represent one of another predetermined communication speeds that is greater than any of the communication speeds.

[0120] In step S28, the microprocessor 112 may set a register value corresponding to the target communication speed TARGET_SPEED determined in step S27 into the register REG2, so as to notify the transmission interface circuit 118 of the target communication speed TARGET_SPEED via the register REG2. The register value in the register REG2 indicates the target communication speed TARGET_SPEED determined in step S27.

[0121] In step S29, the microprocessor 112 may set the register value corresponding to the trigger state into the register REG1, so that the transmission interface circuit 118 sends a speed change request, such as a speed change request, to the host device 50 (e.g., the root complex), wherein the request indicates the target communication speed TARGET_SPEED determined in step S27.

[0122] For better understanding, the method can be used Figure 8 The workflow shown in FIG. 1 is used to illustrate the present invention, but the present invention is not limited thereto. According to some embodiments, the Figure 8 Add, delete, or change one or more steps in the workflow shown.

[0123] Figure 9 The flowchart of the data access method using dynamic speed adjustment with the thermal control unit according to one embodiment of the present invention is shown. For example, the operations of steps S30 and S31 can be performed in a preset speed phase (PHASE 0), the operations of steps S40-S42 can be performed in a deceleration phase (PHASE 1), and the operations of steps S50-S52 can be performed in an acceleration phase (PHASE 2).

[0124] In step S30 , the memory controller 110 may start monitoring the temperature T of the predetermined location within the memory controller 110 using the thermal control unit 119TC.

[0125] In step S31, in response to at least one access request (e.g., one or more access requests, such as one or more read requests and / or one or more write requests) from the host device 50, the memory controller 110 may control the transmission interface circuit 118 to perform data transmission between the host device 50 and the memory controller 110 at a predetermined communication speed (e.g., the highest available communication speed among all PCIe speeds of multiple generations, such as the first generation PCIe speed Gen_1_Speed, the second generation PCIe speed Gen_2_Speed, the third generation PCIe speed Gen_3_Speed, the fourth generation PCIe speed Gen_4_Speed, etc.), so as to access (e.g., read or write) data in the NV memory 120, but the present invention is not limited thereto. For example, in response to the at least one access request, the memory controller 110 may continue to access the NV memory 120 in one or more subsequent phases, and in particular, control the transmission interface circuit 118 to perform data transmission between the host device 50 and the memory controller 110 at one or more other communication speeds (for example, one or more communication speeds among all the multi-generation PCIe speeds such as the 1st generation PCIe speed Gen_1_Speed, the 2nd generation PCIe speed Gen_2_Speed, the 3rd generation PCIe speed Gen_3_Speed, the 4th generation PCIe speed Gen_4_Speed, etc.) in one or more phases of the deceleration phase PHASE(1) and the acceleration phase PHASE(2) to access data in the NV memory 120.

[0126] In step S40, the response temperature T is greater than the first temperature threshold δ H , the memory controller 110 may detect at a first starting time point t 11 and a first end time point t 12 The temperature T increases by an amount ΔT1 from the first starting time point t 11 To the first end time point t 12 A first period Δt1 may be configured to correspond to the first predetermined time difference. For example, the memory controller 110 may accurately control the first period Δt1 with the help of the timer 119TR so that the first period Δt1 is equal to the first predetermined time difference.

[0127] In step S41, based on the at least one first predetermined rule, the memory controller 110 can calculate the amount of increase ΔT l A first communication speed (eg, a lower speed of the deceleration control scheme) is determined.

[0128] In step S42, the memory controller 110 may control the transmission interface circuit 118 to change the transmission speed from an original communication speed (eg, a higher speed of the deceleration control scheme, such as the preset communication speed, or Figure 9 A previously increased communications speed of the acceleration phase PHASE (2) in a previous iteration of the loop is switched to the first communications speed for data transmission between the host device 50 and the memory controller 110 at the first communications speed.

[0129] In step S50, the response temperature T is less than the second temperature threshold δ L , the memory controller 110 may detect at a second starting time point t 21 and a second end time point t 22 The temperature T decreases by an amount ΔT2 from the second starting time point t 21 To the second end time point t 22 A second period Δt2 can be configured to correspond to the second predetermined time difference. For example, the memory controller 110 can accurately control the second period Δt2 by means of the timer 119TR so that the second period Δt2 is equal to the second predetermined time difference.

[0130] In step S51 , based on the at least one second predetermined rule, the memory controller 110 may determine a second communication speed (eg, a higher speed of the acceleration control scheme) according to the reduction amount ΔT2 .

[0131] In step S52, the memory controller 110 may control the transmission interface circuit 118 to switch from the first communication speed (e.g., the lower speed of the acceleration control scheme) to the second communication speed for data transmission between the host device 50 and the memory controller 110 at the second communication speed, wherein the first communication speed may represent a reduced communication speed just used in the deceleration phase PHASE(1).

[0132] For the deceleration phase PHASE (1), the at least one first predetermined rule may be configured to increase the amount ΔT lA first set of possible ranges is respectively mapped to a first set of predetermined communication speeds (e.g., a set of candidate communication speeds, any of which can be selected as the target communication speed TARGET_SPEED such as the lower speed of the deceleration control scheme). The first set of possible ranges can correspond to respective ranges of the intervals (γ1, β1), (β1, α1), and (α1, ∞), and in particular, include varying versions (e.g., half-open and / or closed versions) and / or non-varying versions of the respective ranges of these intervals, wherein each of the values ​​α1, β1, and γ1 can be added to an associated interval of these intervals as an endpoint of the associated interval. For example, the first set of possible ranges can include respective ranges of the intervals [γ1, β1), [β1, α1), and [α1, ∞). For another example, the first set of possible ranges can include respective ranges of the intervals [γ1, β1], (β1, α1), and [α1, ∞). In step S41, in response to the increment ΔT1 falling within a possible range in the first set of possible ranges of increment ΔT1, the memory controller 110 may select a predetermined communication speed corresponding to the possible range from the first set of predetermined communication speeds. For example, the at least one first predetermined rule may include a plurality of mapping relationships between the first set of possible ranges and the first set of predetermined communication speeds.

[0133] For the acceleration phase PHASE(2), the at least one second predetermined rule may be configured to map a second set of possible ranges of the reduction amount ΔT2 to a second set of predetermined communication speeds (e.g., a set of candidate communication speeds, any one of which may be selected as the target communication speed TARGET_SPEED, such as a higher speed in the acceleration control scheme). The second set of possible ranges may correspond to respective ranges of the intervals (γ2, β2), (β2, α2), and (α2, ∞), and in particular, include varying versions (e.g., half-open and / or closed versions) and / or non-varying versions of the respective ranges of these intervals, wherein each of the values ​​α2, β2, and γ2 may be added to an associated interval of these intervals as an endpoint of the associated interval. For example, the second set of possible ranges may include respective ranges of the intervals [γ2, β2), [β2, α2), and [α2, ∞). For another example, the second set of possible ranges may include the intervals [γ2, β2], (β2, α2), and [α2, ∞]. In step S51, in response to the reduction amount ΔT2 falling within a possible range in the second set of possible ranges of reduction amount ΔT2, the memory controller 110 may select a predetermined communication speed corresponding to the possible range from the second set of predetermined communication speeds. For example, the at least one second predetermined rule may include multiple mapping relationships between the second set of possible ranges and the second set of predetermined communication speeds. For the sake of brevity, similar content in this embodiment is not repeated here.

[0134] For better understanding, the method can be used Figure 9 The workflow shown in FIG. 1 is used to illustrate the present invention, but the present invention is not limited thereto. According to some embodiments, the Figure 9 One or more steps may be added, deleted, or modified in the illustrated workflow. For example, a first partial workflow comprising steps S40-S42 may be repeated (e.g., by executing steps S40-S42 multiple times) to decelerate multiple times in deceleration phase (PHASE (1), and a second partial workflow comprising steps S50-S52 may be repeated (e.g., by executing steps S50-S52 multiple times) to accelerate multiple times in acceleration phase (PHASE (2)).

[0135] According to certain embodiments, in response to at least one additional access request (e.g., one or more additional access requests, such as one or more additional read requests and / or one or more additional write requests), the memory controller 110 may control the transmission interface circuit 118 to perform data transmission between the host device 50 and the memory controller 110 at any one of all available communication speeds (e.g., any one of all PCIe generation speeds, such as the first generation PCIe speed Gen_1_Speed, the second generation PCIe speed Gen_2_Speed, the third generation PCIe speed Gen_3_Speed, the fourth generation PCIe speed Gen_4_Speed, etc.) in any phase of the deceleration phase PHASE(1) and the acceleration phase PHASE(2) to access data in the NV memory 120. For the sake of brevity, similar contents in these embodiments are not repeated here.

[0136] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made according to the scope of the patent application of the present invention should fall within the scope of the present invention.

Claims

1. A data access method using dynamic speed adjustment with the aid of a thermal control unit, the data access method being applicable to a memory controller of a memory device, the memory device comprising the memory controller and a non-volatile memory, the non-volatile memory comprising at least one non-volatile memory element, the data access method comprising: Using the thermal control unit in the memory controller, start monitoring the temperature at a predetermined location in the memory controller; In response to at least one access request from a host device, controlling a transmission interface circuit of the memory controller to perform data transmission between the host device and the memory controller at an original communication speed to access data in the non-volatile memory; In response to the temperature being greater than a first temperature threshold, detecting an increase in the temperature between a first starting time point and a first ending time point, wherein a first period from the first starting time point to the first ending time point corresponds to a first predetermined time difference; Determining a first communication speed based on the increase in accordance with at least one first predetermined rule, wherein the increase in accordance with the first predetermined time difference indicates the following relevant factors of the temperature: a change in temperature with respect to time, for use as a reference in determining the first communication speed; as well as The transmission interface circuit is controlled to switch from the original communication speed to the first communication speed, so as to perform data transmission between the host device and the memory controller at the first communication speed.

2. The data access method according to claim 1, wherein: The at least one first predetermined rule is used to map a first set of possible ranges of the increase amount to a first set of predetermined communication speeds, respectively.

3. The data access method according to claim 1, wherein: Determining the first communication speed according to the increase further includes: In response to the increase amount falling within a possible range in a first set of possible ranges of the increase amount, a predetermined communication speed corresponding to the possible range is selected from a first set of predetermined communication speeds, wherein the at least one first predetermined rule includes a mapping relationship between the first set of possible ranges and the first set of predetermined communication speeds.

4. The data access method according to claim 1, wherein: Also includes: In response to the temperature being less than a second temperature threshold, detecting a decrease in the temperature between a second starting time point and a second ending time point, wherein a second period from the second starting time point to the second ending time point corresponds to a second predetermined time difference; determining a second communication speed according to the reduction amount based on at least one second predetermined rule; as well as The transmission interface circuit is controlled to switch from the first communication speed to the second communication speed, so as to perform data transmission between the host device and the memory controller at the second communication speed.

5. The data access method according to claim 4, wherein: The at least one second predetermined rule is used to map a second possible range of the reduction amount to a second predetermined communication speed.

6. The data access method according to claim 4, wherein: Determining the second communication speed according to the reduction further includes: In response to the reduction amount falling within a possible range in a second set of possible ranges of the reduction amount, a predetermined communication speed corresponding to the possible range is selected from a second set of predetermined communication speeds, wherein the at least one second predetermined rule includes a mapping relationship between the second set of possible ranges and the second set of predetermined communication speeds.

7. The data access method according to claim 4, wherein: The second temperature threshold is lower than the first temperature threshold.

8. The data access method according to claim 1, wherein: The predetermined controller location represents a predetermined sub-region of a chip area of ​​an integrated circuit for implementing the memory controller, wherein the predetermined sub-region corresponds to the transmission interface circuit, and the temperature is the temperature of the transmission interface circuit.

9. A memory controller for a memory device, the memory device comprising the memory controller and a non-volatile memory, the non-volatile memory comprising at least one non-volatile memory element, the memory controller comprising: a processing circuit for controlling the memory controller according to a plurality of host commands from a host device to allow the host device to access the non-volatile memory through the memory controller; a transmission interface circuit coupled to the processing circuit and configured to communicate with the host device; as well as A memory device protection circuit is coupled to the processing circuit and is used to protect the memory device, wherein the memory device protection circuit includes: a thermal control unit for performing thermal control to trigger dynamic speed adjustment during data access; in: The memory controller begins monitoring the temperature at a predetermined location within the memory controller using the thermal control unit; In response to at least one access request from the host device, the memory controller controls the transmission interface circuit to perform data transmission between the host device and the memory controller at an original communication speed to access data in the non-volatile memory; In response to the temperature being greater than a first temperature threshold, the memory controller detects an increase in the temperature between a first starting time point and a first ending time point, wherein a first period from the first starting time point to the first ending time point corresponds to a first predetermined time difference; Based on at least one first predetermined rule, the memory controller determines a first communication speed according to the increase, wherein the increase indicates the following related factors of the temperature relative to the first predetermined time difference: a change in temperature relative to time, which is used as a reference for determining the first communication speed; and The memory controller controls the transmission interface circuit to switch from the original communication speed to the first communication speed, so as to perform data transmission between the host device and the memory controller at the first communication speed.

10. A memory device comprising the memory controller according to claim 9, wherein: The non-volatile memory is configured to store information; The memory controller is coupled to the non-volatile memory and configured to control the operation of the memory device.

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