Simulation model and simulation method

Abstract

This invention relates to simulation models and methods. The purpose of this invention is to accurately simulate the operation of a CSTBT. The simulation model (101) of the CSTBT (12) includes: a MOSFET (21); a diode (22), the cathode of which is connected to the drain of the MOSFET (21); and a capacitor (C). GE ), which is connected between the source and gate of MOSFET (21); capacitor (C CG ), which is connected between the gate of the MOSFET (21) and the anode of the diode; capacitor (C CE ), which is connected between the source of MOSFET (21) and the anode of diode; capacitor (C DG ), which is connected between the drain and gate of MOSFET (21); the behavior power supply (V DG ), which is connected between the drain and gate of the MOSFET (21) and the capacitance (C) DG If the gate-emitter voltage (V) of CSTBT(12) is connected in series, GE If the threshold is reached, the behavior power supply (V) will activate. DG To perform the switching action.

Description

Technical Field

[0001] This invention relates to the simulation of CSTBT (Carrier Stored Trench Bipolar Transistor). Background Technology

[0002] Typically, in the development of power electronic devices such as inverters, the circuit structure is first analyzed through simulation, and then verified through trial production and evaluation.

[0003] In the above simulation analysis, circuit simulation is used, for example, using the SPICE (Simulation Program with Integrated Circuit Emphasis) model.

[0004] The SPICE model described above is a model that simulates and calculates the electrical characteristics of power semiconductor devices such as diodes, metal-oxide-semiconductor field-effect transistors (MOSFETs), or insulated-gate bipolar transistors (IGBTs).

[0005] To simulate electrical characteristics with high accuracy, it is necessary to extract the physical parameters of the device model. Therefore, advanced knowledge of semiconductor physics is required.

[0006] However, circuit designers typically do not require knowledge of semiconductor physics and need methods to extract physical parameters with high accuracy even without such knowledge. One method for addressing this problem is, for example, the method described in Patent Document 1.

[0007] Patent Document 1: Japanese Patent Application Publication No. 2020-88080

[0008] The behavior model of the IGBT shown in Patent Document 1 does not reflect the charge storage (Carrier Store: CS) layer, thus it cannot accurately represent the operation of the CSTBT with the CS layer. Summary of the Invention

[0009] This invention was proposed to solve the above problems, and its purpose is to accurately simulate the operation of CSTBT.

[0010] The simulation model of this invention is a simulation model used to evaluate the characteristics of CSTBT, and it includes: a MOSFET; a diode, the cathode of which is connected to the drain of the MOSFET; and a capacitor C. GE It is connected between the source and gate of the MOSFET, representing the gate-emitter capacitance of the CSTBT; capacitance C CG It is connected between the gate of the MOSFET and the anode of the diode, representing the gate-collector capacitance of the CSTBT; capacitance C CE It is connected between the source of the MOSFET and the anode of the diode, representing the collector-emitter capacitance of the CSTBT; capacitance C DG It is connected between the drain and gate of the MOSFET, representing the drain-gate capacitance of the CSTBT; and the behavior power supply V DG It is located between the drain and gate of the MOSFET and the capacitance C. DG Series connection indicates the drain-gate voltage of the CSTBT. If the gate-emitter voltage V of the CSTBT... GE When the pre-defined threshold is reached, the behavior power supply V DG Perform the switching action.

[0011] The effects of the invention

[0012] According to the simulation model of the present invention, the actions of CSTBT can be accurately simulated. Attached Figure Description

[0013] Figure 1 This is a cross-sectional view showing the longitudinal structure of CSTBT.

[0014] Figure 2 This is a diagram showing the simulation circuit of CSTBT in Implementation Method 1.

[0015] Figure 3 This is a diagram showing the simulation circuit of the CSTBT drive circuit.

[0016] Figure 4 This is a diagram showing the high-frequency simulation circuit of the CSTBT test circuit.

[0017] Figure 5 This represents V in the CSTBT's conduction action. CE and I C The actual waveform diagram.

[0018] Figure 6 This represents V in the CSTBT's conduction action. GE and I G The actual waveform diagram.

[0019] Figure 7It means that it was used Figure 2 The V in the CSTBT conduction action during the simulation circuit CE and I C The diagram shows the simulated waveform.

[0020] Figure 8 It means that it was used Figure 2 The V in the CSTBT conduction action during the simulation circuit GE and I G The diagram shows the simulated waveform.

[0021] Figure 9 This is a diagram showing the simulation circuit of CSTBT in Implementation Method 2.

[0022] Figure 10 It means C CG V CG Dependency diagram.

[0023] Figure 11 It means C CG The fitted graph.

[0024] Figure 12 It means that it was used Figure 9 The V in the CSTBT conduction action during the simulation circuit CE and I C The diagram shows the simulated waveform.

[0025] Figure 13 It means that it was used Figure 9 The V in the CSTBT conduction action during the simulation circuit GE and I G The diagram shows the simulated waveform.

[0026] Figure 14 This is a diagram showing the simulation circuit of CSTBT in implementation method 3.

[0027] Figure 15 It indicates that it is used for... Figure 14 The diagram shows a circuit diagram for calculating the current of a current source in a simulation circuit.

[0028] Figure 16 This is a diagram showing the simulation circuit of CSTBT in implementation method 4.

[0029] Figure 17 This is a diagram showing the simulation circuit of a 6-in-1 module with CSTBT.

[0030] Figure 18 It means that it was used Figure 17 The simulation circuit diagram of the conducted noise evaluation system is shown in the simulation circuit diagram of the 6-in-1 module.

[0031] Figure 19 It represents a graph of the analysis result of the conducted noise obtained from the simulation circuit of Figure 18 . Detailed implementation manners

[0032] <A. Embodiment 1>

[0033] <A-1. Structure>

[0034] Figure 1 It is a cross-sectional view showing the longitudinal structure of CSTBT 12. As Figure 1 shown, CSTBT 12 has an emitter electrode 1, a collector electrode 2, a gate electrode 3, a P + layer 4, an N + emitter layer 5, a channel doping layer 6, a charge storage layer (CS layer) 7, an N - drift layer 8, an N + buffer layer 9, a P + collector layer 10 and a gate oxide film 11. On the first main surface of the N - drift layer 8, the CS layer 7, the channel doping layer 6, the N + emitter layer 5 and the P + layer are stacked in sequence. A trench is formed that penetrates the N + emitter layer 5, the channel doping layer 6, and the CS layer 7 to reach the N - drift layer 8. Inside this trench, the gate electrode 3 and the gate oxide film 11 covering the gate electrode 3 are formed. On the P + layer 4 and the N + emitter layer 5, the emitter electrode 1 is formed. On the second main surface of the N - drift layer 8, which is opposite to the first main surface, the N + buffer layer 9, the P + collector layer 10 and the collector electrode 2 are formed in sequence.

[0035] Figure 2 The simulation model 101 of CSTBT 12 in this embodiment is shown. The simulation model 101 is an equivalent circuit of CSTBT 12 and is used for the simulation of CSTBT 12. The simulation model is, for example, input into a computer and then displayed in a simulator, etc.

[0036] The simulation model 101 of CSTBT 12 mainly consists of a MOSFET 21 and a diode 22. The MOSFET 21 is composed of the N + emitter layer 5, the channel doping layer 6, the CS layer 7, the gate oxide film 11 and the gate electrode 3 of CSTBT 12. The diode 22 is composed of the N - drift layer 8, the N +Buffer layer 9 and P + It consists of a collector layer 10.

[0037] The gate of MOSFET 21 is equivalent to the gate of CSTBT 12, and the emitter of MOSFET 21 is equivalent to the emitter of CSTBT 12. The cathode of diode 22 is connected to the drain of MOSFET 21. The anode of diode 22 is equivalent to the collector of CSTBT 12.

[0038] The gate-emitter capacitance C of CSTBT 12 GE It is connected between the gate and emitter of MOSFET 21.

[0039] Between the drain and gate of MOSFET 21, the behavior power supply V DG The drain-gate capacitance C of CSTBT 12 DG Series connection. Behavioral power supply V DG It is a behavioral power supply that can switch with any voltage as a threshold. For example, if the gate-emitter voltage V GE Reaching the threshold voltage V of CSTBT 12 th Then the behavior of the power supply V DG Perform a switch. Alternatively, if the gate-emitter voltage V GE The threshold voltage V below CSTBT 12 th Then the behavior of the power supply V DG Switching is performed. Additionally, the behavior power supply V... DG Switching is optional. Behavioral power supply V DG It can take positive, negative or 0 values ​​based on the gate potential.

[0040] Drain-gate capacitance C DG Formed from CS layer 7 of CSTBT 12. Regarding the drain-gate capacitance C... DG You can enter any value, such as the application design value.

[0041] The gate-collector capacitance C of CSTBT 12 CG It is connected between the gate of MOSFET 21 and the anode of diode 22.

[0042] The collector-emitter capacitance C of CSTBT 12 CE It is connected between the source of MOSFET 21 and the anode of diode 22.

[0043] Figure 3 This is a diagram showing a simulation model of the drive circuit 30 for the CSTBT 12. The drive circuit 30 is a gate drive circuit that applies a gate voltage to the gate terminal of the CSTBT 12, or in other words, the MOSFET 21. Figure 3 The simulation model of the driving circuit 30 shown is the equivalent circuit of the driving circuit 30, which is configured to have an optocoupler 31, PNP transistors 32a and 32b, NPN transistors 33a and 33b, MOSFET 34, diodes 35a and 35b, resistors 36a, 36b and 36c and a power supply 37.

[0044] Optocoupler 31 receives the input signal. The output of optocoupler 31 is input to the bases of PNP transistor 32a and NPN transistor 33a. The emitters of PNP transistor 32a and NPN transistor 33a are connected to the gate of MOSFET 34. The collector of NPN transistor 33a is connected to the power supply potential generated by power supply 37. The drain of MOSFET 34 is connected to the power supply potential via resistor 36c and is connected to the bases of PNP transistor 32b and NPN transistor 33b. The source of MOSFET 34 is connected to the reference potential.

[0045] The collector of NPN transistor 33b is connected to the power supply potential, and the collector of PNP transistor 32b is connected to the reference potential. The emitters of PNP transistor 32b and NPN transistor 33b are connected to the anode and cathode of diode 35a, respectively. Resistor 36a is connected to the cathode of diode 35a. Resistor 36b is connected to the anode of diode 35a. The opposite sides of resistors 36a and 36b to diodes 35a and 35b are connected to the output terminal.

[0046] Figure 4 A simulation model 80 of the test circuit for the CSTBT 12 is shown. Simulation model 80 is the high-frequency equivalent circuit of the CSTBT 12 test circuit. Simulation model 80 is configured as a substrate 50 for chip bonding of the CSTBT 12 and freewheeling diode 57, a drive circuit 30, an inductive load 60, and a power supply circuit 70. The substrate 50 is represented by the freewheeling diode 57, inductors 51 and 52 connected to the cathode and anode of the freewheeling diode 57 respectively, inductor 53 connected to inductor 52, the CSTBT 12 with its collector connected to inductor 53, and inductors 55 and 54 connected to the gate and emitter of the CSTBT 12 respectively. Inductor 54 is connected between the emitter of the CSTBT 12 and a reference potential.

[0047] One output terminal of the drive circuit 30 is connected to inductor 55 via inductor 41, and the other output terminal is connected to a reference potential via inductor 42. Figure 4 In the application of CSTBT 12 Figure 2 The simulation model 101 shown.

[0048] The inductor 51 is connected between the first terminal T1 of the substrate 50 and the freewheeling diode 57. The inductor 52 is connected between the second terminal T2 of the substrate 50 and the freewheeling diode 57. The third terminal T3 of the substrate 50 is connected to the reference potential.

[0049] The inductive load 60 is connected between the first terminal T1 and the second terminal T2 of the substrate 50, and the power supply circuit 70 is connected between the first terminal T1 and the third terminal T3. The inductive load 60 is represented by a series connection of a resistor 64, an inductor 62, and a capacitor 66 and a parallel connection of an inductor 61, a resistor 63, and a capacitor 65. The power supply circuit 70 is represented by an inductor 71, an electric field capacitor 72, and a resistor 73.

[0050] <A - 2. Operation>

[0051] In Figure 5 and Figure 6 representative examples of the double - pulse test results are shown. Figure 5 Shows V in CSTBT 12 CE and I C measurement values. Figure 6 Shows V in CSTBT 12 GE and I G measurement values. In Figure 5 and Figure 6 the horizontal axis is time [μs]. In Figure 5 the vertical axis is I C [A] and V CE [V], in Figure 6 the vertical axis is I G [A] and V GE [V]. As Figure 5 shown, when a V of 300 [V] is applied CE a current of 15 [A] flows through I C . As Figure 6 shown, when V GE reaches an arbitrary voltage, V GE sharply increases due to the switching of V DG , and thus the channel of the MOSFET immediately widens and the current starts to flow sharply.

[0052] Figure 7 and Figure 8 show the simulation results of the double - pulse test obtained from the Figure 4 simulation model 80. Figure 7 The horizontal and vertical axes of Figure 5 are the same as the horizontal and vertical axes of Figure 8 The horizontal and vertical axes of Figure 6 are the same as the horizontal and vertical axes of Figure 7 and Figure 8 the dashed line shows the simulation results and the solid line shows Figure 5 and Figure 6 the measured values shown. According to Figure 7 and Figure 8 it can be seen that Figure 2 the simulation model 101 of CE V C V GE I G in CSTBT 12 was simulated with high precision.

[0053] <A - 3. Effects>

[0054] The simulation model 101 of CSTBT 12 in this embodiment has: a MOSFET 21; a diode 22 whose cathode is connected to the drain of the MOSFET 21; a capacitor C GE which is connected between the source and the gate of the MOSFET 21 and represents the gate - emitter capacitance of CSTBT 12; a capacitor C CG which is connected between the gate of the MOSFET 21 and the anode of the diode 22 and represents the gate - collector capacitance of CSTBT12; a capacitor C CE which is connected between the source of the MOSFET 21 and the anode of the diode 22 and represents the collector - emitter capacitance of CSTBT 12; a capacitor C DG which is connected between the drain and the gate of the MOSFET 21 and represents the drain - gate capacitance of CSTBT 12; and a behavioral power supply V DG which is connected in series with the capacitor C DG between the drain and the gate of the MOSFET 21 and represents the drain - gate voltage of CSTBT 12.

[0055] Moreover, if the gate - emitter voltage V GE of CSTBT 12 reaches a pre - specified threshold, the behavioral power supply V DG performs a switching operation. Therefore, according to the simulation model 101, the operation of CSTBT 12 can be simulated with high precision, that is, by the switching of the behavioral power supply V DG the gate - emitter voltage V GE of CSTBT 12 increases sharply, and thus the channel of the MOSFET immediately widens and the current starts to flow sharply.

[0056] In addition, the simulation model 101 may also have a gate drive circuit for applying a voltage to the gate of the MOSFET 21. Thus, the gate voltage and gate current of CSTBT 12 can be simulated with high precision.

[0057] <B. Embodiment 2>

[0058] <B-1. Structure>

[0059] Figure 9 This is a diagram showing the simulation model 102 of the CSTBT 12 of the present embodiment. Regarding the simulation model 102 of the CSTBT 12, in the simulation model 101 described in Embodiment 1, the gate-collector capacitance C of the CSTBT 12 CG is set as a variable capacitance that depends on the gate-collector voltage V CG and varies. In other aspects, it is the same as the simulation model 101.

[0060] Figure 10 Shows the measured results of the gate-collector capacitance C of the CSTBT 12 CG . Figure 10 The horizontal axis of represents the gate-collector voltage V CG [V], and the vertical axis represents the gate-collector capacitance C CG [F]. As Figure 10 shown, the gate-collector capacitance C CG depends on the gate-collector voltage V CG and varies. Figure 9 The simulation model 102 of represents the gate-collector capacitance C CG by the following mathematical formula with the gate-collector voltage V CG as a variable to reflect this phenomenon. In addition, Ca, Ct, Vt, Vc are arbitrary fixed values, y = arctan(x) is the inverse function of y = tan(x), and π is the ratio of the circumference of a circle to its diameter.

[0061] [Mathematical formula 1]

[0062] C CG = Ca·(1 - Ct*2 / π)·arctan{(V CG - Vt) / Vc}

[0063] From the above formula, as Figure 11 shown, the gate-collector capacitance C CG is fitted to a value close to the measured value.

[0064] <B-2. Operation>

[0065] Figure 12 and Figure 13 show the simulation results obtained using the simulation model 102 of the CSTBT 12. That is, applying the simulation model 102 to the CSTBT 12 in the simulation model 80 of Figure 4 , similar to Embodiment 1, for the V CE , I C , V GE , I GEG The operation of Figure 12 and Figure 13 is simulated. In Figure 12 , the horizontal axis represents time [μs]. In c , the vertical axis represents I CE [A] and V Figure 13 , and in G , the vertical axis represents I GE [A] and V Figure 12 and Figure 13 , the dotted line shows the simulation result, and the solid line shows the measured value. According to Figure 12 and Figure 13 , it can be seen that the simulation model 102 accurately simulates the operation of V CE , I C , V GE , I G in CSTBT 12.

[0066] <B - 3. Effect>

[0067] In the simulation model 102 of CSTBT 12 in this embodiment, the gate - collector capacitance C CG of CSTBT 12 varies depending on the gate - collector voltage V CG of CSTBT 12. Therefore, according to the simulation model 102, the gate - collector capacitance C CG that varies depending on the gate - collector voltage V CG of CSTBT 12 can be accurately reflected.

[0068] In addition, in the simulation model 102, Ca, Ct, Vt, and Vc are made constant, and the gate - collector voltage V CG of CSTBT 12 is made a variable. The gate - collector capacitance C CG of CSTBT 12 is expressed by Ca(1 - Ct * 2 / π)arctan{(V CG - Vt) / Vc}. Thus, according to the simulation model 102, the gate - collector capacitance C CG is represented by a continuous function of the gate - collector voltage V CG . Therefore, the operations of V CE , I C , V GE , and I G can be calculated with high precision and stability.

[0069] <C. Embodiment 3>

[0070] <C - 1. Structure>

[0071] Figure 14It is a diagram showing the simulation model 103 of the CSTBT 12 of the present embodiment. Regarding the simulation model 103 of the CSTBT 12, in the simulation model 101 described in Embodiment 1, based on the voltage between the gate and the collector V CG The capacitance C between the gate and the collector of the CSTBT 12 is represented by the parallel connection of the behavioral current source I1 and the resistor R1 CG , and other aspects are the same as those of the simulation model 101. The behavioral current source I1 is also referred to as the first behavioral current source.

[0072] The current of the behavioral current source I1 in the simulation model 103 is calculated using Figure 15 the circuit shown. Figure 15 The circuit shown consists of a series connection of a reference resistor Rref and a reference capacitor Cref and a parallel connection of a behavioral voltage source V CG and a behavioral current source I2. The behavioral current source I2 is also referred to as the second behavioral current source. The current of the behavioral current source I2 is represented by the time derivative of the voltage between the gate and the collector V CG , the capacitance C between the gate and the collector CG and the reference capacitor Cref. In Figure 15 the behavioral voltage source V in the circuit shown CG the flowing current I = func(V CG ) corresponds to the current of the behavioral current source I1 in the simulation model 103 of the CSTBT 12.

[0073] <C - 2. Effects>

[0074] In the simulation model 103 of the CSTBT 12 of the present embodiment, the capacitance C between the gate and the collector of the CSTBT 12 CG is represented by the parallel connection of the first behavioral current source, that is, the behavioral current source I1 and the resistor R1. In the circuit composed of a series connection of a reference resistor Rref and a reference capacitor Cref, the second behavioral current source, that is, the behavioral current source I2 connected to both ends of the series connection, and a behavioral voltage source V CG representing the voltage between the gate and the collector of the CSTBT 12 connected to both ends of the series connection, the current flowing through the second behavioral current source I2 is represented by the time derivative of the voltage between the gate and the collector V CG of the CSTBT 12, the capacitance C CG and the reference capacitor Cref, and the current flowing through the behavioral voltage source V CG corresponds to the current of the behavioral current source I1.

[0075] According to the simulation model 103, setting the capacitance C between the gate and the collector of the CSTBT 12 CG as a voltage variable capacitor, it can be used as a capacitor with the voltage between the gate and the collector VCG Calculate as a function of variables. Additionally, since the voltage V between the gate and the collector CG is applied to the reference resistor Rref and the reference capacitor Cref and not to the behavioral current source I2, the stability of the calculation can be achieved.

[0076] <D. Embodiment 4>

[0077] <D - 1. Structure>

[0078] Figure 16 is a diagram showing the simulation model 104 of the CSTBT 12 of this embodiment. Regarding the simulation model 104 of the CSTBT 12, in the simulation model 102 described in Embodiment 2, the collector - emitter capacitance C CE and the gate - emitter capacitance C GE are expressed as variable capacitances that are functions of the voltages applied to the respective components.

[0079] Let Ca, Ct, Vt, Vc be arbitrary fixed values, and let V CE be a variable. The collector - emitter capacitance C CE is represented by the following equation.

[0080] [Mathematical formula 2]

[0081] C CE = Ca·(1 - Ct * 2 / π)·arctan{(V CE - Vt) / Vc}

[0082] Let Ca, Ct, Vt, Vc be arbitrary fixed values, and let V GE be a variable. The gate - emitter capacitance C GE is represented by the following equation.

[0083] [Mathematical formula 3]

[0084] C GE = Ca·(1 - Ct * 2 / π)·arctan{(V GE - Vt) / Vc}

[0085] Furthermore, in Figure 16 both the collector - emitter capacitance C CE and the gate - emitter capacitance C GE are expressed as variable capacitances, but it is also possible to express only one of them as a variable capacitance.

[0086] <D - 2. Effects>

[0087] In the simulation model 104 of the CSTBT 12 of this embodiment, it is also possible that the collector - emitter capacitance C of the CSTBT 12CE The collector-emitter voltage V depends on the CSTBT 12 CE and varies. Additionally, it can also be the gate-emitter capacitance C of the CSTBT 12 GE which depends on the gate-emitter voltage V of the CSTBT 12 GE and varies. With such a structure, based on the simulation model 104 of the CSTBT 12, the V GE dependency or the C GE dependency can be stably represented. CE of V CE

[0088] <E. Embodiment 5>

[0089] <E - 1. Structure>

[0090] Figure 17 The simulation model 105 of the semiconductor module of this embodiment is shown. The semiconductor module represented by the simulation model 105 applies the CSTBT ၁၂ to the 6 - in - 1 module. That is, the 6 - in - 1 module has 6 groups each consisting of the CSTBT 12 and the free - wheeling diode 57 connected in anti - parallel to the CSTBT 12. The simulation model 101 - 104 of the CSTBT 12 in any one of Embodiments 1 - 4 is applied to the CSTBT 12 in the simulation model ၁၀၅.

[0091] <E - 2. Effect>

[0092] The simulation model 105 of the semiconductor module of this embodiment is the simulation model of the 6 - in - 1 module with the CSTBT 12, and the simulation models 101 - 104 of any one of Embodiments 1 - 4 are applied to the CSTBT 12 of the 6 - in - 1 module. Therefore, based on the simulation model 105, the operation of the CSTBT 12 can be represented as a 6 - in - 1 module.

[0093] <F. Embodiment 6>

[0094] <F - 1. Structure>

[0095] Figure 18 The simulation model 106 of the conducted noise evaluation system of this embodiment is shown. As Figure 18 shown, the simulation model 106 has a power supply circuit model 82, a LISN model 83, a first cable model 84, a rectifier model 85, the simulation model 105 of the 6 - in - 1 module, a second cable model 86, and a motor model 87.

[0096] ​The power supply circuit model 82 is, for example, a simulation model of a three-phase power supply circuit. The LISN model 83 is a simulation model of LISN and is provided at the next stage of the power supply circuit model 82. The first cable model 84 is, for example, a simulation model of a three-phase four-wire cable and is provided at the next stage of the LISN model 83. The rectifier model 85 is a simulation model of a rectifier and a smoothing capacitor and is provided at the next stage of the first cable model 84. The simulation model 105 is a simulation model of the 6-in-1 module described in Embodiment 5 and is provided at the next stage of the rectifier model 85. The second cable model 86 is, for example, a simulation model of a three-phase four-wire cable and is provided at the next stage of the simulation model 105. The motor model 87 is a simulation model of a motor and is provided at the next stage of the second cable model 86.

[0097] Using Figure 18 the simulation model 106 shown, analysis is performed by transient analysis (Transient), whereby conducted noise can be detected through the output terminal of LISN. In addition, by performing frequency transformation such as discrete Fourier transform (Discrete Fourier Transform: DFT), fast Fourier transform (Fast Fourier Transform: FFT), or wavelet transform on at least a part of the detected conducted noise, the distribution of the conducted noise can be output.

[0098] <F-2. Operation>

[0099] Based on the simulation model 106, analysis of conducted noise (noise terminal voltage), common-mode current, etc. corresponding to the characteristics of the CSTBT 12 installed in a DIPIPM (Dual-In-Line Package Intelligent Power Module) such as a 6-in-1 module can be performed. Moreover, based on the simulation model 106, by analyzing the common-mode or differential-mode current with the power device as the signal source, the dominant part of the frequency domain determined to be noise can be identified.

[0100] Figure 19 The results of simulating the conducted noise in the simulation model 106 for multiple cases with different concentrations of the CS layer 7 of the CSTBT 12 are shown.

[0101] <F-3. Effect>

[0102] The simulation model 106 of the conducted noise evaluation system in this embodiment includes: a power supply circuit model 82, which is a simulation model of a power supply circuit; a LISN model 83, which is a simulation model of a LISN set at the next level after the power supply circuit model 82; a first cable model 84, which is a simulation model of a cable set at the next level after the LISN model 83; a rectifier model 85, which is a simulation model of a rectifier and a smoothing capacitor set at the next level after the first cable model 84; a simulation model 105 of embodiment 5, which is set at the next level after the rectifier model 85; a second cable model 86, which is a simulation model of a cable set at the next level after the simulation model 105; and a motor model 87, which is a simulation model of a motor set at the next level after the second cable model 86. Therefore, based on the simulation model 106, conducted noise corresponding to the characteristics of CSTBT12 can be evaluated.

[0103] Furthermore, the various implementation methods can be freely combined, and appropriate modifications or omissions can be made to each implementation method.

[0104] Explanation of the label

[0105] 1. Emitter electrode, 2. Collector electrode, 3. Gate electrode, 4. P + Layer, 5 N + Emitter layer, 6-channel doped layer, 7-charge accumulation layer (CS layer), 8-N - Drift layer, 9 N + Buffer layer, 10P + Collector layer, 11 Gate oxide film, 12 CSTBT, 21 MOSFET, 22 Diode, 30 Driver circuit, 31 Optocoupler, 32a, 32b PNP transistors, 33a, 33b NPN transistors, 35a, 35b Diodes, 36a, 36b, 36c Resistors, 37 Power supply, 41, 42, 51, 52, 53, 54, 55 Inductors, 50 Substrate, 57 Freewheeling diode, 60 Inductive load, 61, 62 Inductors, 63, 64 Resistors, 65, 66 Capacitors, 70 Power supply circuit, 71 Inductor, 72 Electric field capacitor, 73 Resistor, 80 Simulation model, 82 Power supply circuit model, 83 LISN model, 84 First cable model, 85 Rectifier model, 86 Second cable model, 87 Motor model, 101-106 Simulation models.

Claims

1. A simulation model for evaluating characteristics of a trench gate type IGBT (CSTBT) having a carrier accumulation layer, the simulation model has: a MOSFET; a diode whose cathode is connected to the drain of the MOSFET; Capacitor C GE connected between the source and the gate of the MOSFET, represents the gate-emitter capacitance of the CSTBT; Capacitor C CG Cst, which is connected between the gate of the MOSFET and the anode of the diode, represents the gate-collector capacitance of the CSTBT; a capacitor C CE connected between the source of the MOSFET and the anode of the diode, representing the collector-emitter capacitance of the CSTBT; a capacitor C DG connected between the drain and the gate of the MOSFET, representing a drain-gate capacitance of the CSTBT; and Behavioral power supply V DG which is connected in series between the drain and the gate of the MOSFET, represents the drain-gate voltage of the CSTBT, DG which is connected in series between the drain and the gate of the MOSFET, represents the drain-gate voltage of the CSTBT, If the gate-emitter voltage V GE of the CSTBT reaches a predetermined threshold value, the behavior power source V DG performs a switching action.

2. The simulation model according to claim 1, wherein, The capacitance C CG Depends on the gate-collector voltage V of the CSTBT CG Varies.

3. The simulation model according to claim 2, wherein, Ca, Ct, Vt, Vc are constants, the gate-collector voltage V CG of the CSTBT is expressed by CG Ca(1-Ct*2 / π)arctan{(V CG -Vt) / Vc}.

4. The simulation model according to claim 1, wherein, The capacitor C CG represented by the parallel connection of a current source and a resistance, In a circuit composed of a series connection of a reference resistance and a reference capacitance, a current source connected to both ends of the series connection, a voltage source representing a gate-collector voltage V CG of the CSTBT connected to both ends of the series connection, The current flowing in the second transistor is represented by the time derivative of the gate-collector voltage V CG of the CSTBT, the capacitance C CG and the reference capacitance Cref. the current flowing in the behavioral voltage source is equivalent to the current of the first behavioral current source.

5. The simulation model according to any one of claims 1 to 4, wherein, The capacitance C CE Depends on the collector-emitter voltage V of the CSTBT CE Varies.

6. The simulation model according to any one of claims 1 to 4, wherein, The capacitance C GE Depends on the CSTBT gate-emitter voltage V GE Varies.

7. The simulation model according to claim 5, wherein, The capacitance C GE Depends on the CSTBT gate-emitter voltage V GE Varies.

8. The simulation model according to any one of claims 1 to 5, wherein, a gate drive circuit that applies a voltage to the gate of the MOSFET is further provided.

9. A simulation model that is a simulation model of a 6-in-l module having the CSTBT, the simulation model according to any one of claims 1 to 8 is applied to the CSTBT possessed by the 6-in-l module.

10. The simulation model according to claim 9, wherein, a gate drive circuit that applies a voltage to the gate of the MOSFET is further provided.

11. A simulation model having: a power supply circuit model that is a simulation model of a power supply circuit; a LISN model that is a simulation model of a LISN provided at a stage lower than the power supply circuit model; a first cable model that is a simulation model of a cable provided at a stage lower than the LISN model; a rectifier model that is a simulation model of a rectifier and a smoothing capacitor provided at a stage lower than the first cable model; the simulation model according to claim 9 is provided at a stage lower than the rectifier model; a second cable model that is a simulation model of a cable provided at a stage lower than the simulation model according to claim 9; and a motor model that is a simulation model of a motor provided at a stage lower than the second cable model.

12. A simulation method for evaluating characteristics of a trench gate type IGBT (CSTBT) having a carrier accumulation layer, the characteristics of the CSTBT are evaluated using a simulation model, the simulation model has: a MOSFET; a diode whose cathode is connected to the drain of the MOSFET; Capacitor C GE connected between the source and the gate of the MOSFET, represents the gate-emitter capacitance of the CSTBT; a capacitor C CG connected between the gate of the MOSFET and the anode of the diode, representing the gate-collector capacitance of the CSTBT; a capacitor C CE connected between the source of the MOSFET and the anode of the diode, representing the collector-emitter capacitance of the CSTBT; a capacitor C DG connected between the drain and the gate of the MOSFET, representing a drain-gate capacitance of the CSTBT; and Behavioral power supply V DG which is connected in series between the drain and the gate of the MOSFET, represents the drain-gate voltage of the CSTBT, DG which is connected in series between the drain and the gate of the MOSFET, represents the drain-gate voltage of the CSTBT, If the gate-emitter voltage V GE of the CSTBT reaches a predetermined threshold value, the behavior power source V DG performs a switching action.

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