A method for identifying a lithography defect hot spot pattern and a graphic structure

Abstract

The present invention provides a method for identifying hot spot patterns of lithography defects, including: determining a layer to be identified in a layout; presetting a width range and identifying initial edges; presetting RightSpace and LeftSpace ranges and identifying Edge_out; identifying a polygon area in the plg_out where one side is Fit_width_e_LSW and the other side is Fit_width_e_RSW as plg_out_plus, i.e., the target pattern. The method of the present invention can quickly and accurately identify lithography defect patterns, which is beneficial to improving the production process and has simple steps. The present invention also provides a structure of a hot spot pattern of lithography defects, which can quickly identify whether a pattern has a risk of causing lithography defects.

Description

Technical Field

[0001] The invention belongs to the field of semiconductor design and manufacturing, and in particular relates to a method for identifying a hot spot pattern of photolithography defects and a pattern structure. Background Art

[0002] As the technology nodes of integrated circuit production process continue to advance, the design of integrated circuits has become more and more complex. The wavelength of the mainstream photolithography process currently used in integrated circuit production has been maintained at 193nm. When the wavelength of the exposure machine is not updated, the size of the exposure pattern continues to shrink, which will produce many photolithography patterns that meet the design rules but have poor actual process windows, generally referred to as photolithography defect hotspot patterns. The processing methods for photolithography defect hotspot patterns include optimizing the original layout design before tape-out, and performing special process processing on the detected photolithography process hotspots.

[0003] A lithography defect hotspot pattern generally refers to a pattern or pattern combination in a layout that has certain geometric features and feature sizes within a certain range that are prone to causing lithography defects; in actual manufacturing production, due to different processing methods of different manufacturers, lithography defect hotspot patterns may not actually cause lithography defects, that is, for different manufacturers, the lithography defect hotspot patterns that actually cause lithography defects may be different. Determining what kind of hotspot pattern structure is prone to causing lithography defects is of great practical significance for quickly and accurately locating lithography defect hotspot patterns in a large amount of layout data in advance, and for guiding manufacturers in design and production. The inability to effectively and conveniently identify the hotspot pattern is very unfavorable for the further improvement of lithography technology and design. Summary of the invention

[0004] The present invention is based on all or part of the above-mentioned prior art problems. All explanations or definitions of the terms and related technical principles involved in the following description of this application are only for illustrative purposes and not for limiting purposes. Some commonly used English terms or letters used in this invention for the sake of clarity are only for illustrative purposes and not for limiting purposes or specific usage. The protection scope of this invention should not be limited by their possible Chinese translations or specific letters.

[0005] A method for identifying hot spot patterns of lithography defects provided by the present invention in one aspect includes: Step S1. Obtain layout information and determine the layer to be identified in the layout, that is, the layer where the target pattern is located; Step S2. Preset a width range width, and set the width of the pattern perpendicular to the pattern direction as the line width; Identify the pattern with the line width within the width range as the initial polygon, and identify the contour edge along the pattern direction as the initial edge; Step S3. Preset a first spacing range and a second spacing range; Identify the interval area with the spacing between adjacent patterns within the first spacing range as the first interval area, and identify the interval area with the spacing between adjacent patterns within the second spacing range as the second interval area; Step S4. Identify the edge in the initial edges that contacts the first interval area as the first edge, and the edge that contacts the second interval area as the second edge; Step S5. Identify the polygon area in the initial polygon that satisfies that one side contour edge is the first edge and the other side contour edge is the second edge as plg_out, and identify the edges on both sides of plg_out as Edge_out; Step S6. Identify the interval area with the spacing between the Edge_out and the adjacent pattern within the preset RightSpace range as Fit_RS_plus, and identify the interval area with the spacing between the Edge_out and the adjacent pattern within the preset LeftSpace range as Fit_LS_plus; Step S7. One side of the Fit_LS_plus contacts the plg_out, identify the polygon area with the line width within the preset W1 range in the pattern that contacts the other side of the Fit_LS_plus as plg_out_LS, and identify the contour edge in the plg_out_LS that contacts the Fit_LS_plus as Fit_LSW_e; One side of the Fit_RS_plus contacts the plg_out, identify the polygon area with the line width within the preset W2 range in the pattern that contacts the other side of the Fit_RS_plus as plg_out_RS, and identify the contour edge in the plg_out_RS that contacts the Fit_RS_plus as Fit_RSW_e; Step S8. Identify the interval area between the Fit_LSW_e and the Edge_out as Fit_LSW, and identify the interval area between the Fit_RSW_e and the Edge_out as Fit_RSW; Step S9.Identify the contour edge in the plg_out that contacts the Fit_LSW as Fit_width_e_LSW, and identify the contour edge in the plg_out that contacts the Fit_RSW as Fit_width_e_RSW; identify the polygon area in the plg_out where one side contour edge is Fit_width_e_LSW and the other side contour edge is Fit_width_e_RSW as plg_out_plus; the plg_out_plus is the identified target pattern, that is, the lithography defect hot spot pattern.

[0006] In one implementation, the spacing between adjacent patterns in step S3 refers to the spacing between the initial polygon and its adjacent pattern.

[0007] In a specific implementation, the first spacer, the second spacer, Fit_RS_plus, Fit_LS_plus, Fit_LSW, and Fit_RSW are all polygons. The polygon area can be a rectangle or a polygon area that can be cut into several rectangles.

[0008] It also includes comparing whether one or more of the width range, the W1 range, the W2 range, the RightSpace range, and the LeftSpace range are included within the initial range according to a preset initial range, so as to evaluate the risk degree of the identified target pattern causing lithography defects.

[0009] The layer to be identified is one or more of a polysilicon layer, a metal layer, or an active region layer.

[0010] The RightSpace range and the LeftSpace range are different.

[0011] In the layer to be identified in the layout, the contour edges of all patterns are edges along the pattern direction or perpendicular to the pattern direction edges.

[0012] The graphic structure provided by another aspect of the present invention is obtained by identifying the lithography defect hot spot pattern of the present invention; it includes: a layer and the lithography defect hot spot pattern on the layer.

[0013] In a general case, the lithography defect hot spot pattern is a polygon pattern, denoted as plg_out_plus; and the polygon patterns on both sides of the plg_out_plus are respectively denoted as plg_out_LS_plus and plg_out_RS_plus; the width of the pattern perpendicular to the pattern direction is defined as the line width; the line width of the plg_out_plus is within a preset line width range width, the line width of the plg_out_LS_plus is within a preset W1 range, the line width of the plg_out_RS_plus is within a preset W2 range, and the distance between the plg_out_plus and the plg_out_LS_plus is within a preset LeftSpace range, and the distance between the plg_out_plus and the plg_out_RS_plus is within a preset RightSpace range.

[0014] The contour edges of all patterns in the layer are either the edges along the pattern direction or the edges perpendicular to the pattern direction.

[0015] The layer includes one or more of a polysilicon layer, a metal layer, and an active region layer.

[0016] The present invention has the following beneficial effects: (1) According to the method for identifying lithography defect hot spot patterns of the present invention, the initial edge and Edge_out can be quickly identified through the preset range, and then the plg_out_plus can be visually and accurately located, and the target pattern is identified as a lithography defect pattern, which is beneficial to improving the production process, with simple steps and high efficiency. (2) According to the graphic structure involved in the present invention, it can be obtained by the method for identifying lithography defect hot spot patterns of the present invention, which is beneficial to distinguishing whether the pattern has a risk of causing lithography defects in production and whether it needs to be particularly concerned as a hot spot pattern in production. Description of the Drawings

[0017] Figure 1 It is a schematic diagram of the graphic structure in Embodiment 1 of the present invention.

[0018] Figure 2 It is a schematic diagram of the method for identifying lithography defect hot spot patterns in Embodiment 1 of the present invention.

[0019] Figure 3 It is a schematic diagram of the initial edge in Embodiment 1 of the present invention.

[0020] Figure 4 It is a schematic diagram of the RightSpace range and the LeftSpace range in Embodiment 1 of the present invention.

[0021] Figure 5 It is a schematic diagram of the first spacer and the second spacer in Embodiment 1 of the present invention.

[0022] Figure 6 It is a schematic diagram of the first side and the second side in the first embodiment of the present invention.

[0023] Figure 7(a) is a schematic diagram of plg_out_LS in the first embodiment of the present invention.

[0024] Figure 7(b) is a schematic diagram of plg_out_RS in the first embodiment of the present invention.

[0025] Figure 8 It is a schematic diagram of the process of obtaining Fit_width_e_RSW and Fit_width_e_LSW in the second embodiment of the present invention.

[0026] Figure 9 It is a schematic diagram of the target graph in the first embodiment of the present invention. Detailed implementation manners

[0027] The above and / or additional aspects and advantages of the present invention will become obvious and easy to understand from the description of the embodiments in conjunction with the following drawings.

[0028] The embodiments disclosed by the present invention will be described in more detail below with reference to the drawings. Although some embodiments of the present invention are shown in the drawings, it should be understood that the present invention can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Instead, these embodiments are provided to more thoroughly and completely understand the present disclosure. It should be understood that the drawings and embodiments of the present invention are only for exemplary purposes and are not used to limit the protection scope of the present invention. In the following embodiments, the operations of the embodiments are depicted in a specific order. The description of these orders is for better understanding of the details in the embodiments to comprehensively understand the present invention, but the description of these orders does not necessarily correspond to the method of the present invention one by one, nor can the scope of the present invention be limited thereby.

[0029] It should be noted that the flowcharts and block diagrams in the drawings illustrate the possible operation processes of the methods according to the embodiments of the present invention. It should also be noted that in some alternative implementations, the functions marked in the blocks may also occur in a different order from that marked in the drawings. For example, two consecutive blocks shown may actually be executed substantially in parallel, and they may sometimes be executed alternately, depending on the purpose to be achieved by the steps involved. In addition, each block in the block diagram and / or flowchart, and the combination of the blocks in the block diagram and / or flowchart, can be implemented by a dedicated hardware-based system that performs the specified functions or operations, or can be implemented by a combination of dedicated hardware and manual operations.

[0030] First embodiment

[0031] For the convenience of description, in the following text, the graphic orientation is taken as the first direction Y, and the direction perpendicular to the graphic orientation is taken as the second direction X. It should be noted that in the actual situation, the graphic orientation involved in the present invention changes with the graphic. For the same graphic along its orientation, it may extend along the horizontal direction for a while and along the vertical direction for a while. The first direction Y and the second direction X are only for schematic illustration in cooperation with the attached drawings and are not actually fixed. Therefore, the graphic orientation of the present invention cannot be limited thereby. As Figure 1 shown, the graphic width of the polygon M in the second direction X is the line width LW; other adjacent graphics N are provided at a preset spacing S1 and a spacing S2 from the two side contour edges of the polygon graphic M in the second direction X respectively.

[0032] As Figure 2 shown and with reference to Figure 3 , in this embodiment, the lithography defect hot spot graphic recognition method can recognize the above lithography defect hot spot graphic structure, including: Step S1. Obtain layout information and determine the layer to be recognized in the layout. In this embodiment, the layer to be recognized is one of the polysilicon layer, the active region layer, and the metal layer. Step S2. Preset a width range, and recognize the polygon with the line width LW within the width range as the initial polygon, denoted as Fit_width_p, and recognize the contour edge along the first direction Y as the initial edge, denoted as Fit_width_e; Step S3. Preset a first spacing range and a second spacing range; recognize the interval area with the spacing between adjacent graphics within the first spacing range as the first interval area, and recognize the interval area with the spacing between adjacent graphics within the second spacing range as the second interval area; Step S4. Recognize the edge in the initial edge that contacts the first interval area as the first edge, and the edge that contacts the second interval area as the second edge; Step S5. Recognize the polygon area on the initial polygon Fit_width_p that satisfies that one side contour edge is the first edge and the other side contour edge is the second edge as plg_out, and recognize the edges on both sides of plg_out as Edge_out; Step S6. Recognize the interval area with the spacing between the Edge_out and the adjacent graphics within the preset RightSpace range as Fit_RS_plus, and recognize the interval area with the spacing between the Edge_out and the adjacent graphics within the preset LeftSpace range as Fit_LS_plus; Step S7. As Figure 7(a)-7(b)As shown, one side of the Fit_LS_plus contacts the plg_out. A polygonal region whose line width in the figure contacting the other side of the Fit_LS_plus is within a preset W1 range is identified as plg_out_LS, and the contour edge of the plg_out_LS contacting the Fit_LS_plus is identified as Fit_LSW_e; one side of the Fit_RS_plus contacts the plg_out. A polygonal region whose line width in the figure contacting the other side of the Fit_RS_plus is within a preset W2 range is identified as plg_out_RS, and the contour edge of the plg_out_RS contacting the Fit_RS_plus is identified as Fit_RSW_e; Step S8. The interval region between the Fit_LSW_e and the Edge_out is identified as Fit_LSW, and the interval region between the Fit_RSW_e and the Edge_out is identified as Fit_RSW; Step S9. The contour edge of the plg_out contacting the Fit_LSW is identified as Fit_width_e_LSW, and the contour edge of the plg_out contacting the Fit_RSW is identified as Fit_width_e_RSW; A polygonal region in the plg_out that satisfies one side contour edge being Fit_width_e_LSW and the other side contour edge being Fit_width_e_RSW is identified as plg_out_plus; The plg_out_plus is the identified target figure, that is, the lithography defect hot spot figure.

[0033] In this embodiment, the information recorded for the Fit_width_e_LSW and Fit_width_e_RSW also includes position information and length information, as the information of the identified target figure.

[0034] In a preferred practice of this embodiment, an initial range is also preset, and it is compared whether one or several of the width range, the W1 range, the RightSpace range, and the LeftSpace range are included within the initial range, so as to evaluate the risk degree of the identified target figure causing lithography defects.

[0035] Combined with reference Figure 1 , as Figure 4 , Figure 5In this embodiment, the LeftSpace range and the RightSpace range are different. The line segment in the Fit_width_e that contacts the Fit_LS is identified as the first side Fit_width_e_LS, and the line segment in the Fit_width_e that contacts the Fit_RS is identified as the second side Fit_width_e_RS. The polygonal area in the Fit_width_p that meets the requirement that one side of the contour edge belongs to Fit_width_e_RS and the other side of the contour edge belongs to Fit_width_e_LS is identified as plg_out. In this embodiment, it is also identified which side of the contour edge Fit_width_e_LS and Fit_width_e_RS are in the second direction X, to avoid false positives when the single-side condition is repeatedly entered, such as Figure 6 shown.

[0036] The spacing area between Edge_out and other adjacent graphics within the preset LeftSpace is identified as the first spacing area Fit_LS_plus, and the spacing area between Edge_out and other adjacent graphics within the RightSpace is identified as the second spacing area Fit_RS_plus.

[0037] In this embodiment, Edge_out_plus is also used as information of the identified target pattern. The photolithography defect hot spot pattern can be located by identifying plg_out_plus or its contour edge Edge_out_plus.

[0038] It should be noted that the above examples are only specific embodiments of the present invention. Obviously, the present invention is not limited to the above examples, and many variations are possible. All variations that can be directly derived or associated with the contents disclosed by a person skilled in the art should be considered as the protection scope of the present invention.

[0039] The above-mentioned implementation modes are preferred cases of the present invention and are not intended to limit the protection scope of the present invention. The details of these implementations should not be used to limit the present invention. The technical solutions between some practices described in the embodiments can be combined with each other, but they must be based on the ability of ordinary technicians in the field to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be considered that such combination of technical solutions does not exist and is not within the protection scope required by the present invention.

Claims

1. A method for identifying hot spot patterns of lithography defects, characterized in that: It includes: Step S1. Obtain layout information and determine the layer to be identified in the layout, that is, the layer where the target pattern is located; Step S2. Preset a width range width, and set the width of the pattern perpendicular to the pattern direction as the line width; Identify the pattern with the line width within the width range as the initial polygon, and identify the contour edge along the pattern direction as the initial edge; Step S3. Preset a first spacing range and a second spacing range; Identify the interval area with the spacing between adjacent patterns within the first spacing range as the first interval area, and identify the interval area with the spacing between adjacent patterns within the second spacing range as the second interval area; Step S4. Identify the edge in the initial edge that contacts the first interval area as the first edge, and the edge that contacts the second interval area as the second edge; Step S5. Identify the polygon area in the initial polygon that satisfies that one side contour edge is the first edge and the other side contour edge is the second edge as plg_out, and identify the edges on both sides of plg_out as Edge_out; Step S6. Identify the interval area with the spacing between the Edge_out and the adjacent pattern within the preset RightSpace range as Fit_RS_plus, and identify the interval area with the spacing between the Edge_out and the adjacent pattern within the preset LeftSpace range as Fit_LS_plus; One side of the Fit_LS_plus contacts the plg_out, identify the polygon area with the line width within the preset W1 range in the pattern that contacts the other side of the Fit_LS_plus as plg_out_LS, and identify the contour edge in the plg_out_LS that contacts the Fit_LS_plus as Fit_LSW_e; One side of the Fit_RS_plus contacts the plg_out, identify the polygon area with the line width within the preset W2 range in the pattern that contacts the other side of the Fit_RS_plus as plg_out_RS, and identify the contour edge in the plg_out_RS that contacts the Fit_RS_plus as Fit_RSW_e; Step S8. Identify the interval area between the Fit_LSW_e and the Edge_out as Fit_LSW, and identify the interval area between the Fit_RSW_e and the Edge_out as Fit_RSW; Step S9. Identify the contour edge in the plg_out that contacts the Fit_LSW as Fit_width_e_LSW, and identify the contour edge in the plg_out that contacts the Fit_RSW as Fit_width_e_RSW; In the plg_out, identify the polygonal region where one side contour edge is Fit_width_e_LSW and the other side contour edge is Fit_width_e_RSW as plg_out_plus; the plg_out_plus is the identified target pattern, that is, the lithography defect hot spot pattern.

2. A method for identifying a lithography defect hot spot pattern according to claim 1, wherein: The spacing between adjacent patterns in step S3 refers to the spacing between the initial polygon and its adjacent pattern.

3. A method for identifying a lithography defect hot spot pattern according to claim 1, wherein: The first spacer, the second spacer, Fit_RS_plus, Fit_LS_plus, Fit_LSW, and Fit_RSW are all polygons.

4. A method for identifying a lithography defect hot spot pattern according to claim 1, wherein: The layer to be identified is one or more of a polysilicon layer, a metal layer, or an active region layer.

5. A method for identifying a lithography defect hot spot pattern according to claim 1, wherein: In the layer to be identified in the layout, the contour edges of all patterns are either the edges along the pattern direction or perpendicular to the edges along the pattern direction.

6. A lithography defect hot spot pattern structure, wherein: It is identified by a method for identifying a lithography defect hot spot pattern according to any one of claims 1-5, and includes a layer and a lithography defect hot spot pattern on the layer.

7. A lithography defect hot spot pattern structure according to claim 6, wherein: The lithography defect hot spot pattern is a polygonal pattern, designated as plg_out_plus; and the polygonal patterns on both sides of the plg_out_plus are respectively designated as plg_out_LS_plus and plg_out_RS_plus; a) Let the width of the pattern perpendicular to the pattern direction be the line width; the line width of the plg_out_plus is within the preset line width range width, the line width of the plg_out_LS_plus is within the preset W1 range, the line width of the plg_out_RS_plus is within the preset W2 range, and the spacing between the plg_out_plus and the plg_out_LS_plus is within the preset LeftSpace range, and the spacing between the plg_out_plus and the plg_out_RS_plus is within the preset RightSpace range.

8. A lithography defect hot spot pattern structure according to claim 6, wherein: The layer includes one or more of a polysilicon layer, a metal layer, and an active region layer.

9. A lithography defect hot spot pattern structure according to claim 7, wherein: The contour edges of all patterns in the layer are either the edges along the pattern direction or perpendicular to the edges along the pattern direction.

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