Transformer device and semiconductor device

Abstract

The present invention relates to a transformer device and a semiconductor device. A transformer device is provided that can bond a wire to a pad on the upper side of an insulating layer that insulates between coils with high quality. The transformer device has: a planar first coil; a first insulating layer provided on the upper side of the first coil; an intermediate layer provided on the upper side of the first insulating layer; a second insulating layer provided on the upper side of the intermediate layer; a planar second coil provided on the upper side of the second insulating layer and opposed to the first coil; and a conductive pad provided on the upper side of the second insulating layer and connected to one end side of the second coil, the pad being disposed at a position that at least partially overlaps the intermediate layer in a top view, and the intermediate layer being harder than the first insulating layer and the second insulating layer.

Description

Technical Field

[0001] The present invention relates to a transformer device and a semiconductor device. Background Art

[0002] As a means for signal transmission between two circuits operating at different reference potentials, a technique of forming a coreless transformer on a semiconductor substrate and a technique of using an organic insulating film as an insulating layer between coils of the coreless transformer are known. For example, such a technique is disclosed in Patent Document 1.

[0003] Patent Document 1: Japanese Unexamined Patent Application Publication No. 2017-118128

[0004] In the prior art, there is a problem that when a wire is bonded to a pad formed on the upper side of an insulating layer that insulates between coils, the insulating layer is deformed and the bonding quality is reduced. Summary of the Invention

[0005] The present invention has been made to solve the above-described problems, and an object thereof is to provide a transformer device capable of bonding a wire to a pad on the upper side of an insulating layer that insulates between coils with high quality, and a semiconductor device having the transformer device.

[0006] According to one aspect of the present invention, there is provided a transformer device including: a planar first coil; a first insulating layer provided on the upper side of the first coil; an intermediate layer provided on the upper side of the first insulating layer; a second insulating layer provided on the upper side of the intermediate layer; a planar second coil provided on the upper side of the second insulating layer and opposed to the first coil; and a conductive pad provided on the upper side of the second insulating layer and connected to one end side of the second coil, the pad being disposed at a position that at least partially overlaps the intermediate layer in a plan view, and the intermediate layer being harder than the first insulating layer and the second insulating layer.

[0007] Further, according to another aspect of the present invention, there is provided a transformer device including: a planar first coil; a first insulating layer provided on the upper side of the first coil; an intermediate layer provided on the upper side of the first insulating layer; a second insulating layer provided on the upper side of the intermediate layer; a planar second coil provided on the upper side of the second insulating layer and opposed to the first coil; and a conductive pad provided on the upper side of the second insulating layer and connected to one end side of the second coil, the pad being disposed at a position that at least partially overlaps the intermediate layer in a plan view, the first insulating layer and the second insulating layer being organic insulating layers, and the intermediate layer being a metal layer or a glass layer.

[0008] In addition, according to another aspect of the present invention, there is provided a semiconductor device having: the transformer device of the present invention; and a semiconductor circuit electrically connected to the first coil or the second coil.

[0009] Effects of the Invention

[0010] The transformer device according to one aspect of the present invention has: a first insulating layer provided on the upper side of the first coil; an intermediate layer provided on the upper side of the first insulating layer; a second insulating layer provided on the upper side of the intermediate layer; and a conductive pad provided on the upper side of the second insulating layer and connected to one end side of the second coil. The pad is disposed at a position that at least partially overlaps the intermediate layer in a top view. The intermediate layer is harder than the first insulating layer and the second insulating layer. Thus, there is provided a transformer device capable of high-quality bonding of a wire to the pad on the upper side of the insulating layer that insulates between coils.

[0011] In addition, the transformer device according to another aspect of the present invention has: a first insulating layer provided on the upper side of the first coil; an intermediate layer provided on the upper side of the first insulating layer; a second insulating layer provided on the upper side of the intermediate layer; and a conductive pad provided on the upper side of the second insulating layer and connected to one end side of the second coil. The pad is disposed at a position that at least partially overlaps the intermediate layer in a top view. The first insulating layer and the second insulating layer are organic insulating layers, and the intermediate layer is a metal layer or a glass layer. Thus, there is provided a transformer device capable of high-quality bonding of a wire to the pad on the upper side of the insulating layer that insulates between coils.

[0012] In addition, the semiconductor device according to another aspect of the present invention has: the transformer device of the present invention; and a semiconductor circuit electrically connected to the first coil or the second coil. Thus, there is provided a semiconductor device having the transformer device of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 It is a diagram showing the semiconductor device of Embodiment 1.

[0014] Figure 2 It is a top view of the wiring layer and the pad of the semiconductor device of Embodiment 1.

[0015] Figure 3 It is a diagram showing a modified example of the semiconductor device of Embodiment 1.

[0016] Figure 4 It is a diagram showing a modified example of the semiconductor device of Embodiment 1.

[0017] Figure 5 It is a diagram showing the semiconductor device of Embodiment 2.

[0018] Figure 6This is a diagram showing the semiconductor device of Embodiment 3.

[0019] Figure 7 This is a diagram showing the semiconductor device of Embodiment 4.

[0020] Figure 8 This is a diagram showing the semiconductor device of Embodiment 5.

[0021] Figure 9 This is a top view of the intermediate layer and the insulating layer of the semiconductor device of Embodiment 5.

[0022] Figure 10 This is a diagram showing the semiconductor device of Embodiment 6.

[0023] Figure 11 This is a diagram showing a modified example of the semiconductor device of Embodiment 6.

[0024] Figure 12 This is a diagram showing the semiconductor device of Embodiment 7. Detailed Embodiment

[0025] In the following description, expressions such as "upper" and "lower" refer to designating one direction of the transformer device or the semiconductor device as the upper direction and the opposite direction as the lower direction, and do not limit the up-down direction during the manufacturing or use of the transformer device or the semiconductor device.

[0026] <A. Embodiment 1>

[0027] <A - 1. Structure>

[0028] Figure 1 This is a diagram showing the semiconductor device 200 of the present embodiment.

[0029] The semiconductor device 200 includes a transformer device 101, a circuit region 16, and a circuit region 23.

[0030] The transformer device 101 has: a substrate 1; an insulating layer 2 provided above the upper surface of the substrate 1; a wiring layer 3 provided above a partial region of the upper surface of the insulating layer 2; an insulating layer 4 provided above the upper surface of the wiring layer 3 and above the region of the upper surface of the insulating layer 2 where the wiring layer 3 is not provided; a wiring layer 5 provided above a partial region of the upper surface of the insulating layer 4; an insulating layer 7 provided above the region of the upper surface of the insulating layer 4 where the wiring layer 5 is not provided and above the upper surface of the wiring layer 5; an insulating layer 8 (an example of a first insulating layer) provided above the upper surface of the insulating layer 7; an intermediate layer 9 provided above a partial region of the upper surface of the insulating layer 8; an insulating layer 10 (an example of a second insulating layer) provided above the region of the upper surface of the insulating layer 8 where the intermediate layer 9 is not provided and above the upper surface of the intermediate layer 9; a wiring layer 11 provided above a partial region of the upper surface of the insulating layer 10; a pad 21 provided above a partial region of the upper surface of the insulating layer 10; a pad 22 provided above a partial region of the upper surface of the insulating layer 10; and an insulating layer 12 provided above the region of the upper surface of the insulating layer 10 where the wiring layer 11, the pad 21, and the pad 22 are not provided and above the wiring layer 11.

[0031] When viewed from above, the outer peripheral portions of the pad 21 and the pad 22 are covered by the insulating layer 12, and the central portions of the pad 21 and the pad 22 are not covered by the insulating layer 12.

[0032] The pad 21 is disposed at a position that at least partially overlaps with the intermediate layer 9 when viewed from above. For example, the pad 21 is disposed such that the entire pad 21 overlaps with the intermediate layer 9 when viewed from above. In Figure 1 FIG. shows a case where the pad 21 is disposed at a position that at least partially overlaps with the intermediate layer 9 when viewed from above. However, instead of the pad 21, the pad 22 may be disposed at a position that at least partially overlaps with the intermediate layer 9 when viewed from above, or both the pad 21 and the pad 22 may be disposed at positions that at least partially overlap with the intermediate layer 9 when viewed from above.

[0033] The intermediate layer 9 is formed so as not to protrude from the upper surface of the insulating layer 8. In Figure 1 FIG., the intermediate layer 9 is formed above a partial region of the upper surface of the insulating layer 8. However, the intermediate layer 9 may also be formed above the entire upper surface of the insulating layer 8. When viewed from above, if the intermediate layer 9 and the insulating layer 8 are formed in substantially the same region, for example, if the outer periphery of the intermediate layer 9 is included in a region within 1.5 μm from the outer periphery of the insulating layer 8, then during manufacturing, the same mask as the mask used for forming the insulating layer 8 can be used to form the intermediate layer 9.

[0034] The intermediate layer 9 is harder than the insulating layer 8 and the insulating layer 10. In the present invention, the hardness refers to the Vickers hardness. For example, the Vickers hardness of the intermediate layer 9 is greater than or equal to twice the Vickers hardness of the insulating layer 8 and the insulating layer 10.

[0035] The wiring layer 5 is the primary coil (an example of the first coil) of the transformer device 101, and the wiring layer 11 is the secondary coil (an example of the second coil) of the transformer device 101. Each of the wiring layer 5 and the wiring layer 11 is a planar coil. The wiring layer 5 as the planar coil and the wiring layer 11 as the planar coil are arranged to face each other. The transformer device 101 is a coreless transformer device, that is, signal transmission between the circuit connected to the wiring layer 5 and the circuit connected to the wiring layer 11 can be performed through magnetic coupling between the primary coil, i.e., the wiring layer 5, and the secondary coil, i.e., the wiring layer 11. Insulation between the wiring layer 5 and the wiring layer 11 is achieved through the insulating layer 8 and the insulating layer 10. In order to insulate between the wiring layer 5 and the wiring layer 11, it is preferable that each of the insulating layer 8 and the insulating layer 10 has a thickness of 5 μm or more.

[0036] The transformer device 101 also has a pad 14 and a pad 15. The pad 14 and the pad 15 are each provided on the insulating layer 4. The outer peripheral portions of the pad 14 and the pad 15 are covered by the insulating layer 7, and the central portions of the pad 14 and the pad 15 are not covered by the insulating layer 7.

[0037] One end of the circuit formed by the wiring layer 5, i.e., the end 13 located inside in a top view, is connected to the wiring layer 3 through the contact via hole 6 that penetrates the insulating layer 4 in the vertical direction. In addition, the other end of the circuit formed by the wiring layer 5, i.e., the end located outside in a top view, is connected to the pad 15. The wiring layer 3 is connected to the pad 14 through the contact via hole 40 that penetrates the insulating layer 4 in the vertical direction. That is, the wiring layer 5 is connected to the pad 14 through the contact via hole 6, the wiring layer 3, and the contact via hole 40.

[0038] The wiring layer 3, the wiring layer 5, the wiring layer 11, the contact via hole 6, the contact via hole 40, the pad 14, the pad 15, the pad 21, and the pad 22 each have conductivity.

[0039] Figure 2 is a top view of the wiring layer 11, the pad 21, and the pad 22. As Figure 2 shown, in a top view, the wiring layer 11 is formed in a spiral shape with the pad 21 as the center. One end of the circuit formed by the wiring layer 11, i.e., the end located inside in a top view, is connected to the pad 21. The other end of the circuit formed by the wiring layer 11, i.e., the end located outside in a top view, is connected to the pad 22.

[0040] The circuit region 16 has pads 17 and 18. The pad 17 and the pad 14 of the transformer device 101 are connected by a wire 19. The pad 18 and the pad 15 of the transformer device 101 are connected by a wire 20.

[0041] The circuit region 23 has pads 24 and 25. The pad 24 and the pad 22 of the transformer device 101 are connected by a wire 26. The pad 25 and the pad 21 of the transformer device 101 are connected by a wire 27.

[0042] In the circuit region 16, an n-channel lateral MOSFET is formed through an n-type semiconductor region 50, an n-type semiconductor region 51, a p-type semiconductor region 52, a gate electrode 53, and an insulating film 54. The lateral MOSFET is connected to the pad 17 via a contact via hole 55, and can be connected to an external circuit via a contact via hole 56. Similarly, a p-channel lateral MOSFET connected to the pad 18 via a contact via hole is formed in the circuit region 16, and this MOSFET can be connected to an external circuit via a contact via hole.

[0043] In the circuit region 23, an n-channel lateral MOSFET is formed through an n-type semiconductor region 60, an n-type semiconductor region 61, a p-type semiconductor region 62, a gate electrode 63, and an insulating film 64. The lateral MOSFET is connected to the pad 25 via a contact via hole 65, and can be connected to an external circuit via a contact via hole 66. Similarly, a p-channel lateral MOSFET connected to the pad 24 via a contact via hole is formed in the circuit region 23, and this MOSFET can be connected to an external circuit via a contact via hole.

[0044] In the circuit region 16, for example, a semiconductor circuit may also be formed, which is used to control the current flowing in the wiring layer 5 based on the signal to be transmitted to the circuit on the circuit region 23 side. In addition, in the circuit region 23, for example, a semiconductor circuit for restoring a signal according to the voltage generated in the wiring layer 11 may also be formed.

[0045] As described above, the transformer device 101 has: a wiring layer 5, which is a planar coil; an insulating layer 8, which is provided on the upper side of the wiring layer 5; an intermediate layer 9, which is provided on the upper side of the insulating layer 8; an insulating layer 10, which is provided on the upper side of the intermediate layer 9; a wiring layer 11, which is provided on the upper side of the insulating layer 10 and is a planar coil opposite to the wiring layer 5 as a planar coil; and a conductive pad 21, which is provided on the upper side of the insulating layer 10 and is connected to one end side of the wiring layer 11. In addition, the pad 21 is disposed at a position that at least partially overlaps the intermediate layer 9 in a top view, and the intermediate layer 9 is harder than the insulating layer 8 and the insulating layer 10. Thus, the bonding quality between the pad 21 and the wire 27 is high.

[0046] <A-2. Manufacturing Method>

[0047] When manufacturing the transformer device 101, for example, prepare the substrate 1, and successively form the insulating layer 2, wiring layer 3, insulating layer 4, contact via hole 6, contact via hole 40, wiring layer 5, pad 14, pad 15, insulating layer 7, insulating layer 8, intermediate layer 9, insulating layer 10, wiring layer 11, pad 21, pad 22, and insulating layer 12.

[0048] The substrate 1 is, for example, a substrate of a single semiconductor such as a silicon semiconductor substrate. The substrate 1 may also be a compound semiconductor substrate. The substrate 1 may also be a wide bandgap semiconductor substrate using SiC or GaN. The substrate 1 may also be an SOI (Silicon on Insulator) substrate. The substrate 1 may also be an insulator substrate using an insulator such as glass.

[0049] The insulating layer 2 is, for example, an SiO2 layer. The SiO2 layer as the insulating layer 2 is formed, for example, by coating TEOS (Tetraethylorthosilicate) or coating a solution containing SiO2. When the semiconductor substrate is used as the substrate 1, the insulating layer 2 may also be formed as a thermal oxide film.

[0050] The materials of the wiring layer 3, wiring layer 5, and wiring layer 11 are, for example, aluminum or a compound containing aluminum widely used in semiconductor processes. The materials of the wiring layer 3, wiring layer 5, and wiring layer 11 may also be other metals (such as copper), or conductors other than metals. Each of the wiring layer 3, wiring layer 5, and wiring layer 11 is, for example, obtained by patterning through wet etching or dry etching after forming a metal layer as a parent by sputtering. The wiring layer 3, wiring layer 5, and wiring layer 11 may also be formed by plating, for example.

[0051] The insulating layer 4 is, for example, an SiO2 layer. The SiO2 layer as the insulating layer 4 is formed, for example, by coating TEOS or coating a solution containing SiO2.

[0052] Each of the insulating layer 7 and insulating layer 12 is, for example, a SiN layer or a polyimide layer, but may also be an insulating layer formed using other materials. As a method of forming the polyimide layer as the insulating layer 7 or insulating layer 12, there is a method of forming a pattern by exposure after forming a layer by spin coating.

[0053] The insulating layers 8 and 10 are formed of, for example, polyimide with high insulating strength widely used in semiconductor processes. The insulating layers 8 and 10 may also be organic insulating layers formed of organic insulating materials other than polyimide. Additionally, the material of the insulating layer 8 and the material of the insulating layer 10 may be different. If the insulating layers 8 and 10 are organic insulating layers, the insulating layers 8 and 10 can be formed at low cost.

[0054] The intermediate layer 9 is formed of, for example, a conductor such as aluminum that is widely used in semiconductor manufacturing processes and is generally harder than organic insulating layers. By forming the intermediate layer 9 in the same manner as the wiring layers 3, 5, and 11, the intermediate layer 9 can be formed at low cost. The intermediate layer 9 is, for example, a metal, such as aluminum or copper, or a compound containing any of them. As long as the intermediate layer 9 is a layer harder than the insulating layers 8 and 10, it may also be an insulating layer such as a glass layer, for example. The intermediate layer 9 may also be a silicate glass layer, for example.

[0055] The intermediate layer 9 is a non-magnetic layer formed of a non-magnetic material (i.e., a material that is not a ferromagnetic material). The absolute value of the volume magnetic susceptibility of the intermediate layer 9 is, for example, less than or equal to 1×10 -3 . As long as the intermediate layer 9 has a small response to the magnetic field, the influence on the magnetic coupling between the wiring layer 5 and the wiring layer 11 caused by the provision of the intermediate layer 9 can be suppressed.

[0056] When manufacturing the semiconductor device 200 using the transformer device 101, the wire 27 is bonded to the pad 21, and the wire 26 is bonded to the pad 22. In the transformer device 101, an intermediate layer 9 having a hardness higher than that of the insulating layers 8 and 10 is formed between the insulating layers 8 and 10 that insulate between the wiring layer 5 and the wiring layer 11. Additionally, the pad 21 is disposed at a position that at least partially overlaps the intermediate layer 9 in a top view. Therefore, the insulating layers 8 and 10 are less likely to be deformed with respect to the pressure from above when the wire 27 is bonded to the pad 21. As a result, the bonding between the pad 21 and the wire 27 becomes stronger, and the wire 27 can be bonded to the pad 21 with high quality. Additionally, since the bonding quality between the pad 21 and the wire 27 is high, the quality of the semiconductor device 200 is improved.

[0057] <A - 3. Modification Example>

[0058] Regarding Figure 1For the semiconductor device 200 shown, the transformer device 101, the circuit region 16, and the circuit region 23 are each illustrated as different chips, but the circuit region 16 or the circuit region 23, or both, may be formed within the same chip as the transformer device 101. Further, when the transformer device 101 and the circuit region 16 or the circuit region 23 are formed within the same chip, the primary coil or the secondary coil of the transformer device 101 and the circuit region 16 or the circuit region 23 may be connected by a wiring layer formed within the chip instead of a wire.

[0059] In Figure 3 shows the semiconductor device 200 in the case where the circuit region 16 is formed within the same chip as the transformer device 101. For Figure 3 the semiconductor device 200 shown, the circuit region 16 and the wiring layer 5 are connected by the wiring layer 41 and the wiring layer 3. Different circuits such as MOSFETs that are different from the Figure 3 shown circuit may also be formed within the chip in which the transformer device 101 is formed.

[0060] Figure 1 Or Figure 3 the semiconductor device 200 shown has the transformer device 101 as the transformer device, but the semiconductor device 200 may also have the transformer devices of the respective embodiments described later in place of the transformer device 101.

[0061] In the present embodiment, as a typical example of the transformer device 101, a structure is shown in which the primary coil is formed as the wiring layer 5, and the wiring layer 5 and the pad 14 are connected via the wiring layer 3 below the wiring layer 5, but other wiring layers may be further formed above and below the wiring layer 3 and the wiring layer 5.

[0062] Further, the transformer device 101 may also be replaced with Figure 1 and be provided as Figure 4 shown. For Figure 4 the transformer device 101 having the structure shown, compared with the Figure 1 shown structure, there are no wiring layer 3 and insulating layer 4, and further, the wiring layer 5 and the pad 14 are connected via the diffusion layer 30 formed on the substrate 1. One end 13 of the wiring layer 5 and the diffusion layer 30 are connected by the contact via hole 28, and the pad 14 and the diffusion layer 30 are connected by the contact via hole 29. In Figure 4 the structure shown, the substrate 1 is a semiconductor substrate, and the diffusion layer 30, the contact via hole 28, and the contact via hole 29 are formed using ordinary semiconductor manufacturing processes.

[0063] <B. Embodiment 2>

[0064] Figure 5This is the transformer device 102 related to Embodiment 2.

[0065] Compared with the transformer device 101 of Embodiment 1, the transformer device 102 is different in that the intermediate layer 9 is formed to entirely cover the upper surface and the side surface of the insulating layer 8. The transformer device 102 is the same as the transformer device 101 in other aspects.

[0066] Regarding the transformer device 102, by using the intermediate layer 9 to entirely cover the upper surface and the side surface of the insulating layer 8 during etching, it is possible to prevent the insulating layer 8 from being damaged during the etching when forming the pattern of the intermediate layer 9, and thus prevent the insulation between the primary coil and the secondary coil from deteriorating.

[0067] <C. Embodiment 3>

[0068] Figure 6 This is a diagram showing the transformer device 103 related to Embodiment 3.

[0069] Compared with the transformer device 101 of Embodiment 1, the transformer device 103 is different in that in a top view, a partial area in the intermediate layer 9 is inserted from the upper side of the insulating layer 8 into the interior of the insulating layer 8. The transformer device 103 is the same as the transformer device 101 in other aspects. In particular, similar to the case of the transformer device 101, the intermediate layer 9 is harder than the insulating layer 8 and the insulating layer 10, and in addition, the pad 21 is disposed at a position that at least partially overlaps with the intermediate layer 9 in a top view.

[0070] Regarding the transformer device 103, since a partial area in the intermediate layer 9 is inserted from the upper side of the insulating layer 8 into the interior of the insulating layer 8 in a top view, the insulating layer 8 and the insulating layer 10 are less likely to be deformed when the wire is bonded to the pad 21. Thus, the wire can be bonded to the pad 21 with high quality. In addition, the adhesion between the intermediate layer 9 and the insulating layer 8 is improved, and the peeling between the intermediate layer 9 and the insulating layer 8 is less likely to occur.

[0071] <D. Embodiment 4>

[0072] Figure 7 This is a diagram showing the transformer device 104 related to Embodiment 4.

[0073] Compared with the transformer device 101 of Embodiment 1, the transformer device 104 is different in that in a top view, a partial area in the intermediate layer 9 penetrates the insulating layer 8 in the vertical direction and contacts the insulating layer 7. The transformer device 104 is the same as the transformer device 101 in other aspects. In particular, similar to the case of the transformer device 101, the intermediate layer 9 is harder than the insulating layer 8 and the insulating layer 10, and in addition, the pad 21 is disposed at a position that at least partially overlaps with the intermediate layer 9 in a top view.

[0074] The transformer device 104 has the same effects as the transformer device 103 of Embodiment 3. Further, in the case where the hardness of the insulating layer 7 is higher than the hardness of the insulating layer 8, since the intermediate layer 9 is in contact with the insulating layer 7, deformation of the intermediate layer 9 when bonding a wire to the pad 21 is suppressed, and as a result, the wire can be bonded to the pad 21 with high quality.

[0075] <E. Embodiment 5>

[0076] Figure 8 It is a diagram showing the transformer device 105 according to Embodiment 5.

[0077] Figure 9 It is a top view showing the insulating layer 8 and the intermediate layer 9 of the transformer device 105 according to Embodiment 5 extracted. In Figure 9 only a part near the intermediate layer 9 of the insulating layer 8 is shown. Further, in Figure 9 the arrangement of the pads 21 is shown by a dashed line.

[0078] The transformer device 105 is different from the transformer device 101 of Embodiment 1 in that holes penetrating in the vertical direction are provided in the intermediate layer 9. The transformer device 105 is the same as the transformer device 101 in other respects. In particular, also in the case of the transformer device 105, the intermediate layer 9 is harder than the insulating layer 8 and the insulating layer 10, and further, the pads 21 are arranged at positions that at least partially overlap with the intermediate layer 9 in a top view.

[0079] A plurality of holes penetrating in the vertical direction may be provided in the intermediate layer 9.

[0080] For the transformer devices of Embodiments 2 to 4, holes penetrating in the vertical direction may also be provided in the intermediate layer 9.

[0081] When pressure or other stress is applied to the intermediate layer 9 when bonding a wire to the pad 21, cracks may occur in the intermediate layer 9. However, by providing holes penetrating in the vertical direction in the intermediate layer 9, generation of cracks when pressure or stress is applied to the intermediate layer 9 can be suppressed.

[0082] <F. Embodiment 6>

[0083] Figure 10 It is a diagram showing the transformer device 106 according to Embodiment 6.

[0084] The transformer device 106 is different from the transformer device 101 of Embodiment 1 in that an insulating layer 31 is further provided between the insulating layer 8 and the intermediate layer 9. The insulating layer 31 is provided to entirely cover the upper surface and the side surface of the insulating layer 8. The transformer device 106 is the same as the transformer device 101 in other aspects. In particular, similar to the case of the transformer device 101, for the transformer device 106, the intermediate layer 9 is harder than the insulating layer 8 and the insulating layer 10, and further, the pad 21 is disposed at a position that at least partially overlaps with the intermediate layer 9 in a top view.

[0085] The insulating layer 31 may also be added to the transformer devices of Embodiments 2 to 5.

[0086] By providing the insulating layer 31, damage to the insulating layer 8 caused by processes such as etching when forming the intermediate layer 9 can be prevented.

[0087] In addition, the insulating layer 31 may be partially removed in the process after forming the intermediate layer 9, for example, as Figure 11 shown, the insulating layer 31 is formed on a part of the main surface of the insulating layer 8. Alternatively, the insulating layer 31 may be formed in a partial area below the intermediate layer 9 instead of the whole, and a partial area of the intermediate layer 9 in a top view contacts the insulating layer 8.

[0088] The insulating layer 31 may be an insulating layer using an insulator such as SiO2 or SiN widely used in semiconductor processes, or may be an inorganic insulating layer formed of other materials. In the case where the insulating layer 31 is partially removed in the process after forming the intermediate layer 9, for the insulating layer 31, it is preferable that the damage to the insulating layer 8 in the removal process is small or there is no damage to the insulating layer 8.

[0089] The thickness of the insulating layer 31 is, for example, thinner than that of the insulating layer 8 and the insulating layer 10. By setting the thickness of the insulating layer 31 to be less than or equal to 1 μm, for example, the additional cost caused by forming the insulating layer 31 can be suppressed.

[0090] <G. Embodiment 7>

[0091] Figure 12 It is a diagram showing the transformer device 107 according to Embodiment 7.

[0092] The transformer device 107 is a structure in which an insulating layer 32 is added between the insulating layer 8 and the insulating layer 10 with respect to the transformer device 101 of Embodiment 1. The transformer device 107 is the same as the transformer device 101 in other aspects. In particular, for the transformer device 107, the pad 21 is also disposed at a position that at least partially overlaps with the intermediate layer 9 in a top view. In addition, for the transformer device 107, the intermediate layer 9 is harder than the insulating layer 8, the insulating layer 10, and the insulating layer 32.

[0093] The insulating layer 32 is formed of polyimide, for example. The insulating layer 32 may also be an organic insulating layer formed of an organic insulating material other than polyimide. For any of the transformer devices in Embodiments 2 to 6, an insulating layer 32 may be added between the insulating layer 8 and the insulating layer 10.

[0094] Compared with the transformer device 101, in the transformer device 107, since the total thickness of the insulating layers between the wiring layer 5 and the wiring layer 11 increases, the insulation between the wiring layer 5 and the wiring layer 11 is improved. In addition, by increasing the number of layers, it is possible to easily increase the total thickness of the insulating layers between the wiring layer 5 and the wiring layer 11. For the transformer device 107, the fact that the insulating layer 8 and the insulating layer 32 are formed as different layers can be confirmed, for example, by observing a cross section as shown. Figure 12 as shown.

[0095] Compared with forming the intermediate layer 9 on the upper surface of the insulating layer 8, forming the intermediate layer 9 on the upper surface of the insulating layer 32 can further suppress the deformation around the pad 21 when bonding a wire to the pad 21, and can improve the bonding quality between the pad 21 and the wire. Therefore, this is preferred. However, when the intermediate layer 9 is formed on the upper surface of the insulating layer 8, the effect of suppressing the deformation around the pad 21 and improving the bonding quality between the pad 21 and the wire can also be obtained. In addition, in order to further improve the insulation between the wiring layer 5 and the wiring layer 11, other insulating layers may be further added in addition to the insulating layer 8, the insulating layer 32, and the insulating layer 10. That is, three or more insulating layers including the insulating layer 8 and the insulating layer 10 may be stacked in the vertical direction between the wiring layer 5 and the wiring layer 11. In this case, similarly, the intermediate layer 9 is disposed at a certain position between the three or more insulating layers, and by making the hardness of the intermediate layer 9 higher than the hardness of each of the three or more insulating layers, the effect of suppressing the deformation around the pad 21 and improving the bonding quality between the pad 21 and the wire can be obtained. In addition, if the three or more insulating layers are, for example, organic insulating layers, the three or more insulating layers can be formed at low cost.

[0096] In addition, the various embodiments can be freely combined, and the various embodiments can be appropriately deformed and omitted.

[0097] Description of Reference Numerals

[0098] 1 Substrate, 2, 4, 7, 8, 10, 12, 31, 32 Insulating layers, 3, 5, 11, 41 Wiring layers, 9 Intermediate layer, 14, 15, 17, 18, 21, 22, 24, 25 Pads, 16, 23 Circuit regions, 101, 102, 103, 104, 105, 106, 107 Transformer devices, 200 Semiconductor device.

Claims

1. A transformer device, comprising: A planar first coil; A first insulating layer disposed on the upper side of the first coil; An intermediate layer disposed on the upper side of the first insulating layer; A second insulating layer disposed on the upper side of the intermediate layer; A planar second coil disposed on the upper side of the second insulating layer and opposite to the first coil; And A conductive pad disposed on the upper side of the second insulating layer and connected to one end side of the second coil, The pad is disposed at a position that at least partially overlaps with the intermediate layer when viewed from above, The intermediate layer is harder than the first insulating layer and the second insulating layer, The intermediate layer entirely covers the upper surface and the side surface of the first insulating layer.

2. The transformer device according to claim 1, wherein The first insulating layer and the second insulating layer are organic insulating layers.

3. The transformer device according to claim 1, wherein The first insulating layer and the second insulating layer contain polyimide.

4. The transformer device according to any one of claims 1 to 3, wherein The intermediate layer is a conductor.

5. The transformer device according to claim 4, wherein The intermediate layer contains aluminum or copper.

6. The transformer device according to claim 2 or 3, wherein An inorganic insulating layer is further provided on the upper surface of the first insulating layer, At least a part of the intermediate layer is disposed on the upper surface of the inorganic insulating layer, The thickness of the inorganic insulating layer is less than or equal to 1 μm.

7. The transformer device according to claim 6, wherein The inorganic insulating layer entirely covers the upper surface and the side surface of the first insulating layer.

8. The transformer device according to claim 2 or 3, wherein Greater than or equal to 3 layers of organic insulating layers including the first insulating layer and the second insulating layer are stacked in the vertical direction between the first coil and the second coil.

9. The transformer device according to any one of claims 1 to 3, wherein Greater than or equal to 3 layers of insulating layers including the first insulating layer and the second insulating layer are stacked in the vertical direction between the first coil and the second coil, The intermediate layer is harder than each of the greater than or equal to 3 layers of insulating layers.

10. The transformer device according to any one of claims 1 to 3, wherein When viewed from above, the outer periphery of the intermediate layer is included in a region within 1.5 μm from the outer periphery of the first insulating layer.

11. The transformer device according to any one of claims 1 to 3, wherein When viewed from above, a local area in the intermediate layer is inserted from the upper side of the first insulating layer into the interior of the first insulating layer.

12. The transformer device according to any one of claims 1 to 3, wherein A third insulating layer is further provided on the upper side of the first coil and below the first insulating layer, The third insulating layer is harder than the first insulating layer, When viewed from above, a local area in the intermediate layer penetrates the first insulating layer and contacts the third insulating layer.

13. The transformer device according to any one of claims 1 to 3, wherein, a hole penetrating in the vertical direction is provided in the intermediate layer.

14. The transformer device according to any one of claims 1 to 3, wherein, the thicknesses of the first insulating layer and the second insulating layer are each greater than or equal to 5 μm.

15. The transformer device according to any one of claims 1 to 3, wherein, the intermediate layer is a non-magnetic layer.

16. A transformer device, comprising: a planar first coil; a first insulating layer provided on the upper side of the first coil; an intermediate layer provided on the upper side of the first insulating layer; a second insulating layer provided on the upper side of the intermediate layer; a planar second coil provided on the upper side of the second insulating layer and opposed to the first coil; and a conductive pad provided on the upper side of the second insulating layer and connected to one end side of the second coil, the pad is disposed at a position where it at least partially overlaps with the intermediate layer in a top view, the first insulating layer and the second insulating layer are organic insulating layers, the intermediate layer is a metal layer or a glass layer, the intermediate layer entirely covers the upper surface and the side surface of the first insulating layer.

17. The transformer device according to claim 16, wherein, the first insulating layer and the second insulating layer contain polyimide.

18. The transformer device according to claim 16, wherein, the intermediate layer contains aluminum or copper.

19. The transformer device according to any one of claims 16 to 18, wherein, it further has an inorganic insulating layer provided on the upper surface of the first insulating layer, at least a part of the intermediate layer is provided on the upper surface of the inorganic insulating layer, the thickness of the inorganic insulating layer is less than or equal to 1 μm.

20. The transformer device according to claim 19, wherein, the inorganic insulating layer entirely covers the upper surface and the side surface of the first insulating layer.

21. The transformer device according to any one of claims 16 to 18, wherein, more than or equal to 3 layers of organic insulating layers including the first insulating layer and the second insulating layer are laminated in the vertical direction between the first coil and the second coil.

22. The transformer device according to any one of claims 16 to 18, wherein, more than or equal to 3 layers of insulating layers including the first insulating layer and the second insulating layer are laminated in the vertical direction between the first coil and the second coil, the intermediate layer is harder than each of the more than or equal to 3 layers of insulating layers.

23. The transformer device according to any one of claims 16 to 18, wherein, in a top view, the outer periphery of the intermediate layer is included in a region within 1.5 μm from the outer periphery of the first insulating layer.

24. The transformer device according to any one of claims 16 to 18, wherein, in a top view, a partial region in the intermediate layer is inserted from the upper side of the first insulating layer into the inside of the first insulating layer.

25. The transformer device according to any one of claims 16 to 18, wherein, There is also a third insulating layer disposed on the upper side of the first coil and below the first insulating layer. The third insulating layer has a higher hardness than the first insulating layer. When viewed from above, a local area in the intermediate layer penetrates the first insulating layer and contacts the third insulating layer.

26. The transformer device according to any one of claims 16 to 18, wherein A hole penetrating in the vertical direction is provided in the intermediate layer.

27. The transformer device according to any one of claims 16 to 18, wherein The thicknesses of the first insulating layer and the second insulating layer are each greater than or equal to 5 μm.

28. The transformer device according to any one of claims 16 to 18, wherein The intermediate layer is a non-magnetic layer.

29. A semiconductor device having: The transformer device according to any one of claims 16 to 28; and A semiconductor circuit electrically connected to the first coil or the second coil.

30. The semiconductor device according to claim 29, wherein The transformer device and the semiconductor circuit are formed on the same chip.

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