Method for forming semiconductor structure

Abstract

A method for forming a semiconductor structure, the method comprising: providing a substrate, the substrate comprising a first region and a second region, the substrate comprising a substrate, a fin separated from the substrate, an isolation layer located on the fin and exposed on the substrate, a dummy gate structure located on the isolation layer and spanning the fin, and an interlayer dielectric layer covering the sidewall of the dummy gate structure and exposing the top of the dummy gate structure; removing the dummy gate structure, forming a gate opening in the interlayer dielectric layer; forming an annealed sacrificial layer in the gate opening; removing the annealed sacrificial layer; forming a mask layer having a first groove, the extension direction of the first groove being the same as the extension direction of the fin, the first groove exposing a portion of the gate opening at the junction of the first region and the second region; and forming a first blocking layer in the first groove. Therefore, the removal process window of the annealed sacrificial layer at the junction of the first region and the second region is large, and it is not easy to have residues, so that the first gate structure and the second gate structure can better control the threshold voltage of the semiconductor structure.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular to a method for forming a semiconductor structure. Background Art

[0002] In semiconductor manufacturing, with the development trend of ultra-large-scale integrated circuits, the feature size of integrated circuits continues to decrease. In order to adapt to smaller feature sizes, the channel length of metal-oxide-semiconductor field-effect transistors (MOSFETs) is also shortened accordingly. However, as the channel length of the device shortens, the distance between the source and drain of the device also shortens, so the control ability of the gate structure over the channel becomes worse, and the difficulty of pinching off the channel by the gate voltage becomes increasingly greater, making subthreshold leakage, the so-called short-channel effects (SCE), more likely to occur.

[0003] Therefore, in order to better adapt to the reduction of feature size, semiconductor processes have gradually begun to transition from planar MOSFET to three-dimensional transistors with higher power efficiency, such as fin field effect transistors (FinFET). In FinFET, the gate structure can control the ultra-thin body (fin) from at least two sides. Compared with planar MOSFET, the gate structure has a stronger control ability over the channel and can effectively suppress the short channel effect; the gate structure has also changed from the original polysilicon gate structure to the metal gate structure. The work function layer in the metal gate structure can adjust the threshold voltage of the semiconductor structure.

[0004] Threshold voltage is an important parameter of transistors and has a significant impact on the performance of transistors. Summary of the invention

[0005] The problem solved by the embodiments of the present invention is to provide a method for forming a semiconductor structure, so that the threshold voltage of the semiconductor structure meets the process requirements and the electrical performance of the semiconductor structure is optimized.

[0006] To solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate comprising a first region and a second region adjacent to each other, the substrate comprising a substrate, a fin separated from the substrate, an isolation layer located on the fin and exposed on the substrate, a dummy gate structure located on the isolation layer and spanning the fin, and an interlayer dielectric layer covering the sidewalls of the dummy gate structure and exposing the top of the dummy gate structure; removing the dummy gate structure to form a gate opening in the interlayer dielectric layer; forming a gate dielectric layer conformally covering the gate opening; forming an annealed sacrificial layer covering the gate dielectric layer in the gate opening; removing the annealed sacrificial layer; after removing the annealed sacrificial layer, forming a mask layer having a first groove in the gate opening and on the interlayer dielectric layer, the extension direction of the first groove being the same as the extension direction of the fin, the first groove exposing a portion of the gate opening at the junction of the first region and the second region; and forming a first blocking layer in the first groove.

[0007] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0008] In the method for forming a semiconductor structure provided in an embodiment of the present invention, the pseudo gate structure is removed, and after a gate opening is formed in the interlayer dielectric layer, a gate dielectric layer conformally covering the gate opening is formed. After the gate dielectric layer is formed, in the step of forming the annealing sacrificial layer, the gate dielectric layer is repaired to improve the density of the gate dielectric layer. After the annealing sacrificial layer is removed, a mask layer having a first groove is formed in the gate opening and on the interlayer dielectric layer, the extension direction of the first groove is the same as the extension direction of the fin, the first groove exposes a portion of the gate opening at the junction of the first region and the second region, and a first blocking layer is formed in the first groove. In an embodiment of the present invention, compared with the situation in which, after forming a dummy gate structure, a blocking layer of the dummy gate structure is formed that penetrates the junction of the first region and the second region, and then the dummy gate structure is removed to form a gate opening, a gate dielectric layer and an annealed sacrificial layer covering the gate dielectric layer are formed in the gate opening, and then the annealed sacrificial layer is removed, in an embodiment of the present invention, in the step of removing the annealed sacrificial layer, no blocking layer is formed at the junction of the first region and the second region. Therefore, the removal process window of the annealed sacrificial layer at the junction of the first region and the second region is large, easy to remove, and less likely to have residue. Subsequently, the mask layer is removed to form a first gate structure in the gate opening of the first region and a second gate structure in the gate opening of the second region. The first gate structure and the second gate structure will not be formed on the residual annealed sacrificial layer, so that the first gate structure and the second gate structure can better control the threshold voltage of the semiconductor structure, which is beneficial to improving the electrical reliability of the semiconductor structure.

[0009] In an optional solution, in the step of forming the mask layer, the mask layer further has a second groove that exposes part of the gate opening, and the extension direction of the second groove is perpendicular to the extension direction of the fin. The mask layer formed in the embodiment of the present invention has both the first groove and the second groove, that is, the first groove and the second groove are formed by an all-in-one (AIO) etching process. Compared with the case where the mask layer with the first groove and the mask layer with the second groove are formed successively, the cost of the mask is saved in the embodiment of the present invention, which is conducive to reducing the process flow of the semiconductor formation method and increasing the yield. In addition, after forming the mask layer and before forming the first blocking layer, the fin exposed by the second groove is removed to form the second opening. In the step of forming the first blocking layer in the first groove, the second blocking layer is also formed in the second groove and the opening, that is, the first blocking layer and the second blocking layer are formed at the same time. Compared with the case where the first blocking layer and the second blocking layer are formed separately in different steps, the formation process of the first blocking layer and the second blocking layer is simplified, which is conducive to reducing the process flow of the semiconductor formation method and improving the yield of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figures 1 to 13 It is a schematic structural diagram corresponding to each step in a method for forming a semiconductor structure;

[0011] Figures 14 to 32 It is a schematic structural diagram corresponding to each step in a method for forming a semiconductor structure according to an embodiment of the present invention. DETAILED DESCRIPTION

[0012] As can be seen from the background technology, the semiconductor structure currently formed still has the problem of poor electrical performance. Now, in combination with a method for forming a semiconductor structure, the reasons for the poor electrical performance of the semiconductor structure are analyzed.

[0013] refer to Figures 1 to 13 , showing a structural schematic diagram corresponding to each step in a method for forming a semiconductor structure.

[0014] like Figure 1 and Figure 2 As shown, Figure 1 is a top view, Figure 2 for Figure 1 In the cross-sectional view at aa, a substrate is provided, the substrate includes a substrate 1, a fin 2 separated from the substrate 1, an isolation layer 4 located on the fin 2 exposed from the substrate 1, a pseudo gate structure 3 located on the isolation layer 4 and spanning the fin 2, and a source-drain doping layer (not shown in the figure) in the fin 2 on both sides of the pseudo gate structure 3, and the substrate includes adjacent first regions I and second regions II.

[0015] The pseudo gate structure 3 is formed by a self-aligned double patterning process (SADP). Specifically, the formation process of the pseudo gate structure 3 includes: forming a pseudo gate material layer covering the fin 2 on the isolation layer 4; forming a core layer (mandrel) (not shown in the figure) on the pseudo gate material layer; forming a side wall material layer (not shown in the figure) conformally covering the core layer and the pseudo gate material layer; removing the side wall material layer on the top of the core layer and the top of the pseudo gate material layer, and the remaining side wall material layer located on the side wall of the core layer is used as the side wall layer; removing the core layer; using the side wall layer as a mask, patterning the pseudo gate material layer to form the pseudo gate structure 3.

[0016] It should be noted that the two ends of the core layer in the extension direction are located outside the first region I and the second region II, and correspondingly, the two ends of the dummy gate structure 3 in the extension direction are located outside the first region I and the second region II.

[0017] like Figure 3 and Figure 4 As shown, Figure 3 is a top view, Figure 4 for Figure 3 In the cross-sectional view at aa, an interlayer dielectric layer 5 is formed to cover the source-drain doping layer, and the interlayer dielectric layer 5 exposes the top of the dummy gate structure 3; a mask layer (not shown in the figure) is formed on the interlayer dielectric layer 5 and the dummy gate structure 3, and the mask layer has an opening that exposes a portion of the dummy gate structure 3 on the isolation layer 4 at the junction of the first region I and the second region II; the dummy gate structure 3 exposed by the opening is removed, and a blocking opening (P2 cut) (not shown in the figure) that cuts off a portion of the dummy gate structure 3 on the isolation layer 4 at the junction of the first region I and the second region II is formed in a direction perpendicular to the extension direction of the dummy gate structure 3; and a blocking layer 6 is formed in the blocking opening.

[0018] It should be noted that the opening in the mask layer also exposes the pseudo gate structure 3 outside the first region I and the second region II; in the process of forming the blocking opening, the pseudo gate structure 3 outside the first region I and the second region II is also etched to form an external opening; in the process of forming the blocking layer 6 in the blocking opening, an external blocking layer 7 is formed in the external opening.

[0019] like Figure 5 and Figure 6 As shown, Figure 5 is a top view, Figure 6 for Figure 5 In the cross-sectional view at aa, the dummy gate structure 3 is removed to form a gate opening 8 .

[0020] like Figure 7As shown, a gate dielectric layer 9 is formed to conformally cover the gate opening 8; a cap layer (not shown in the figure) is formed in the gate opening 8 to conformally cover the gate dielectric layer 9; an annealed sacrificial layer (not shown in the figure) is formed to cover the cap layer, and the formation process of the annealed sacrificial layer includes annealing treatment (Anneal) for repairing the gate dielectric layer 9 and improving the density of the gate dielectric layer 9; and the annealed sacrificial layer is removed.

[0021] like Figure 8 and Fig. 9 As shown, Figure 8 is a top view, Fig. 9 for Figure 8 In the cross-sectional view at aa, a first work function layer (not shown in the figure) is formed in the first region I; a second work function layer (not shown in the figure) is formed in the second region II; a gate layer (not shown in the figure) is formed on the first work function layer and the second work function layer, the first work function layer and the gate layer serve as a first gate structure 10, and the second work function layer and the gate layer serve as a second gate structure 11.

[0022] like Fig.10 and Fig.11 As shown, Fig.10 is a top view, Fig.11 for Fig.10 In the cross-sectional view at aa, a shielding layer 12 is formed on the first gate structure 10 , the second gate structure 11 , the blocking layer 6 and the external blocking layer 7 , and the shielding layer 12 has a groove 13 , and the groove 13 exposes a portion of the first gate structure 10 and the second gate structure 11 .

[0023] like Fig.12 As shown, the first gate structure 10 and the second gate structure 11 exposed by the groove 13 and the fin 2 are etched using the blocking layer 12 as a mask to form a single diffusion break (SDB) opening 14 .

[0024] like Fig.13 As shown, a single diffusion interruption layer 15 is formed in the single diffusion interruption opening 14 .

[0025] The step of forming the annealed sacrificial layer includes an annealing treatment, and the annealing treatment is used to repair the gate dielectric layer 9, so as to improve the quality and performance of the gate dielectric layer 9, and further improve the electrical performance and reliability performance of the formed semiconductor structure. The blocking opening cuts off the pseudo gate structure 3 on the isolation layer 4 at the junction of the first region I and the second region II. Because the isolation layer 4 is formed on the substrate 1 between the fins 2, the blocking opening is located on the isolation layer 4 between the fins 2, and the corresponding blocking layer 6 is located on the isolation layer 4 between the fins 2. As the integration of semiconductor structures becomes higher and higher, the interval between adjacent fins 2 becomes smaller and smaller, and the blocking layer 6 is located between the fins 2, so that the interval between the blocking layer 6 and the fins 2 becomes smaller and smaller, and the corresponding external blocking layer 7 is smaller from the fins 2 in the first region I and the second region II. In the step of removing the annealed sacrificial layer, because the removal window of the annealed sacrificial layer between the blocking layer 6 and the fin 2 is small, it is easy to have residual annealed sacrificial layer 20 (such as Figure 7 As shown in FIG. 1 , there is also a residual annealed sacrificial layer 20 between the external blocking layer 7 and the fins 2 in the first region I and the second region II.

[0026] In the subsequent process of forming the first gate structure 10 and the second gate structure 11, the second gate structure 11 will be formed on the residual annealed sacrificial layer 20. When the semiconductor structure is working, the residual annealed sacrificial layer 20 formed in the second region II will cause the threshold voltage of the second region II to fail to meet the process requirements. In addition, it will also cause the electrical reliability of the semiconductor structure to be poor.

[0027] In addition, it is also necessary to explain that a blocking opening is formed, a blocking layer 6 is formed in the blocking opening, a single diffusion interrupt opening 14 is formed, and a single diffusion interrupt layer 15 is formed in the single diffusion interrupt opening 14. The blocking opening and the single diffusion interrupt opening 14 are formed in different steps, which results in complicated steps for forming the semiconductor structure, which is not conducive to improving the formation efficiency of the semiconductor structure and has low yield.

[0028] In the process of etching the groove 13 to expose the first gate structure 10 and the second gate structure 11 and the fin 2 to form the single diffusion interruption opening 14, the gate layer, the first work function layer and the second work function layer need to be etched, and the process controllability is poor.

[0029] In order to solve the technical problem, in the method for forming a semiconductor structure provided in an embodiment of the present invention, the pseudo gate structure is removed, and after a gate opening is formed in the interlayer dielectric layer, a gate dielectric layer conformally covering the gate opening is formed. After the gate dielectric layer is formed, in the step of forming the annealing sacrificial layer, the gate dielectric layer is repaired to improve the density of the gate dielectric layer; after the annealing sacrificial layer is removed, a mask layer having a first groove is formed in the gate opening and on the interlayer dielectric layer, the extension direction of the first groove is the same as the extension direction of the fin, the first groove exposes a portion of the gate opening at the junction of the first region and the second region, and a first blocking layer is formed in the first groove. In an embodiment of the present invention, compared with the situation in which, after forming a dummy gate structure, a blocking layer of the dummy gate structure is formed that penetrates the junction of the first region and the second region, and then the dummy gate structure is removed to form a gate opening, a gate dielectric layer and an annealed sacrificial layer covering the gate dielectric layer are formed in the gate opening, and then the annealed sacrificial layer is removed, in an embodiment of the present invention, in the step of removing the annealed sacrificial layer, no blocking layer is formed at the junction of the first region and the second region. Therefore, the removal process window of the annealed sacrificial layer at the junction of the first region and the second region is large, easy to remove, and less likely to have residue. Subsequently, the mask layer is removed to form a first gate structure in the gate opening of the first region and a second gate structure in the gate opening of the second region. The first gate structure and the second gate structure will not be formed on the residual annealed sacrificial layer, so that the first gate structure and the second gate structure can better control the threshold voltage of the semiconductor structure, which is beneficial to improving the electrical reliability of the semiconductor structure.

[0030] Figures 14 to 32 , is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure according to an embodiment of the present invention.

[0031] refer to Figure 14 to Figure 15 , Fig.14 It is a top view. Fig.15 for Fig.14 In the cross-sectional view at AA, a substrate is provided, the substrate includes a first region I and a second region II, the substrate includes a substrate 100, a fin 104 separated from the substrate 100, an isolation layer 101 located on the fin 104 and exposed on the substrate 100, a pseudo gate structure 102 located on the isolation layer 101 and spanning the fin 104, and an interlayer dielectric layer 103 covering the sidewalls of the pseudo gate structure 102 and exposing the top of the pseudo gate structure 102.

[0032] The substrate provides a process basis for the subsequent formation of a semiconductor structure. In this embodiment, the first region I is used to form an NMOS (Negative channel Metal Oxide Semiconductor), and the second region II is used to form a PMOS (Positive Channel Metal Oxide Semiconductor). In other embodiments, the first region I is used to form a PMOS, and the second region II is used to form an NMOS. In other embodiments, the first region I and the second region II can also form a PMOS or NMOS at the same time.

[0033] In this embodiment, the semiconductor structure subsequently formed is a fin field effect transistor (FinFET) as an example. In other embodiments, the substrate further includes a channel stack located on the fin, the channel stack includes a sacrificial layer and a channel layer located on the sacrificial layer, and accordingly, the semiconductor structure subsequently formed is a gate-all-around transistor (GAA).

[0034] In this embodiment, the substrate 100 is a silicon substrate. In other embodiments, the substrate material may also be other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium, and the substrate may also be other types of substrates such as a silicon on insulator substrate or a germanium on insulator substrate.

[0035] The fin 104 is located in the first region I and the second region II.

[0036] In this embodiment, the material of the fin 104 is the same as that of the substrate 100 , including silicon.

[0037] The isolation layer 101 is used to electrically isolate the substrate 100 from a gate structure formed subsequently. The isolation layer 101 covers a portion of the sidewall of the fin 104 .

[0038] In this embodiment, the material of the isolation layer 101 includes silicon oxide. Silicon oxide is a commonly used dielectric material with low cost and high process compatibility, which is conducive to reducing the process difficulty and process cost of forming the isolation layer 101.

[0039] The dummy gate structure 102 is used to occupy process space for subsequently forming a gate structure.

[0040] In this embodiment, the dummy gate structure 102 is formed by a self-aligned double patterning process (SADP). In other embodiments, the dummy gate structure may also be formed by a self-aligned quadruple patterning process (SAQP).

[0041] Specifically, the steps of forming the pseudo gate structure 102 include: forming a pseudo gate material layer covering the fin 104 on the isolation layer 101; forming a core layer (mandrel) (not shown in the figure) on the pseudo gate material layer; forming a sidewall material layer (not shown in the figure) conformally covering the core layer and the pseudo gate material layer; removing the sidewall material layer on the top of the core layer and the top of the pseudo gate material layer, and the remaining sidewall material layer located on the side wall of the core layer serves as the sidewall layer; removing the core layer; using the sidewall layer as a mask, patterning the pseudo gate material layer to form the pseudo gate structure 102.

[0042] Since the sidewall material layer covers the sidewalls and ends of the core layer, the sidewall layer is annular. Accordingly, the pseudo gate structure 102 is annular, and the extension direction of the pseudo gate structure 102 located in the first region I and the second region II is perpendicular to the fin 104, and the two ends of the pseudo gate structure 102 along its extension direction are located outside the first region I and the second region II.

[0043] The two ends of the dummy gate structure 102 along the extension direction thereof are located outside the first region I and the second region II, so that the length of the dummy gate structure 102 can meet the process requirements. Accordingly, in the step of forming the core layer, along the extension direction of the core layer, the core layer spans the first region I and the second region II, and the two ends of the core layer along the extension direction thereof are located outside the first region I and the second region II.

[0044] In this embodiment, the dummy gate structure 102 is a stacked structure, including a dummy gate oxide layer (not shown) and a dummy gate layer (not shown) located on the dummy gate oxide layer. In other embodiments, the dummy gate structure may also be a single-layer structure.

[0045] Specifically, the dummy gate oxide layer includes silicon oxide, and the dummy gate layer includes polysilicon.

[0046] In the step of providing a substrate, the substrate further includes: a source-drain doping layer (not shown in the figure) located in the fins 104 on both sides of the dummy gate structure 102 .

[0047] When the semiconductor structure is working, the source-drain doped layer is used to provide stress to the channel and increase the migration rate of carriers in the channel.

[0048] In this embodiment, the first region I is used to form an NMOS, and the source-drain doping layer is silicon carbide or silicon phosphide doped with N-type ions. In this embodiment, the N-type ions include: phosphorus, arsenic or antimony. The second region II is used to form a PMOS. The source-drain doping layer is silicon germanium doped with P-type ions. In this embodiment, the P-type ions include: boron, gallium or indium.

[0049] It should be noted that in the step of providing a substrate, the substrate further includes: a sidewall layer (not shown in the figure), which is formed on the sidewall of the dummy gate structure 102. This makes it difficult for the source-drain doped layer and the subsequently formed gate structure to bridge, reduces the capacitive coupling effect between the source-drain doped layer and the gate structure, and is conducive to improving the electrical performance of the semiconductor structure.

[0050] The material of the spacer layer includes: SiON, SiBCN, SiCN, SiN. In this embodiment, the material of the spacer layer is SiN.

[0051] The interlayer dielectric layer 103 is used to electrically isolate adjacent devices.

[0052] In this embodiment, the material of the interlayer dielectric layer 103 is an insulating material. Specifically, the material of the interlayer dielectric layer 103 includes silicon oxide. Silicon oxide is a commonly used dielectric material with low cost and has high process compatibility, which is conducive to reducing the process difficulty and process cost of forming the interlayer dielectric layer 103.

[0053] It should be noted that the interlayer dielectric layer 103 exposes the top of the dummy gate structure 102 to prepare for the subsequent removal of the dummy gate structure 102 .

[0054] refer to Fig.16 and Fig.17 , the dummy gate structure 102 is removed, and a gate opening 105 is formed in the interlayer dielectric layer 103 .

[0055] The gate opening 105 is prepared for the subsequent formation of a gate structure.

[0056] In this embodiment, a wet etching process is used to remove the dummy gate structure 102. The wet etching process has a high etching rate, simple operation and low process cost.

[0057] In this embodiment, the dummy gate structure 102 includes a dummy gate oxide layer and a dummy gate layer. The dummy gate oxide layer is made of silicon oxide, and the dummy gate layer is made of polysilicon. Specifically, in the step of removing the dummy gate structure 102, the etching solution used includes ammonia water and tetramethylammonium hydroxide solution.

[0058] It should be noted that, because both ends of part of the pseudo gate structure 102 are located outside the first region I and the second region II in the extension direction perpendicular to the fin 104, in the step of forming the gate opening 105, the gate opening 105 is also formed outside the first region I and the second region II.

[0059] refer to Fig.18 , forming a gate dielectric layer 106 conformally covering the gate opening 105 .

[0060] The gate dielectric layer 106 is used to electrically isolate the fin 104 from the gate structure formed subsequently. It should be noted that the gate dielectric layer 106 is made of a high-k dielectric material, which refers to a dielectric material having a relative dielectric constant greater than that of silicon oxide.

[0061] In this embodiment, the material of the gate dielectric layer 106 is HfO 2 In other embodiments, the material of the gate dielectric layer 106 may also be selected from ZrO 2 , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO or Al 2 O 3 One or more of the .

[0062] In this embodiment, the gate dielectric layer 106 is formed by an atomic layer deposition process (Atomic Layer Deposition, ALD). The atomic layer deposition process can accurately control the thickness of the gate dielectric layer 106, and the atomic layer deposition process has good gap filling performance and step coverage, so that the gate dielectric layer 106 can conformally cover the bottom and sidewalls of the gate opening 105, and can better electrically isolate the fin 104 and the subsequently formed gate structure. In other embodiments, the gate dielectric layer can also be formed by a chemical vapor deposition process (Chemical Vapor Deposition, CVD).

[0063] The method for forming the semiconductor structure further includes: after forming the gate dielectric layer 106 conformally covering the gate opening 105 , forming a cap layer 107 conformally covering the gate opening 105 .

[0064] After forming the cap layer 107, an annealed sacrificial layer is formed in the gate opening 105. The formation process of the annealed sacrificial layer includes annealing treatment, which is used to repair the gate dielectric layer 106 and improve the density of the gate dielectric layer 106. In the step of removing the annealed sacrificial layer, the cap layer 107 is used to protect the gate dielectric layer 106 from being easily damaged.

[0065] In addition, after the annealed sacrificial layer is subsequently removed, a work function layer is formed on the cap layer 107. The cap layer 107 is formed between the gate dielectric layer 106 and the work function layer. The cap layer 107 makes it difficult for metal ions in the work function layer to diffuse into the gate dielectric layer 106. At the same time, the cap layer 107 can also make it difficult for oxygen ions in the gate dielectric layer 106 to diffuse into the work function layer, so that the gate dielectric layer 106 is not prone to the problem of increased oxygen vacancy content.

[0066] In this embodiment, the material of the capping layer 107 is TiN. In other embodiments, the material of the capping layer may also be TiSiN or TaN.

[0067] In this embodiment, the capping layer 107 is formed by an atomic layer deposition process. In other embodiments, the capping layer may also be formed by a physical vapor deposition process.

[0068] Continue to refer Fig.18 After forming the gate dielectric layer 106 , an annealed sacrificial layer 108 is formed in the gate opening 106 .

[0069] The step of forming the annealed sacrificial layer 108 includes an annealing treatment, and the annealing treatment is used to repair the gate dielectric layer 106, improve the density of the gate dielectric layer 106, and is beneficial to improving the quality and performance of the gate dielectric layer 106, and improving the electrical properties and reliability performance of the formed semiconductor structure, such as the positive bias temperature instability (PBTI) of NMOS; in addition, the cap layer 107 is closer to the fin 104 than the subsequently formed work function layer, and the annealing treatment is also used to adsorb oxygen in the cap layer 107, which is beneficial to improving the stability and reliability of the threshold voltage of the semiconductor structure.

[0070] The difficulty of etching the annealed sacrificial layer 108 is lower than that of etching the cap layer 107 , so that in the subsequent step of removing the annealed sacrificial layer 108 , the cap layer 107 can protect the gate dielectric layer 106 .

[0071] In this embodiment, the material of the annealing sacrificial layer 108 includes amorphous silicon (a-Si).

[0072] The step of forming the annealed sacrificial layer 108 covering the gate opening 106 includes: forming a sacrificial material layer (not shown) covering the gate dielectric layer 106 in the gate opening 106 ; and annealing the sacrificial material layer to form the annealed sacrificial layer 108 .

[0073] In this embodiment, the sacrificial material layer is formed by a chemical vapor deposition process.

[0074] It should be noted that, in the step of forming the annealed sacrificial layer 108, the first work function layer matching the first region I, the second work function layer matching the second region II, and the gate layer located on the first work function layer and the second work function layer have not been formed in the first region I, that is, in the step of forming the annealed sacrificial layer 108, the high temperature of the annealing treatment will not affect the first work function layer, the second work function layer and the gate layer to be formed subsequently, so that the first work function layer, the second work function layer and the gate layer to be formed subsequently are not prone to performance deviation.

[0075] refer to Fig.19 , remove the annealed sacrificial layer 108.

[0076] In the method for forming a semiconductor structure provided in an embodiment of the present invention, the pseudo gate structure 102 is removed, and after a gate opening 105 is formed in the interlayer dielectric layer 103, a gate dielectric layer 106 conformally covering the gate opening 105 is formed. After the gate dielectric layer 106 is formed, in the step of forming the annealed sacrificial layer 108, the gate dielectric layer 106 is repaired to improve the density of the gate dielectric layer 108. After removing the annealed sacrificial layer 108, a mask layer having a first groove is subsequently formed in the gate opening 105 and on the interlayer dielectric layer 103, wherein the extension direction of the first groove is the same as the extension direction of the fin 104, and the first groove exposes a portion of the gate opening 105 at the junction of the first region I and the second region II, and a first blocking layer is formed in the first groove. In the embodiment of the present invention, compared with the situation where, after forming a dummy gate structure, a blocking layer is formed that penetrates the dummy gate structure at the junction of the first region and the second region, the dummy gate structure is removed to form a gate opening, a gate dielectric layer is formed in the gate opening, after the gate dielectric layer is formed, the gate dielectric layer is conformally covered in the gate opening, after the gate dielectric layer is formed, an annealed sacrificial layer is formed in the gate opening, and then the annealed sacrificial layer is removed, in the step of removing the annealed sacrificial layer 108 in the embodiment of the present invention, no blocking layer is formed at the junction of the first region I and the second region II. Therefore, the removal process window of the annealed sacrificial layer 108 at the junction of the first region I and the second region II is large, easy to remove, and not prone to residue. Subsequently, a first gate structure is formed in the gate opening 105 of the first region I, and a second gate structure is formed in the gate opening 105 of the second region II. The first gate structure and the second gate structure will not be formed on the residual annealed sacrificial layer 108, so that the first gate structure and the second gate structure can better control the threshold voltage of the semiconductor structure, which is beneficial to improving the electrical reliability of the semiconductor structure.

[0077] The annealed sacrificial layer 108 is removed to prepare for the subsequent formation of a first gate structure in the first region I and a second gate structure in the second region II.

[0078] In this embodiment, a wet etching process is used to remove the annealed sacrificial layer 108. The wet etching process has isotropic etching characteristics, a high etching rate, simple operation, and low process cost. In other embodiments, a dry etching process can also be used to remove the annealed sacrificial layer.

[0079] In this embodiment, the material of the annealing sacrificial layer 108 includes amorphous silicon, and the material of the capping layer 107 is TiN, which is a metal material. In the step of removing the annealing sacrificial layer 108, the etching rate of the capping layer 107 is lower than the etching rate of the annealing sacrificial layer 108. In the process of removing the annealing sacrificial layer 108 by a wet etching process, the capping layer 107 is not easily damaged, so that the top of the capping layer 107 can be used as the removal stop position of the annealing sacrificial layer 108, and the gate dielectric layer 106 covered by the capping layer 107 is not easily damaged.

[0080] It should be noted that the cap layer 107 can also be used as a work function layer for adjusting the threshold voltage of NMOS and PMOS. Therefore, the cap layer 107 in the region for subsequently forming the first gate structure and the second gate structure does not need to be removed.

[0081] In this embodiment, after removing the annealed sacrificial layer 108 , the film materials in the first region I and the second region II are the same, namely, the gate dielectric layer 106 and the cap layer 107 located on the gate dielectric layer 106 , and the annealed sacrificial layer 108 is unlikely to remain.

[0082] refer to Figure 20 to Figure 23 , Fig.21 for Fig. 20 The cross-section at AA, Fig.23 for Fig. 22 In the cross-sectional view at AA, after removing the annealed sacrificial layer 108, a mask layer 110 having a first groove 109 is formed in the gate opening 105 and on the interlayer dielectric layer 103 (eg, Fig.23 As shown in FIG. 1 , the extension direction of the first groove 109 is the same as the extension direction of the fin 104 , and the first groove 109 exposes a portion of the gate opening 105 at the junction of the first region I and the second region II.

[0083] The first groove 109 exposes a portion of the gate opening 105 at the junction of the first region I and the second region II, providing a process space for subsequently forming a first blocking layer in the gate opening 105 at the junction of the first region I and the second region II.

[0084] Subsequently, a first blocking layer is formed in the first groove 109. In the extension direction perpendicular to the fin 104, the mask layer 110 of the first region I on one side of the first groove 109 is replaced with a first gate structure, and the mask layer 110 of the second region II on the other side of the first groove 109 is replaced with a second gate structure. The first blocking layer is used to block part of the first gate structure in the first region I and the second gate structure in the second region II. The purpose of the corresponding first groove 109 is the same as that of the opening formed by the existing gate cutting (P2 cut) process.

[0085] In this embodiment, the mask layer 110 is made of a material that can function as a mask and is easy to remove, so that damage to the gate opening 105 and the interlayer dielectric layer 103 can be reduced when the mask layer 110 is subsequently removed.

[0086] In this embodiment, the mask layer 110 includes a bottom anti-reflective coating (BARC). In other embodiments, the mask layer may further include a filling material layer, or include both a filling material layer and an anti-reflective coating on the filling material layer.

[0087] Specifically, the material of the bottom anti-reflective coating includes: BARC (bottom anti-reflective coating) material and DARC (dielectric anti-reflective coating) material.

[0088] The filling material layer includes: ODL (organic dielectric layer) material or SOC (spin-on-carbon) material.

[0089] The step of forming the mask layer 110 includes: forming the mask material layer 113 covering the first region I and the second region II; forming a photoresist layer 114 on the mask material layer 113; etching the mask material layer 113 using the photoresist layer 114 as a mask, and the remaining mask material layer 113 serves as the mask layer 110.

[0090] In this embodiment, the mask material layer 113 is formed by a spin coating process.

[0091] Specifically, the mask material layer 113 is etched by dry etching process with the photoresist layer 114 as a mask to form the mask layer 110. The dry etching process has anisotropic etching characteristics, has good etching profile controllability, can obtain quite accurate pattern conversion, and is conducive to making the morphology of the first groove 109 in the mask layer 110 meet the process requirements.

[0092] In the step of etching the mask material layer 113 using the photoresist layer 114 as a mask, the material of the mask material layer 113 is a bottom anti-reflective coating, which is a material layer that is easy to remove, so it is not easy for the mask material layer 113 to remain in the area where the photoresist layer 114 is exposed, so that the process controllability is strong. Correspondingly, in the subsequent process of etching the cap layer 107 and the gate dielectric layer 106 in the area where the photoresist layer 114 is exposed, it is not suitable for the cap layer 107 and the gate dielectric layer 106 to remain.

[0093] It should be noted that the first groove 109 also exposes a portion of the interlayer dielectric layer 108 between the first region I and the second region II.

[0094] It should be noted that, in the step of forming the mask layer 110, the first groove 109 also exposes the gate opening 105 outside the first region I and the second region II (i.e., the end position of the gate opening 105 along its extension direction). The gate opening 105 outside the first region I and the second region II is prepared for the subsequent formation of the first blocking layer.

[0095] It should be noted that, in the step of forming the mask layer 110 , the mask layer 110 further has a second groove 112 exposing a portion of the gate opening 105 , and an extension direction of the second groove 112 is perpendicular to an extension direction of the fin 104 .

[0096] The second groove 112 is used to prepare for subsequently removing a portion of the fin 104 in the gate opening 105 to form an opening.

[0097] It should be noted that, in this embodiment, part of the second groove 112 is connected to the first groove 109. In other embodiments, according to process requirements, the second groove may not be connected to the first groove.

[0098] The mask layer 110 formed in the embodiment of the present invention has both the first groove 109 and the second groove 112, that is, the first groove 109 and the second groove 112 are formed by an all-in-one (AIO) etching process. Compared with the case where the mask layer 110 having the first groove 109 and the mask layer 110 having the second groove 112 are formed successively, the cost of the mask is saved, which is conducive to reducing the process flow of the semiconductor formation method and increasing the yield. In addition, in the embodiment of the present invention, after the mask layer 110 is formed and before the first blocking layer is formed, the fin 104 exposed by the second groove 112 is removed to form a second opening. In the step of forming the first blocking layer in the first groove 109, the second blocking layer is also formed in the second groove 112 and the opening. That is, the first blocking layer and the second blocking layer are formed at the same time. Compared with the case where the first blocking layer and the second blocking layer are formed separately in different steps, the formation process of the first blocking layer and the second blocking layer is simplified, which is conducive to reducing the process flow of the semiconductor formation method and increasing the yield of the semiconductor structure.

[0099] It should be noted that in the subsequent steps of forming the first blocking layer and the second blocking layer, the top of the mask layer 110 is used as the removal stop position, and the position of the top of the mask layer 110 determines the position of the tops of the subsequent first blocking layer and the second blocking layer.

[0100] Specifically, the mask layer 110 covers the interlayer dielectric layer 108, that is, the height of the mask layer 110 is higher than the height of the interlayer dielectric layer 108. The height of the mask layer 110 is higher than the height of the interlayer dielectric layer 108, so that the height of the first blocking layer subsequently formed in the first groove and the height of the second blocking layer formed in the second groove are higher than the height of the interlayer dielectric layer.

[0101] The mask layer 110 is subsequently removed to form a third groove 111 surrounded by the interlayer dielectric layer 108, the first barrier layer, the second barrier layer, and the cap layer. A first initial gate structure is subsequently formed in the third groove 111 of the first region I, and a second initial gate structure is subsequently formed in the third groove 111 of the second region II. The top of the interlayer dielectric layer 108 is used as the flattening stop position, and the first initial gate structure and the second initial gate structure are flattened to form the first gate structure and the second gate structure, respectively. In other words, the height of the mask layer 110 is higher than the height of the interlayer dielectric layer 108 to prepare for the subsequent formation of the first initial gate structure and the second initial gate structure with higher heights, thereby preparing for the flattening of the first initial gate structure and the second initial gate structure to form the first gate structure and the second gate structure with higher flatness, respectively.

[0102] Continue to refer Fig. 22 and Fig.23 The method for forming the semiconductor structure further includes: after forming the mask layer 110 , removing the cap layer 107 exposed by the first groove 109 and the second groove 112 .

[0103] The cap layer 107 exposed in the first groove 109 and the second groove 112 is removed to prepare for the subsequent removal of the gate dielectric layer 106 exposed in the first groove 109 and the second groove 112 .

[0104] In this embodiment, an isotropic dry etching process is used to remove the cap layer 107 exposed by the first groove 109 and the second groove 112. The isotropic dry etching process has an isotropic etching characteristic, and can remove the cap layer 107 exposed by the mask layer 110 and located on the top and sidewall of the fin 104 and the surface of the isolation layer 101, without leaving residue.

[0105] It should be noted that, in the step of removing the cap layer 107 exposed by the first groove 109 and the second groove 110, the etching rate of the cap layer 107 is greater than the etching rate of the gate dielectric layer 106, so that the top of the gate dielectric layer 106 can be used as the removal stop position, so that the process controllability of the cap layer 107 is strong, and the gate dielectric layer 106 is not easily damaged. When the semiconductor structure is working, the gate dielectric layer 106 can better electrically isolate the fin 104 from the first gate structure and the second gate structure formed subsequently.

[0106] refer to Fig.24 and Fig.25 As shown, Fig.25 for Fig.24 The method for forming the semiconductor structure further comprises: after removing the cap layer 107 exposed by the first groove 109 and the second groove 112, before forming the first blocking layer in the first groove 109, using the mask layer 110 as a mask, removing the gate dielectric layer 106 in the gate opening 105 exposed by the first groove 109 and the second groove 112.

[0107] The gate dielectric layer 106 exposed by the second groove 112 is removed to expose the fin 104 , in preparation for subsequently removing the fin 104 exposed by the second groove 112 to form an opening.

[0108] The gate dielectric layer 106 exposed by the first groove 109 is removed. Accordingly, in this embodiment, the gate dielectric layer 106 exposed by the second groove 112 and the first groove 109 is directly removed using the mask layer 110 as a mask without forming another film layer, thereby saving a mask and reducing the process cost of removing the gate dielectric layer 106.

[0109] In this embodiment, an isotropic etching process is used to remove the gate dielectric layer 106. Specifically, the isotropic etching process includes an isotropic dry etching process or a wet etching process.

[0110] Continue to refer Fig.24 and Fig.25 As shown, the method for forming the semiconductor structure further includes: after forming the mask layer 110 and before forming the first blocking layer, using the mask layer 110 as a mask to remove the fin 104 exposed by the second groove 112 to form an opening 115 .

[0111] The opening 115 provides a process space for subsequently forming a second blocking layer.

[0112] Specifically, the opening 115 is surrounded by the isolation layer 101 , the substrate 100 and the fin 104 .

[0113] In this embodiment, the mask layer 110 is used as a mask to remove the fin 104 exposed by the second groove 112 by a dry etching process to form an opening 115. The dry etching process has anisotropic etching characteristics, has good etching profile controllability, can obtain a fairly accurate pattern conversion, is conducive to making the morphology of the opening 115 meet the process requirements, and is also conducive to improving the removal efficiency of the fin 104 exposed by the second groove 112.

[0114] In the step of removing the fin 104 exposed by the second groove 112 with the mask layer 110 as a mask to form an opening 115, the etching rate of the fin 104 is greater than the etching rate of the isolation layer 101, so that the damage to the isolation layer 101 is small, which is conducive to limiting the formation area of ​​the opening 105, so that the process controllability of the semiconductor structure is strong; in the step of forming the opening 115, the etching rate of the fin 104 is greater than the etching rate of the gate dielectric layer 106, so that the side wall of the gate dielectric layer 106 covered by the mask layer 110 is not easily damaged, and then the space at the bottom of the first groove 109 and the second groove 112 will not expand, which is conducive to controlling the subsequent formation area of ​​the first barrier layer and the second barrier layer, so that the process controllability of the semiconductor structure is strong.

[0115] In this embodiment, the material of the fin 104 includes silicon, and the material of the isolation layer 101 includes silicon oxide. Accordingly, the gas used in the dry etching process includes a fluorine-based gas, such as CF 4 , CHF 3 or C 2 F 6 wait.

[0116] It should be noted that the space formed by the opening 115 and the second groove 112 located thereon is equivalent to a single diffusion break opening formed by a single diffusion break (SDB) process.

[0117] It should be noted that, in the step of removing the fin portion 104 exposed by the second groove 112 by using the mask layer 110 as a mask, the isolation layer 101 exposed by the first groove 109 will also be damaged.

[0118] In this embodiment, after the opening 115 is formed, the photoresist layer 114 on the mask layer 110 is removed. Removing the photoresist layer 114 in time is beneficial to avoid the photoresist layer 114 from contaminating the machine.

[0119] In this embodiment, the photoresist layer 114 is removed by an ashing process or a wet stripping process.

[0120] refer to Figure 26 to Figure 28 As shown, Fig.26 Based on Fig.25 Schematic diagram of the cross section, Fig.28 for Fig. 27 In the cross-sectional view at AA, a first blocking layer 116 is formed in the first groove 109 .

[0121] In this embodiment, the first blocking layer 116 is used to define the formation position of the first gate structure formed subsequently. In other cases, the first blocking layer is used to block the first gate structure and the second gate structure formed subsequently on both sides of the first blocking layer.

[0122] In the step of forming the first blocking layer 116 in the first groove 109 , a second blocking layer 117 is also formed in the second groove 112 and the opening 115 .

[0123] The extension direction of the second blocking layer 117 is perpendicular to the fin 104 , and the second blocking layer 117 is used to electrically isolate the fins 104 located on both sides thereof.

[0124] It should be noted that in the steps of forming the first blocking layer 116 in the first groove 109 and forming the second blocking layer 117 in the second groove 112 and the opening 115 , both the first blocking layer 116 and the second blocking layer 117 penetrate the gate dielectric layer 106 .

[0125] Specifically, the steps of forming the first blocking layer 116 and the second blocking layer 117 include:

[0126] like Fig.26 As shown, the dielectric material layer 118 is formed to cover the first groove 109 , the second groove 112 and the opening 115 , and the top of the dielectric material layer 118 is higher than the top of the mask layer 110 .

[0127] Subsequently, the dielectric material layer 118 above the mask layer 110 is removed to form a first blocking layer and a second blocking layer.

[0128] In this embodiment, the dielectric material layer 118 is formed by a flowable chemical vapor deposition (FCVD) process. The flowable chemical vapor deposition process has good filling ability and is suitable for filling spaces with high aspect ratios, which is beneficial to reducing the probability of defects such as voids being formed in the dielectric material layer 118, and correspondingly is beneficial to improving the film formation quality of the first blocking layer 116 and the second blocking layer 117.

[0129] Specifically, the material of the dielectric material layer 118 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbide nitride, boron nitride, silicon boron nitride and silicon boron nitride carbon. In this embodiment, the material of the dielectric material layer 118 includes silicon oxide.

[0130] like Fig. 27 and Fig.28 , the dielectric material layer 118 above the mask layer 110 is removed, and the remaining dielectric material layer 118 located in the first groove 109 serves as the first blocking layer 116, and the remaining dielectric material layer 118 located in the second groove 112 and the opening 115 serves as the second blocking layer 117.

[0131] In this embodiment, a chemical mechanical planarization (CMP) process is used to remove the dielectric material layer 118 above the mask layer 110. Chemical mechanical polishing is a global surface planarization technology, which is conducive to making the top surface of the first blocking layer 116 and the second blocking layer 117 consistent with the top surface height of the mask layer 110.

[0132] It should be noted that, in the step of forming the first blocking layer 116 in the first groove 109 , the first blocking layer 116 is also formed in the gate opening 105 outside the first region I and the second region II.

[0133] refer to Fig.29 and Fig.30 , Fig.30 for Fig.29 In the cross-sectional view at AA, the method for forming the semiconductor structure further includes: after forming the first blocking layer 116 and the second blocking layer 117 , removing the mask layer 110 .

[0134] The mask layer 110 is removed to prepare for subsequently forming a first gate structure in the first region I and a second gate structure in the second region II.

[0135] In this embodiment, the mask layer 110 is removed to form a third groove 111 surrounded by the interlayer dielectric layer 108 , the first barrier layer 116 , the second barrier layer 117 and the cap layer 107 .

[0136] The top of the mask layer 110 is higher than the top of the interlayer dielectric layer 108 , and the corresponding third groove 111 exposes the top of the interlayer dielectric layer 108 .

[0137] Subsequently, a first initial gate structure is formed in the third groove 111 of the first region I, and a second initial gate structure is formed in the third groove 111 of the second region II. The top of the interlayer dielectric layer 108 is used as the flattening stop position, and the first initial gate structure and the second initial gate structure are flattened to form a first gate structure and a second gate structure, respectively. In other words, the height of the mask layer 110 is higher than the height of the interlayer dielectric layer 108 to prepare for the subsequent formation of the first initial gate structure and the second initial gate structure with a higher height, thereby preparing for the flattening of the first initial gate structure and the second initial gate structure to form the first gate structure and the second gate structure, respectively, which is conducive to improving the flatness of the top of the first gate structure and the second gate structure.

[0138] In this embodiment, the material of the mask layer 110 includes a BARC material, and the mask layer 110 is removed by an ashing process.

[0139] refer to Fig.31 and Fig.32 The method for forming the semiconductor structure further includes: after removing the mask layer 110, forming a first gate structure 119 in the gate opening 105 of the first region I, and forming a second gate structure 120 in the gate opening 105 of the second region II.

[0140] When the semiconductor structure is working, the first gate structure 119 is used to control the opening and closing of the channel in the first region I, and the second gate structure 120 is used to control the opening and closing of the channel in the second region II.

[0141] The steps of forming a first gate structure in the first region I and forming a second gate structure in the second region II include: forming a first work function material layer in the gate opening 105 of the first region I and the second region II; forming a first shielding layer covering the first region I and exposing the second region II; removing the first work function material layer in the second region II exposed by the first shielding layer, and the remaining first work function material layer serves as the first work function layer; after forming the first work function layer, removing the first shielding layer; forming a second work function layer covering the first region I and the second region II; after forming the second work function layer, forming a gate layer on the second work function layer, the first work function layer, the second work function layer and the gate layer located in the first region I serve as the first initial gate structure, and the second work function layer and the gate layer located in the second region II serve as the second initial gate structure; taking the top of the interlayer dielectric layer 108 as the flattening stop position, flattening the first initial gate structure and the second initial gate structure, respectively forming the first gate structure 119 and the second gate structure 120.

[0142] In this embodiment, the first region I is used to form an NMOS, and accordingly, the material of the first work function layer includes: one or more of titanium aluminide, tantalum carbide, aluminum and titanium carbide.

[0143] In this embodiment, the first work function layer is formed by an atomic layer deposition process.

[0144] In this embodiment, the second region II is used to form a PMOS, and accordingly, the material of the second work function layer includes: one or more of titanium nitride, tantalum nitride, titanium carbide, tantalum silicon nitride, titanium silicon nitride and tantalum carbide.

[0145] In this embodiment, the second work function layer is formed by an atomic layer deposition process.

[0146] In this embodiment, the material of the gate layer includes: one or more of magnesium-tungsten alloy, tungsten, copper, nickel and titanium.

[0147] Taking the top of the interlayer dielectric layer as the flattening stop position, the first initial gate structure and the second initial gate structure are flattened, which is beneficial to improving the flatness of the top of the first gate structure 119 and the second gate structure 120, controlling the height of the first gate structure 119 and the second gate structure 120, and improving the process controllability of the semiconductor structure.

[0148] In this embodiment, chemical mechanical planarization (CMP) is used to perform the planarization process.

[0149] It should also be noted that after the first barrier layer 116 and the second barrier layer 117 are formed, the first initial gate structure is formed in the third groove 111 of the first region I, and the second initial gate structure is formed in the third groove 111 of the second region II, the first initial gate structure and the second initial gate structure above the interlayer dielectric layer 108 are removed, and the remaining first initial gate structure is used as the first gate structure 119, and the remaining second initial gate structure is used as the second gate structure 120. Compared with the case where the first blocking layer is first formed, then the first gate structure and the second gate structure are formed, the first gate structure and the second gate structure and the fin are etched to form a single diffusion interruption opening for forming the second blocking layer, and the second blocking layer is formed in the single diffusion interruption opening, the present embodiment avoids etching the gate layer, the first work function layer and the second work function layer, and there is no residual gate layer, the first work function layer and the second work function layer at the bottom of the second blocking layer. The controllability of the formation process of the first gate structure 119 and the second gate structure 120 is strong, so that the first gate structure 119 and the second gate structure 120 can better control the threshold voltage of the semiconductor structure, which is conducive to improving the electrical reliability of the semiconductor structure.

[0150] Although the embodiments of the present invention are disclosed above, the embodiments of the present invention are not limited thereto. Any person skilled in the art may make various changes and modifications without departing from the spirit and scope of the embodiments of the present invention. Therefore, the protection scope of the embodiments of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, It is characterized in that include: Providing a substrate, the substrate comprising a first region and a second region adjacent to each other, the substrate comprising a substrate, a fin separated from the substrate, an isolation layer located on the fin and exposed on the substrate, a dummy gate structure located on the isolation layer and spanning the fin, and an interlayer dielectric layer covering the sidewalls of the dummy gate structure and exposing the top of the dummy gate structure; removing the dummy gate structure and forming a gate opening in the interlayer dielectric layer; forming a gate dielectric layer conformally covering the gate opening; forming an annealed sacrificial layer covering the gate dielectric layer in the gate opening; removing the annealed sacrificial layer; After removing the annealed sacrificial layer, forming a mask layer having a first groove in the gate opening and on the interlayer dielectric layer, wherein the extension direction of the first groove is the same as the extension direction of the fin, and the first groove exposes a portion of the gate opening at the junction of the first region and the second region; A first blocking layer is formed in the first groove.

2. The method for forming a semiconductor structure according to claim 1, It is characterized in that In the step of forming the mask layer, the mask layer further has a second groove exposing a portion of the gate opening, and an extension direction of the second groove is perpendicular to an extension direction of the fin; The method for forming a semiconductor structure further comprises: after forming the mask layer and before forming the first blocking layer, using the mask layer as a mask to remove the fin exposed by the second groove to form an opening; In the step of forming the first blocking layer in the first groove, a second blocking layer is also formed in the second groove and the opening.

3. The method for forming a semiconductor structure according to claim 2, It is characterized in that The method for forming a semiconductor structure further comprises: after forming the mask layer and before forming the opening, using the mask layer as a mask, removing the gate dielectric layer in the gate opening exposed by the first groove and the second groove; In the step of forming a first blocking layer in the first groove and forming a second blocking layer in the second groove and the opening, both the first blocking layer and the second blocking layer penetrate the gate dielectric layer.

4. The method for forming a semiconductor structure according to claim 3, It is characterized in that The method for forming a semiconductor structure further comprises: after forming a gate dielectric layer conformally covering the gate opening, and before forming the annealed sacrificial layer, forming a cap layer conformally covering the gate opening; In the step of removing the annealed sacrificial layer, the etching rate of the cap layer is lower than the etching rate of the annealed sacrificial layer; The method for forming a semiconductor structure further comprises: after forming the mask layer, before removing the gate dielectric layer in the gate opening exposed by the first groove and the second groove, removing the cap layer exposed by the first groove and the second groove.

5. The method for forming a semiconductor structure according to claim 4, It is characterized in that In the step of removing the capping layer exposed by the first groove and the second groove, the etching rate of the capping layer is greater than the etching rate of the gate dielectric layer.

6. The method for forming a semiconductor structure according to claim 4, It is characterized in that An isotropic dry etching process is used to remove the capping layer exposed by the first groove and the second groove.

7. The method for forming a semiconductor structure according to claim 2, It is characterized in that The mask layer is used as a mask to remove the fin exposed by the second groove by a dry etching process to form the opening.

8. The method for forming a semiconductor structure according to claim 2, It is characterized in that The steps of forming the first blocking layer and the second blocking layer include: forming a dielectric material layer covering the first groove, the second groove and the opening, wherein a top of the dielectric material layer is higher than a top of the mask layer; The dielectric material layer above the mask layer is removed, and the remaining dielectric material layer in the first groove serves as a first blocking layer, and the remaining dielectric material layer in the second groove and the opening serves as a second blocking layer.

9. The method for forming a semiconductor structure according to claim 8, It is characterized in that The dielectric material layer is formed by a flow chemical vapor deposition process.

10. The method for forming a semiconductor structure according to claim 8, It is characterized in that The material of the dielectric material layer includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbide nitride, boron nitride, silicon boron nitride and silicon boron nitride carbon.

11. The method for forming a semiconductor structure according to claim 8, It is characterized in that The dielectric material layer above the mask layer is removed by a chemical mechanical planarization process.

12. The method for forming a semiconductor structure according to claim 1, It is characterized in that The method for forming the semiconductor structure further comprises: After forming the first blocking layer and the second blocking layer, the mask layer is removed.

13. The method for forming a semiconductor structure according to claim 12, It is characterized in that The mask layer is removed by an ashing process.

14. The method for forming a semiconductor structure according to claim 12, It is characterized in that The method for forming the semiconductor structure further includes: after removing the mask layer, forming a first gate structure in the gate opening of the first region, and forming a second gate structure in the gate opening of the second region.

15. The method for forming a semiconductor structure according to claim 14, It is characterized in that The steps of forming a first gate structure in the gate opening of the first region and forming a second gate structure in the gate opening of the second region include: forming a first work function material layer in the gate openings of the first and second regions; forming a first shielding layer covering the first area and exposing the second area; removing the first work function material layer in the second region exposed by the first shielding layer, and using the remaining first work function material layer in the first region as a first work function layer; After forming the first work function layer, removing the first shielding layer; After removing the first shielding layer, a second work function layer covering the first region and the second region is formed; After forming the second work function layer, forming a gate layer on the second work function layer, the first work function layer, the second work function layer and the gate layer located in the first region serve as a first initial gate structure, and the second work function layer and the gate layer located in the second region serve as a second initial gate structure; The first initial gate structure and the second initial gate structure are planarized with the top of the interlayer dielectric layer being the planarization stop position to form the first gate structure and the second gate structure respectively.

16. The method for forming a semiconductor structure according to claim 1, It is characterized in that The step of forming the mask layer comprises: forming a mask material layer covering the first region and the second region; forming a photoresist layer on the mask material layer; The mask material layer is etched using the photoresist layer as a mask, and the remaining mask material layer serves as the mask layer.

17. The method for forming a semiconductor structure according to claim 1, It is characterized in that The material of the mask layer includes one or more of an ODL material, a SOC material, a BARC material and a DARC material.

18. The method for forming a semiconductor structure according to claim 1, It is characterized in that In the step of providing a substrate, the dummy gate structure is formed by a self-aligned double patterning process or a self-aligned quadruple patterning process.

19. The method for forming a semiconductor structure according to claim 1, It is characterized in that The step of forming an annealed sacrificial layer in the gate opening comprises: forming a sacrificial material layer covering the gate dielectric layer in the gate opening; The sacrificial material layer is annealed to form the annealed sacrificial layer.

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