Semiconductor element structure with manganese-containing interconnect structure and method of making the same

Abstract

The present disclosure provides a semiconductor element structure with a manganese-containing interconnect structure and a method of fabricating the semiconductor element structure. The semiconductor element structure has a first interconnect structure disposed in a semiconductor substrate, a dielectric layer disposed on the semiconductor structure, and a second interconnect structure disposed in the dielectric layer and electrically connected to the first interconnect structure. The first interconnect structure has a first conductive line and a first manganese-containing layer disposed on the first conductive line. The second interconnect structure has a second conductive line and a second manganese-containing layer disposed between the second conductive line and the dielectric layer.

Description

Technical Field

[0001] This application claims priority and benefits to U.S. Official Application No. 17 / 148,041, filed January 13, 2021, the contents of which are incorporated herein by reference in their entirety.

[0002] This disclosure relates to a semiconductor device structure and a method for fabricating the same. In particular, it relates to a semiconductor device structure having a manganese-containing interconnect structure and a method for fabricating the same. Background Technology

[0003] Semiconductor components are indispensable for many modern applications. With advancements in electronic technology, semiconductor components have become increasingly smaller, while simultaneously offering superior functionality and incorporating a greater number of integrated circuits. Due to the miniaturization of semiconductor components, different forms and sizes of semiconductor components realizing different functions are integrated and packaged into a single module. Furthermore, numerous manufacturing steps are performed on the integration of various types of semiconductor devices.

[0004] However, the fabrication and integration of semiconductor devices involve many complex steps and operations. Integration within these devices becomes increasingly complex. This increased complexity in the fabrication and integration of semiconductor devices can lead to several defects, such as voids formed in conductive lines, which are difficult to fill due to high aspect ratio openings. Therefore, there is a need for continuous improvement of the semiconductor device manufacturing process to address these defects and enhance its performance.

[0005] The above description of "prior art" provides background information only and does not acknowledge that the above description of "prior art" discloses the subject matter of this disclosure. It does not constitute prior art of this disclosure, and no description of the above "prior art" should be considered part of this case. Summary of the Invention

[0006] One embodiment of this disclosure provides a semiconductor device structure. The semiconductor device structure includes a first interconnect structure disposed in a semiconductor substrate; a dielectric layer disposed on the semiconductor substrate; and a second interconnect structure disposed in the dielectric layer and electrically connected to the first interconnect structure. The first interconnect structure includes a first conductive line and a first manganese-containing layer disposed on the first conductive line. The second interconnect structure includes a second conductive line and a second manganese-containing layer disposed between the second conductive line and the dielectric layer.

[0007] In one embodiment, the first manganese-containing layer and the second manganese-containing layer comprise manganese, wherein the first conductive line and the second conductive line comprise copper. In one embodiment, an upper surface of the first manganese-containing layer is substantially flush with an upper surface of the semiconductor substrate. In one embodiment, the first interconnect structure further includes a first barrier layer surrounding the first conductive line and the first manganese-containing layer, wherein the first conductive line is disposed on the first barrier layer. In one embodiment, the second interconnect structure further includes a second barrier layer disposed between the second manganese-containing layer and the dielectric layer, wherein the second barrier layer directly contacts the first manganese-containing layer of the first interconnect structure.

[0008] In one embodiment, the semiconductor device structure further includes a third interconnect structure disposed in the semiconductor substrate. The third interconnect structure includes a third conductive line and a third manganese-containing layer disposed on the third conductive line. The third manganese-containing layer of the third interconnect structure contains the same material as the first manganese-containing layer of the first interconnect structure. In one embodiment, the first interconnect structure and the second interconnect structure are disposed in a sparse pattern region, wherein the third interconnect structure is disposed in a dense pattern region. In one embodiment, the third interconnect structure is completely covered by the dielectric layer.

[0009] Another embodiment of this disclosure provides a semiconductor device structure. The semiconductor device structure includes a first interconnect structure disposed in a semiconductor substrate; and a second interconnect structure disposed on the semiconductor substrate and electrically connected to the first interconnect structure. The first interconnect structure includes a first barrier layer; a first conductive line disposed on the first barrier layer; and a first manganese-containing layer disposed on the first conductive line. The first manganese-containing layer and the first conductive line are separated from the semiconductor substrate by the first barrier layer. The second interconnect structure includes a second barrier layer disposed on and in direct contact with the first manganese-containing layer; a second manganese-containing layer disposed on the second barrier layer; and a second conductive line disposed on the second manganese-containing layer.

[0010] In one embodiment, the second conductive line is surrounded by the second manganese-containing layer, and the second manganese-containing layer is surrounded by the second barrier layer. In one embodiment, the width of an upper portion of the second conductive line is greater than the width of a lower portion of the second conductive line. In one embodiment, the semiconductor device structure further includes a dielectric layer disposed on the semiconductor substrate and covering a portion of the first barrier layer and a portion of the first manganese-containing layer, wherein the second interconnect structure passes through the dielectric layer.

[0011] In one embodiment, the first conductive line and the second conductive line comprise copper. In one embodiment, the first interconnect structure has a first manganese atomic percentage, the second interconnect structure has a second manganese atomic percentage, and the first manganese atomic percentage is different from the second manganese atomic percentage. In one embodiment, the first manganese atomic percentage is greater than the second manganese atomic percentage.

[0012] Another embodiment of this disclosure provides a semiconductor device structure. The semiconductor device structure includes a first interconnect structure disposed in a semiconductor substrate; and a second interconnect structure disposed on and electrically connected to the first interconnect structure. The first interconnect structure includes a first conductive line; and a first manganese-containing layer disposed on the first conductive line. An upper surface of the first manganese-containing layer is substantially flush with an upper surface of the semiconductor substrate. The second interconnect structure includes a second manganese-containing layer; and a second conductive line disposed on the second manganese-containing layer. The second manganese-containing layer covers each sidewall of the second conductive line. The first interconnect structure has a first manganese atomic percentage, the second interconnect structure has a second manganese atomic percentage, and the first manganese atomic percentage is different from the second manganese atomic percentage.

[0013] In one embodiment, the first manganese atomic percentage is greater than the second manganese atomic percentage. In one embodiment, the semiconductor device structure further includes a third interconnect structure disposed in the semiconductor substrate. The third interconnect structure includes a third conductive line and a third manganese-containing layer disposed on the third conductive line. The third interconnect structure is disposed in a densely patterned region, and the first interconnect structure and the second interconnect structure are disposed in a sparsely patterned region.

[0014] In one embodiment, the third interconnect structure has a third manganese atomic percentage, which is greater than the second manganese atomic percentage. In another embodiment, the first interconnect structure further includes a first barrier layer that separates the first conductive line and the first manganese-containing layer from the semiconductor substrate, and the second interconnect structure further includes a second barrier layer sandwiched between the second manganese-containing layer and the first manganese-containing layer.

[0015] This disclosure provides some embodiments of a semiconductor device structure and its fabrication method. In some embodiments, the semiconductor device structure has a first interconnect structure disposed in a semiconductor substrate; and a second interconnect structure disposed in a dielectric layer on the semiconductor substrate. The first interconnect structure is electrically connected to the second interconnect structure. The first interconnect structure includes a first manganese-containing layer disposed on a first conductive line, and the second interconnect structure includes a second manganese-containing layer disposed between a second conductive line and the dielectric layer. The first and second manganese-containing layers are configured to reduce or avoid the formation of multiple voids in the first and second conductive lines, thereby reducing contact resistance.

[0016] The technical features and advantages of this disclosure have been broadly summarized above, thus enabling a better understanding of the detailed description of this disclosure that follows. Other technical features and advantages constituting the subject matter of the claims will be described below. Those skilled in the art to which this disclosure pertains will understand that the concepts and specific embodiments disclosed below can be readily utilized to achieve the same purpose as this disclosure through modifications or design of other structures or processes. Those skilled in the art will also understand that such equivalent constructions cannot depart from the concept and scope of this disclosure as defined by the claims. Attached Figure Description

[0017] A more comprehensive understanding of the disclosure of this application can be obtained by referring to the accompanying drawings in conjunction with the embodiments and claims. The same element symbols in the drawings refer to the same elements.

[0018] Figure 1 This is a cross-sectional schematic diagram illustrating the semiconductor device structure of some embodiments of the present disclosure.

[0019] Figure 2 This is a flowchart illustrating a method for fabricating a semiconductor device structure according to some embodiments of this disclosure.

[0020] Figure 3 This is a cross-sectional schematic diagram illustrating an intermediate stage in the formation of a patterned mask on a semiconductor substrate during the formation of a semiconductor device structure, according to some embodiments of the present disclosure.

[0021] Figure 4 This is a cross-sectional schematic diagram illustrating an intermediate stage in some embodiments of the present disclosure where a patterned mask is used as a mask to etch a semiconductor substrate to form multiple openings during the formation of a semiconductor device structure.

[0022] Figure 5 This is a cross-sectional schematic diagram illustrating some embodiments of the present disclosure during the intermediate stage of forming a barrier material in the plurality of openings and on the semiconductor substrate during the formation of a semiconductor element structure.

[0023] Figure 6 This is a cross-sectional schematic diagram illustrating some embodiments of the present disclosure during the intermediate stages of forming a conductive material in the plurality of openings and on the barrier layer during the formation of a semiconductor device structure.

[0024] Figure 7 This is a cross-sectional schematic diagram illustrating an intermediate stage in some embodiments of the present disclosure during the formation of a semiconductor device structure, in which barrier materials and conductive materials are planarized to form multiple barrier layers and multiple conductive lines.

[0025] Figure 8This is a cross-sectional schematic diagram illustrating an intermediate stage in some embodiments of the present disclosure where the plurality of conductive lines are etched back during the formation of a semiconductor device structure to form a plurality of recesses.

[0026] Figure 9 This is a cross-sectional schematic diagram illustrating some embodiments of the present disclosure of the intermediate stage during the formation of a manganese-containing material in the plurality of recesses and on the semiconductor substrate.

[0027] Figure 10 This is a cross-sectional schematic diagram illustrating an intermediate stage of planarizing manganese-containing material during the formation of a semiconductor device structure, according to some embodiments of the present disclosure.

[0028] Figure 11 This is a cross-sectional schematic diagram illustrating an intermediate stage in the formation of a dielectric layer on a semiconductor substrate during the formation of a semiconductor device structure, according to some embodiments of the present disclosure.

[0029] Figure 12 This is a cross-sectional schematic diagram illustrating an intermediate stage in the formation of a patterned mask on a dielectric layer during the formation of a semiconductor device structure, according to some embodiments of the present disclosure.

[0030] Figure 13 This is a cross-sectional schematic diagram illustrating an intermediate stage in the etching of dielectric layers using a patterned mask as a mask during the formation of a semiconductor device structure, according to some embodiments of the present disclosure.

[0031] Figure 14 This is a cross-sectional schematic diagram illustrating an intermediate stage in the formation of a patterned mask on a dielectric layer during the formation of a semiconductor device structure, according to some embodiments of the present disclosure.

[0032] Figure 15 This is a cross-sectional schematic diagram illustrating an intermediate stage in some embodiments of the present disclosure where a patterned mask is used as a mask to etch a dielectric layer to form an opening structure during the formation of a semiconductor device structure.

[0033] Figure 16 This is a cross-sectional schematic diagram illustrating some embodiments of the present disclosure of the intermediate stages of forming a barrier material during the formation of a semiconductor device structure, both in the open-hole structure and on the dielectric layer.

[0034] Figure 17 This is a cross-sectional schematic diagram illustrating some embodiments of the present disclosure of an intermediate stage during the formation of a manganese-containing material in an open-hole structure and on a barrier material.

[0035] Figure 18 This is a cross-sectional schematic diagram illustrating some embodiments of the present disclosure of the intermediate stages during the formation of a conductive material in an open-hole structure and on a manganese-containing material.

[0036] Figure 19 This is a partial structural schematic diagram illustrating an exemplary integrated circuit having an array of multiple memory cells in some embodiments of this disclosure.

[0037] Explanation of reference numerals in the attached figures:

[0038] 10: Preparation method

[0039] 50: Memory cell

[0040] 51: Field-Effect Transistor

[0041] 53: Capacitor

[0042] 55: Drain

[0043] 57: Source Extreme

[0044] 59: Gate

[0045] 100: Semiconductor Component Structure

[0046] 101: Semiconductor substrate

[0047] 101T: Upper surface

[0048] 103: Patterned Masking

[0049] 106a: Opening

[0050] 106b: Opening

[0051] 111: Barrier Materials

[0052] 111a: Barrier layer

[0053] 111b: Barrier Layer

[0054] 113: Conductive materials

[0055] 113a: Conductive wire

[0056] 113b: Conductive wire

[0057] 116a: Depression

[0058] 116b: Depression

[0059] 119: Manganese-containing materials

[0060] 119a: Manganese-containing layer

[0061] 119aT: Upper surface

[0062] 119b: Manganese-containing layer

[0063] 119bT: Upper surface

[0064] 121a: Interconnection structure

[0065] 121b: Interconnection structure

[0066] 123: Dielectric layer

[0067] 123T: Upper surface

[0068] 125: Patterned Masking

[0069] 128: Opening

[0070] 130: Opening

[0071] 133: Patterned Masking

[0072] 136: Opening

[0073] 138: Opening

[0074] 140: Opening structure

[0075] 143: Barrier Materials

[0076] 143': Barrier Layer

[0077] 145: Manganese-containing materials

[0078] 145': Manganese-containing layer

[0079] 145'S: Sidewall

[0080] 147: Conductive materials

[0081] 147': Conductive wire

[0082] 147'S: Sidewall

[0083] 149: Interconnection Structure

[0084] 1000: Memory element

[0085] A: Area with dense patterns

[0086] B: Area with sparse pattern

[0087] BL: Bitline

[0088] S11: Steps

[0089] S13: Steps

[0090] S15: Steps

[0091] S17: Steps

[0092] S19: Steps

[0093] W1: Width

[0094] W2: Width

[0095] WL: Character Line Detailed Implementation

[0096] The following describes specific examples of components and configurations to simplify embodiments of this disclosure. Of course, these embodiments are merely illustrative and are not intended to limit the scope of this disclosure. For example, in the description, a first component is formed on top of a second component, which may include embodiments where the first and second components are in direct contact, or embodiments where an additional component is formed between the first and second components such that the first and second components do not directly contact each other. Furthermore, reference numerals and / or letters may be repeated in many examples of embodiments of this disclosure. These repetitions are for simplicity and clarity and, unless specifically stated herein, do not in themselves represent a specific relationship between the various embodiments and / or the configurations discussed.

[0097] Furthermore, for ease of explanation, spatial relative terms such as "beneath," "below," "lower," "above," and "upper" may be used herein to describe the relationship between one element or feature shown in the figures and another element or feature. These spatial relative terms are intended to encompass different orientations of the elements in use or operation, in addition to those shown in the figures. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatial relative descriptions used herein can be interpreted accordingly.

[0098] Figure 1 This is a cross-sectional schematic diagram illustrating the semiconductor device structure of some embodiments of this disclosure. For example... Figure 1 As shown, the semiconductor device structure 100 has a pattern-dense region A and a pattern-loose region B. In some embodiments, for clarity of this disclosure, in Figure 1 The dashed line in the middle represents the boundary between the dense pattern region A and the sparse pattern region B. There is no clear interface between the dense pattern region A and the sparse pattern region B.

[0099] In some embodiments, the semiconductor device structure 100 includes a semiconductor substrate 101 and interconnect structures 121a and 121b (also referred to as lower interconnect structures) disposed in the semiconductor substrate 101. In some embodiments, interconnect structure 121a is disposed in a pattern-dense region A, and interconnect structure 121b is disposed in a pattern-sparse region B. In some embodiments, the details of interconnect structure 121a are similar to or the same as the details of interconnect structure 121b, except that they are disposed in different regions.

[0100] In some embodiments, the interconnect structure 121a includes a barrier layer 111a; a conductive line 113a disposed on the barrier layer 111a; and a manganese-containing layer 119a disposed on the conductive line 113a. In some embodiments, the barrier layer 111a covers each sidewall of the conductive line 113a and each sidewall of the manganese-containing layer 119a. In some embodiments, the conductive line 113a and the manganese-containing layer 119a are separated from the semiconductor substrate 101 by the barrier layer 1110a.

[0101] Similar to the interconnect structure 121a of the densely patterned region A, the interconnect structure 121b of the sparsely patterned region B includes a barrier layer 111b; a conductive line 113b disposed on the barrier layer 111b; and a manganese-containing layer 119b disposed on the conductive line 113b. In some embodiments, the conductive line 111b in the sparsely patterned region B is parallel to the conductive line 111a in the densely patterned region A. Furthermore, in some embodiments, the barrier layer 111b covers each sidewall of the conductive line 113b and each sidewall of the manganese-containing layer 119b.

[0102] In some embodiments, the conductive line 113b and the manganese-containing layer 119b are separated from the semiconductor substrate 101 by a barrier layer 111b. Furthermore, according to some embodiments, an upper surface 119aT of the manganese-containing layer 119a and an upper surface 119bT of the manganese-containing layer 119b are flush with the upper surface 101T of the semiconductor substrate 101. In this disclosure, the term "substantially" means preferably 90%, more preferably 95%, even more preferably 98%, and most preferably 99%.

[0103] Please refer to the following: Figure 1 The semiconductor device structure 100 also includes a dielectric layer 123 disposed on the semiconductor substrate 101; and an interconnect structure 149 (also referred to as an upper interconnect structure) disposed in the dielectric layer 123. It should be understood that the interconnect structure 149 is disposed in the pattern sparse region B and electrically connected to the interconnect structure 121b. In some embodiments, the interconnect structure 149 directly contacts the interconnect structure 121b.

[0104] In some embodiments, the interconnect structure 149 has a barrier layer 143'; a manganese-containing layer 145' disposed on the barrier layer 143'; and a conductive line 147' disposed on the manganese-containing layer 145'. In some embodiments, the conductive line 147' is surrounded by the manganese-containing layer 145', and the manganese-containing layer 145' is surrounded by the barrier layer 143'. In some embodiments, each sidewall 147'S of the conductive line 147' is covered by the manganese-containing layer 145', and each sidewall 145'S of the manganese-containing layer 145' is covered by the barrier layer 143'.

[0105] In some embodiments, a manganese-containing layer 145' is sandwiched between a barrier layer 143' and a conductive line 147', and the conductive line 147' is separated from the barrier layer 143' by the manganese-containing layer 145'. In some embodiments, a portion of the barrier layer 143' is sandwiched between the manganese-containing layer 145' of the interconnect structure 149 and the manganese-containing layer 119b of the interconnect structure 121b. In some embodiments, the manganese-containing layer 145' is separated from the dielectric layer 123 by the barrier layer 143'.

[0106] Furthermore, in some embodiments, an upper surface of the conductive line 147' is substantially flush with an upper surface of the manganese-containing layer 145' and an upper surface of the barrier layer 143. In some embodiments, a portion of the manganese-containing layer 119b and a portion of the barrier layer 111b of the interconnect structure 121b are covered by the dielectric layer 123. It should be understood that, in some embodiments, the interconnect structure of the patterned dense region A is completely covered by the dielectric layer 123.

[0107] In some embodiments, manganese-containing layers 119a, 119b, and 145' comprise manganese (Mn), and conductive lines 113a, 113b, and 147' comprise copper (Cu). In some embodiments, barrier layers 111a, 111b, and 143' comprise tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), combinations thereof, or other applicable materials. In some embodiments, the percentage of manganese atoms in interconnect structure 121b is substantially the same as the percentage of manganese atoms in interconnect structure 121a, and the percentage of manganese atoms in interconnect structure 121b differs from the percentage of manganese atoms in interconnect structure 149. In some embodiments, the percentage of manganese atoms in interconnect structure 121b is greater than the percentage of manganese atoms in interconnect structure 149.

[0108] Figure 2 This is a flowchart illustrating a method 10 for fabricating a semiconductor device structure (e.g., semiconductor device structure 10) according to some embodiments of the present disclosure. The fabrication method 10 includes steps S11, S13, S15, S17, and S19. Figure 2 Steps S11 to S19 are described in detail with reference to the following figures.

[0109] Figures 3 to 19 This is a cross-sectional schematic diagram illustrating various intermediate stages of the semiconductor device structure 100 according to some embodiments of the present disclosure. For example... Figure 3 As shown, a semiconductor substrate 101 is provided. The semiconductor substrate 101 may be a semiconductor wafer, such as a silicon wafer.

[0110] Additionally, the semiconductor substrate 101 may comprise elemental semiconductor materials, compound semiconductor materials, and / or alloy semiconductor materials. Examples of elemental semiconductor materials may include, but are not limited to, crystalline silicon, polycrystalline silicon, amorphous silicon, germanium, and / or diamond. Examples of compound semiconductor materials may include, but are not limited to, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide. Examples of alloy semiconductor materials may include, but are not limited to, germanium silicon (SiGe), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), and / or gallium arsenide phosphide (GaInAsP).

[0111] In some embodiments, the semiconductor substrate 101 includes an epitaxial layer. For example, the semiconductor substrate 101 has an epitaxial layer covering a bulk semiconductor. In some embodiments, the semiconductor substrate 101 is a semiconductor-on-insulator (SOI) substrate, which may include a substrate, a buried oxide layer, and a semiconductor layer, wherein the buried oxide layer is located on the substrate, the semiconductor layer is located on the buried oxide layer, and the SOI substrate is, for example, a silicon-on-insulator (SOI) substrate, a silicon-germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate. The SOI substrate can be fabricated using separation by implanted oxygen (SIMOX), wafer bonding, and / or other applicable methods.

[0112] Please refer to the following: Figure 3According to some embodiments, a patterned mask 103 is formed on a semiconductor substrate 101. In some embodiments, the upper surface 101T of the semiconductor substrate 101 is partially exposed through openings 106a and 106b in the patterned mask 103, and the openings 106a and 106b are respectively disposed in the patterned dense region A and the patterned sparse region B.

[0113] Next, as Figure 4 As shown, according to some embodiments, a patterned mask 103 is used as a mask to etch the semiconductor substrate 101 to form openings 108a and 108b. The corresponding steps are shown in... Figure 2 Step S11 in method 10 is shown. In some embodiments, the semiconductor substrate 101 is not etched through, and the openings 108a and 108b are respectively disposed in the patterned dense region A and the patterned sparse region B. The semiconductor substrate 101 can be etched by a wet etching process, a dry etching process, or a combination thereof. After the openings 108a and 108b are formed, the patterned mask 103 can be removed.

[0114] Next, as Figure 5 As shown, according to some embodiments, a barrier material 111 is conformally deposited in the openings 108a and 108b and on the upper surface 101T of the semiconductor substrate 101. In some embodiments, the sidewalls and lower surfaces of the openings 108a and 108b are covered by the barrier material 111. In some embodiments, the barrier material 111 comprises tantalum, tantalum nitride, titanium, titanium nitride, combinations thereof, or other applicable materials. The fabrication technique of the barrier material 111 may include using a conformal deposition method, such as a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, or an atomic layer deposition (ALD) process.

[0115] like Figure 6 As shown, according to some embodiments, after the barrier material 111 is formed, a conductive material 113 is formed on the remaining portions of the openings 108a and 108b and on the upper surface 101T of the semiconductor substrate 101. In some embodiments, the plurality of remaining portions of the openings 108a and 108b are completely filled with the conductive material 113.

[0116] In some embodiments, the conductive material 113 comprises a low-resistivity conductive material, such as copper (Cu). In other embodiments, the conductive material 113 comprises tungsten, aluminum, titanium, tantalum, gold, silver, combinations thereof, or other applicable conductive materials. The fabrication technology of the conductive material 113 may include a CVD process, a PVD process, a sputtering process, a plating process, or other applicable processes.

[0117] Then, as Figure 7As shown, according to some embodiments, a planarization process is performed to remove excess portions of the barrier material 111 and conductive material 113 on the upper surface 101T of the semiconductor substrate 101. The planarization process may include a chemical mechanical polishing (CMP) process. According to some embodiments, after the planarization process, the upper surface 101T of the semiconductor substrate 101 is exposed, with the barrier layer 111a and conductive line 113a formed in a patterned dense region A, and the barrier layer 111b and conductive line 113b formed in a patterned sparse region B.

[0118] Next, as Figure 8 As shown, according to some embodiments, etch-back of conductive lines 113a and 113b results in the formation of multiple recesses 116a and 116b in the patterned dense region A and the patterned sparse region B, respectively. In some embodiments, according to some embodiments, recess 116a is formed on the remaining portion of conductive line 113a, and recess 116b is formed on the remaining portion of conductive line 113b. In other words, the lower surfaces of recesses 116a and 116b are lower than the upper surface 101T of the semiconductor substrate 101. In some embodiments, recess 116a is surrounded by a barrier layer 111a, and recess 116b is surrounded by a barrier layer 111b.

[0119] Next, as Figure 9 As shown, according to some embodiments, a manganese-containing material 119 is formed in the recesses 116a and 116b and on the upper surface 101T of the semiconductor substrate 101. In some embodiments, the barrier layers 111a and 111b and the conductive lines 113a and 113b are covered by the manganese-containing material 119, and the recesses 116a and 116b are completely filled with the manganese-containing material 119.

[0120] In some embodiments, the manganese-containing material 119 comprises manganese (Mn). In other embodiments, the manganese-containing material 119 comprises a manganese-rich material, such as manganese-rich copper manganese (CuMn) or manganese-rich silicon manganese (MnSi). Furthermore, the fabrication technique of the manganese-containing material 119 may include using a conformal deposition method, such as CVD, PVD, ALD, metal-organic chemical vapor deposition (MOCVD), sputtering, or plating.

[0121] Next, as Figure 10 As shown, according to some embodiments, a planarization process is performed to remove excess portions of the manganese-containing material 119 on the upper surface 101T of the semiconductor substrate 101. The planarization process may include a CMP process. After the planarization process, manganese-containing layers 119a and 119b are formed in a patterned dense region A and a patterned sparse region B, respectively, resulting in an interconnect structure 121a in the patterned dense region A and an interconnect structure 121b in the patterned sparse region B. The corresponding steps are shown in... Figure 2Step S13 in method 10 shown. In some embodiments, the upper surface 119aT of the manganese-containing layer 119a and the upper surface 119bT of the manganese-containing layer 119b are substantially flush with the upper surface 101T of the semiconductor substrate 101.

[0122] like Figure 11 As shown, according to some embodiments, after the interconnect structures 121a and 121b are formed, a dielectric layer 123 is formed on the semiconductor substrate 101. The corresponding steps are shown in... Figure 2 Step S15 in method 10 is shown. For example, dielectric layer 123 may comprise or include silicon oxide, silicon nitride, or silicon oxynitride. Furthermore, the fabrication technique of dielectric layer 123 may include a deposition process, such as a CVD process, a flowable chemical vapor deposition (FCVD) process, a PVD process, a spin coating process, or other applicable processes.

[0123] Next, as Figure 12 As shown, according to some embodiments, a patterned mask 125 is formed on a dielectric layer 123. In some embodiments, the patterned mask 125 has an opening 128 in a pattern sparse region B, and the dielectric layer 123 is partially exposed through the opening 128.

[0124] Then, as Figure 13 As shown, according to some embodiments, a patterned mask 125 is used as a mask to etch the dielectric layer 123 to form an opening 130. In some embodiments, the opening 130 passes through the dielectric layer 123, and the upper surface 119bT of the manganese-containing layer 119b is partially exposed through the opening 130. The dielectric layer 123 can be etched by a wet etching process, a dry etching process, or a combination thereof. After the opening 130 is formed, the patterned mask 125 can be removed.

[0125] like Figure 14 As shown, according to some embodiments, after the opening 130 is formed on the dielectric layer 123, another patterned mask 133 is formed on the dielectric layer 123. In some embodiments, the patterned mask 133 has an opening 136 in the pattern sparse region B and on the opening 130. In some embodiments, the opening 130 in the dielectric layer 123 is fully exposed by the opening 136 in the patterned mask 133.

[0126] Next, as Figure 15 As shown, according to some embodiments, a patterned mask 133 is used as a mask to etch the dielectric layer 123 to form an opening 138. The etching process may be a wet etching process, a dry etching process, or a combination thereof. In some embodiments, multiple etching parameters are adjusted to etch the dielectric layer 123 to a desired plane.

[0127] In some embodiments, opening 138 is connected to opening 130, and the width W1 of opening 138 is greater than the width W2 of opening 130. In some embodiments, openings 130 and 138 together form an opening structure 140, which has multiple stepped sidewalls. Opening 138 is also referred to herein as an upper part of opening structure 140, and opening 130 is also referred to herein as a lower part of opening structure 140. The corresponding steps are shown in... Figure 2 Step S17 in method 10 shown. After the opening structure 140 is formed, the patterned mask 133 can be removed.

[0128] Next, as Figure 16 As shown, according to some embodiments, a barrier material 143 is conformally deposited in the aperture structure 140 and on the upper surface 123T of the dielectric layer 123. In some embodiments, the sidewalls (e.g., the plurality of stepped sidewalls) and the lower surface of the aperture structure 140 are covered by the barrier material 143. In some embodiments, the barrier material 143 comprises tantalum, tantalum nitride, titanium, titanium nitride, combinations thereof, or other applicable materials. The fabrication technique of the barrier material 143 may include using a conformal deposition method, such as a CVD process, a PVD process, or an ALD process.

[0129] like Figure 17 As shown, according to some embodiments, after the barrier material 143 is formed, a manganese-containing material 145 is formed in the remaining portion of the opening structure 140 and on the upper surface 123T of the dielectric layer 123. In some embodiments, the barrier material 143 is completely covered by the manganese-containing material 145. In some embodiments, the manganese-containing material 145 contains manganese. In other embodiments, the manganese-containing material 145 contains a manganese-rich material, such as manganese-rich copper manganese or manganese-rich silicon manganese. Furthermore, the fabrication technique of the manganese-containing material 145 may include using a conformal deposition method, such as CVD, PVD, ALD, metal-organic chemical vapor deposition (MOCVD), sputtering, or plating.

[0130] Then, as Figure 18 As shown, according to some embodiments, a conductive material 147 is formed in the remaining portion of the opening structure 140 and on the upper surface 123T of the dielectric layer 123. In some embodiments, the remaining portion of the opening structure 140 on the manganese-containing material 145 is completely filled with the conductive material 147. In some embodiments, the conductive material 147 comprises a low-resistivity conductive material, such as copper. In other embodiments, the conductive material 147 comprises tungsten, aluminum, titanium, tantalum, gold, silver, combinations thereof, or other applicable conductive materials. The fabrication techniques of the conductive material 147 may include a CVD process, a PVD process, a sputtering process, a plating process, or other applicable processes.

[0131] Please refer back to the previous page. Figure 1 According to some embodiments, after the conductive material 147 is formed, a planarization process is performed to remove the remaining portions of the barrier material 143, the manganese-containing material 145, and the conductive material 147 on the upper surface 123T of the dielectric layer 123. The planarization process may include a CMP process.

[0132] After planarization, the upper surface 123T of the dielectric layer 123 is exposed. A barrier layer 143', a manganese-containing layer 145', and conductive lines 147' are formed in the dielectric layer 123, thus obtaining the interconnect structure 149 in the patterned sparse region B. The corresponding steps are shown in... Figure 2 Step S19 in method 10 shown. In some embodiments, opening 138 (refer to...) Figure 15 The upper part of the interconnect structure 149 is occupied, and the opening 130 (reference) Figure 15 It is occupied by the lower part of the interconnect structure 149.

[0133] Please refer to Figure 1 and Figure 15 According to some embodiments, the conductive line 147 has an upper portion filling the opening 138 and a lower portion filling the opening 130, and the width of the upper portion of the conductive line 147 is greater than the width of the lower portion. In some embodiments, the upper surfaces of the barrier layer 143', the manganese-containing layer 145', and the conductive line 147' are substantially flush with the upper surface 123T of the dielectric layer 123. After the interconnect structure 149 is formed, a semiconductor device structure 100 is obtained. In some embodiments, the semiconductor device structure 100 is a portion of dynamic random access memory (DRAM).

[0134] Figure 19 This is a partial structural schematic diagram illustrating an exemplary integrated circuit having an array of multiple memory cells 50 in some embodiments of this disclosure, such as a memory element 1000. In some embodiments, the memory element 1000 has a dynamic random access memory (DRAM) element. In some embodiments, the memory element 1000 has multiple memory cells 50 configured in a grid pattern and having multiple rows and columns. The multiple memory cells 50 may be varied according to system requirements and fabrication technology.

[0135] In some embodiments, each memory cell 50 has an access element and a storage element. The access element is configured to provide control access to the storage element. In some embodiments, according to some examples, the access element is a field-effect transistor (FET) 51, and the storage element is a capacitor 53. In each memory cell 50, the FET 51 has a drain 55, a source 57, and a gate 59. One terminal of the capacitor 53 is electrically connected to the source 57 of the FET 51, and the other terminal of the capacitor 53 may be electrically connected to ground. Furthermore, in each memory cell 50, the gate 59 of the FET 51 is electrically connected to a word line WL, and the drain 55 of the FET 51 is electrically connected to a word line BL.

[0136] The above description states that the terminal of the field-effect transistor 51 electrically connected to the capacitor 53 is the source 57, and the terminal of the field-effect transistor 51 electrically connected to the bit line BL is the drain 55. However, during read and write operations, the terminal of the field-effect transistor 51 electrically connected to the capacitor 53 can be the drain, and the terminal of the field-effect transistor 51 electrically connected to the bit line BL can be the source. That is, either terminal of the field-effect transistor 51 can be a source or a drain, depending on how the field-effect transistor 51 is controlled by the voltages applied to its source, drain, and gate.

[0137] By controlling the voltage at the gate 59 via the word line WL, a voltage potential can be generated across the field-effect transistor 51, allowing electrical charge to flow from the source 55 to the capacitor 53. Therefore, the charge stored in the capacitor 53 can be represented as a binary digit in the memory cell 50. For example, a positive charge stored at a threshold voltage in the capacitor 53 is represented as the binary digit "1". If the charge in the capacitor 53 is below the threshold value, a binary digit "0" can be said to be stored in the memory cell 50.

[0138] The plurality of bit lines BL are configured to read or write data from and to the plurality of memory cells 50. The plurality of word lines WL are configured to activate field-effect transistors 51 to access a specific column of the plurality of memory cells 50. Accordingly, the memory element 1000 also has a surrounding circuitry region which may include an address buffer, a row decoder, and a column decoder. The row and column decoders selectively access the plurality of memory cells 50 in response to a plurality of address signals provided to the address buffer during read, write, and refresh operations. The plurality of address signals are typically provided by an external controller, such as a microprocessor or other type of memory controller.

[0139] Please refer back to the previous page. Figure 1 Interconnect structure 121a is formed in pattern-dense region A, while interconnect structures 121b and 149 are formed in pattern-sparse region B. Pattern-dense region A can be located in any region of the plurality of memory cells 50 in memory element 1000, and pattern-sparse region B can be located in any region of address buffer, row decoder, or column decoder in memory element 1000.

[0140] This disclosure provides several embodiments of a semiconductor device structure 100 and its fabrication method. In some embodiments, the semiconductor device structure 100 includes a first interconnect structure (e.g., interconnect structure 121b) disposed in a semiconductor substrate; and a second interconnect structure (e.g., interconnect structure 149) disposed in a dielectric layer on the semiconductor substrate. The first interconnect structure is electrically connected to the second interconnect structure, and both the first and second interconnect structures are disposed in a pattern sparse region. The first interconnect structure includes a first manganese-containing layer (e.g., manganese-containing layer 119b) disposed on a conductive line (e.g., conductive line 113b), and the second interconnect structure includes a second manganese-containing layer (e.g., manganese-containing layer 145') disposed between a conductive line (e.g., conductive line 147') and the dielectric layer. The first and second manganese-containing layers are configured to reduce or prevent the formation of vias in the first and second conductive lines, thereby reducing contact resistance. Therefore, the operating speed of the semiconductor device structure 100 can be improved, which greatly improves the overall device performance.

[0141] One embodiment of this disclosure provides a semiconductor device structure. The semiconductor device structure includes a first interconnect structure disposed in a semiconductor substrate; a dielectric layer disposed on the semiconductor substrate; and a second interconnect structure disposed in the dielectric layer and electrically connected to the first interconnect structure. The first interconnect structure includes a first conductive line and a first manganese-containing layer disposed on the first conductive line. The second interconnect structure includes a second conductive line and a second manganese-containing layer disposed between the second conductive line and the dielectric layer.

[0142] Another embodiment of this disclosure provides a semiconductor device structure. The semiconductor device structure includes a first interconnect structure disposed in a semiconductor substrate; and a second interconnect structure disposed on the semiconductor substrate and electrically connected to the first interconnect structure. The first interconnect structure includes a first barrier layer; a first conductive line disposed on the first barrier layer; and a first manganese-containing layer disposed on the first conductive line. The first manganese-containing layer and the first conductive line are separated from the semiconductor substrate by the first barrier layer. The second interconnect structure includes a second barrier layer disposed on and in direct contact with the first manganese-containing layer; a second manganese-containing layer disposed on the second barrier layer; and a second conductive line disposed on the second manganese-containing layer.

[0143] Another embodiment of this disclosure provides a semiconductor device structure. The semiconductor device structure includes a first interconnect structure disposed in a semiconductor substrate; and a second interconnect structure disposed on and electrically connected to the first interconnect structure. The first interconnect structure includes a first conductive line; and a first manganese-containing layer disposed on the first conductive line. An upper surface of the first manganese-containing layer is substantially flush with an upper surface of the semiconductor substrate. The second interconnect structure includes a second manganese-containing layer; and a second conductive line disposed on the second manganese-containing layer. The second manganese-containing layer covers each sidewall of the second conductive line. The first interconnect structure has a first manganese atomic percentage, the second interconnect structure has a second manganese atomic percentage, and the first manganese atomic percentage is different from the second manganese atomic percentage.

[0144] The embodiments disclosed herein have several advantageous features. By forming multiple manganese-containing layers in multiple interconnect structures, the resistance of the multiple conductive lines in the multiple interconnect structures can be reduced. Therefore, the operating speed of the semiconductor device structure is improved, which greatly enhances the overall device performance.

[0145] While this disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions, and alternatives can be made without departing from the concept and scope of this disclosure as defined in the claims. For example, many of the processes described above can be implemented using different methods, and other processes or combinations thereof can be substituted for many of the processes described above.

[0146] Furthermore, the scope of this application is not limited to the specific embodiments of the processes, machinery, manufacturing, material compositions, means, methods, and steps described in the specification. Those skilled in the art will understand from the disclosure of this publication that existing or future processes, machinery, manufacturing, material compositions, means, methods, or steps that have the same function or achieve substantially the same results as the corresponding embodiments described herein can be used according to this publication. Accordingly, such processes, machinery, manufacturing, material compositions, means, methods, or steps are included within the scope of the claims of this publication.

Claims

1. A semiconductor device structure, comprising: a first interconnect structure disposed in a semiconductor substrate, wherein the first interconnect structure comprises: a first conductive line; and a first manganese-containing layer disposed on the first conductive line; a dielectric layer disposed on the semiconductor substrate; a second interconnect structure disposed in the dielectric layer and electrically connected to the first interconnect structure, wherein the second interconnect structure comprises: a second conductive line; and a second manganese-containing layer disposed between the second conductive line and the dielectric layer; and a third interconnect structure disposed in the semiconductor substrate, wherein the third interconnect structure comprises a third conductive line and a third manganese-containing layer disposed on the third conductive line, wherein the third manganese-containing layer of the third interconnect structure and the first manganese-containing layer of the first interconnect structure comprise the same material, wherein the first interconnect structure and the second interconnect structure are disposed in a pattern sparse region, wherein the third interconnect structure is disposed in a pattern dense region.

2. The semiconductor device structure of claim 1, wherein the first conductive line and the second conductive line comprise copper.

3. The semiconductor device structure of claim 1, wherein an upper surface of the first manganese-containing layer is substantially flush with an upper surface of the semiconductor substrate.

4. The semiconductor device structure of claim 1, wherein the first interconnect structure further comprises a first barrier layer surrounding the first conductive line and the first manganese-containing layer, wherein the first conductive line is disposed on the first barrier layer.

5. The semiconductor device structure of claim 1, wherein the second interconnect structure further comprises a second barrier layer disposed between the second manganese-containing layer and the dielectric layer, wherein the second barrier layer directly contacts the first manganese-containing layer of the first interconnect structure.

6. A semiconductor device structure, comprising: a first interconnect structure disposed in a semiconductor substrate, wherein the first interconnect structure comprises: a first barrier layer; a first conductive line disposed on the first barrier layer; and a first manganese-containing layer disposed on the first conductive line, wherein the first manganese-containing layer and the first conductive line are separated from the semiconductor substrate by the first barrier layer; a second interconnect structure disposed on the semiconductor substrate and electrically connected to the first interconnect structure, wherein the second interconnect structure comprises: a second barrier layer disposed on and directly contacting the first manganese-containing layer; a second manganese-containing layer disposed on the second barrier layer; and a second conductive line disposed on the second manganese-containing layer; and a third interconnect structure disposed in the semiconductor substrate, wherein the third interconnect structure comprises a third conductive line and a third manganese-containing layer disposed on the third conductive line, wherein the third manganese-containing layer of the third interconnect structure and the first manganese-containing layer of the first interconnect structure comprise the same material, wherein the third interconnect structure is completely covered by a dielectric layer.

7. The semiconductor device structure of claim 6, wherein the second conductive line is surrounded by the second manganese-containing layer, and the second manganese-containing layer is surrounded by the second barrier layer.

8. The semiconductor device structure of claim 6, wherein a width of an upper portion of the second conductive line is greater than a width of a lower portion of the second conductive line.

9. The semiconductor device structure of claim 6, further comprising a dielectric layer disposed on the semiconductor substrate and covering a portion of the first barrier layer and a portion of the first manganese-containing layer, wherein the second interconnect structure penetrates the dielectric layer.

10. The semiconductor device structure of claim 6, wherein the first conductive line and the second conductive line comprise copper.

11. The semiconductor device structure of claim 6, wherein the first interconnect structure has a first manganese atomic percentage, the second interconnect structure has a second manganese atomic percentage, and the first manganese atomic percentage is different than the second manganese atomic percentage.

12. The semiconductor device structure of claim 11, wherein the first manganese atomic percentage is greater than the second manganese atomic percentage.

13. A semiconductor device structure, comprising: a first interconnect structure disposed in a semiconductor substrate, wherein the first interconnect structure comprises: a first conductive line; and a first manganese-containing layer disposed on the first conductive line, wherein an upper surface of the first manganese-containing layer is substantially flush with an upper surface of the semiconductor substrate; a second interconnect structure disposed on and electrically connected to the first interconnect structure, wherein the second interconnect structure comprises: a second manganese-containing layer; and a second conductive line disposed on the second manganese-containing layer, wherein the second manganese-containing layer covers sidewalls of the second conductive line; wherein the first interconnect structure has a first manganese atomic percentage, the second interconnect structure has a second manganese atomic percentage, and the first manganese atomic percentage is different than the second manganese atomic percentage; and a third interconnect structure disposed in the semiconductor substrate, wherein the third interconnect structure comprises a third conductive line and a third manganese-containing layer disposed on the third conductive line, wherein the third interconnect structure is disposed in a pattern dense region, and the first interconnect structure and the second interconnect structure are disposed in a pattern sparse region.

14. The semiconductor device structure of claim 13, wherein the first manganese atomic percentage is greater than the second manganese atomic percentage.

15. The semiconductor device structure of claim 13, wherein the third interconnect structure has a third manganese atomic percentage, and the third manganese atomic percentage is greater than the second manganese atomic percentage.

16. The semiconductor device structure of claim 13, wherein the first interconnect structure further comprises a first barrier layer separating the first conductive line and the first manganese-containing layer from the semiconductor substrate, and the second interconnect structure further comprises a second barrier layer interposed between the second manganese-containing layer and the first manganese-containing layer.

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