Package and method of forming the same

Abstract

The method includes forming a reconfigurable wafer, comprising: forming a redistribution structure over a carrier; bonding a first plurality of memory dies over the redistribution structure; bonding a plurality of bridge dies over the redistribution structure; and bonding a plurality of logic dies over the first plurality of memory dies and the plurality of bridge dies. Each of the plurality of bridge dies interconnects four of the plurality of logic dies and overlaps with corner regions of four of the plurality of logic dies. A second plurality of memory dies is bonded over the plurality of logic dies. The plurality of logic dies form a first array, and the second plurality of memory dies form a second array. Embodiments of this application relate to packages and methods of forming thereof.

Description

Technical Field

[0001] Embodiments of this application relate to packages and methods of forming the same. Background Technology

[0002] Integrated circuit packaging is becoming increasingly complex, integrating more device dies into a single package to achieve more functions. For example, system packages have been developed to include multiple device dies, such as processors and memory blocks, within the same package. In system packages, devices with different functions formed using different technologies can be joined using both 2D side-by-side and 3D stacking methods to form a system with high computing efficiency, high bandwidth, high functional package density, low communication latency, and low power consumption per bit of data. Summary of the Invention

[0003] Some embodiments of this application provide a method for forming a package, including: forming a reconfigurable wafer, including: forming a redistribution structure over a carrier; bonding a first plurality of memory dies over the redistribution structure; bonding a plurality of bridge dies over the redistribution structure; bonding a plurality of logic dies over the first plurality of memory dies and the plurality of bridge dies, wherein each of the plurality of bridge dies interconnects four of the plurality of logic dies and overlaps with corner regions of four of the plurality of logic dies; and bonding a second plurality of memory dies over the plurality of logic dies, wherein the plurality of logic dies form a first array and the second plurality of memory dies form a second array.

[0004] Other embodiments of this application provide a package including: a redistribution structure; a first plurality of memory dies located above the redistribution structure; a plurality of bridge dies located above the redistribution structure; a plurality of logic dies located above the first plurality of memory dies and the plurality of bridge dies, wherein each of the plurality of bridge dies interconnects at least two of the plurality of logic dies and overlaps with corner regions of at least two of the plurality of logic dies; and a second plurality of memory dies located above and coupled to the plurality of logic dies, wherein the plurality of logic dies form a first array and the second plurality of memory dies form a second array.

[0005] Further embodiments of this application provide a package comprising: a reconfigurable wafer including: a redistribution structure including a plurality of redistribution lines; a plurality of bridge dies located above and bonded to the redistribution structure; a plurality of logic dies located above and bonded to the plurality of bridge dies, wherein at least one of the plurality of bridge dies is bonded to corner regions of four of the plurality of logic dies; and a second plurality of memory dies located above and bonded to the plurality of logic dies, wherein the second plurality of memory dies is bonded to the plurality of logic dies. Attached Figure Description

[0006] The various aspects of the invention can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industrial practice, the various components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various components can be arbitrarily increased or decreased.

[0007] Figure 1A , Figure 1B , Figure 1C , Figure 1D , Figure 1E , Figure 1F and Figure 1G Cross-sectional views, perspective views, top views, and bottom views of a computing system package according to some embodiments are shown.

[0008] Figures 2 to 14 A cross-sectional view is shown of an intermediate stage in the formation of a computing system package according to some embodiments.

[0009] Figure 15A , Figure 15B , Figure 15C , Figure 16A , Figure 16B , Figure 16C , Figure 17A , Figure 17B and Figure 17C A cross-sectional view of a computing system package according to some embodiments is shown.

[0010] Figure 18A and Figure 18B Top and bottom views of a computing system package according to some embodiments are shown.

[0011] Figure 19A , Figure 19B , Figure 20A , Figure 20B , Figure 21A , Figure 21B , Figure 22A and Figure 22B A cross-sectional view of a computing system package according to some embodiments is shown.

[0012] Figure 23 A perspective view of a die-wafer bonding process according to some embodiments is shown.

[0013] Figure 24 A perspective view of a wafer-to-wafer bonding process according to some embodiments is shown.

[0014] Figure 25 A portion of the interconnect structure in the bridge tube core is shown according to some embodiments.

[0015] Figure 26 A capacitor in a bridge tube core is shown according to some embodiments.

[0016] Figure 27 An enlarged view of a sealant in a computing system package according to some embodiments is shown.

[0017] Figure 28 A process flow diagram for forming a computing system package is shown according to some embodiments. Detailed Implementation

[0018] The following disclosure provides various embodiments or examples to achieve different features of the invention. Specific examples of components and arrangements will be described below to simplify the invention. Of course, these are merely examples and are not intended to limit the invention. For example, in the following description, forming a first component above or on a second component can include embodiments where the first and second components are in direct contact, or embodiments where an additional component is formed between the first and second components such that the first and second components are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. Such repetition is merely for brevity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0019] Furthermore, for ease of description, spatial relative terms such as "below," "under," "lower," "above," and "upper" may be used herein to describe the relationship between one element or component and another (or other elements or components) as shown in the figures. In addition to the orientations shown in the figures, spatial relation terms are intended to include different orientations of the device during use or operation. The device may be positioned in other ways (rotated 90 degrees or in other orientations), and the spatial relation descriptors used herein can be interpreted accordingly.

[0020] According to various embodiments, a computing system package and a method of forming the same are provided. The computing system package may include three levels, wherein the middle level includes logic dies, and the bottom and top levels include memory dies. Therefore, the logic dies have the shortest paths to the memory dies they access. Bridge dies are located in the bottom level and are used to interconnect the logic dies. Thus, each logic die has maximum access to other logic dies and memory dies without increasing system complexity. Similarly, the scalability of the system is improved due to the array of logic dies, memory dies, and bridge dies. With this setup, computational efficiency can be improved, system bandwidth can be increased, and latency can be reduced due to the close proximity and efficient layout of the memory dies and logic dies. Intermediate stages in the formation of the package are shown according to some embodiments. Some variations of some embodiments are discussed. Throughout the various views and exemplary embodiments, the same reference numerals are used to designate the same elements.

[0021] Figure 1A , Figure 1B , Figure 1C , Figure 1D , Figure 1E , Figure 1F and Figure 1G Cross-sectional views, perspective views, and top and bottom views of a computing system package 100 according to some embodiments are shown. The computing system package 100 includes logic dies, memory dies, and bridge dies distributed in multiple layers including layer 1, layer 2, and layer 3, which are sealed in sealants 130, 132, and 134, respectively. Layer 1 may include memory die MD1 and bridge die BD. Layer 2 may include logic die LD. Layer 3 may include memory die MD3. Logic die LD performs computational functions, and logic die LD accesses memory dies MD1 and MD3. In the accompanying drawings of this disclosure, the reference numerals for device dies may begin with the symbol "LD", the symbol "MD", or the symbol "BD". The symbol "LD" is used to indicate that the corresponding die is a logic die. The symbol "MD1" is used to indicate that the corresponding die is a memory die in layer 1, and the symbol "MD3" is used to indicate that the corresponding die is a memory die in layer 3. Memory dies MD1 and MD3 are collectively referred to as memory die MD. The letters "BD" indicate that the corresponding die is a bridge die. In each of Level 1, Level 2, and Level 3, the number of logic dies and memory dies can be more than shown. It should be understood that although a three-level package is shown as an example, computing system packages can include more than three levels, such as four, five, or more, and additional levels can be below Level 1 shown and / or above Level 3 shown.

[0022] According to some embodiments of this disclosure, the logic die LD may be an application processor (AP) die, a graphics processing unit (GPU) die, a field-programmable gate array (FPGA) die, an application-specific integrated circuit (ASIC) die, an input / output (IO) die, a network processing unit (NPU) die, a tensor processing unit (TPU) die, an artificial intelligence (AI) engine die, etc.

[0023] According to some embodiments of this disclosure, memory dies MD1 and MD3 may include static random access memory (SRAM) dies, dynamic random access memory (DRAM) dies, wide I / O memory dies, NAND memory dies, resistive random access memory (RRAM) dies, magnetoresistive random access memory (MRAM) dies, phase-change random access memory (PCRAM) dies, or other types of volatile or non-volatile memory dies. The memory die may include a controller, or it may not include a controller. In embodiments where the memory die does not include a controller, the controller may be built into a logic die. The memory die may also be in the form of a single memory die or a pre-stacked block of memory.

[0024] In the computing system package 100, and possibly in each layer, different types of memory dies can be mixed. For example, layer 1 can use one type of memory die as described above, while layer 3 can use another type of memory die. However, all memory dies in layer 1 can be of the same type and identical to each other, while all memory dies in layer 3 can be of the same type and identical to each other, to improve system scalability and reduce package thickness (since different types are mixed, the thickness of the corresponding layer is determined by the thickest type). The logic dies LD in layer 2 can include different types of logic dies, which may include the logic dies described above. Alternatively, all logic dies in layer 2 can be of the same type and identical to each other.

[0025] Level 1 can include multiple memory dies (MD1) and multiple bridge dies (BD), and may not include or have other types of dies, such as logic dies or independent passive device dies. Level 2 can include multiple logic dies (LD), and may or may not include, or have other types of dies, such as memory dies, bridge dies, or passive device dies. Level 3 can include multiple memory dies (MD3), and may or may not include, or have other types of dies, such as logic dies, bridge dies, or passive device dies.

[0026] Each of the logic die LD, memory dies MD1 / MD3, and bridge die BD may include a semiconductor substrate 20A, 20B, or 20C, which may be a silicon substrate. Interconnect structures 22 are formed on the corresponding semiconductor substrates 20A / 20B / 20C and are used to interconnect devices in the corresponding dies. Substrate vias 26A and 26B may be formed to penetrate the corresponding semiconductor substrates 20 of layer 1 dies and layer 2 dies, and are used to interconnect upper components to lower components. Furthermore, electrical connections 28 may be formed to bond to other device dies. Electrical connections 28 are used for bonding between dies in different layers and may be metal pads, metal pillars, solder areas, etc. According to some embodiments, electrical connections 28 are metal pillars (such as copper pillars) and are in a corresponding surface dielectric layer 30. According to some embodiments, the surface dielectric layer 30 is formed of or includes silicon oxide. According to other embodiments, the surface dielectric layer 30 comprises polymers such as polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), etc. Throughout the specification, the side of the semiconductor substrate 20 having the interconnect structure 22 (and active devices, such as transistors, not shown) is referred to as the front side (or "face"), and its opposite side as the back side (or "back"). Therefore, depending on which sides of the die are bonded to each other, the bonding can be face-to-back bonding, face-to-face bonding, or back-to-back bonding. For example, in Figure 1A In this process, a face-to-back bonding method is used.

[0027] Refer again Figure 1A , Figure 1F or Figure 1G Adjacent layers are joined to each other by direct metal-metal bonding, solder bonding, or hybrid bonding. Hybrid bonding includes dielectric-dielectric bonding (also known as fusion bonding, where Si-O-Si bonds can be formed between the two joined dielectric layers).

[0028] The lower layer 1 die may have an interconnect structure (redistribution structure) 50. The redistribution structure 50 may include dielectric layers 54, 108 and 116, RDL 106 and 112, and under-bump metal (UBM) 114. Electrical connections 142, including solder regions, metal pillars, microbumps, etc., may be formed on the bottom surface of the redistribution structure 50.

[0029] Figure 1B and Figure 1C Show them respectively as follows Figure 1A The diagram shows a top view and a bottom view of the computing system package 100. (See reference...) Figure 1A , Figure 1F and Figure 1G Find the cross-section of the computing system package 100, in which Figure 1A Show Figure 1B and Figure 1C Reference section 1A-1A in the middle, Figure 1F Show Figure 1B and Figure 1C Reference section 1F-1F in Figure 1G Show Figure 1B and Figure 1C The reference section is 1G-1G. For example... Figure 1B As shown, memory die MD1 and bridge die BD are shown in dashed lines because they are below logic die DL. According to some embodiments, memory die MD3 can be arranged in an array. Logic die LD can be arranged in an array. Bridge die BD can be arranged in an array, and memory die MD1 can also be arranged in an array. Although a 3×3 array is shown as an example, larger arrays can be formed. Forming device dies in an array configuration has the advantageous characteristic of high scalability. This is particularly useful for increasing computing power by adding more logic dies, memory dies, and bridge dies. As will be discussed in later paragraphs, cooperation among logic dies can be achieved by sharing memory dies and interacting through bridge dies, thereby easily scaling up the system and increasing computing power by expanding the device array.

[0030] According to some embodiments, all logic dies (LDs) are identical to each other. According to alternative embodiments, some logic dies (LDs) are identical to each other and different from other logic dies (LDs) that are also identical to each other. For example, a first plurality of logic dies (LDs) may be identical to each other, and a second plurality of logic dies (LDs) may be identical to each other and different from the first plurality of logic dies (LDs). The first and second plurality of logic dies (LDs) may be arranged in an alternating layout, for example, alternating in each row and column of an array.

[0031] According to some embodiments, each memory die MD3 is coupled to one of the logic dies LD and is accessed by it for signal processing. Each memory die MD1 is coupled to two adjacent logic dies LD and is accessed by them for signal processing. Figure 1G As shown in the diagram. Using this layout, each logic die can directly access three memory dies without requiring wiring between them. This significantly increases the amount of memory accessed by the logic die without increasing power consumption or latency.

[0032] Also refer to Figure 1B and Figure 1CEach bridging die BD is coupled to and interconnects four logic dies LD. The bridging die BD is used for communication between the four connected logic dies. For example, the bridging die BD may include wires that directly interconnect each pair of the four logic dies LD. The bridging die BD may also include networking circuitry (therefore it can be a networked die on-chip), which includes switches, router circuitry, etc., for switching signals between each pair of the four logic dies. Therefore, through the bridging die BD, all four logic dies LD can be used as an integrated system. Furthermore, since each logic dies LD is connected to the four bridging dies, signals can be routed from any of the four bridging dies to another. Therefore, all logic dies LD can work together (through the bridging die BD) to form an integrated computing system and enable parallel computing. (As from...) Figure 1B and Figure 1C It is conceivable that the computing system package 100 can be enlarged to increase computing power by replicating and expanding the array of logic dies LD, memory dies MD1 and MD3, and bridge dies BD.

[0033] Figure 1D and Figure 1E A perspective view of a computing system package 100 according to some embodiments is shown. Figure 1D A three-dimensional view is shown from the top side. Figure 1E A three-dimensional view is shown from the bottom side.

[0034] Figure 1F As shown Figure 1B and Figure 1C The reference section 1F-1F is shown. Since the memory die MD1 is not shown in the cross-sectional view, therefore... Figure 1F Memory die MD1 is not shown. Two logic dies LD connected to the same bridge die are shown, while two other logic dies connected to the same bridge die BD are not shown because they are not in the cross-sectional view shown.

[0035] Figure 25A bridging die BD is schematically shown, including a bridging structure 34 for interconnecting logic dies LD. According to some embodiments, the bridging structure 34 is formed within an interconnect structure 22 of the bridging die BD. For example, the interconnect structure 22 may include a dielectric layer (sometimes referred to as an inter-metal dielectric (IMD)) that may include a low-k dielectric material. The bridging structure 34 may include metal wires and vias that may extend into multiple metallization layers within the interconnect structure 22. The metal wires and vias are interconnected to form multiple electrical paths 36, each electrical path 36 having its opposite end connected to an electrical connector 28A, which may include metal pads, metal pillars, solder areas, etc. The logic die LD has an electrical connector 28B that is coupled to the electrical connector 28A. The bridging structure 34 may also include digital switches, routers, etc., which may include electrical paths and switches (including active devices such as transistors and control circuitry).

[0036] Return to reference Figure 1F The bridge core BD can also include passive components 42 / 43, such as capacitors, resistors, inductors, etc. Figure 26 An example bridging die BD is shown. According to some embodiments, the bridging die BD includes a deep trench capacitor 42 and / or a metal-insulator-metal (MIM) capacitor 43. The deep trench capacitor 42 may include an insulator 42A between capacitor electrodes 42B and 42B, wherein the deep trench capacitor 42 extends into a trench formed in the semiconductor substrate 20, thereby increasing capacitance. The MIM capacitor 43 may include an insulator 43A between capacitor electrodes 43B and 43B, and may be formed in the interconnect structure 22 in the bridging die BD. According to some embodiments, the MIM capacitor 43 and the electrical path 36 ( Figure 25 It extends into the same interconnect structure 22 in the bridge core BD.

[0037] Figure 1G As shown Figure 1B and Figure 1C The reference section 1G-1G is shown. Since the bridging pipe core BD is not shown in the cross-sectional view, therefore... Figure 1G The bridge pipe core BD is not shown in the diagram.

[0038] like Figure 1A , Figure 1F and Figure 1G As shown, a through-hole 26A is formed in the memory die MD1 and the bridge die BD, and passes through the semiconductor substrate 20A of the memory die MD1 and the bridge die BD. The through-hole 26A is used to electrically and signal-couple the redistribution structure 50 to the logic die LD. Figure 1F and Figure 1GAs shown, a through-hole 120 (molded through-hole) is formed to pass through the sealant 130 and is used to electrically and signal couple the redistribution structure 50 to the logic die LD.

[0039] Figures 2 to 14 Examples of embodiments according to this disclosure are shown as follows: Figure 1A , Figure 1B , Figure 1C , Figure 1D , Figure 1E , Figure 1F and Figure 1G The diagram shows a cross-sectional view of an intermediate stage in the formation of the computing system package 100. According to some embodiments, such as... Figures 2 to 14 As shown, the method of first RDL (“RDL” stands for “redistribution line”) is adopted, wherein the redistribution structure 50 is formed before the die is placed and joined. Figure 1A The corresponding processes are also schematically reflected in... Figure 28 In the process flow shown, according to an alternative embodiment, a post-RDL method can be used, where the die is first placed and joined, and then the redistribution structure 50 is formed.

[0040] Figure 2 A carrier 102 and a release film 104 formed on the carrier 102 are shown. The carrier 102 may be a glass carrier, a silicon wafer, an organic carrier, etc. According to some embodiments, the carrier 102 may have a circular top view shape. The release film 104 may be formed of a polymer-based material (such as a photothermal conversion (LTHC) material) that is capable of decomposition under thermal radiation such as a laser beam, thereby allowing the carrier 102 to detach from the above structure to be formed in subsequent processes. According to some embodiments of this disclosure, the release film 104 is formed of an epoxy resin-based thermal release material coated on the carrier 102.

[0041] like Figures 2 to 5 As shown, multiple dielectric layers and multiple RDLs are formed above the release film 104. (Reference) Figure 2 A dielectric layer 54 is formed on the release film 104. According to some embodiments of the present invention, the dielectric layer 54 is formed of a polymer, which may also be a photosensitive material such as polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), etc., that can be patterned using photolithography processes (including exposure and development processes).

[0042] According to some embodiments, redistribution lines (RDLs) 106 are formed above dielectric layer 54. The corresponding process is shown as follows. Figure 28Process 202 in process flow 200 shown in the diagram. The formation of RDL 106 may include forming a metal seed layer (not shown) over dielectric layer 54, forming a patterned mask (not shown) such as photoresist over the metal seed layer, and then performing a metal plating process on the exposed seed layer. The patterned mask and the portion of the seed layer covered by the patterned mask are then removed, leaving, as shown in the diagram. Figure 2 The RDL 106 shown. According to some embodiments of the invention, the seed layer comprises a titanium layer and a copper layer located above the titanium layer. For example, the seed layer can be formed using processes such as physical vapor deposition (PVD). Plating can be performed using, for example, electrochemical plating or electroless plating processes.

[0043] refer to Figure 3 A dielectric layer 108 is formed on RDL 106. The corresponding process is shown as follows. Figure 28 Process 204 in process flow 200 is shown in the diagram. The bottom surface of dielectric layer 108 contacts the top surfaces of RDL 106 and dielectric layer 54. According to some embodiments of the invention, dielectric layer 108 is formed of a polymer, which may be a photosensitive material such as PBO, polyimide, BCB, etc. Optionally, dielectric layer 108 may include an organic dielectric material such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, etc. Dielectric layer 108 is then patterned to form openings 110 in dielectric layer 28. Some portions of RDL 106 are exposed through the openings 110 in dielectric layer 108.

[0044] Next, refer to Figure 4 This forms RDL 112 to connect to RDL 106. The corresponding process is shown as follows. Figure 28 Process 206 in process flow 200 shown in the diagram. RDL 112 includes a metal trace (metal line) located above dielectric layer 108. RDL 112 also includes a via extending into an opening 110 in dielectric layer 108. RDL 112 can also be formed by a plating process, wherein each RDL 112 includes a seed layer (not shown) and a plated metal material located above the seed layer. According to some embodiments, the formation of RDL 112 may include: depositing a blanket metal seed layer extending into the via opening; and forming and patterning a first plating mask (such as photoresist) wherein an opening is formed above and bonded to the via opening. A plating process is then performed to plate a metal material that completely fills the via opening 110. Figure 3 It has a portion that is higher than the top surface of dielectric layer 108. Then, the first plating mask is removed.

[0045] The metal seed layer and the plating material can be formed from the same material or different materials. The metal material in RDL 112 can include metals or metal alloys, including copper, aluminum, tungsten, or alloys thereof. RDL 112 includes RDL lines (also called traces or trace portions) 112L and via portions (also called vias) 112V, wherein the trace portion 112L is located above the dielectric layer 108, and the via portion 112V is located within the dielectric layer 108. Since the trace portion 112L and the via portion 112V are formed in the same plating process, there is no distinguishable interface between the via 112V and the corresponding upper trace portion 112L. Moreover, each via 112V can have a tapered profile, with its upper portion wider than its corresponding lower portion.

[0046] Also refer to Figure 4 Conductive bumps 114 are formed on RDL 112. The corresponding process is shown as follows. Figure 28 Process 208 in process flow 200 is shown in the figure. It should be understood that although only one RDL layer 112 is shown in the example embodiment, more RDL layers may be formed on top of and electrically connected to RDL layer 112. Subsequent formation processes involve bonding the device die MD1 ( Figure 7 ) and BD ( Figure 1A The method of bonding is described, and it relates to whether the device die is placed face down or face up, and whether solder bonding, direct metal-to-metal bonding, or hybrid bonding is used. Therefore, although one forming process is discussed as an example, other forming processes and structures are also within the scope of this disclosure.

[0047] According to some embodiments, a second plating mask is used to plate the conductive bumps 114, and the same metal seed layer used for plating the RDL 112 can be used for plating. The conductive bumps 114 may include copper, nickel, gold, etc. After plating the conductive bumps 114, the second plating mask is removed, and then an etching process is performed to remove the exposed portion of the metal seed layer, which was previously covered by the second plating mask and the plated RDL 112. The metal seed layer is also considered to be part of the RDL 112. This forms the redistribution structure 50.

[0048] Next, as Figure 5 As shown, dielectric layer 116 is formed. The corresponding process is shown as follows. Figure 28Process 210 in the process flow 200 shown in the diagram. A planarization process can be performed to make the top surfaces of the conductive bumps 114 and the dielectric layer 116 flush. When hybrid bonding is to be performed, the dielectric layer 116 may include a silicon-containing dielectric material such as silicon oxide. According to an alternative embodiment, the conductive bumps 114 may be formed after the dielectric layer 116 is formed, and the formation process may include forming an opening in the dielectric layer 116 to expose the underlying RDL 112, and then forming the conductive bumps 114. The corresponding dielectric layer 116 may include organic materials such as PBO, polyimide, BCB, etc., or may include inorganic dielectric materials such as silicon oxide, silicon nitride, silicon oxynitride, etc. The formation process also includes forming a metal seed layer, forming a plating mask, plating a metal material, removing the plating mask, and then etching the unwanted portions of the metal seed layer.

[0049] Next, as Figure 6 As shown, a metal pillar 120 is formed. The corresponding process is shown as follows. Figure 28 Process 212 in process flow 200 shown in the diagram. The formation process may include forming a metal seed layer, forming a plating mask (not shown, but may be photoresist) over the metal seed layer, patterning the plating mask to expose the underlying metal seed layer, and then plating a metal material in the openings of the plating mask. The metal pillars 120 are alternatively referred to as through holes or molded through holes because they will pass through a subsequently formed sealing material (which may be molding compound). The plated metal material may be copper or a copper alloy. The metal pillars 120 may have substantially vertical and straight edges. According to an alternative embodiment, conductive bumps 114A are not formed in the prior process. Instead, they are formed using the same process as forming the metal pillars 120.

[0050] Figure 7 This shows the placement / attachment of the level 1 dies, which includes the memory die MD1 and the bridge die BD (see also...). Figure 1A The corresponding process is shown as follows: Figure 28 Process 214 in process flow 200 is shown in the diagram. The bridge pipe core BD is located in a cross-sectional view not shown, and therefore is not included. Figure 7 As shown in the diagram. According to some embodiments, the layer 1 die MD1 and BD face downwards, and the electrical connectors 122 in the layer 1 die MD1 and BD are engaged to the conductive bumps 114. According to alternative embodiments, for example, as... Figure 16A , Figure 16B and Figure 16C As shown, dies MD1 and BD can face upwards, and electrical connectors on the rear side of dies MD1 and BD are engaged with conductive bumps 114.

[0051] The memory die MD1 and the bridge die BD may have electrical connections 124A (such as metal pads, metal bumps, etc.) pre-formed as part of the respective device dies. The electrical connections 124A are located on the rear side of the respective dies. A dielectric layer 126A may also be formed on the back side of the memory die MD1 and the bridge die BD. According to an alternative embodiment, the electrical connections 124A are not pre-formed in the memory die MD1 and the bridge die BD. Instead, through-holes 26A extend to the intermediate level between the top and back surfaces of the semiconductor substrate 20, and the electrical connections are formed after the memory die MD1 and the bridge die BD are sealed. Figure 8 The process and Figure 9 The processes shown are formed between them.

[0052] Next, as Figure 8 As shown, the layer 1 die MD1 and BD, along with the metal pillar 120, are sealed within a sealant 130. The corresponding process is illustrated as follows: Figure 28 Process 216 in process flow 200 shown in the diagram. Sealant 130 fills the gap between adjacent through-holes 120 and the stage 1 die MD1 and BD. Sealant 130 may include molding compound, molded underfill, epoxy resin, and / or resin. When formed from molding compound, sealant 130 may include a base material (which may be a polymer, resin, epoxy resin, etc.) and filler particles in the base material. The filler particles may be dielectric particles such as SiO2, Al2O3, silicon dioxide, etc., and may be spherical. Moreover, the spherical filler particles may have a variety of different diameters.

[0053] Then, a planarization process, such as a chemical mechanical polishing (CMP) step or a mechanical polishing step, is performed to thin the sealant 130 until the through-hole 120 and the layer 2 dies MD1 and BD are exposed. Due to the planarization process, the top of the through-hole 120 is substantially flush (coplanar) with the top surface of the electrical connector 124A (if pre-formed) and substantially coplanar with the top surface of the sealant 130. Throughout the specification, the layer 1 die and the sealant 130 are collectively referred to as the reconstructed wafer 131.

[0054] refer to Figure 9 The layer 2 die LD is bonded to the layer 1 die MD1 and BD, as well as through-hole 120 (and reconstructed wafer 131). The corresponding process is shown as follows. Figure 28Process 218 in process flow 200 is shown. In the example embodiment shown, the layer 2 die LD is directly bonded to the layer 1 dies MD1 and BD and the through-hole 120, without an RDL in between. According to an alternative embodiment, an additional fan-out redistribution structure (not shown) including a dielectric layer and an RDL can be formed on and connected to the layer 1 dies MD1 and BD and the through-hole 120, and the layer 2 die LD is bonded to the additional fan-out redistribution structure. Similar to the layer 1 die, the electrical connector 124B and the dielectric layer 126B can be pre-formed in the layer 2 die LD, or can be formed in another additional fan-out redistribution structure above the layer 2 die LD.

[0055] Figure 10 The sealing of the Level 2 die LD in sealant 132 is shown, which may be similar to or the same as sealant 130. A planarization process is then performed to make the top surfaces of the Level 2 die LD and sealant 132 flush. The corresponding process is shown as follows. Figure 28 Process 220 is shown in process flow 200. Throughout the specification, layer 2 die LD and sealant 132 are collectively referred to as reconstructed wafer 133.

[0056] exist Figure 9 and Figure 10 In the example embodiment shown, firstly, the layer 1 die is placed and sealed to form the reconstructed wafer 131, and then discrete layer 2 dies are placed on the reconstructed wafer 131 via die-wafer bonding. A perspective view of the die-wafer bonding process is shown below. Figure 23 As shown, the reconstructed wafer 131 includes layer 1 dies MD1 and BD, and sealant 130. Layer 2 die LD is placed on the reconstructed wafer 131. Figure 24 An alternative embodiment is shown, wherein reconstructed wafers 131 and 133 are pre-formed, and reconstructed wafer 133 is bonded to reconstructed wafer 131 via wafer-to-wafer bonding. Similar to... Figure 23 and Figure 24 As shown, the Level 3 die MD3 can also be bonded to the Level 2 die via die-to-wafer bonding or wafer-to-wafer bonding.

[0057] refer to Figure 11 The layer 3 die MD3 is bonded to the layer 2 die LD (and reconstructed wafer 133). The corresponding process is shown as follows. Figure 28 Process 222 is shown in process flow 200. In the example embodiment shown, layer 3 die MD3 is directly bonded to layer 2 die LD without RDL in between. According to an alternative embodiment, an additional fan-out redistribution structure (not shown) including a dielectric layer and RDL can be formed on and connected to layer 2 die LD, and layer 3 die MD3 is bonded to the additional fan-out redistribution structure.

[0058] Figure 12 The sealing of the MD3 layer 3 die in sealant 134 is shown, which may be similar to or the same as sealants 130 and / or 132. The corresponding process is shown as follows. Figure 28 Process 224 in process flow 200 shown in the diagram. A planarization process is then performed to flush the top surfaces of the layer 3 die MD3 and sealant 134. The layer 3 die MD3 and sealant 134 are collectively referred to as reconstructed wafer 135. Throughout the specification, the structure including dielectric layer 54 and the structures above it is referred to as reconstructed wafer 100, which is also referred to as computing system package 100. Next, for example, the reconstructed wafer 100 is peeled from carrier 102 by decomposing release film 104 by projecting a laser beam onto release film 104. Figure 11 The corresponding process is shown as follows: Figure 28 Process 226 in the process flow 200 shown in the figure.

[0059] Figure 13 The formation of an electrical connector 142 is shown, which may include solder areas, metal pads, metal pillars, or combinations thereof. The corresponding process is shown as follows: Figure 28 Process 228 in process flow 200 shown in the figure. The forming process may include forming an opening in dielectric layer 54 and forming an electrical connector 142 extending into the opening to contact RDL 106.

[0060] Figure 14 The diagram illustrates the bonding of the reconstructed wafer 100 to a package assembly 144, which may be or may include a printed circuit board, a package substrate, a silicon middleware, an organic middleware, a power module, a socket, etc. The corresponding process is shown as follows: Figure 28 Process 230 in process flow 200 shown in the diagram. Underfill 146 is applied to the gap between the reconstructed wafer 100 and the package assembly 144. This forms the package 148. According to some embodiments, a connector 152, such as an adapter, socket (including pin holes for inserting pins), etc., may be formed in the package 148, for example, attached to the package assembly 144, so that the circuitry in the package 148 can be electrically connected to external components.

[0061] According to some embodiments, the entire unsaved reconstructed wafer 100 is bonded to the package assembly 144 and included in the resulting package 148. Therefore, the reconstructed wafer 100 in the package 148 can have a circular top view, similar to... Figure 23 and Figure 24 As shown. According to an alternative embodiment, the reconstructed wafer 100 is trimmed to remove portions without device dies and wires, without trimming portions including devices and portions containing wires. According to yet another alternative embodiment, along scribing line 141 ( Figure 13 The reconstructed wafer 100 is sawn into multiple identical packages, each package including, for example, Figure 13 All of the multiple device dies shown are formed using one of the same packages, as described above. Figure 14 The package shown.

[0062] Figure 27 Show Figure 14 A magnified view of region 150 in the image. Figure 27 As shown, sealant 130 includes base material 130A and filler particles 130B in base material 130A. Sealant 132 includes base material 132A and filler particles 132B in base material 130A. Sealant 134 includes base material 134A and filler particles 134B in base material 134A. Since planarization is not performed on the bottom surface of sealant 130, the spherical particles 130B in contact with the redistribution structure 50 are rounded, and the rounded surface contacts the redistribution structure 50. The portion of sealant 130 in contact with sealant 132 (or any additional redistribution structure) is... Figure 8 The steps shown have already been planarized. Therefore, during planarization, the spherical particles 130B at the top surface of sealant 130 are partially polished, thus having a substantially planar top surface. Similarly, in each of sealants 132 and 134, the spherical particles 132B / 134B at the bottom surface are not polished but remain spherical, while the spherical particles 132B / 134B at the top surface are polished and are partially spherical particles with a circular bottom surface and a flat top surface.

[0063] Figure 15A , Figure 15B , Figure 15C , Figure 16A , Figure 16B , Figure 16C , Figure 17A , Figure 17B , Figure 17C , Figure 19A , Figure 19B , Figure 20A , Figure 20B , Figure 21A , Figure 21B , Figure 22A and Figure 22B A cross-sectional view of a computing system package 100 according to an alternative embodiment is shown. These embodiments are similar to... Figure 1A , Figure 1B , Figure 1C , Figure 1D , Figure 1E , Figure 1F and Figure 1G (as well as Figures 2 to 13 The embodiments shown in the previous embodiments have been modified in some respects. Therefore, the discussions provided in the previous embodiments can also be applied to these embodiments as long as applicable.

[0064] Figure 15A , Figure 15B , Figure 15C , Figure 16A , Figure 16B , Figure 16C , Figure 17A , Figure 17B and Figure 17C The illustrated embodiments can also be found from Figure 1B and Figure 1C The reference sections 1A-1A, 1F-1F, and 1G-1G were obtained.

[0065] Figure 15A , Figure 15B and Figure 15C A computing system package 100 is shown according to some embodiments. These embodiments are similar to... Figure 1A , Figure 1B , Figure 1C , Figure 1D , Figure 1E , Figure 1F and Figure 1G (Too Figure 13 The embodiments in the structure) except in Figure 13 In the original text, each memory die MD1 and MD3 is a single memory die, while... Figure 15A , Figure 15B and Figure 15C In some embodiments, memory stacks MD1' and MD3' can be used, each comprising a plurality of stacked memory dies MD1 and MD3, respectively. The plurality of memory dies MD1 can be interconnected via substrate through-holes formed therein. According to these embodiments, layer 1 dies, layer 2 dies, and layer 3 dies face downwards. Layer 3 dies MD3 can also be part of a die stack MD3'.

[0066] Figure 16A , Figure 16B and Figure 16C A computing system package 100 is shown according to some embodiments. These embodiments are similar to... Figure 1A , Figure 1B , Figure 1C , Figure 1D , Figure 1E , Figure 1F and Figure 1G (Too Figure 13 The embodiments in the structure) except in Figure 13 In the middle, the MD1 and BD of the level 1 die are facing down, while... Figure 16A , Figure 16B and Figure 16C In this embodiment, layer 1 dies MD1 and BD face upwards. Layer 2 dies LD and layer 3 dies MD3 remain facing downwards.

[0067] Figure 17A , Figure 17B and Figure 17C A computing system package 100 is shown according to some embodiments. These embodiments are similar to... Figure 15A , Figure 15B and Figure 15C In the embodiments, except in Figure 15A , Figure 15B and Figure 15C In the middle, the memory die MD1 and the bridge die BD face downwards, while... Figure 17A , Figure 17B and Figure 17C In this embodiment, memory die MD1 and bridge die BD face upwards. Layer 2 die LD and layer 3 die MD3 remain facing downwards.

[0068] Figure 18A and Figure 18B Top and bottom views of a computing system package 100 according to some embodiments are shown respectively, these embodiments being related to Figure 1B and Figure 1C The illustrated embodiment is similar, except that in addition to the bridge terminal BD (labeled BD1) that interconnects four logic dies, a bridge terminal BD (labeled BD2) can be added to interconnect two adjacent logic dies LD. According to an alternative embodiment, bridge terminal BD2 is formed instead of BD1. In the following... Figure 19A , Figure 19B , Figure 20A , Figure 20B , Figure 21A , Figure 21B , Figure 22A and Figure 22B In the figure, the figure whose reference numeral includes the letter "A" is from Figure 18A and Figure 18B The reference section AA in the figure is obtained, and the figure with the letter "B" in the figure reference is from the figure above. Figure 18A and Figure 18B The reference section BB was obtained.

[0069] Figure 19A and Figure 19B A computing system package 100 is shown according to some embodiments. These embodiments are similar to... Figure 1A , Figure 1B , Figure 1C , Figure 1D , Figure 1E , Figure 1F and Figure 1G (Too Figure 13In the embodiment of the structure shown, a bridging die BD2 is added, and each of the shown bridging dies BD2 interconnects two level 2 dies LD, instead of interconnecting four level 2 dies as bridging dies BD1. The memory dies in level 1 and level 3 are single memory dies.

[0070] Figure 20A and Figure 20B A computing system package 100 is shown according to some embodiments. These embodiments are similar to... Figure 19A and Figure 19B In the embodiments, except in Figure 20A and Figure 20B In this process, memory die stacks MD1' and MD3' are used.

[0071] Figure 21A and Figure 21B A computing system package 100 is shown according to some embodiments. These embodiments are similar to... Figure 19A and Figure 19B In the embodiments, except in Figure 19A and Figure 19B In the middle, the MD1 and BD1 dies of level 1 face downwards, while... Figure 21A and Figure 21B In the middle, the MD1 and BD1 of the first-level die are facing upwards.

[0072] Figure 22A and Figure 22B A computing system package 100 is shown according to some embodiments. These embodiments are similar to... Figure 20A and Figure 20B In the embodiments, except in Figure 20A and Figure 20B In the middle, the bridge die BD and the memory die stack MD1' have layer 1 die MD1 facing down, while... Figure 22A and Figure 22B In the middle, the bridge die BD and the memory die stack MD1' have the layer 1 die MD1 facing upwards.

[0073] Embodiments of the present invention have several advantageous features. By forming a computing system package comprising three layers, wherein the middle layer has logic dies, and the upper and lower layers have memory dies, with the logic dies having the shortest path to the memory dies, bridge dies are formed to interconnect adjacent logic dies. Due to the use of an array of logic dies, memory dies, and bridge dies, the scalability of the system is improved. Computational efficiency can be increased, system bandwidth can be increased, and latency can be reduced.

[0074] According to some embodiments of this disclosure, the method includes forming a reconstructed wafer, including: forming a redistribution structure over a carrier; bonding a first plurality of memory dies over the redistribution structure; bonding a plurality of bridge dies over the redistribution structure; bonding a plurality of logic dies over the first plurality of memory dies and the plurality of bridge dies, wherein each of the plurality of bridge dies interconnects four of the plurality of logic dies and overlaps with corner regions of four of the plurality of logic dies; and bonding a second plurality of memory dies over the plurality of logic dies, wherein the plurality of logic dies form a first array and the second plurality of memory dies form a second array. According to an embodiment, the method further includes bonding a package assembly to the reconstructed wafer to form an additional package. According to an embodiment, when bonding the package assembly to the reconstructed wafer, the reconstructed wafer includes the first array and the second array. According to an embodiment, the method further includes attaching a socket to the additional package, wherein, after attaching the socket, the reconstructed wafer includes both the first array and the second array. According to an embodiment, the method further includes: sealing a first plurality of memory dies and a plurality of bridged-pipe dies in a first sealant; sealing a plurality of logic dies in a second sealant; and sealing a second plurality of memory dies in a third sealant. According to an embodiment, the reconstructed wafer has no logic dies in the first and third sealants, and no memory dies in the second sealant. According to an embodiment, the plurality of logic dies have a bottom surface that is in physical contact with the top surface of the first sealant. According to an embodiment, the second sealant is sealed over the first sealant and is in physical contact with the first sealant. According to an embodiment, the first plurality of memory dies are identical to each other, the plurality of logic dies are identical to each other, and the second plurality of memory dies are identical to each other. According to an embodiment, the plurality of logic dies are bonded to the first plurality of memory dies by a hybrid bonding process. According to an embodiment, bonding of the plurality of logic dies over the first plurality of memory dies and the plurality of bridged-pipe dies is performed by die-wafer bonding. According to an embodiment, performing the bonding of multiple logic dies over a first plurality of memory dies and a plurality of bridge dies via a wafer-to-wafer bonding process includes: sealing the first plurality of memory dies and the plurality of bridge dies to form a first reconstructed wafer; sealing the plurality of logic dies to form a second reconstructed wafer; and bonding the second reconstructed wafer to the first reconstructed wafer via wafer-to-wafer bonding.

[0075] According to some embodiments of this disclosure, the package includes: a redistribution structure; a first plurality of memory dies located above the redistribution structure; a plurality of bridge dies located above the redistribution structure; a plurality of logic dies located above the first plurality of memory dies and the plurality of bridge dies, wherein each of the plurality of bridge dies interconnects at least two of the plurality of logic dies and overlaps with corner regions of at least two of the plurality of logic dies, wherein the plurality of logic dies are identical to each other; and a second plurality of memory dies located above and engaged with the plurality of logic dies, wherein the plurality of logic dies form a first array and the second plurality of memory dies form a second array. According to embodiments, the first plurality of memory dies are identical to each other, the second plurality of memory dies are identical to each other, the plurality of logic dies are identical to each other, and the plurality of bridge dies are identical to each other. According to embodiments, the plurality of bridge dies also include capacitors. According to embodiments, the package further includes: a first sealant sealing the first plurality of memory dies; a second sealant sealing the plurality of logic dies, wherein the bottom surfaces of the plurality of logic dies contact the top surface of the first sealant; and a third sealant sealing the second plurality of memory dies. According to an embodiment, the third sealant is in physical contact with the second sealant.

[0076] According to some embodiments of this disclosure, the package includes a reconfigurable wafer comprising: a redistribution structure including a plurality of redistribution lines; a plurality of bridge dies located above and engaged with the redistribution structure; a plurality of logic dies located above and engaged with the plurality of bridge dies, wherein at least one of the plurality of bridge dies is engaged to corner regions of four of the plurality of logic dies; and a second plurality of memory dies located above and engaged with the plurality of logic dies, wherein the second plurality of memory dies is engaged to the plurality of logic dies. According to embodiments, the package further includes a package assembly engaged to the reconfigurable wafer. According to embodiments, the package further includes a socket engaged to the package assembly.

[0077] The foregoing has described components of several embodiments, enabling those skilled in the art to better understand the various embodiments of the present invention. Those skilled in the art should understand that other processes and structures can be readily designed or modified based on the present invention to achieve the same objectives and / or realize the same advantages as the embodiments described herein. Those skilled in the art should also recognize that these equivalent structures do not depart from the spirit and scope of the present invention, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of the present invention.

Claims

1. A method of forming a package, comprising: Forming a reconstructed wafer includes: A redistribution structure is formed above the carrier; A first plurality of memory dies are joined above the redistribution structure; Multiple bridge pipe cores are joined above the redistribution structure; A plurality of logic dies are joined above the first plurality of memory dies and the plurality of bridge dies, wherein each of the plurality of bridge dies interconnects four of the plurality of logic dies and overlaps with the corner regions of four of the plurality of logic dies; and A second plurality of memory dies are joined above the plurality of logic dies, wherein the plurality of logic dies form a first array and the second plurality of memory dies form a second array.

2. The method according to claim 1, further comprising: The packaging components are bonded to the reconstructed wafer to form an additional package.

3. The method of claim 2, wherein, When the packaging assembly is bonded to the reconstructed wafer, the reconstructed wafer includes the first array and the second array.

4. The method of claim 3, further comprising: The socket is attached to the additional package, wherein, after the socket is attached, the reconstructed wafer includes both the first array and the second array.

5. The method according to claim 1, further comprising: The first plurality of memory dies and the plurality of bridge dies are sealed in a first sealant; The plurality of logic dies are sealed in a second sealant; as well as The second plurality of memory dies are sealed in a third sealant.

6. The method of claim 5, wherein, The reconstructed wafer has no logic dies in the first and third sealants and no memory dies in the second sealant.

7. The method of claim 5, wherein, The plurality of logic dies have a bottom surface that is in physical contact with the top surface of the first sealant.

8. The method of claim 5, wherein, The second sealant is sealed over the first sealant and is in physical contact with the first sealant.

9. The method of claim 1, wherein, The first plurality of memory dies are identical to each other, the plurality of logic dies are identical to each other, and the second plurality of memory dies are identical to each other.

10. The method of claim 1, wherein, The plurality of logic dies are coupled to the first plurality of memory dies through a hybrid bonding process.

11. The method of claim 1, wherein, The bonding of the plurality of logic dies over the first plurality of memory dies and the plurality of bridge dies is performed via die-wafer bonding.

12. The method according to claim 1, wherein, Performing the bonding of the plurality of logic dies over the plurality of memory dies and the plurality of bridge dies via a wafer-to-wafer bonding process includes: The first plurality of memory dies and the plurality of bridge dies are sealed to form a first reconfiguration wafer; Sealing the plurality of logic dies to form a second reconfigurable wafer; and The second reconstructed wafer is bonded to the first reconstructed wafer via wafer-to-wafer bonding.

13. A package comprising: Redistributed structure; The first plurality of memory dies are located above the redistribution structure; Multiple bridge pipe cores are located above the redistribution structure; A plurality of logic dies are located above the first plurality of memory dies and the plurality of bridge dies, wherein each of the plurality of bridge dies interconnects at least two of the plurality of logic dies and overlaps with the corner regions of at least two of the plurality of logic dies; and A second plurality of memory dies are located above and connected to the plurality of logic dies, wherein the plurality of logic dies form a first array and the second plurality of memory dies form a second array.

14. The package of claim 13, wherein, The first plurality of memory dies are identical to each other, the second plurality of memory dies are identical to each other, the plurality of logic dies are identical to each other, and the plurality of bridge dies are identical to each other.

15. The package of claim 13, wherein, The multiple bridge cores also include capacitors.

16. The package according to claim 13, further comprising: A first sealant is used to seal the first plurality of memory dies; A second sealant is used to seal the plurality of logic dies, wherein the bottom surface of the plurality of logic dies contacts the top surface of the first sealant. as well as A third sealant is used to seal the second plurality of memory dies.

17. The package according to claim 16, wherein, The third sealant is in physical contact with the second sealant.

18. A package comprising: Reconstructing wafers, including: The redistribution structure includes multiple redistribution lines; Multiple bridge pipe cores are located above the redistribution structure and joined to the redistribution structure; A plurality of logic dies are located above and connected to a plurality of bridge connector dies, wherein at least one of the plurality of bridge connector dies is connected to corner regions of four of the plurality of logic dies; and A second plurality of memory dies are located above and connected to the plurality of logic dies, wherein the second plurality of memory dies are connected to the plurality of logic dies.

19. The package of claim 18, further comprising a package assembly bonded to the reconstructed wafer.

20. The package of claim 19, further comprising a socket coupled to the package assembly.

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