Semiconductor device and method of forming the same

Abstract

An embodiment of the present invention provides a semiconductor device and a method for forming the same. The semiconductor device includes a first conductive line above a substrate and a memory structure above the first conductive line. The memory structure is electrically coupled to the first conductive line through a conductive via. A spacer layer is located at the side of the memory structure and covers the sidewalls of the memory structure. A first dielectric layer is located on the spacer layer and at the side of the memory structure. A second dielectric layer is located on the memory structure, the spacer layer, and the first dielectric layer. A second conductive line passes through the second dielectric layer, the first dielectric layer, and the spacer layer to be electrically coupled to the memory structure. The second conductive line includes a main body portion at least partially embedded in the second dielectric layer and an extension portion located below the main body portion and laterally protruding from the sidewall of the main body portion. The extension portion is electrically connected to the upper electrode of the memory structure and is surrounded by the spacer layer.

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a method for forming the same, and more particularly to a memory device and a method for forming the same. Background Art

[0002] Memory devices are widely used in various electronic devices. Among various memory devices, resistive random access memory (RRAM) devices have become a type of non-volatile memory that has been widely studied in recent years due to their advantages such as fast operation speed and low power consumption. Generally, an RRAM device has a transistor and a memory structure electrically coupled to the transistor. A conductive via and a conductive line are usually disposed above the memory structure, and the conductive line is electrically coupled to the memory structure through the conductive via.

[0003] In the formation process of traditional memory devices, after forming the memory structure, an etching process (e.g., reactive ion etching (RIE)) is usually used to pattern the dielectric material above the memory stack structure to form a via hole exposing the memory stack structure, and a conductive via is formed in the via hole. Then, a dielectric layer and a conductive line embedded in the dielectric layer are formed above the conductive via. However, in the traditional process, during the etching process of forming the via hole, the upper part (e.g., the upper electrode) of the memory structure may be exposed to the etching plasma and thus damaged by the etching process, thereby affecting the reliability of the memory device. Summary of the Invention

[0004] Embodiments of the present invention provide a semiconductor device including a memory and a method for forming the same, which can improve the durability and reliability of the memory device.

[0005] Embodiments of the present invention provide a semiconductor device, which includes a first conductive line above a substrate and a memory structure above the first conductive line. The memory structure is electrically coupled to the first conductive line through a conductive via. A spacer layer is located at a side of the memory structure and covers a sidewall of the memory structure. A first dielectric layer is located on the spacer layer and at a side of the memory structure. A second dielectric layer is located on the memory structure, the spacer layer, and the first dielectric layer. A second conductive line passes through the second dielectric layer, the first dielectric layer, and the spacer layer to be electrically coupled to the memory structure. The second conductive line includes a main body portion at least partially embedded in the second dielectric layer and an extension portion located below the main body portion and laterally protruding from a sidewall of the main body portion. The extension portion is electrically connected to an upper electrode of the memory structure and is surrounded and covered by the spacer layer.

[0006] An embodiment of the present invention provides a method for forming a semiconductor device, which includes: forming a first conductive line above a substrate; forming a memory structure above the first conductive line, the memory structure being electrically connected to the first conductive line through a conductive via; forming a sacrificial layer on the memory structure; forming a spacer layer to cover sidewalls of the memory structure and sidewalls and a top surface of the sacrificial layer; forming a first dielectric layer to cover the spacer layer; performing a planarization process to remove at least a portion of the first dielectric layer located above a topmost surface of the spacer layer; forming a second dielectric layer on the spacer layer and the first dielectric layer; performing a patterning process to form an opening that at least penetrates through the second dielectric layer, the opening exposing a portion of the top surface of the sacrificial layer; removing the sacrificial layer to form a groove; and forming a second conductive line in the opening and the groove to be electrically coupled to the memory structure.

[0007] In summary, in the embodiment of the present invention, a sacrificial layer is formed on the memory structure, and then an etching process is performed to form a wire trench above the memory structure. The sacrificial layer can serve as an etch stop layer and protect the underlying memory structure from damage during the etching process, thereby improving the durability and reliability of the formed memory device. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Reading the following detailed description in conjunction with the accompanying drawings will best understand various aspects of the present invention. It should be noted that, according to standard practices in the industry, various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of various features may be arbitrarily increased or decreased.

[0009] Figures 1A to 1K A cross-sectional view showing a method for forming a semiconductor device according to some embodiments of the present invention;

[0010] Figures 2A to 2C Showing according to some embodiments of the present invention Figure 1K An enlarged view of region R1 in;

[0011] Figures 3A to 3D A cross-sectional view showing a method for forming a semiconductor device according to other embodiments of the present invention. DETAILED DESCRIPTION

[0012] The present invention will be described more fully with reference to the accompanying drawings of this embodiment. However, the present invention can be embodied in various different forms and should not be limited to the embodiments described herein. The thicknesses of layers and regions in the drawings are enlarged for clarity. Identical or similar component numerals represent identical or similar components, and will not be repeated in the following paragraphs.

[0013] Figures 1A to 1K A cross-sectional view showing a method for forming a semiconductor device according to some embodiments of the present invention.Figures 2A to 2C An enlarged view of region R1 according to some embodiments of the present invention is shown. Figure 1K of the middle region R1.

[0014] Referring to Figure 1A , a substrate 100 is provided. The substrate 100 is, for example, a semiconductor substrate. By way of example, the semiconductor substrate may include a silicon substrate. The silicon substrate may be an undoped silicon substrate or a doped silicon substrate. The doped silicon substrate may be an N-type doped silicon substrate or a P-type doped silicon substrate.

[0015] In some embodiments, the substrate 100 includes a first region 100a and a second region 100b. The first region 100a is, for example, a memory region for forming a memory device. The second region 100b is a peripheral region, for example, a logic circuit region. A plurality of devices (not shown), such as active devices, passive devices, or a combination thereof, may be formed in and / or on the substrate 100. In some embodiments, the devices include transistors, such as metal-oxide-semiconductor field-effect transistors (MOSFETs). The transistor may include a gate disposed on the substrate 100, a gate dielectric layer disposed between the gate and the substrate 100, and source / drain regions disposed in the substrate 100 and on both sides of the gate.

[0016] A dielectric layer 101 is formed over the substrate 100. The dielectric layer 101 may be a single-layer or multi-layer structure. The dielectric layer 101 may include a suitable dielectric material such as silicon oxide, and may be formed by a suitable deposition process such as chemical vapor deposition (CVD). The dielectric layer 101 is formed over the substrate 100 and covers the devices (e.g., transistors) on the substrate 100.

[0017] Continuing to refer to Figure 1A , a plurality of conductive lines M1 are formed in the dielectric layer 101. Each of the conductive lines M1 includes a barrier layer 102 and a conductive layer 103. The material of the barrier layer 102 may include titanium, tantalum, titanium nitride, tantalum nitride, analogs thereof, or a combination thereof. The material of the conductive layer 103 includes a metal or a metal alloy, such as copper, tungsten, aluminum, alloys thereof, analogs thereof, or a combination thereof. In some embodiments, the barrier layer 102 is located between the dielectric layer 101 and the conductive layer 103, and surrounds the sidewalls and the bottom surface of the conductive layer 103.

[0018] In some embodiments, the method for forming the conductive wire M1 includes the following processes: for example, patterning the dielectric layer 101 through photolithography and etching to form a plurality of wire trenches in the dielectric layer 101; then, using a suitable process such as a deposition process (e.g., CVD, physical vapor deposition (PVD)) or electroplating, forming a barrier material and a conductive material on the top surface of the dielectric layer 101 and in the trenches; performing a planarization process (e.g., chemical mechanical polishing (CMP)) to remove the excess barrier material and conductive material on the top surface of the dielectric layer 101, and the barrier material and conductive material remaining in the trenches form the conductive wire M1. In some embodiments, the top surfaces of the barrier layer 102 and the conductive layer 103 of the conductive wire M1 are substantially flush with the top surface of the dielectric layer 101.

[0019] In some embodiments, the dielectric layer 101 further includes a plurality of conductive features (not shown), such as conductive contacts, conductive vias, and / or conductive wires. The conductive features are located below the conductive wire M1 and electrically connect the conductive wire M1 to the devices formed on the substrate 100. For example, in the first region 100a, the conductive wire M1 can be electrically connected to a transistor on the substrate 100 through a conductive contact below it. In some embodiments, the conductive contact lands on the drain region of the transistor.

[0020] Continuing to refer to Figure 1A , an etch stop layer 105 is formed on the dielectric layer 101 and the conductive wire M1. The material of the etch stop layer 105 is different from that of the dielectric layer 101. In some examples, the etch stop layer 105 may include silicon nitride, silicon oxynitride, silicon carbonitride, or a combination thereof. The method for forming the etch stop layer 105 may include a suitable deposition process such as CVD.

[0021] Referring to Figure 1B , a dielectric layer 106 is formed on the etch stop layer 105. The material of the dielectric layer 106 may be similar to that of the dielectric layer 101, for example, it is or includes silicon oxide, silane, its analogs, or a combination thereof. The method for forming the dielectric layer 106 may include CVD. A patterned mask layer 107 is formed on the dielectric layer 106. The patterned mask layer 107 includes a plurality of mask openings 107a to expose a part of the top surface of the dielectric layer 106. The patterned mask layer 107 is used to define a plurality of interlayer holes in the dielectric layer 106 and the etch stop layer 105. In some embodiments, the patterned mask layer 107 may be or may include a patterned photoresist and may be formed by a photolithography process.

[0022] Referring to Figure 1C, a patterning mask layer 107 is used as an etching mask for an etching process to remove some portions of the dielectric layer 106 and the etch stop layer 105 exposed by the mask openings 107a, and a plurality of openings 108 are formed in the dielectric layer 106 and the etch stop layer 105. The openings 108 penetrate through the dielectric layer 106 and the etch stop layer 105 to expose a partial top surface of the conductive line M1. In some embodiments, the openings 108 may be vias.

[0023] Referring to Figure 1C and Figure 1D , the patterning mask layer 107 is removed, for example, by processes such as ashing or stripping. Then, a conductive via V2 is formed in the via 108 to electrically connect to the conductive line M1. In some embodiments, the conductive via V2 includes a barrier layer 109 and a conductive pillar 110. The materials of the barrier layer 109 and the conductive pillar 110 may be respectively selected from the same candidate materials as the barrier layer 102 and the conductive layer 103, and may be the same as or different from the materials of the barrier layer 102 and the conductive layer 103. In some embodiments, different metal materials are used for the conductive pillar 110 and the conductive layer 103. For example, the conductive layer 103 includes copper, while the conductive pillar 110 includes tungsten. However, the present invention is not limited thereto.

[0024] In some embodiments, the method for forming the conductive via V2 includes forming (e.g., depositing) a barrier material and a conductive material on the top surface of the dielectric layer 106 and in the via 108. Then, a planarization process (e.g., CMP) is used to remove the excess barrier material and conductive material on the top surface of the dielectric layer 106, and the remaining barrier layer 109 and conductive pillar 110 in the via 108 form the conductive via V2. In some embodiments, the top surface of the barrier layer 109 of the conductive via V2 and the top surface of the conductive pillar 110 are substantially flush with the top surface of the dielectric layer 106.

[0025] Referring to Figure 1E, a plurality of stacked structures 120 are formed on the dielectric layer 106 and the conductive vias V2 located in the first region 100a. The stacked structure 120 includes a memory structure MS and a sacrificial layer 115 formed on the memory structure MS. In some embodiments, the memory structure MS is, for example, a data storage structure for a resistive random access memory (RRAM). That is, the memory structure MS can be a resistor structure. The memory structure MS is electrically coupled to the source / drain region of a transistor on the substrate 100 through the conductive via V2 and the conductive line M1. Each memory structure MS and the corresponding transistor form a memory cell. In some embodiments, the memory cell is in a 1-transistor-1-resistor (1T1R) configuration and forms an RRAM cell. However, the present invention is not limited thereto.

[0026] In some embodiments, the memory structure MS is a stacked structure including a plurality of electrode layers 112 and dielectric layers 113 stacked alternately. For example, the memory structure MS may include, from bottom to top, a first electrode layer 112a, a first dielectric layer 113a, a second electrode layer 112b, a second dielectric layer 113b, and a third electrode layer 112c (the electrode layers 112a, 112b, 112c can be collectively referred to as the electrode layer 112, and the dielectric layers 113a, 113b can be collectively referred to as the dielectric layer 113). The dielectric layers 113 are respectively sandwiched between two corresponding electrode layers. In some embodiments, the bottommost electrode layer 112a can also be referred to as the lower electrode or the bottom electrode, and the topmost electrode layer 112c can also be referred to as the upper electrode or the top electrode.

[0027] Although Figure 1E the memory structure MS is described by taking three electrode layers 112 and two dielectric layers 113 as an example, the number of electrode layers and dielectric layers included in the memory structure MS is not limited thereto. The memory structure MS includes at least two electrode layers and dielectric layers sandwiched between the two electrode layers. For example, the second dielectric layer 113b and the third electrode layer 112c can be selectively formed and can be omitted in some embodiments. In these embodiments, the memory structure MS may include only the first electrode layer 112a, the first dielectric layer 113a, and the second electrode layer 112b from bottom to top. In still other embodiments, the memory structure MS may include more dielectric layers and electrode layers stacked alternately above the third electrode layer 112c.

[0028] The material of the electrode layer 112 may include metals, metal nitrides, analogs thereof, or combinations thereof. For example, the electrode layer 112 may include titanium, titanium nitride, tantalum, tantalum nitride, platinum, tungsten, ruthenium, or combinations thereof or other suitable metal materials. The materials of different electrode layers 112 may be the same as or different from each other. In some embodiments, the first electrode layer 112a and the third electrode layer 112c include titanium, while the second electrode layer 112b includes titanium nitride. However, the present invention is not limited thereto.

[0029] In some embodiments, the material of the dielectric layer 113 includes a variable resistance dielectric material and may be referred to as a variable resistance layer. The variable resistance dielectric material includes, for example, metal oxides, such as hafnium oxide (HfO x ), tungsten oxide (WO x ), analogs thereof, or combinations thereof.

[0030] The sacrificial layer 115 is formed on the topmost layer of the memory structure MS (e.g., the third electrode layer 112c) to cover the top surface of the electrode layer 112c on the top of the memory structure MS. In some embodiments, the sacrificial layer 115 may also be referred to as a protective layer or a capping layer. The material of the sacrificial layer 115 may include a suitable material different from the materials of the electrode layer 112 and the subsequently formed spacer layer and dielectric layer. In some embodiments, the sacrificial layer 115 includes a semiconductor material, such as polysilicon. However, the present invention is not limited thereto.

[0031] Continuing to refer to Figure 1E , in some embodiments, the method of forming the memory structure MS and the sacrificial layer 115 includes: sequentially forming, on the dielectric layer 106 and the conductive via V2, respective electrode material layers, dielectric material layers, and sacrificial material layers for the memory structure MS through suitable deposition processes (e.g., CVD, PVD); then patterning the sacrificial material layer, the electrode material layer, and the dielectric material layer by photolithography and etching to form a stacked structure 120 including the memory structure MS and the sacrificial layer 115 in the first region 100a. In some embodiments, the sidewalls of the respective electrode layers 112 and dielectric layers 113 of the memory structure MS and the sidewalls of the sacrificial layer 115 are substantially aligned in a direction perpendicular to the top surface of the substrate 100. However, the present invention is not limited thereto.

[0032] Referring to Figure 1F, a spacer layer 122 and a dielectric layer 123 are formed above the substrate 100. The spacer layer 122 covers the top surface of the dielectric layer 106 and the top surfaces and sidewalls of the plurality of stacked structures 120. In some embodiments, the spacer layer 122 is conformally formed on the dielectric layer 106 and the stacked structures 120. The spacer layer 122 includes a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, analogs thereof, or combinations thereof, and can be formed by suitable deposition processes such as CVD, atomic layer deposition (ALD), etc. The spacer layer 122 can also be referred to as a spacer material layer.

[0033] The dielectric layer 123 is formed on the spacer layer 122 and covers the surface of the spacer layer 122. The dielectric layer 123 can include, for example, a dielectric material such as silicon oxide, and can be formed by deposition processes such as CVD, high density plasma (HDP) CVD, etc. The material of the dielectric layer 123 can be similar to or different from the material of the spacer layer 122. In some embodiments, the spacer layer 122 can be used as a stop layer in subsequent processes, such as a CMP stop layer or an etch stop layer.

[0034] Referring to Figures 1F to 1G , in some embodiments, a planarization process (e.g., CMP) is performed to at least remove a portion of the dielectric layer 123 and form a dielectric layer 123a. In some embodiments, the planarization process is performed to remove the portion of the dielectric layer 123 located above the topmost surface of the spacer layer 122 until the topmost surface of the spacer layer 122 is exposed. That is, the spacer layer 122 serves as a CMP stop layer. In some embodiments, after the planarization process, the dielectric layer 123a is located on and at the sides of the spacer layer 122, and the top surface of the dielectric layer 123a is substantially flush with the top surface of the spacer layer 122. However, the present invention is not limited thereto.

[0035] Referring to Figure 1H , a dielectric layer 125 is formed above the dielectric layer 123a, for example, by a deposition process (such as CVD). The dielectric layer 125 can include silicon oxide. Then, a patterned mask layer 126 is formed on the dielectric layer 125. The patterned mask layer 126 can include a patterned photoresist and has a plurality of mask openings 126a and 126b to expose a portion of the top surface of the dielectric layer 125. In some embodiments, the mask opening 126a is located in the first region 100a, and at least a portion of the mask opening 126a is located directly above the stacked structure 120. The mask opening 126b is located in the second region 100b, and at least a portion of the mask opening 126b is located directly above the conductive via V2. In some embodiments, the mask openings 126a and 126b are trenches extending in a direction perpendicular to the plane of the paper and are used to define wire trenches.

[0036] Referring to Figure 1H and Figure 1I, a patterned mask layer 126 is used as an etch mask for an etching process, such as reactive ion etching (RIE), to form openings 127a and 127b. In some embodiments, the spacer layer 122 serves as an etch stop layer, and the etching process is carried out until the spacer layer 122 exposed by the mask openings 127a / 127b is removed, and a spacer layer 122a is formed. In the first region 100a, the etching process removes a portion of the dielectric layer 125 and a portion of the spacer layer 122 exposed by the mask opening 126a, and forms an opening 127a. In the second region 100b, the etching process removes a portion of the dielectric layer 125, a portion of the dielectric layer 123a, and a portion of the spacer layer 122 exposed by the mask opening 126b, and forms an opening 127b. In some embodiments, the openings 127a and 127b are wire trenches and extend at least partially in a direction perpendicular to the plane of the paper. The opening 127a is located in the first region 100a, passes through the dielectric layer 125 and the spacer layer 122a, to expose a partial top surface of the sacrificial layer 115 of the stacked structure 120. The opening 127b is located in the second region 100b, passes through the dielectric layer 125, the dielectric layer 123a, and the spacer layer 122a, to expose the top surface of the conductive via V2 and a partial top surface of the dielectric layer 106.

[0037] In some embodiments, the width of the mask opening 126a is less than the width of the stacked structure 120, such that the width W1 of the formed opening 127a is less than the width W2 of the stacked structure 120. After the etching process, a portion of the top surface of the sacrificial layer 115 is exposed by the opening 127a, while another portion (e.g., the edge portion) of the top surface of the sacrificial layer 115 is covered by the spacer layer 122a and the dielectric layer 125 above it. In some embodiments, the width of the mask opening 126b and the width of the opening 127b defined by it may be greater than the width of the corresponding conductive via V2.

[0038] In the above etching process, since the sacrificial layer 115 is disposed on the memory structure MS, the memory structure MS can be prevented from being exposed to the etching plasma, and thus the sacrificial layer 115 can protect the memory structure MS below it from damage by the etching process. After the etching process, the patterned mask layer 126 is removed using a process such as ashing or stripping. In some embodiments, a cleaning process may be further performed to remove by-products and / or residues that may be generated during the etching process and / or the removal of the patterned mask layer 126.

[0039] Refer to Figure 1I and Figure 1J, the sacrificial layer 115 is removed to form a recess 128 at the position previously occupied by the sacrificial layer 115, exposing the memory structure MS. In some embodiments, the sacrificial layer 115 is removed by an etching process, such as a wet etching process. The etching process has a high etching selectivity of the sacrificial layer 115 to the memory structure MS (e.g., the electrode layer 112), and may have a high etching selectivity of the sacrificial layer 115 to other adjacent layers (e.g., the dielectric layer 125, the spacer layer 122a). For example, the etchant used in the wet etching process may include Rezi-38, but the present invention is not limited thereto. In some embodiments, the entire sacrificial layer 115 (including the portion covered by the spacer layer) is completely removed, while other adjacent layers are substantially not removed. Since the wet etching process does not use etching plasma and has a high etching selectivity of the sacrificial layer 115 to the memory structure MS, the etching process does not damage the memory structure MS. In some embodiments, a small portion of the spacer layer 122a may be slightly damaged and removed during the removal of the sacrificial layer 115. In other embodiments, the spacer layer 122a is substantially not removed. In some embodiments, after removing the sacrificial layer 115, a cleaning process may be further performed to remove by-products and / or residues that may be generated by the etching process. The cleaning process may use, for example, a Sc1 cleaning solution.

[0040] Referring to Figure 1J , in some embodiments, after removing the sacrificial layer 115, some portions of the spacer layer 122a overhang the memory structure MS, and a recess 128 is formed below the opening 127a and between the memory structure MS and the spacer layer 122a. The recess 128 or a portion of the recess 128 may also be referred to as the gap between the memory structure MS and the spacer layer 122a above it. The recess 128 is in spatial communication with the opening 127a and is defined by the top surface of the memory structure MS and the partial sidewalls and bottom surface of the spacer layer 122a. In some embodiments, the width of the recess 128 is substantially equal to the width of the memory structure MS and is greater than the width of the opening 127a. In other embodiments where a portion of the spacer layer 122a may be removed by the etching process, the width of the recess 128 may be slightly greater than the width of the memory structure MS.

[0041] Referring to Figure 1K, a conductive line M2 is formed in the openings 127a, 127b and the groove 128. The conductive line M2 includes a conductive line M2a located in the opening 127a and the groove 128 and a conductive line M2b located in the opening 127b. The conductive line M2a is electrically connected to and physically contacts the top electrode 112c of the memory structure MS. The conductive line M2b is electrically connected to and physically contacts the conductive via V2. In some embodiments, the conductive line M2 each includes a barrier layer 129 and a conductive layer 130. The material and formation method of the conductive line M2 are similar to those of the conductive line M1. For example, the formation of the conductive line M2 may include the following process: after forming the groove 128, a barrier material and a conductive material are formed above the substrate 100 to cover the surface of the dielectric layer 125 and fill the openings 127a, 127b and the groove 128. Then, a planarization process (e.g., CMP) is performed to remove excess barrier material and conductive material located above the top surface of the dielectric layer 125. The barrier layer 129 and the conductive layer 130 remaining in the opening 127a and the groove 128 constitute the conductive layer M2a, and the barrier layer 129 and the conductive layer 130 remaining in the opening 127b constitute the conductive line M2b. In some embodiments, the top surface of the barrier layer 129 and the top surface of the conductive layer 130 of the conductive line M2 are substantially flush with the top surface of the dielectric layer 125.

[0042] Continue to refer to Figure 1K , so far, the semiconductor device 500A has been formed. In some embodiments, the semiconductor device 500A includes a substrate 100, a conductive line M1 embedded in a dielectric layer 101, a conductive via V2, a memory structure MS, and conductive lines M2a and M2b. The conductive via V2 is embedded in and passes through the dielectric layer 101 and the etching stop layer 105, and is electrically connected to the conductive line M1. The memory structure MS and the conductive line M2a are located in the first region 100a, and are electrically coupled to the conductive line M1 through the conductive via V2. The conductive line M2b is located in the second region 100b, passes through the dielectric layers 125, 123a and the spacer layer 122a to be electrically connected to the conductive via V2.

[0043] The memory structure MS is located on the dielectric layer 106 and the conductive via V2, and is surrounded and wrapped by the spacer layer 122a. In some embodiments, a portion FP of the spacer layer 122a overlies the topmost surface of the memory structure MS (for example, the top surface of the electrode layer 112c), and is spaced apart from the topmost surface of the memory structure MS by a non-zero distance. The portion FP of the spacer layer 122a may also be referred to as an overlying portion FP. In other words, there is a gap between the overlying portion FP of the spacer layer 122a and the topmost surface of the memory structure MS. In some embodiments, the cross-sectional shape of the overlying portion FP of the spacer layer 122a is square, rectangular, or the like, as shown in the enlarged view. Figure 2Aas shown, but the present invention is not limited thereto. In some other embodiments, a part of the overlying portion FP of the spacer layer 122a may be removed during the process of removing the sacrificial layer 115, and thus the cross-sectional shape of the overlying portion FP may be trapezoidal, triangular, similar shapes or other suitable shapes, and the surface of the overlying portion FP contacting the conductive wire M2a may be inclined or arc-shaped, as shown in the enlarged Figure 2B as shown.

[0044] In some embodiments, the conductive wire M2a passes through the dielectric layer 125, the dielectric layer 123a and the spacer layer 122a, and fills the gap between the spacer layer 122a and the memory structure MS to physically contact and electrically connect with the electrode layer 112c of the memory structure MS. In other words, the conductive wire M2a has a main body portion P1 and an extension portion P2 located below the main body portion P1. In some embodiments, the main body portion P1 is embedded in the overlying portion FP of the dielectric layer 125, the dielectric layer 123a and the spacer layer 122a. The extension portion P2 is located between the main body portion P1 and the memory structure MS, laterally protrudes from the side wall of the main body portion P1 and extends to the gap between the overlying portion FP of the spacer layer 122a and the memory structure MS. That is to say, the overlying portion FP of the spacer layer 122a and the topmost surface of the memory structure MS are spaced apart by the extension portion P2 of the conductive wire M2a located therebetween. In this embodiment, the top surface of the extension portion P2 is covered by the overlying portion FP of the spacer layer 122a and is lower than the top surface of the spacer layer 122a and the top surface of the dielectric layer 123a.

[0045] In some embodiments, the main body portion P1 is, for example, line-shaped, and at least partially extends in a direction perpendicular to the paper surface, and physically contacts the side walls of the dielectric layer 125, the dielectric layer 123a and the overlying portion FP of the spacer layer 122a. The extension portion P2 is located on the memory structure MS and physically contacts and electrically connects with the electrode layer 112c. In some embodiments, the stack including the memory structure MS and the extension portion P2 has a pillar structure and is surrounded by the spacer layer 122a. A part of the side wall and the top surface of the extension portion P2 (for example, the edge portion) physically contacts the spacer layer 122a. In some embodiments, viewed from a top view (not shown), the memory structure MS and the extension portion P2 may be, for example, circular, elliptical, similar shapes or other suitable shapes, and the vertically extending portion of the spacer layer 122a may be, for example, annular, surrounding and contacting the side walls of the memory structure MS and the extension portion P2. The annular shape may include a circular ring shape, an elliptical ring shape or other types of annular shapes.

[0046] The width W1’ of the main body portion P1 is smaller than the width W2’ of the extending portion P2. In this document, the widths of the main body portion P1 and the extending portion P2 refer to their widths in the direction perpendicular to the extending direction of the main body portion P1 (for example, the direction parallel to the paper surface and parallel to the top surface of the substrate 100). In some embodiments, the width W2’ of the extending portion P2 of the conductive wire M2a is substantially equal to the width of the memory structure MS, and the sidewalls of the extending portion P2 and the memory structure MS can be substantially aligned in the direction perpendicular to the top surface of the substrate 100, but the present invention is not limited thereto. In some embodiments where part of the spacer layer 122a is also removed during the process of removing the sacrificial layer 115, the width of the groove 128 may be greater than the width of the memory structure MS, such that the width of the extending portion P2 of the conductive wire M2a formed therein is also greater than the width of the memory structure MS, as shown in the enlarged Figure 2C view. In other words, the extending portion P2 can protrude laterally from the sidewalls of the memory structure MS, and the protruding portion of the extending portion P2 from the memory structure MS can be embedded in the spacer layer 122a.

[0047] Figures 3A to 3D is a cross-sectional view of a method for forming a semiconductor device according to other embodiments of the present invention. This embodiment is similar to the foregoing embodiment, except that: in this embodiment, Figures 1F to 1G the planarization process stops at the sacrificial layer 115.

[0048] Referring to Figure 1F and Figure 3A , in some embodiments, after forming the dielectric layer 123, a planarization process (such as CMP) is performed to remove a part of the dielectric layer 123 above the top surface of the stacked structure 120 and a part of the spacer layer 122, and form the spacer layer 122b and the dielectric layer 123b on the sides of the stacked structure 120. After the planarization process, the top surface of the sacrificial layer 115 is exposed, and the top surfaces of the dielectric layer 123b and the spacer layer 122b are substantially flush with the top surface of the sacrificial layer 115.

[0049] Referring to Figure 3B , a dielectric layer 125 is formed on the stacked structure 120, the dielectric layer 123b, and the spacer layer 122b. Then, openings 127a are formed in the dielectric layer 125 in the first region 100a, for example, by photolithography and etching, to expose a part of the top surface of the sacrificial layer 115; and openings 127b are formed in the dielectric layer 125, 123b, and the spacer layer 122b in the second region 100b to expose the top surface of the conductive via V2 and a part of the top surface of the dielectric layer 106. The openings 127a and 127b are trenches, for example. In some embodiments, the openings 127a and 127b can be formed simultaneously or separately.

[0050] Referring to Figure 3B andFigure 3C , for example, the sacrificial layer 115 is removed using wet etching to form a recess 128 below the opening 127a. The recess 128 is spatially connected to the opening 127a, is located between the memory structure MS and the dielectric layer 125, and is defined by the top surface of the memory structure MS, the sidewalls of the spacer layer 122b, and the bottom surface of the dielectric layer 125. After removing the sacrificial layer 115, a cleaning process may be performed to remove byproducts and / or residues that may be generated by the etching process.

[0051] Reference Figure 3D , a conductive line M2a is formed in the opening 127a and the groove 128, and a conductive line M2b is formed in the opening 127b. At this point, the semiconductor device 500B is completed. In the semiconductor device 500B, the spacer layer 122b does not have the upper covering portion of the above-mentioned embodiment. The conductive line M2a is filled in the groove 128 and contacts the bottom surface of the dielectric layer 125.

[0052] The conductive line M2a has a main body portion P1' and an extension portion P2' located below the main body portion P1' and laterally protruding from the sidewall of the main body portion P1'. In the present embodiment, the main body portion P1' is embedded in the dielectric layer 125. The extension portion P2' is located between the memory structure MS and the main body portion P1', and between the memory structure MS and the dielectric layer 125. The portion of the extension portion P2' protruding from the main body portion P1' contacts the sidewall of the spacer layer 122b and the bottom surface of the dielectric layer 125. In some embodiments, the top surface of the extension portion P2' is substantially flush with the top surface of the spacer layer 122b and the top surface of the dielectric layer 123b. Other features of the semiconductor device 500B are similar to those of the embodiment of the present invention. Figure 1K The semiconductor device 500A is not described in detail here.

[0053] In the above embodiments, the memory structure MS is a memory structure of an RRAM device as an example to illustrate the concept of the present invention, but the present invention is not limited thereto. The present invention can also be applied to other types of memory devices, such as dynamic random access memory (DRAM), etc. For example, in some embodiments, the material of the variable resistance layer of the memory structure MS can be replaced with a dielectric material (e.g., a high dielectric constant dielectric material), so that the memory structure forms a capacitor and is electrically coupled with a transistor on a substrate to form a memory cell of a DRAM device.

[0054] In an embodiment of the present invention, after a sacrificial layer is formed on a memory structure, an etching process (e.g., RIE) is performed to form a wire trench above the memory structure, and the etching process stops at the sacrificial layer. In this way, the RIE process for forming a conductive via that exposes the memory structure in the conventional method is omitted, and in the etching process for forming a wire trench in the present invention, the sacrificial layer can prevent the underlying memory structure from being exposed to the etching plasma, and thus protect the memory structure from damage by the etching plasma. Furthermore, the performance of the formed memory device, such as endurance reliability, can be improved, and the product yield can be increased.

[0055] Although the present invention has been disclosed as above by way of embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to that defined by the appended claims.

Claims

1. A semiconductor device, comprising: A first conductive line disposed above a substrate; A memory structure located above the first conductive line and electrically coupled to the first conductive line through a conductive via; A spacer layer located at a side of the memory structure and covering sidewalls of the memory structure; A first dielectric layer located on the spacer layer and at a side of the memory structure; A second dielectric layer located above the memory structure, the spacer layer, and the first dielectric layer; And A second conductive line passing through the second dielectric layer, the first dielectric layer, and the spacer layer to be electrically coupled to the memory structure, the second conductive line comprising: A main body portion at least partially embedded in the second dielectric layer; And An extension portion located below the main body portion and electrically connected to an upper electrode of the memory structure, wherein the extension portion laterally protrudes from a sidewall of the main body portion and is surrounded and covered by the spacer layer, Wherein the spacer layer further includes a covering portion covering the memory structure, and the covering portion and the upper electrode of the memory structure are spaced apart by a part of the extension portion therebetween.

2. The semiconductor device according to claim 1, wherein a width of the extension portion is greater than a width of the main body portion.

3. The semiconductor device according to claim 1, wherein a part of the extension portion protruding from the main body portion is located between the memory structure and the second dielectric layer and contacts a bottom surface of the second dielectric layer.

4. The semiconductor device according to claim 1, wherein a topmost surface of the spacer layer is flush with a top surface of the first dielectric layer and contacts a bottom surface of the second dielectric layer.

5. The semiconductor device according to claim 4, wherein a top surface of the extension portion of the second conductive line is flush with or lower than the topmost surface of the spacer layer and the top surface of the first dielectric layer.

6. The semiconductor device according to claim 1, wherein the memory structure includes a resistive random access memory structure and at least includes a lower electrode, an upper electrode, and a variable resistance layer disposed between the upper electrode and the lower electrode.

7. A method of forming a semiconductor device, comprising: Forming a first conductive line above a substrate; Forming a memory structure above the first conductive line, the memory structure being electrically connected to the first conductive line through a conductive via; Forming a sacrificial layer on the memory structure; Forming a spacer layer to cover sidewalls of the memory structure and sidewalls and a top surface of the sacrificial layer; Forming a first dielectric layer to cover the spacer layer; Performing a planarization process to remove at least a part of the first dielectric layer located above a topmost surface of the spacer layer; Forming a second dielectric layer on the spacer layer and the first dielectric layer; Performing a patterning process to form an opening at least passing through the second dielectric layer, the opening exposing a part of the top surface of the sacrificial layer; Removing the sacrificial layer to form a groove; A second conductive line is formed in the opening and the groove to be electrically coupled to the memory structure, wherein the width of the opening is formed to be smaller than the width of the sacrificial layer, such that the width of the opening is smaller than the width of the groove formed by removing the sacrificial layer, the second conductive line has a main body portion located in the opening and an extension portion located in the groove, and the extension portion laterally protrudes from the sidewall of the main body portion.

8. The method of forming a semiconductor device according to claim 7, wherein the patterning process removes a portion of the second dielectric layer and a portion of the spacer layer, and the opening is formed in the second dielectric layer and the spacer layer.

9. The method of forming a semiconductor device according to claim 7, wherein the planarization process further includes removing a portion of the spacer layer located on the top surface of the sacrificial layer to expose the top surface of the sacrificial layer.

Images