Semiconductor device

Abstract

A semiconductor device includes a substrate, a semiconductor channel layer, a semiconductor barrier layer, and a gate electrode. The semiconductor channel layer is disposed on the substrate, and the semiconductor barrier layer is disposed on the semiconductor channel layer, wherein a surface of the semiconductor barrier layer includes at least one recess. The gate electrode is disposed on the semiconductor barrier layer, wherein the gate electrode includes a main portion and at least one vertically extending portion that overlaps the recess.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor devices, and particularly to a high electron mobility transistor and a method of fabricating the same. BACKGROUND

[0002] In semiconductor technology, III-V semiconductor compounds can be used to form various integrated circuit devices, such as high power field effect transistors, high frequency transistors or high electron mobility transistors (HEMTs). A HEMT is a type of field effect transistor having a two dimensional electron gas (2DEG) layer adjacent to a junction between two materials having different bandgaps (i.e., a heterojunction). Since a HEMT does not use a doped region as a carrier channel for the transistor, but rather uses a 2-DEG layer as a carrier channel for the transistor, a HEMT has several attractive features over conventional metal-oxide-semiconductor field effect transistors (MOSFETs), such as high electron mobility and the ability to transmit signals at high frequencies. For conventional HEMTs, there is still a need to further reduce the on-resistance (Ron) and to improve the transconductance (gm) and the breakdown voltage (V ON ) to meet the current industry demands. BR SUMMARY

[0003] In view of the foregoing, it would be desirable to provide an improved high electron mobility transistor to meet the current industry demands for high electron mobility transistors.

[0004] According to an embodiment of the present application, a semiconductor device is disclosed, comprising a substrate, a semiconductor channel layer, a semiconductor barrier layer, and a gate electrode. The semiconductor channel layer is disposed on the substrate, and the semiconductor barrier layer is disposed on the semiconductor channel layer, wherein a surface of the semiconductor barrier layer includes at least one recess. The gate electrode is disposed on the semiconductor barrier layer, wherein the gate electrode includes a main portion and at least one vertically extending portion overlapping the recess.

[0005] According to an embodiment of the present application, a semiconductor device is disclosed, comprising a substrate, a semiconductor channel layer, a semiconductor barrier layer, a gate electrode, and an interlayer dielectric layer. The semiconductor channel layer is disposed on the substrate, and the semiconductor barrier layer is disposed on the semiconductor channel layer, wherein the semiconductor barrier layer includes a first portion and a second portion adjacent to each other, and a thickness of the first portion is greater than a thickness of the second portion. The gate electrode is disposed on the semiconductor barrier layer, wherein the gate electrode includes a main portion and at least one vertically extending portion overlapping the second portion. The interlayer dielectric layer is disposed between the main portion and the vertically extending portion. ​

[0006] In order to make the above object, features, and advantages of the present application more comprehensible, preferred embodiments along with attached drawings for the purpose of description are specifically disclosed below. However, the preferred embodiments and drawings below are for reference and description only, and are not intended to limit the present application. BRIEF DESCRIPTION OF DRAWINGS

[0007] Figure 1 is a cross-sectional view of a semiconductor device according to an embodiment of the present application;

[0008] Figure 2 is a top view of a semiconductor device according to an embodiment of the present application;

[0009] Figure 3 is a top view of a semiconductor device according to an embodiment of the present application;

[0010] Figure 4 is a cross-sectional view of a semiconductor device with a gate dielectric layer according to a variant embodiment of the present application;

[0011] Figure 5 is a cross-sectional view of a semiconductor device according to a variant embodiment of the present application;

[0012] Figure 6 is a cross-sectional view of a semiconductor device with multiple vertical extensions according to a variant embodiment of the present application;

[0013] Figure 7 is a cross-sectional view of a semiconductor device with multiple vertical extensions according to a variant embodiment of the present application;

[0014] Figure 8 is a top view of a semiconductor device according to an embodiment of the present application;

[0015] Figure 9 is a cross-sectional view of a semiconductor device with multiple vertical extensions according to a variant embodiment of the present application;

[0016] Figure 10 is a cross-sectional view of a semiconductor device according to a variant embodiment of the present application;

[0017] Figure 11 is a graph showing the electrical behavior of the transconductance (gm) of semiconductor devices according to embodiments and comparative examples of the present application;

[0018] Figure 12 is a graph showing the relationship between the electric field and the position in semiconductor devices according to embodiments and comparative examples of the present application;

[0019] Figure 13 is a graph showing the breakdown voltage (Vbd) of semiconductor devices according to embodiments and comparative examples of the present application;BR ) and specific on-resistance (Ron ON,SP ) of the semiconductor device.

[0020] Explanation of main element symbols

[0021] 100-1 semiconductor device

[0022] 100-2 semiconductor device

[0023] 100-3 semiconductor device

[0024] 100-4 semiconductor device

[0025] 100-5 semiconductor device

[0026] 100-6 semiconductor device

[0027] 100-7 semiconductor device

[0028] 102 substrate

[0029] 104 buffer layer

[0030] 106 semiconductor channel layer

[0031] 106a first portion

[0032] 106b second portion

[0033] 107-1 two-dimensional electron gas

[0034] 107-2 two-dimensional electron gas

[0035] 108 semiconductor barrier layer

[0036] 108a first portion

[0037] 108b second portion

[0038] 109 recess

[0039] 109a first recess

[0040] 109b second recess

[0041] 109c third recess

[0042] 109d fourth recess

[0043] 111a fifth recess

[0044] 111b sixth recess

[0045] 110 gate cap layer

[0046] 120 gate electrode

[0047] 122 body portion

[0048] 124 horizontally extending portion

[0049] 126 vertically extending portion

[0050] 126a first vertically extending portion

[0051] 126b second vertically extending portion

[0052] 126c third vertically extending portion

[0053] 126d fourth vertically extending portion

[0054] 130a fifth vertically extending portion

[0055] 130b sixth vertically extending portion

[0056] 132 drain electrode

[0057] 134 source electrode

[0058] 136 first interlayer dielectric layer

[0059] 140 second interlayer dielectric layer

[0060] 150 gate dielectric layer

[0061] A region

[0062] H overlap height

[0063] H1 overlap height

[0064] H2 overlap height

[0065] Lb length

[0066] Lh length

[0067] Lv length

[0068] Lv1 length

[0069] Lv2 length

[0070] T1 thickness

[0071] T2 thickness DETAILED DESCRIPTION

[0072] Those skilled in the art will appreciate the teachings of the present application more in detail upon considering the detailed description in conjunction with the accompanying drawings. It is to be noted, however, that the figures illustrate only a typical embodiment of the application and therefore, should not be considered to limit the scope of the present application. In the drawings:

[0073] In this specification and the appended claims, certain terminology will be used to refer to certain elements. Those skilled in the art will appreciate that semiconductor manufacturers can refer to the same element by different names. This document does not intend to distinguish between those elements that do not differ in any meaningful way. In the claims and the specification, the words "comprising," "including," and "having" and the like are used to mean "including but not limited to."

[0074] In the specification and the claims, the use of ordinal terms such as "first", "second", etc., to modify a claim element does not imply that the element with such designation must be in any particular order or position. Rather, the use of ordinal terms is intended to identify different claim elements from each other without limiting the scope of the claims.

[0075] In the specification and the claims, the use of the terms "coupled", "coupling", "electrically connected" and the like, unless otherwise specified, includes any direct or indirect electrical connection. For example, if a first element is coupled to a second element, it means that the first element can be directly electrically connected to the second element, or indirectly electrically connected to the second element through other elements or connection means.

[0076] In addition, for the spatially relative terms used herein, such as "under", "below", "lower", "above", "upper", "up", "down", "top", "bottom", and the like, are used for ease of description to describe the relative position of one element or feature to another element(s) or feature(s) as illustrated in the drawings. These spatially relative terms are used to describe the possible positions of semiconductor devices in use and operation, in addition to the orientation shown in the drawings. As the semiconductor device is oriented differently (rotated 90 degrees or other orientations), the spatially relative terms used to describe its orientation should also be interpreted accordingly.

[0077] Although the numerical ranges and parameters setting forth the described aspects of the application are approximations, the numerical values set forth in the specific examples are reported as precisely as possible. Any numerical value, however, can inherently contain certain errors necessarily resulting from the standard deviation found in their respective testing measurements. Furthermore, the term "about" as used herein when used in conjunction with a recitation of a numerical value or range of values can mean within 10%, 5%, 1%, or 0.5% of that value or range of values. Alternatively, the term "about" can mean within an acceptable standard deviation range for one of ordinary skill in the art, when using the numerical value or range of values. All numerical ranges disclosed herein are understood to include all numerical values and ranges within the recited range, when the numerical values and ranges are used in a manner that is clear to one of ordinary skill in the art. Accordingly, unless indicated to the contrary, the numerical parameters set forth in the specification and attached claims are approximations. Any numerical value, however, can inherently contain certain errors necessarily resulting from the standard deviation found in their respective testing measurements. Numerical parameters include all values from the range written, by way of example. Any numerical value, however, can inherently contain certain errors necessarily resulting from the standard deviation found in their respective testing measurements. In this document, the terms "range" or "range of values" means a range of endpoints, when a range of values is expressed as between one endpoint to another endpoint. Unless specifically stated otherwise, and as is apparent from the above teachings, it is appreciated that, throughout the specification, data can be presented in a number of different formats and used to not only quantify one aspect of a particular embodiment but also to quantify an aspect of another embodiment. For example, weight percent, percent by weight, % by weight, %wt, and wt % are synonyms that can be used to describe the same dimensionless value. Alternatively, density, specific gravity, and gravity are synonyms that can be used to describe the same dimensional quantity. As such, these values should not be construed as lacking generality and scope.

[0078] The technical features in the different embodiments described below can be replaced, recombined, and mixed with each other to form other embodiments without departing from the spirit of the present application.

[0079] The present application relates to a semiconductor device including a high electron mobility transistor (HEMT). The HEMT can be used as a power switching transistor for voltage converters. Compared to silicon power transistors, III-V HEMTs have a wide energy band gap and thus have low on-state resistance and low switching loss. In the present application, "group III-V semiconductor" refers to a compound semiconductor including at least one group III element and at least one group V element, wherein the group III element can be boron (B), aluminum (Al), gallium (Ga), or indium (In), and the group V element can be nitrogen (N), phosphorus (P), arsenic (As), or antimony (Sb). Further, "group III-V semiconductor" can include gallium nitride (GaN), indium phosphide (InP), aluminum arsenide (AlAs), gallium arsenide (GaAs), aluminum gallium nitride (AlGaN), indium aluminum gallium nitride (InAlGaN), indium gallium nitride (InGaN), the like, or a combination thereof, but is not limited thereto. In addition, "group III-nitride semiconductor" refers to a compound semiconductor including nitrogen and at least one group III element, such as GaN, aluminum nitride (AlN), indium nitride (InN), AlGaN, InGaN, InAlGaN, the like, or a combination thereof, but is not limited thereto.

[0080] Figure 1 is a cross-sectional schematic view of a semiconductor device according to an embodiment of the present application. Referring to Figure 1 , the semiconductor device 100-1 can include at least a substrate 102, a semiconductor channel layer 106, a semiconductor barrier layer 108, and a gate electrode 120, wherein the semiconductor channel layer 106 is disposed on the substrate 102. The semiconductor barrier layer 108 is disposed on the semiconductor channel layer 106. According to an embodiment of the present application, the surface of the semiconductor barrier layer 108 can include at least one recess 109. The gate electrode 120 is disposed on the semiconductor barrier layer 108, and the gate electrode 120 includes a main body portion 122 and at least one vertically extending portion 126, which can overlap the recess 109. According to another embodiment of the present application, the semiconductor barrier layer 108 can include a first portion 108a and a second portion 108b abutting each other, the thickness T1 of the first portion 108a can be greater than the thickness T2 of the second portion 108b, and the vertically extending portion 126 of the gate electrode 120 can overlap the second portion 108b of the semiconductor barrier layer 108. Further, according to an embodiment of the present application, a buffer layer 104 can be additionally included between the substrate 102 and the semiconductor channel layer 106, which can be used to reduce the leakage current between the substrate 102 and the semiconductor channel layer 106, or to reduce the degree of stress accumulation or lattice mismatch between the substrate 102 and the semiconductor channel layer 106. According to an embodiment of the present application, the semiconductor device 100-1 can additionally include a gate cap layer 110, a first interlayer dielectric layer 136, a second interlayer dielectric layer 140, a drain electrode 132, and a source electrode 134. The gate cap layer 110 can be disposed between the semiconductor barrier layer 108 and the main body portion 122 of the gate electrode 120. The gate electrode 120, the source electrode 134, and the drain electrode 132 can be disposed in the first interlayer dielectric layer 136, and the source electrode 134 and the drain electrode 132 are disposed on two sides of the gate electrode 120, respectively. According to an embodiment of the present application, a two-dimensional electron gas (2-DEG) 107-1, 107-2 can be generated at the interface between the semiconductor channel layer 106 and the semiconductor barrier layer 108, and the carrier concentration of the 2-DEG 107-1 can be higher than that of the 2-DEG 107-2. By disposing the gate cap layer 110, the 2-DEG 107-1, 107-2 can not be generated in the corresponding semiconductor channel layer 106 below the gate cap layer 110, so that part of the 2-DEG is cut off.

[0081] According to an embodiment of the present application, the substrate 102 can be a bulk silicon substrate, a silicon carbide (SiC) substrate, a sapphire substrate, a silicon on insulator (SOI) substrate, or a germanium on insulator (GOI) substrate, but is not limited thereto. The various layers of the stack disposed on the substrate 102 can be formed by any suitable method, such as molecular-beam epitaxy (MBE), metal organic chemical vapor deposition (MOCVD), hydride vapor phase epitaxy (HVPE), atomic layer deposition (ALD), or other suitable methods, to form the buffer layer 104, the semiconductor channel layer 106, the semiconductor barrier layer 108, and the gate cap layer 110 disposed on the substrate 102.

[0082] The buffer layer 104 can include a plurality of sub-semiconductors, and the overall resistance of the buffer layer 104 can be higher than the resistance of other layers on the substrate 102. In particular, the proportion of some elements in the buffer layer 104, such as metal elements, can gradually change from the substrate 102 to the semiconductor channel layer 106. For example, for a case in which the substrate 102 and the semiconductor channel layer 106 are a silicon substrate and a GaN layer, respectively, the buffer layer 104 can be an aluminum gallium nitride (AlxGa1-xN) layer with a gradually changing composition, and the value of x can decrease from 0.9 to 0.15 in a continuous or stepwise manner from the substrate 102 to the semiconductor channel layer 106; or the buffer layer 104 can also be a multi-layer superlattice structure. x Ga (1-x) N), and the value of x decreases from 0.9 to 0.15 in a continuous or stepwise manner from the substrate 102 to the semiconductor channel layer 106; or the buffer layer 104 can also be a multi-layer superlattice structure.

[0083] The semiconductor channel layer 106 can include one or more layers of III-V semiconductor layers, and the III-V semiconductor layers can be GaN, AlGaN, InGaN, or InAlGaN, but are not limited thereto. In addition, the semiconductor channel layer 106 can also be one or more layers of doped III-V semiconductor layers, such as a p-type III-V semiconductor layer. For a p-type III-V semiconductor layer, the dopant can be C, Fe, Mg, or Zn, or is not limited thereto.

[0084] The semiconductor barrier layer 108 can include one or more layers of III-V semiconductor layers, and the composition of the III-V semiconductor layers can be different from the III-V semiconductor layers of the semiconductor channel layer 106. For example, the semiconductor barrier layer 108 can include AlN, Al y Ga(1-y) According to an embodiment, the semiconductor channel layer 106 can be an undoped GaN layer, and the semiconductor barrier layer 108 can be an n-type AlGaN layer. Due to the discontinuous energy gap between the semiconductor channel layer 106 and the semiconductor barrier layer 108, by stacking the semiconductor channel layer 106 and the semiconductor barrier layer 108 on top of each other, electrons can be accumulated at the heterojunction between the semiconductor channel layer 106 and the semiconductor barrier layer 108 due to piezoelectric effect, thus creating a high electron mobility thin layer, i.e., two-dimensional electron gas 107-1, 107-2. In addition, since the thickness Tl of the first portion 108a of the semiconductor barrier layer 108 can be greater than the thickness T2 of the second portion 108b, an unequal piezoelectric effect can be generated, such that the two-dimensional electron gas 107-1 under the first portion 108a has a higher carrier concentration than the two-dimensional electron gas 107-2 under the second portion 108b. For example, the thickness Tl can be between 6 nm and 30 nm, and the thickness T2 can be between 3 nm and 15 nm, but not limited thereto. In addition, when the thickness T2 of the second portion 108b is greater than zero, the bottom surface of the recess 109 can be separated from the underlying semiconductor channel layer 106, such that the semiconductor channel layer 106 is not exposed at the bottom surface of the recess 109. Further, the recess 109 can be disposed between the main body portion 122 of the gate electrode 120 and the drain electrode 132.

[0085] The gate cap layer 110 can adjoin the recess 109, and can be a doped one or more layers of III-V semiconductor layers, and the composition of the gate cap layer 110 can be different from the underlying semiconductor barrier layer 108, for example, a P-type III-V semiconductor layer. For a P-type III-V semiconductor layer, the dopant can be C, Fe, Mg, or Zn, but not limited thereto. According to an embodiment, the gate cap layer 110 can be a P-type GaN layer. For example, the thickness of the gate cap layer 110 can be greater than the thickness Tl of the first portion 108a of the semiconductor barrier layer 108, and the thickness of the gate cap layer 110 can be, for example, between 30 nm and 100 nm, but not limited thereto.

[0086] According to an embodiment of the present disclosure, the main body portion 122 of the gate electrode 120 can be disposed on the first portion 108a of the semiconductor barrier layer 108, and the vertical extension portion 126 of the gate electrode 120 can be disposed on the second portion 108b of the semiconductor barrier layer 108. Thus, the vertical extension portion 126 of the gate electrode 120 can be considered to be disposed corresponding to the location of the recess 109. In addition, the gate electrode 120 can further include a horizontal extension portion 124, which can be used to electrically connect the main body portion 122 to the vertical extension portion 126.

[0087] Specifically, the body portion 122 can be electrically connected to the gate cap layer 110 and not overlap the recess 109. The lower portion of the body portion 122 can be disposed in the first ILD layer 136, and the upper portion of the body portion 122 can be disposed in the second ILD layer 140. The length Lb of the body portion 122 can be 0.5 μm to 4 μm, but is not limited thereto. The horizontal extension portion 124 can be disposed at one side of the body portion 122, extend toward the drain electrode 132, and be disposed along the surface of the first ILD layer 136. The length Lh of the horizontal extension portion 124 can be greater than the length Lb of the body portion 122, for example, 1 μm to 5 μm, but is not limited thereto. The vertical extension portion 126 can be disposed at the bottom surface of the horizontal extension portion 124 and extend toward the recess 109, such that the bottom surface of the vertical extension portion 126 can be lower than the bottom surface of the horizontal extension portion 124. In addition, the vertical extension portion 126 can be disposed in the first ILD layer 136.

[0088] Referring to Figure 1 Referring to

[0089] Still referring to Figure 1The first interlayer dielectric layer 136 of the semiconductor device 100-1 can be disposed on the semiconductor barrier layer 108 and fill the recess 109. In addition, the first interlayer dielectric layer 136 can surround the main body portion 122 and the vertical extension portion 126 of the gate electrode 120 and be disposed between the main body portion 122 and the vertical extension portion 126. According to an embodiment of the present application, a plurality of contact holes can be formed in the first interlayer dielectric layer 136 for receiving the main body portion 122 and the vertical extension portion 126 of the gate electrode 120, the drain electrode 132, and the source electrode 134, respectively. According to an embodiment of the present application, the first interlayer dielectric layer 136 can serve as a passivation layer to reduce defects on the surface of the semiconductor barrier layer 108 and increase the carrier concentration of the two-dimensional electron gas 107-1, 107-2.

[0090] A second interlayer dielectric layer 140 can be disposed on the first interlayer dielectric layer 136 such that the upper portion of the main body portion 122 and the horizontal extension portion 124 are embedded in the second interlayer dielectric layer 140.

[0091] According to an embodiment, the source electrode 134 and the drain electrode 132 are electrically connected to the semiconductor barrier layer 108 and the semiconductor channel layer 106. According to an embodiment of the present application, when the semiconductor device 100-1 is operated, the source electrode 134 can be electrically connected to an external voltage of a lower voltage (e.g., 0 V), and the drain electrode 132 can be electrically connected to an external voltage of a higher voltage (e.g., 10 V to 200 V), but is not limited thereto. By applying appropriate bias to the source electrode 134 and the drain electrode 132, current can flow into or out of the semiconductor device 100-1. In addition, by applying appropriate bias to the gate electrode 120, the degree of conduction of the channel region under the main body portion 122 and the vertical extension portion 126 can be controlled, and current can flow between the source electrode 134 and the drain electrode 132. The gate electrode 120, the source electrode 134, and the drain electrode 132 can be single-layer or multi-layer structures and can include Al, Cu, W, Au, Pt, Ti, polysilicon, or other low-resistance semiconductors, metals, or alloys, but are not limited thereto. In addition, the source electrode 134 and the drain electrode 132 can form ohmic contacts with the semiconductor channel layer 106 thereunder.

[0092] Figure 2 and Figure 3 is a top view of a semiconductor device according to an embodiment of the present application. Referring to Figure 2 The recess 109 in the semiconductor device 100-1 can be disposed on one side of the gate cap layer 110 and have a rectangular profile. The long axis direction of the recess 109 can be parallel to the long axis direction of the gate cap layer 110, but is not limited thereto. Referring to Figure 3For the semiconductor device with multiple recesses 109, the top of each recess 109 can be correspondingly provided with a vertically extending portion, so that the bottom surface of each vertically extending portion can overlap each recess 109. According to an embodiment of the present application, the recess 109 is not limited to be rectangular, but can be other geometric shapes. For example, when the top view profile of the gate cap layer 110 presents an arc shape or a ring shape, then the top view profile of the recess 109 provided along the side of the gate cap layer 110 can present an arc shape or a ring shape, but is not limited thereto.

[0093] In addition to the above embodiments, the present application also includes other variant embodiments of the semiconductor device. For the sake of simplicity, the following description mainly focuses on the differences between the embodiments, and the same parts are not repeated. In addition, the same elements in the embodiments of the present application are denoted by the same reference numerals, so as to facilitate mutual comparison between the embodiments.

[0094] Figure 4 is a cross-sectional schematic view of a semiconductor device with a gate dielectric layer according to a variant embodiment of the present application. As shown in Figure 4 , the structure of the semiconductor device 100-2 is similar to that of the semiconductor device 100-1 shown in the Figure 1 embodiment, and the main difference is that the semiconductor device 100-2 additionally includes a gate dielectric layer 150 provided below the main body portion 122 of the gate electrode 120. According to an embodiment of the present application, the gate dielectric layer 150 can be provided between the gate cap layer 110 and the semiconductor barrier layer 108, and its composition can be, for example, aluminum nitride. According to another embodiment of the present application, the gate dielectric layer 150 can be provided between the main body portion 122 of the gate electrode 120 and the gate cap layer 110, and its composition can be, for example, oxide or nitride.

[0095] Figure 5 is a cross-sectional schematic view of a semiconductor device according to a variant embodiment of the present application. As shown in Figure 5 , the structure of the semiconductor device 100-3 is similar to that of the semiconductor device 100-1 shown in the Figure 1 embodiment, and the main difference is that the semiconductor device 100-3 does not have a gate cap layer provided between the main body portion 122 of the gate electrode 120 and the semiconductor barrier layer 108, so that the main body portion 122 can directly contact the semiconductor barrier layer 108.

[0096] Figure 6 is a cross-sectional schematic view of a semiconductor device with multiple vertically extending portions according to a variant embodiment of the present application. As shown in Figure 6As shown, the structure of the semiconductor device 100-4 is similar to that of the semiconductor device 100-1 Figure 1 The structure of the semiconductor device 100-1 shown in the embodiment, the main difference is that the gate electrode 120 of the semiconductor device 100-4 includes a plurality of vertically extending portions, such as the first vertically extending portion 126a and the second vertically extending portion 126b, and the semiconductor device 100-4 includes a plurality of grooves, such as the first groove 109a and the second groove 109b. The long axis direction (the direction of the vertical section) of each groove can be parallel to each other.

[0097] Referring to Figure 6 In the enlarged view of the region A, the bottom surface length Lv1 of the first vertically extending portion 126a and the bottom surface length Lv2 of the second vertically extending portion 126b can be respectively smaller than the bottom surface of the first groove 109a and the bottom surface of the second groove 109b. Therefore, the first vertically extending portion 126a can completely overlap the bottom surface of the first groove 109a, and the bottom surface of the second vertically extending portion 126b can completely overlap the bottom surface of the second groove 109b. The bottom surface of the first vertically extending portion 126a can be located within the first groove 109a, and the bottom surface of the second vertically extending portion 126b can be located within the second groove 109b, each having an overlap height H1, H2. The overlap heights H1, H2 can be smaller than the thickness T1 of the first portion 108a of the semiconductor barrier layer 108.

[0098] Figure 7 is a cross-sectional view of a semiconductor device with a plurality of vertically extending portions according to a variant embodiment of the present application. As shown, Figure 7 As shown, the structure of the semiconductor device 100-5 is similar to that of the semiconductor device 100-1 Figure 6 The structure of the semiconductor device 100-4 shown in the embodiment, the main difference is that the gate electrode 120 of the semiconductor device 100-5 includes more than two vertically extending portions, such as the first vertically extending portion 126a, the second vertically extending portion 126b, the third vertically extending portion 126c, and the fourth vertically extending portion 126d; and the semiconductor device 100-5 includes more than two grooves, such as the first groove 109a, the second groove 109b, the third groove 109c, and the fourth groove 109d. According to the embodiment of the present application, the first groove 109a, the second groove 109b, the third groove 109c, and the fourth groove 109d can be separated from each other and parallel to each other, such that the top view thereof can exhibit the arrangement shown in Figure 8

[0099] Figure 8 is a top view of a semiconductor device according to an embodiment of the present application. Referring to Figure 8 ​The first groove 109a, the second groove 109b, the third groove 109c, and the fourth groove 109d in the semiconductor device 100-5 can be disposed on one side of the gate cap layer 110 and have a rectangular outline. The major axis direction of each groove 109a-109d can be parallel to the major axis direction of the gate cap layer 110, but is not limited thereto. According to an embodiment of the present invention, each groove 109a-109d is not limited to being rectangular; it can also be other geometric shapes. For example, when the top view outline of the gate cap layer 110 is arc-shaped or annular, the top view outline of each groove 109a-109d disposed along the side of the gate cap layer 110 can also be arc-shaped or annular, but is not limited thereto.

[0100] Figure 9 This is a schematic cross-sectional view of a semiconductor device having multiple vertical extensions, according to a variant embodiment of the present invention. Figure 9 As shown, the structure of semiconductor device 100-6 is similar. Figure 7 The main difference in the structure of the semiconductor device 100-5 shown in the embodiment is that the vertical extension of the gate electrode 120 of the semiconductor device 100-6 is not only located on the side near the drain electrode 132, but also on the side near the source electrode 134. For example, the gate electrode 120 of the semiconductor device 100-6 may further include a fifth vertical extension 130a and a sixth vertical extension 130b, and may also include a fifth recess 111a and a sixth recess 111b.

[0101] Figure 10 This is a schematic cross-sectional view of a semiconductor device according to a variant embodiment of the present invention. Figure 10 As shown, the structure of semiconductor device 100-7 is similar. Figure 1 The main difference in the structure of the semiconductor device 100-1 shown in the embodiment is that the recess 109 of the semiconductor device 100-7 penetrates the semiconductor barrier layer 108, and the bottom surface of the recess 109 exposes the semiconductor channel layer 106, or even the bottom surface of the recess 109 can be located in the semiconductor channel layer 106, so that the semiconductor channel layer 106 can have a thicker first portion 106a and a thinner second portion 106b. Furthermore, the bottom surface of the vertical extension 126 can extend into the recess 109, but does not directly contact the semiconductor channel layer 106. According to an embodiment of the present invention, the number, length, width, depth, and orientation of the recesses 109 in the semiconductor device 100-7 can be adjusted according to actual needs, so that its top view can present a similar appearance. Figure 2 , Figure 3 ,and Figure 8 The arrangement shown is not limited to this.

[0102] According to the embodiments of the present application, the depth of each recess 109 of the semiconductor devices 100-1, 100-2, 100-3, 100-4, 100-5, 100-6 can also be adjusted accordingly, so that all or part of the recesses 109 penetrate the semiconductor barrier layer 108, causing the bottom surface of the recesses 109 to expose the semiconductor channel layer 106, or even the bottom surface of the recesses 109 can be located in the semiconductor channel layer 106, so that the semiconductor channel layer 106 can have a first portion with a relatively thick thickness and a second portion with a relatively thin thickness. In addition, the bottom surface of the vertical extension 126 can extend into each recess 109, but does not directly contact the semiconductor channel layer 106.

[0103] The following is a further description of the electrical performance of the semiconductor devices according to the embodiments of the present application. According to the semiconductor devices 100-1, 100-2, 100-3, 100-4, 100-5, 100-6 disclosed in the above embodiments, the semiconductor barrier layer 108 has a first portion 108a with a relatively thick thickness and at least one second portion 108b with a relatively thin thickness, and the vertical extension 126, 126a-126d, 130a-130b of the gate electrode 120 is arranged directly above the second portion 108b; and according to the semiconductor device 100-7 disclosed in the above embodiments, the semiconductor barrier layer 108 is penetrated by the recess 109. The vertical extension 126, 126a-126d, 130a-130b can be regarded as a field plate for controlling or adjusting the electric field distribution in the semiconductor barrier layer 108 and / or the semiconductor channel layer 106. By arranging at least one recess 109 and at least one vertical extension 126, in addition to reducing the on-resistance (Ron) of the semiconductor devices 100-1, 100-2, 100-3, 100-4, 100-5, 100-6, 100-7, the transfer conductance (gm) and the breakdown voltage (V ON ) can also be improved, thereby improving the electrical performance of the semiconductor devices 100-1, 100-2, 100-3, 100-4, 100-5, 100-6, 100-7.

[0104] Figure 11 The transfer conductance (gm) of the semiconductor devices according to the embodiments and the comparative examples of the present application is shown in the following table. Comparative example 1 corresponds to a conventional semiconductor device, in which the semiconductor barrier layer does not include a recess, and the gate electrode does not include a horizontal extension and a vertical extension; comparative example 2 corresponds to a conventional semiconductor device, in which the semiconductor barrier layer includes a recess, but the gate electrode does not include a horizontal extension and a vertical extension; embodiment 1 corresponds to the semiconductor device 100-1. Figure 1 Figure 11 When the bias voltage (V DS = 10V) between the source electrode and the drain electrode is fixed, and the gate voltage (V GS ) is gradually increased, the transfer conductance (gm) of the semiconductor devices according to the embodiments and the comparative examples of the present application is shown in the following table.​GS ) is greater than that of Comparative Example 2.

[0105] Figure 12 is a diagram of the relationship between the electric field and the position in the semiconductor device of the embodiments and the comparative examples. Among them, the semiconductor device structure of Comparative Example 1, Comparative Example 2, and Example 1 is similar to that described in Figure 11 ; Example 2 corresponds to the semiconductor device 100-4 of Figure 6 ; and Example 3 corresponds to the semiconductor device 100-5 of Figure 7 . Among them, Figure 12 The "position" on the horizontal axis refers to the horizontal position. The position where the value is 0 generally corresponds to the boundary between the gate cover layer and the recess of the semiconductor device. When the value of the position is greater, it means that it is closer to the drain electrode. Referring to the left graph of Figure 12 , for the semiconductor devices of Comparative Example 1 and Comparative Example 2, the electric field distribution is unimodal and the peak value is between 7E5 and 9E5 V / cm, and the electric field peak is close to the gate. The electric field distribution is less uniform. In contrast, for the semiconductor device 100-1 of Example 1, the electric field distribution is bimodal and the peak value is less than 5E5 V / cm. The electric field can be more uniformly distributed between the gate and the drain. Therefore, the semiconductor device of Example 1 can effectively change the electric field distribution and reduce the electric field peak, so that the semiconductor device is less likely to produce impact ionization. Referring to the right graph of Figure 12 , for the semiconductor device 100-4 of Example 2, the electric field distribution is 3-peak and the peak value is less than 5.5E5 V / cm. In addition, for the semiconductor device 100-5 of Example 3, the electric field distribution is 5-peak and the peak value is less than 3.5E5 V / cm. Therefore, compared with Example 1, the semiconductor device 100-5 of Example 3 can further change the electric field distribution and reduce the electric field peak, so that the semiconductor device is less likely to produce impact ionization.

[0106] Figure 13 is the breakdown voltage (V BR ) and the specific on-resistance (R ON,SP ) of the semiconductor devices of the embodiments and the comparative examples. Among them, the semiconductor device structure of Comparative Example 1, Comparative Example 2, Example 1, and Example 2 is similar to that described in Figure 11 and Figure 12 . For Comparative Example 3, Comparative Example 3 corresponds to the existing semiconductor device, the semiconductor barrier layer of which includes a recess and the gate electrode includes a horizontal extension, but the gate electrode does not include a vertical extension; for Example 3, Example 3 corresponds to the semiconductor device 100-5 of Figure 7 . Referring to Figure 13, the breakdown voltage of each of Examples 1 to 3 is greater than the breakdown voltage of each of Comparative Examples 1 to 3, and Example 3 can withstand the highest breakdown voltage (about 165 V). With respect to the specific on-resistance, the specific on-resistance of each of Examples 1 to 3 is about 20 mΩ˙cm 2 ~ 25 mΩ˙cm 2 This specific on-resistance is greater than the specific on-resistance of Comparative Example 1, but is less than the specific on-resistance of each of Comparative Examples 2 and 3.

[0107] The above merely provides preferred embodiments of the present application, and any equivalent changes and modifications made according to the claims of the present application shall fall within the scope of the present application.

Claims

1. A semiconductor device, characterized in that, include: Base; A semiconductor channel layer is disposed on the substrate; A semiconductor barrier layer is disposed on the semiconductor channel layer, wherein the surface of the semiconductor barrier layer includes at least one groove; A first interlayer dielectric layer is disposed on the semiconductor barrier layer, and the first interlayer dielectric layer has a single-layer structure. A gate electrode is disposed on the first interlayer dielectric layer, wherein the gate electrode includes a main body portion extending to the first interlayer dielectric layer and at least one vertical extension portion, the at least one vertical extension portion overlaps the at least one groove, and a portion of the first interlayer dielectric layer is located between the bottom surface of the at least one vertical extension portion and the at least one groove in a direction perpendicular to the top surface of the semiconductor barrier layer. A gate capping layer is disposed between the semiconductor barrier layer and the main body of the gate electrode; as well as The second interlayer dielectric layer is disposed on the first interlayer dielectric layer and directly covers the gate electrode and the first interlayer dielectric layer. The top surface of the first interlayer dielectric layer between the main body and the at least one vertical extension is flush with the other top surface of the second interlayer dielectric layer, which is in direct contact with the first interlayer dielectric layer. The at least one groove includes a plurality of grooves that are separated from each other, a portion of which is disposed on one side of the main body of the gate electrode, and other portions of which are disposed on the other side of the main body of the gate electrode.

2. The semiconductor device of claim 1, wherein the semiconductor device further includes a drain electrode, a portion of the plurality of recesses being disposed between the body portion of the gate electrode and the drain electrode.

3. The semiconductor device of claim 1, wherein the gate cap layer adjoins the at least one recess.

4. The semiconductor device of claim 1, wherein the main body portion of the gate electrode does not overlap the at least one groove.

5. The semiconductor device of claim 1, wherein the bottom surface of the at least one groove is separated from the semiconductor channel layer.

6. The semiconductor device of claim 1, wherein the gate electrode further includes a horizontal extension that electrically connects the body portion to the at least one vertical extension.

7. The semiconductor device of claim 6, wherein the bottom surface of the at least one vertical extension is lower than the bottom surface of the horizontal extension.

8. The semiconductor device of claim 1, wherein the bottom surface of the at least one vertical extension completely overlaps the bottom surface of the at least one groove.

9. The semiconductor device of claim 1, wherein the bottom surface of the at least one vertical extension is lower than the bottom surface of the body portion of the gate electrode.

10. The semiconductor device of claim 1, wherein the bottom surface of the at least one vertical extension is located within the at least one recess.

11. The semiconductor device of claim 1, wherein the at least one vertical extension includes a first vertical extension and a second vertical extension separated from each other, the plurality of grooves includes a first groove and a second groove separated from each other, the bottom surface of the first vertical extension completely overlaps the bottom surface of the first groove, and the bottom surface of the second vertical extension completely overlaps the bottom surface of the second groove.

12. The semiconductor device of claim 11, wherein the bottom surface of the first vertical extension is located within the first groove, and the bottom surface of the second vertical extension is located within the second groove.

13. The semiconductor device of claim 11, wherein the long axis direction of the first groove is parallel to the long axis direction of the second groove.

14. The semiconductor device according to claim 1, wherein a gate dielectric layer is disposed between the main body portion of the gate electrode and the semiconductor barrier layer.

15. The semiconductor device of claim 1, wherein the bottom surface of the at least one groove is located in the semiconductor channel layer.

16. A semiconductor device, characterized in that, include: Base; A semiconductor channel layer is disposed on the substrate; A semiconductor barrier layer is disposed on the semiconductor channel layer, wherein the surface of the semiconductor barrier layer includes at least one groove, and the bottom surface of the at least one groove is located in the semiconductor channel layer; A gate electrode is disposed on the semiconductor barrier layer, wherein the gate electrode includes a main body and at least one vertical extension, the at least one vertical extension overlapping the at least one groove; and The drain electrode is disposed on the semiconductor barrier layer. The at least one vertical extension extends into the at least one groove and is located between the main body and the drain electrode.

17. The semiconductor device of claim 16, further comprising an interlayer dielectric layer directly contacting the semiconductor barrier layer and disposed between the main body portion and the at least one vertical extension portion, wherein the interlayer dielectric layer is disposed between the at least one groove of the semiconductor barrier layer and the at least one vertical extension portion of the gate electrode.

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