Semiconductor device

Abstract

A semiconductor device includes a substrate and a first transistor disposed on the substrate. The first transistor includes a plurality of first semiconductor pieces and two first source / drain structures. The plurality of first semiconductor pieces are disposed in a vertical direction and separated from each other. Each first semiconductor piece includes two first doped layers and a second doped layer disposed between the two first doped layers in the vertical direction. The second doped layer has a conductive type complementary to that of each first doped layer. The two first source / drain structures are disposed on two opposite sides of each first semiconductor piece in a horizontal direction, and the two first source / drain structures are connected to the plurality of first semiconductor pieces.

Description

TECHNICAL FIELD

[0001] The present application relates to a semiconductor device, and more particularly to a semiconductor device having a semiconductor sheet. BACKGROUND

[0002] With the continuous development of semiconductor element technology, it is difficult to continue to shrink using the conventional planar metal-oxide-semiconductor (MOS) transistor fabrication process, and therefore, the industry has proposed a solution approach of replacing planar transistor elements with three-dimensional or non-planar multi-gate transistor elements. For example, dual-gate Fin Field effect transistor (FinFET) elements, tri-gate FinFET elements, and omega FinFET elements have been proposed. In addition, in recent years, gate-all-around (GAA) transistor elements using nanowires as channels have been developed as a solution to continue to improve element integration and element performance. However, under the design concept of GAA, how to further improve the element characteristics (such as electrical performance) through fabrication processes or / and structural design is still the direction of continuous efforts for those skilled in the art. SUMMARY

[0003] The present application provides a semiconductor device, a second doped layer of a different conductivity type is sandwiched between two first doped layers to form a semiconductor sheet, thereby achieving the effect of improving the electrical performance of the semiconductor device.

[0004] An embodiment of the present application provides a semiconductor device, which includes a substrate and a first transistor disposed on the substrate. The first transistor includes a plurality of first semiconductor sheets and two first source / drain structures. The plurality of first semiconductor sheets are disposed in a vertical direction and separated from each other. Each first semiconductor sheet includes two first doped layers and a second doped layer disposed between the two first doped layers in the vertical direction. The conductivity type of the second doped layer is complementary to the conductivity type of each first doped layer. The two first source / drain structures are respectively disposed on two opposite sides of each first semiconductor sheet in a horizontal direction, and the two first source / drain structures are connected to the plurality of first semiconductor sheets. BRIEF DESCRIPTION OF DRAWINGS

[0005] Figure 1 FIG. 1 is a schematic diagram of a semiconductor device according to a first embodiment of the present application;

[0006] Figure 2 schematic diagram of a first semiconductor chip according to a first embodiment of the present application;

[0007] Figure 3 schematic diagram of a second semiconductor chip according to a first embodiment of the present application;

[0008] Figure 4 schematic diagram of a first semiconductor chip or a second semiconductor chip according to a first embodiment of the present application in an operating state;

[0009] Figure 5 schematic diagram of a semiconductor chip according to another embodiment of the present application in an operating state;

[0010] Figure 6 schematic diagram of a semiconductor chip according to yet another embodiment of the present application in an operating state;

[0011] Figures 7 to 15 schematic diagram of a manufacturing method of a semiconductor device according to a first embodiment of the present application, wherein

[0012] Figure 8 schematic diagram of a manufacturing method of a semiconductor device according to a first embodiment of the present application, wherein Figure 7 schematic diagram of a subsequent state;

[0013] Figure 9 schematic diagram of a subsequent state; Figure 8 schematic diagram of a subsequent state;

[0014] Figure 10 schematic diagram of a subsequent state; Figure 9 schematic diagram of a subsequent state;

[0015] Figure 11 schematic diagram of a subsequent state; Figure 10 schematic diagram of a subsequent state;

[0016] Figure 12 schematic diagram of a subsequent state; Figure 11 schematic diagram of a subsequent state;

[0017] Figure 13 schematic diagram of a subsequent state; Figure 12 schematic diagram of a subsequent state;

[0018] Figure 14 schematic diagram of a subsequent state; Figure 13 schematic diagram of a subsequent state;

[0019] Figure 15 schematic diagram of a subsequent state; Figure 14 schematic diagram of a subsequent state;

[0020] Figure 16 schematic diagram of a semiconductor device according to a second embodiment of the present application;

[0021] Figures 17 to 22 schematic diagram of a manufacturing method of a semiconductor device according to a second embodiment of the present application, wherein

[0022] Figure 18 for Figure 17 A diagram illustrating the subsequent situation;

[0023] Figure 19 for Figure 18 A diagram illustrating the subsequent situation;

[0024] Figure 20 for Figure 19 A diagram illustrating the subsequent situation;

[0025] Figure 21 for Figure 20 A diagram illustrating the subsequent situation;

[0026] Figure 22 for Figure 21 A diagram illustrating the subsequent situation.

[0027] Explanation of main component symbols

[0028] 10 base

[0029] 12 Sacrificial Materials

[0030] 14 First semiconductor stacked structure

[0031] 14A First Doped Layer

[0032] 14B second doped layer

[0033] 14P First Semiconductor Wafer

[0034] 16 Second semiconductor stacked structure

[0035] 16A Third Doped Layer

[0036] 16B fourth doped layer

[0037] 16P Second Semiconductor Wafer

[0038] 18. Isolation Structure

[0039] 20. Dummy gate structure

[0040] 22 Dielectric layers

[0041] 24 Dummy gate material

[0042] 26 Gate capping layer

[0043] 28. Spacer wall

[0044] 32. Spacer wall

[0045] 34 First epitaxial material

[0046] 34P First Source / Drain Structure

[0047] 42 dielectric layer

[0048] 44 second epitaxial material

[0049] 44P second source / drain structure

[0050] 52 etch stop layer

[0051] 54 dielectric layer

[0052] 56 gate dielectric layer

[0053] 58 gate material layer

[0054] 58A first gate material layer

[0055] 58B second gate material layer

[0056] 82 first patterned mask layer

[0057] 84 second patterned mask layer

[0058] 91 patterning fabrication process

[0059] 92 trenching fabrication process

[0060] 101 semiconductor device

[0061] 102 semiconductor device

[0062] D1 first direction

[0063] D2 second direction

[0064] D3 third direction

[0065] DR1 first depletion region

[0066] DR2 second depletion region

[0067] FS stack structure

[0068] FS1 first stack structure

[0069] FS2 second stack structure

[0070] GS gate structure

[0071] GS1 first gate structure

[0072] GS2 second gate structure

[0073] OP opening

[0074] S1 first portion

[0075] S2 second portion

[0076] T1 first transistor

[0077] T2 second transistor

[0078] TK1 thickness

[0079] TK2 thickness

[0080] TK3 thickness

[0081] TK4 thickness

[0082] TK5 thickness

[0083] TK6 thickness

[0084] TR trench DETAILED DESCRIPTION

[0085] The following detailed description of the application discloses sufficient information to enable one of ordinary skill in the art to practice the application. The embodiments described below are exemplary and not limiting. It is apparent to a person of ordinary skill in the art that various changes and modifications can be made thereto without departing from the spirit and scope of the application.

[0086] Before further description of the embodiments, certain language used in the following description will be explained.

[0087] The terms "on," "over," and "above" are to be interpreted in the broadest context to mean not only "directly on" something but also to include the meaning of being on something with other intervening features or layers therebetween, and "over" or "above" something not only means "over" or "above" something but also can include the meaning of being "over" or "above" something without other intervening features or layers therebetween (i.e., directly on something).

[0088] The use of ordinal terms such as "first," "second," etc., in the specification and claims to modify a claim element does not imply and should not be construed as implying, any order or sequence among or between such claim elements and does not imply and should not be construed as implying a specific sequence or order of manufacture or use of such claim elements. The use of the ordinal terms is merely intended to distinguish one claim element from another.

[0089] The term "etching" is generally used herein to describe a fabrication process for patterning material such that at least a portion of the material is left after etching. When a material is "etched," at least a portion of the material is retained after etching. Conversely, when a material is "removed," essentially all of the material can be removed during the process. However, in some embodiments, "removal" can be considered a broad term that includes etching.

[0090] The terms “forming” or “setting” are used below to describe the behavior of applying a layer of material to a substrate. These terms are intended to describe any feasible layer forming technique, including but not limited to thermal growth, sputtering, evaporation, chemical vapor deposition, epitaxial growth, electroplating, etc.

[0091] Please see Figures 1 to 3 . Figure 1 The diagram shown is a schematic representation of a semiconductor device according to a first embodiment of the present invention. Figure 2 The diagram shown is a schematic representation of the first semiconductor chip in this embodiment. Figure 3 The diagram shown is a schematic representation of the second semiconductor wafer in this embodiment. Figures 1 to 3 As shown, the semiconductor device 101 includes a substrate 10 and a first transistor T1 disposed on the substrate 10. The first transistor T1 includes a plurality of first semiconductor sheets 14P and two first source / drain structures 34P. The plurality of first semiconductor sheets 14P are arranged in a vertical direction (e.g., Figure 1 The first semiconductor wafers 14P are stacked and separated from each other on the first direction D1. Each first semiconductor wafer 14P includes two first doped layers 14A and a second doped layer 14B disposed on the first direction D1 between the two first doped layers 14A. The conductivity type of the second doped layer 14B is complementary to the conductivity type of each first doped layer 14A. Two first source / drain structures 34P are respectively disposed on each first semiconductor wafer 14P in a horizontal direction (e.g., ...). Figure 1 The two opposite sides of the second direction D2 shown, and the two first source / drain structures 34P are connected to a plurality of first semiconductor chips 14P.

[0092] In some embodiments, the first direction D1 described above can be considered as the thickness direction of the substrate 10, and the substrate 10 may have an upper surface and a lower surface opposite to each other in the first direction D1, and the first transistor T1 may be disposed on one side of the upper surface of the substrate 10, but is not limited thereto. Furthermore, a horizontal direction that is substantially orthogonal to the first direction D1 (e.g., Figure 1The second direction D2 and the third direction D3 shown in FIG. 1 can be substantially parallel to the upper surface or / and the lower surface of the substrate 10, but are not limited thereto. In addition, in the context that a position or / and a component which is relatively higher in the first direction D1 is farther from the substrate 10 in the first direction D1 than a position or / and a component which is relatively lower in the first direction D1, a lower portion or a bottom portion of a component can be closer to the substrate 10 in the first direction D1 than an upper portion or a top portion of the component, a component above another component can be considered to be relatively farther from the substrate 10 in the first direction D1, and a component below another component can be considered to be relatively closer to the substrate 10 in the first direction D1.

[0093] At least a portion of each first semiconductor sheet 14P can be considered as a channel region in the first transistor T1, and each first source / drain structure 34P can be directly in contact with two first doped layers 14A and a second doped layer 14B of each first semiconductor sheet 14P to connect to each other. In some embodiments, the thickness of each first semiconductor sheet 14P can be between 5 nanometers and 100 nanometers, so each first semiconductor sheet 14P can be considered as a nanosheet, and the first transistor T1 can be considered as a nanosheet transistor, but are not limited thereto. Each first semiconductor sheet 14P can be composed of two first doped layers 14A and a second doped layer 14B sandwiched between the two first doped layers 14A in the first direction D1. In each first semiconductor sheet 14P, the second doped layer 14B can be directly in contact with the two first doped layers 14A to connect to each other in the first direction D1, and the conduction type of the second doped layer 14B can be complementary to the conduction type of the first doped layer 14A.

[0094] For example, when the first transistor T1 is an n-type transistor, the first doped layer 14A can be an n-type doped semiconductor layer having an n-type conduction type, and the second doped layer 14B can be a p-type doped semiconductor layer having a p-type conduction type. Conversely, when the first transistor T1 is a p-type transistor, the first doped layer 14A can be a p-type doped semiconductor layer having a p-type conduction type, and the second doped layer 14B can be an n-type doped semiconductor layer having an n-type conduction type. The p-type doped semiconductor layer described above can include a p-type impurity such as boron or other suitable elements having a p-type conduction type characteristic, and the n-type doped semiconductor layer described above can include an n-type impurity such as phosphorus, arsenic or other suitable elements having a p-type conduction type characteristic. In some embodiments, the thickness of each second doped layer 14B (e.g. the thickness TK2 shown in FIG. 1) can be less than or equal to the thickness of each first doped layer 14A (e.g. the thickness TK1 shown in FIG. 1). Figure 2 For example, when the first transistor T1 is an n-type transistor, the first doped layer 14A can be an n-type doped semiconductor layer having an n-type conduction type, and the second doped layer 14B can be a p-type doped semiconductor layer having a p-type conduction type. Conversely, when the first transistor T1 is a p-type transistor, the first doped layer 14A can be a p-type doped semiconductor layer having a p-type conduction type, and the second doped layer 14B can be an n-type doped semiconductor layer having an n-type conduction type. The p-type doped semiconductor layer described above can include a p-type impurity such as boron or other suitable elements having a p-type conduction type characteristic, and the n-type doped semiconductor layer described above can include an n-type impurity such as phosphorus, arsenic or other suitable elements having a p-type conduction type characteristic. In some embodiments, the thickness of each second doped layer 14B (e.g. the thickness TK2 shown in FIG. 1) can be less than or equal to the thickness of each first doped layer 14A (e.g. the thickness TK1 shown in FIG. 1). Figure 2The thicknesses TK1 and TK3 of the first doped layer 14A can be substantially equal to each other, but are not limited thereto. For example, in each first semiconductor sheet 14P, the thickness TK2 of the second doped layer 14B can be between 2.5 nm and 5 nm, the thickness TK1 of the first doped layer 14A below the second doped layer 14B and the thickness TK3 of the first doped layer 14A above the second doped layer 14B can each be between 5 nm and 10 nm, and the thickness TK1 of the first doped layer 14A below the second doped layer 14B can be substantially equal to the thickness TK3 of the first doped layer 14A above the second doped layer 14B, but are not limited thereto. In some embodiments, the thicknesses of the doped layers described above can also be considered as the lengths of the doped layers in the first direction D1. In addition, the impurity concentration of each second doped layer 14B can be lower than the impurity concentration of each first doped layer 14A. For example, the impurity concentration of each first doped layer 14A can be between 1E+19 atoms / cm 3 and 1E+20 atom / cm 3 , and the impurity concentration of each second doped layer 14B can be between 1E+17 atoms / cm 3 and 1E+18 atom / cm 3 , but are not limited thereto.

[0095] In some embodiments, the conductivity type of each first source / drain structure 34P can be the same as the conductivity type of each first doped layer 14A, such that each first doped layer 14A and the two first source / drain structures 34P directly connected to this first doped layer 14A can form a junctionless structure in the first transistor T1, and the first transistor T1 can be considered as a junctionless transistor, but are not limited thereto. In addition, in some embodiments, each first source / drain structure 34P can include impurities, the impurities in each first source / drain structure 34P can have the same conductivity type as the impurities in each first doped layer 14A, and the impurity concentration of each first source / drain structure 34P can be substantially equal to the impurity concentration of each first doped layer 14A within a tolerance of ±10%, but are not limited thereto. In other words, the impurity concentration of each first source / drain structure 34P is preferably equal to the impurity concentration of each first doped layer 14A, but considering the process variation, the impurity concentration of each first source / drain structure 34P can be between 90% of the impurity concentration of each first doped layer 14A and 110% of the impurity concentration of each first doped layer 14A, and within this range of impurity concentration, the difference in impurity concentration between the first source / drain structure 34P and the first doped layer 14A can still reduce the negative impact on the operation of the first transistor T1, but are not limited thereto.

[0096] In some embodiments, the semiconductor device 101 can further include a second transistor T2 disposed on the substrate 10, and the second transistor T2 can include a plurality of second semiconductor pieces 16P and two second source / drain structures 44P. The plurality of second semiconductor pieces 16P can be disposed in the first direction D1 and separated from each other, and each second semiconductor piece 16P can include two third doped layers 16A and a fourth doped layer 16B disposed between the two third doped layers 16A in the first direction D1. The two second source / drain structures 44P can be disposed on two opposite sides of each second semiconductor piece 16P in the second direction D2, and the two second source / drain structures 44P can be connected with the plurality of second semiconductor pieces 16P. In some embodiments, the fourth doped layer 16B can have a conductive type complementary to that of each third doped layer 16A, and the fourth doped layer 16B can have the same conductive type as the first doped layer 14A, but the disclosure is not limited thereto. For example, when the first transistor T1 is an n-type transistor, the second transistor T2 can be a p-type transistor, the third doped layer 16A can be a p-type doped semiconductor layer having a p-type conductive type, and the fourth doped layer 16B can be an n-type doped semiconductor layer having an n-type conductive type. Conversely, when the first transistor T1 is a p-type transistor, the second transistor T2 can be an n-type transistor, the third doped layer 16A can be an n-type doped semiconductor layer having an n-type conductive type, and the fourth doped layer 16B can be a p-type doped semiconductor layer having a p-type conductive type, but the disclosure is not limited thereto.

[0097] At least a portion of each second semiconductor piece 16P can be regarded as a channel region in the second transistor T2, and each second source / drain structure 44P can be directly in contact with the two third doped layers 16A and the fourth doped layer 16B in each second semiconductor piece 16P to be connected with each other. In some embodiments, the thickness of each second semiconductor piece 16P can be between 5 nanometers and 100 nanometers, but the disclosure is not limited thereto. Each second semiconductor piece 16P can be composed of the two third doped layers 16A and the fourth doped layer 16B sandwiched between the two third doped layers 16A in the first direction D1. In each second semiconductor piece 16P, the fourth doped layer 16B can be directly in contact with the two third doped layers 16A in the first direction D1 to be connected with each other, and the thickness (e.g., the thickness TK5 shown in FIG. 5) of each fourth doped layer 16B can be less than or equal to the thickness (e.g., the thickness TK4 shown in FIG. 4) of each third doped layer 16A, but the disclosure is not limited thereto. Figure 3 In some embodiments, the thickness of each fourth doped layer 16B can be between 5 nanometers and 100 nanometers, but the disclosure is not limited thereto. In some embodiments, the thickness of each fourth doped layer 16B can be less than or equal to the thickness of each third doped layer 16A, but the disclosure is not limited thereto. In some embodiments, the thickness of each fourth doped layer 16B can be less than or equal to the thickness of each second source / drain structure 44P, but the disclosure is not limited thereto. Figure 3The thicknesses TK4 and TK6 can be substantially equal, but are not limited thereto. For example, in each second semiconductor sheet 16P, the thickness TK5 of the fourth doped layer 16B can be between 2.5 nm and 5 nm, the thickness TK4 of the third doped layer 16A below the fourth doped layer 16B and the thickness TK6 of the third doped layer 16A above the fourth doped layer 16B can each be between 5 nm and 10 nm, and the thickness TK4 of the third doped layer 16A below the fourth doped layer 16B can be substantially equal to the thickness TK6 of the third doped layer 16A above the fourth doped layer 16B, but are not limited thereto.

[0098] In some embodiments, the dopant concentration of each fourth doped layer 16B can be lower than the dopant concentration of each third doped layer 16A. For example, the dopant concentration of each third doped layer 16A can be between 1E+19 atoms / cm 3 and 1E+20 atom / cm 3 , and the dopant concentration of each fourth doped layer 16B can be between 1E+17 atoms / cm 3 and 1E+18 atom / cm 3 , but are not limited thereto. In some embodiments, the conductivity type of each third doped layer 16A can be the same as the conductivity type of each second doped layer 14B, but the dopant concentration of each third doped layer 16A can be higher than the dopant concentration of each second doped layer 14B, and the conductivity type of each fourth doped layer 16B can be the same as the conductivity type of each first doped layer 14A, but the dopant concentration of each first doped layer 14A can be higher than the dopant concentration of each fourth doped layer 16B, but are not limited thereto.

[0099] In some embodiments, the conductivity type of each second source / drain structure 44P can be the same as the conductivity type of each third doped layer 16A, such that each third doped layer 16A and the two second source / drain structures 44P directly connected to this third doped layer 16A can form a junctionless structure in the second transistor T2, and the second transistor T2 can also be considered as a junctionless transistor, but the disclosure is not limited in this way. In addition, in some embodiments, each second source / drain structure 44P can include dopants, the dopants in each second source / drain structure 44P can have the same conductivity type as the dopants in each third doped layer 16A, and the dopant concentration of each second source / drain structure 44P can be substantially equal to the dopant concentration of each third doped layer 16A within a tolerance of ±10%, but the disclosure is not limited in this way. In other words, the dopant concentration of each second source / drain structure 44P is preferably equal to the dopant concentration of each third doped layer 16A, but considering the process variation, the dopant concentration of each second source / drain structure 44P can be between 90% of the dopant concentration of each third doped layer 16A and 110% of the dopant concentration of each third doped layer 16A, and within this range of dopant concentration, the difference in dopant concentration between the second source / drain structure 44P and the third doped layer 16A can reduce the negative impact on the operation of the second transistor T2, but the disclosure is not limited in this way. Therefore, in some embodiments, the conductivity type of each second source / drain structure 44P of the second transistor T2 can be complementary to the conductivity type of each first source / drain structure 34P of the first transistor T1, and each second source / drain structure 44P and each first source / drain structure 34P can include dopants of different conductivity types, but the disclosure is not limited in this way.

[0100] In some embodiments, the first transistor T1 can be disposed between the substrate 10 and the second transistor T2 in the first direction D1, and the plurality of first semiconductor pieces 14P in the first transistor T1 can be disposed between the substrate 10 and the plurality of second semiconductor pieces 16P of the second transistor T2 in the first direction D1. In some embodiments, the semiconductor device 101 can include a gate structure GS disposed on the substrate 10, and the first transistor T1 and the second transistor T2 disposed in a stack in the first direction D1 can share the gate structure GS. For example, the first transistor T1 can include a first portion S1 of the gate structure GS, and the second transistor T2 can include a second portion S2 of the gate structure GS. The first portion S1 of the gate structure GS can surround each of the first semiconductor pieces 14P, and the second portion S2 of the gate structure GS can surround each of the second semiconductor pieces 16P, the first portion S1 and the second portion S2 of the gate structure GS can be directly connected, and the first portion S1 of the gate structure GS can be disposed between the substrate 10 and the second portion S2 of the gate structure GS in the first direction D1. Thus, the first transistor T1 and the second transistor T2 can also be considered as a gate-all-around (GAA) transistor structure, but the scope of the disclosure is not limited in this regard. In some embodiments, the gate structure GS can include a gate dielectric layer 56 and a gate material layer 58, but the scope of the disclosure is not limited in this regard. In the first portion S1 of the gate structure GS, the gate dielectric layer 56 can be disposed between the gate material layer 58 and each of the first semiconductor pieces 14P, and in the second portion S2 of the gate structure GS, the gate dielectric layer 56 can be disposed between the gate material layer 58 and each of the second semiconductor pieces 16P.

[0101] In some embodiments, at least a portion of the first source / drain structure 34P of the first transistor T1 can be disposed between the substrate 10 and the second source / drain structure 44P of the second transistor T2 in the first direction D1, and the semiconductor device 101 can further include a dielectric layer 42 disposed between the first source / drain structure 34P and the second source / drain structure 44P in the first direction D1, but the scope of the disclosure is not limited in this regard. In some embodiments, the first source / drain structure 34P and the second source / drain structure 44P at least partially overlapping in the first direction D1 can be electrically connected to each other by a connection structure (not shown), or the first source / drain structure 34P can have a region not overlapping with the second source / drain structure 44P to form a corresponding contact structure (not shown) thereon, but the scope of the disclosure is not limited in this regard.

[0102] In some embodiments, the semiconductor device 101 can further include a spacer 28, a spacer 32, an etch stop layer 52, and a dielectric layer 54. The spacer 32 can be disposed on the sidewalls of the lower portion (e.g., the first portion S1 and a portion of the second portion S2 as described above) of the gate structure GS, and the spacer 28 can be disposed on the sidewalls of the upper portion of the gate structure GS. Thus, in some embodiments, a portion of the spacer 32 can be disposed between the gate structure GS and the first source / drain structure 34P in the second direction D2, and another portion of the spacer 32 can be disposed between the gate structure GS and the second source / drain structure 44P in the second direction D2. In addition, the etch stop layer 52 can be disposed on the sidewalls of the spacer 28 and on the second source / drain structure 44P, and the dielectric layer 54 can be disposed on the etch stop layer 52.

[0103] In some embodiments, the semiconductor device 101 can include a plurality of first transistors T1 and a plurality of second transistors T2. The plurality of first transistors T1 can be arranged in the second direction D2, and adjacent first transistors T1 can share a first source / drain structure 34P. The plurality of second transistors T2 can be arranged in the second direction D2, and adjacent second transistors T2 can share a second source / drain structure 44P, but the disclosure is not limited in this regard. By stacking the first transistors T1 and the second transistors T2 in the first direction D1 and sharing the gate structure GS by the first transistors T1 and the second transistors T2, the area occupied by the semiconductor device 101 can be reduced, which is helpful for increasing the transistor density in related products.

[0104] In some embodiments, the substrate 10 can include a semiconductor substrate such as a silicon substrate, an epitaxial silicon substrate, a silicon germanium substrate, a silicon carbide substrate, or a silicon-on-insulator (SOI) substrate, but the disclosure is not limited in this regard. The first semiconductor piece 14P and the second semiconductor piece 16P can each include a semiconductor material such as silicon, silicon germanium, or other suitable semiconductor material. In some embodiments, the first doped layer 14A and the second doped layer 14B can each be formed by doping a same semiconductor material with dopants of different conductivity types, and the third doped layer 16A and the fourth doped layer 16B can each be formed by doping a same semiconductor material with dopants of different conductivity types, but the disclosure is not limited in this regard. In some embodiments, the first doped layer 14A and the second doped layer 14B can each be a different semiconductor material and have dopants of different conductivity types, and the third doped layer 16A and the fourth doped layer 16B can each be a different semiconductor material and have dopants of different conductivity types.

[0105] The first source / drain structure 34P and the second source / drain structure 44P may each comprise an epitaxial material such as epitaxial silicon, epitaxial silicon germanium (SiGe), epitaxial silicon phosphide (SiP), or other suitable epitaxial materials. Spacer 28 and spacer 32 may each comprise a single layer or multiple layers of insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, or other suitable insulating materials. Dielectric layer 42, etch stop layer 52, and dielectric layer 54 may each comprise silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric materials, or other suitable dielectric materials. Gate dielectric layer 56 may comprise a high-k dielectric material or other suitable dielectric materials. The aforementioned high-k dielectric material may include hafnium oxide (HfO). X Hafnium silicon oxide (HfSiO4), hafnium silicon oxynitride (HfSiON), aluminum oxide (Al2O3), tantalum oxide (Ta2O5), zirconium oxide (ZrO2), or other suitable high-dielectric-constant materials may be used. The gate material layer 58 may include, but is not limited to, non-metallic conductive materials (e.g., doped polycrystalline silicon) or metallic conductive materials, such as a metal gate structure formed by stacking a work function layer and a low-resistance layer. The aforementioned work function layer may include titanium nitride (TiN), titanium carbide (TiC), tantalum nitride (TaN), tantalum carbide (TaC), tungsten carbide (WC), titanium tri-aluminide (TiAl3), aluminum titanium nitride (TiAlN), or other suitable conductive work function materials, while the aforementioned low resistance layer may include, for example, tungsten, aluminum, copper, titanium aluminide, titanium, or other suitable materials with relatively low resistivity.

[0106] Please see Figure 1 as well as Figures 4 to 6 . Figure 4 The illustration shows the first semiconductor chip 14P or the second semiconductor chip 16P in an operational state according to this embodiment. Figure 5 The illustration shows a semiconductor wafer in an operational state, according to another embodiment of the present invention. Figure 6 The illustration shows a semiconductor wafer in an operational state, representing another embodiment of the present invention. Figure 1 andFigure 4 As shown, the gate structure GS can surround each first semiconductor piece 14P and each second semiconductor piece 16P in the first direction D1 and the third direction D3. When the first transistor T1 and the second transistor T2 are in operation, the first semiconductor piece 14P and the second semiconductor piece 16P can reach a full depletion state by the first doped layer 14A and the second doped layer 14B in the first semiconductor piece 14P having different conductive types and the third doped layer 16A and the fourth doped layer 16B in the second semiconductor piece 16P having different conductive types, and a first depletion region DR1 and a second depletion region DR2 surrounded by the first depletion region DR1 can be formed in the first semiconductor piece 14P and the second semiconductor piece 16P, respectively. The first depletion region DR1 can be regarded as a depletion region induced by the gate structure GS, and the second depletion region DR2 can be regarded as a depletion region induced by the second doped layer 14B and the fourth doped layer 16B. By reaching the full depletion state and changing the electric field distribution by the second depletion region DR2, the carrier scattering rate can be reduced, the carrier mobility can be improved, the leakage current in the middle channel region can be improved, and the capacitance of the depletion region can be reduced, thereby improving the electrical performance of the first transistor T1 and the second transistor T2. For example, the variation of the drain current, the variation of the subthreshold swing (SS) with temperature, and the breakdown voltage can be improved, but the application is not limited thereto.

[0107] In comparison, if the semiconductor piece is only composed of a single doped layer, the above-mentioned effects cannot be achieved. For example, as shown in FIG. 2A, when the semiconductor piece is only composed of a single doped layer (e.g., the first doped layer 14A or the third doped layer 16A) and has a relatively thin thickness (e.g., less than 10 nanometers), although a full depletion state can still be achieved, the carrier scattering rate can be increased and the carrier mobility can be reduced due to the first depletion region DR1 induced by the gate structure GS. In addition, as shown in FIG. 2B, when the semiconductor piece is only composed of a single doped layer (e.g., the first doped layer 14A or the third doped layer 16A) and has a relatively thick thickness, the carrier scattering rate can be reduced and the carrier mobility can be improved, but only a partial depletion state can be achieved, and the middle channel region surrounded by the first depletion region DR1 can easily generate a leakage current, thereby affecting the overall electrical performance. Figure 5 Figure 6 In comparison, if the semiconductor piece is only composed of a single doped layer, the above-mentioned effects cannot be achieved. For example, as shown in FIG. 2A, when the semiconductor piece is only composed of a single doped layer (e.g., the first doped layer 14A or the third doped layer 16A) and has a relatively thin thickness (e.g., less than 10 nanometers), although a full depletion state can still be achieved, the carrier scattering rate can be increased and the carrier mobility can be reduced due to the first depletion region DR1 induced by the gate structure GS. In addition, as shown in FIG. 2B, when the semiconductor piece is only composed of a single doped layer (e.g., the first doped layer 14A or the third doped layer 16A) and has a relatively thick thickness, the carrier scattering rate can be reduced and the carrier mobility can be improved, but only a partial depletion state can be achieved, and the middle channel region surrounded by the first depletion region DR1 can easily generate a leakage current, thereby affecting the overall electrical performance.

[0108] Please refer to Figure 1 and Figures 7 to 15 . Figures 7 to 15 ​A schematic view of a method of manufacturing the semiconductor device of the present embodiment is shown, wherein Figure 8 A schematic view of a method of manufacturing the semiconductor device of the present embodiment is shown, wherein Figure 7 A schematic view of a method of manufacturing the semiconductor device of the present embodiment is shown, wherein Figure 9 A schematic view of a method of manufacturing the semiconductor device of the present embodiment is shown, wherein Figure 8 A schematic view of a method of manufacturing the semiconductor device of the present embodiment is shown, wherein Figure 10 A schematic view of a method of manufacturing the semiconductor device of the present embodiment is shown, wherein Figure 9 A schematic view of a method of manufacturing the semiconductor device of the present embodiment is shown, wherein Figure 11 A schematic view of a method of manufacturing the semiconductor device of the present embodiment is shown, wherein Figure 10 A schematic view of a method of manufacturing the semiconductor device of the present embodiment is shown, wherein Figure 12 A schematic view of a method of manufacturing the semiconductor device of the present embodiment is shown, wherein Figure 11 A schematic view of a method of manufacturing the semiconductor device of the present embodiment is shown, wherein Figure 13 A schematic view of a method of manufacturing the semiconductor device of the present embodiment is shown, wherein Figure 12 A schematic view of a method of manufacturing the semiconductor device of the present embodiment is shown, wherein Figure 14 A schematic view of a method of manufacturing the semiconductor device of the present embodiment is shown, wherein Figure 13 A schematic view of a method of manufacturing the semiconductor device of the present embodiment is shown, wherein Figure 15 A schematic view of a method of manufacturing the semiconductor device of the present embodiment is shown, wherein Figure 14 A schematic view of a method of manufacturing the semiconductor device of the present embodiment is shown, wherein Figure 1 A schematic view of a method of manufacturing the semiconductor device of the present embodiment is shown, wherein Figure 15 A schematic view of a method of manufacturing the semiconductor device of the present embodiment is shown, wherein Figure 1 The method of manufacturing the semiconductor device 101 of the present embodiment can include the following steps. First, a substrate 10 is provided, and a first transistor T1 and a second transistor T2 are formed on the substrate 10. The first transistor T1 includes a plurality of first semiconductor pieces 14P and two first source / drain structures 34P. The plurality of first semiconductor pieces 14P are arranged in a vertical direction (e.g., a first direction D1) and are separated from each other. Each first semiconductor piece 14P includes two first doped layers 14A and a second doped layer 14B arranged between the two first doped layers 14A in the first direction D1. The second doped layer 14B has a conductivity type complementary to that of each first doped layer 14A. The two first source / drain structures 34P are arranged on two opposite sides of each first semiconductor piece 14P in a horizontal direction (e.g., a second direction D2), and the two first source / drain structures 34P are connected to the plurality of first semiconductor pieces 14P. The second transistor T2 includes a plurality of second semiconductor pieces 16P and two second source / drain structures 44P. The plurality of second semiconductor pieces 16P can be arranged in the first direction D1 and separated from each other, and each second semiconductor piece 16P can include two third doped layers 16A and a fourth doped layer 16B arranged between the two third doped layers 16A in the first direction D1. The two second source / drain structures 44P can be arranged on two opposite sides of each second semiconductor piece 16P in the second direction D2, and the two second source / drain structures 44P can be connected to the plurality of second semiconductor pieces 16P.

[0109] Further, the method of manufacturing the semiconductor device 101 of the present embodiment can include, but is not limited to, the following steps. First, as shown in Figure 7As shown, a stack structure FS is formed on the substrate 10, and the stack structure FS includes a plurality of first semiconductor stack structures 14, a plurality of second semiconductor stack structures 16, and a sacrificial material 12. Each of the first semiconductor stack structures 14 can include two first doped layers 14A and a second doped layer 14B sandwiched between the two first doped layers 14A in the first direction D1, and each of the second semiconductor stack structures 16 can include two third doped layers 16A and a fourth doped layer 16B sandwiched between the two third doped layers 16A in the first direction D1. The plurality of first semiconductor stack structures 14 can be disposed in a stack with each other in the first direction D1, the plurality of second semiconductor stack structures 16 can be disposed on the plurality of first semiconductor stack structures 14 and can be disposed in a stack with each other in the first direction D1, and the sacrificial material 12 can be partially disposed between the plurality of first semiconductor stack structures 14, partially disposed between the plurality of second semiconductor stack structures 16, and partially disposed between the plurality of first semiconductor stack structures 14 and the plurality of second semiconductor stack structures 16. In other words, the sacrificial material 12 and the first semiconductor stack structures 14 can be alternately disposed in a lower portion of the stack structure FS, and the sacrificial material 12 and the second semiconductor stack structures 16 can be alternately disposed in an upper portion of the stack structure FS, but the present disclosure is not limited thereto.

[0110] In some embodiments, the material composition of the sacrificial material 12 may differ from that of the first semiconductor stack 14 and the second semiconductor stack 16, thereby achieving the desired etch selectivity. For example, in some embodiments, the materials of the first semiconductor stack 14 and the second semiconductor stack 16 may be silicon semiconductor materials, while the material of the sacrificial material 12 may be silicon germanium (SiGe), thereby forming a superlattice epitaxial structure, but this is not a limitation. In some embodiments, other different material combinations may also be used to form the stack structure FS as required by the design. Furthermore, the first doped layer 14A and the second doped layer 14B in each of the first semiconductor stack structures 14 and the third doped layer 16A and the fourth doped layer 16B in each of the second semiconductor stack structures 16 may be formed by performing different doping processes on the semiconductor materials, but this is not a limitation. In some embodiments, the first doped layer 14A, the second doped layer 14B, the third doped layer 16A and / or the fourth doped layer 16B may also be formed using other suitable fabrication methods as required by the design. For example, the doped layers described above may be formed directly by in-situ doping during the film deposition process. Furthermore, in some embodiments, the sacrificial material 12, the first semiconductor stack structure 14, and the second semiconductor stack structure 16 may be formed on the substrate 10 in a comprehensive manner first, and then the sacrificial material 12, the first semiconductor stack structure 14, and the second semiconductor stack structure 16 may be patterned to form multiple mutually separated stacked structures FS, but this is not a limitation.

[0111] Then, as Figures 7 to 9 As shown, a dummy gate structure 20 can be formed on the stacked structure FS, and the dummy gate structure 20 can span across opposite sides of the stacked structure FS in the third direction D3. In some embodiments, the dummy gate structure 20 may include a dielectric layer 22, a dummy gate material 24, and a gate capping layer 26. The dielectric layer 22 may include oxide or other suitable dielectric materials, the dummy gate material 24 may include polysilicon, amorphous silicon, or other suitable materials, and the gate capping layer 26 may include nitride, oxynitride, or other suitable insulating materials, but is not limited thereto. In some embodiments, multiple stacked structures FS can be formed on the substrate 10, each stacked structure FS may extend substantially along the second direction D2, and an isolation structure 18 may be provided in the substrate 10 between adjacent stacked structures FS, but is not limited thereto. The isolation structure 18 may include a single layer or multiple layers of insulating material, such as oxide insulating materials (e.g., silicon oxide) or other suitable insulating materials. In some embodiments, the stacked structure FS can be considered as a fin-like structure extending along the second direction D2, and the dummy gate structure 20 can extend along a third direction D3 that is substantially orthogonal to the second direction D2 and span across the multiple stacked structures FS, but is not limited thereto.

[0112] Then, as Figure 9 and Figure 10 As shown, a spacer wall 28 can be formed on the sidewall of the dummy gate structure 20, and a patterning fabrication process 91 can be performed on the stacked structure FS using the dummy gate structure 20 and the spacer wall 28 as masks. In some embodiments, the patterning fabrication process 91 may include an etching process or other suitable patterning methods. Each first semiconductor stacked structure 14 can be patterned by the patterning fabrication process 91 to become a plurality of first semiconductor wafers 14P, and each second semiconductor stacked structure 16 can be patterned by the patterning fabrication process 91 to become a plurality of second semiconductor wafers 16P. In some embodiments, since the dummy gate structure 20 and the spacer wall 28 can be used as masks for the patterning fabrication process 91, the projected shape and / or projected area of ​​each first semiconductor wafer 14P and each second semiconductor wafer 16P in the first direction D1 may be substantially the same, but this is not a limitation. It is worth noting that the method for forming the first semiconductor wafer 14P and the second semiconductor wafer 16P in this embodiment may include, but is not limited to, the above-described methods. Figures 7 to 10 The steps are shown. In some embodiments, the first semiconductor wafer 14P and the second semiconductor wafer 16P may also be formed by other suitable methods depending on the manufacturing process and / or design requirements.

[0113] Next, as Figures 10 to 11 As shown, a recessing fabrication process can be performed on the sacrificial material 12 to shorten its length in the second direction D2, thereby further exposing a portion of each of the first semiconductor wafers 14P and a portion of each of the second semiconductor wafers 16P. The recessing fabrication process described above may include an etching process with a high etch selectivity for the sacrificial material 12, the first semiconductor wafers 14P, and the second semiconductor wafers 16P, thereby reducing negative impacts on the first semiconductor wafers 14P and the second semiconductor wafers 16P, but is not limited thereto. Then, as... Figures 11 to 12 As shown, a spacer wall 32 can be formed on the sidewall of the sacrificial material 12, and a first epitaxial material 34 can be formed on the substrate 10 after the spacer wall 32 is formed. In some embodiments, the first epitaxial material 34 can be formed by an epitaxial growth process from the substrate 10, the edges of each first semiconductor wafer 14P and / or the edges of each second semiconductor wafer 16P, so the first epitaxial material 34 can be connected to each first semiconductor wafer 14P and each second semiconductor wafer 16P, but is not limited thereto. Then, as Figures 12 to 13As shown, a tunneling fabrication process 92 can be performed on the first epitaxial material 34 to remove a portion of the first epitaxial material 34 and partially expose the sides of each of the second semiconductor wafers 16P, thereby forming a plurality of first source / drain structures 34P with the first epitaxial material 34 remaining on the substrate 10. In other words, at least a portion of the first epitaxial material 34 can be etched by the tunneling fabrication process 92 to form a plurality of first source / drain structures 34P, but this is not a limitation. It is worth noting that the method for forming the first source / drain structures 34P in this embodiment may include, but is not limited to, the above-described method. Figures 12 to 13 The steps shown. In some embodiments, the first source / drain structure 34P may also be formed by other suitable methods depending on the manufacturing process and / or design requirements. For example, the size of the first epitaxial material 34 may be controlled to directly form the first source / drain structure 34P without performing the above-described tunneling process 92, but this is not a limitation.

[0114] Then, as Figure 14 As shown, a dielectric layer 42 can be formed on the first source / drain structure 34P, and a second source / drain structure 44P can be formed on the dielectric layer 42. In some embodiments, an epitaxial growth process can be performed from the exposed edges of each second semiconductor wafer 16P to form a second epitaxial material 44. Therefore, the second epitaxial material 44 can be directly connected to each second semiconductor wafer 16P. By controlling the formation of the second epitaxial material 44 (e.g., controlling the fabrication process time of forming the second epitaxial material 44), the required second source / drain structure 44P can be formed at opposite ends of each second semiconductor wafer 16P in the second direction D2. In some embodiments, a portion of the second source / drain structure 44P can be removed so that a portion of the first source / drain structure 34P does not overlap with the second source / drain structure 44P in the first direction D1, thereby forming the required space for the contact structure corresponding to the first source / drain structure 34P, but this is not a limitation. Furthermore, the method for forming the second source / drain structure 44P in this embodiment may include, but is not limited to, the above. Figure 13 and Figure 14 The steps are shown. In some embodiments, the second source / drain structure 44P may also be formed using other suitable methods depending on the manufacturing process and / or design requirements.

[0115] like Figure 14 , Figure 15 as well as Figure 1 As shown, in some embodiments, the gate structure GS can be formed by replacing the dummy gate structure 20 and the sacrificial material 12 with the gate dielectric layer 56 and the gate material layer 58. Further explanation is provided below. Figures 14 to 15As shown, after the second source / drain structure 44P is formed, an etch stop layer 52 and a dielectric layer 54 can be formed. A planarization process is then used to remove the gate cap layer 26, a portion of the dielectric layer 54, and a portion of the etch stop layer 52 to expose the dummy gate structure 20. The planarization process can include chemical mechanical polishing (CMP), etch-back, or other suitable planarization methods. After the planarization process, the exposed dummy gate structure 20 and sacrificial material 12 can be removed to form a trench TR. The trench TR can be surrounded horizontally by spacer walls 28 and 32, and each of the first semiconductor wafers 14P and each of the second semiconductor wafers 16P can be partially located within the trench TR. Then, as... Figure 15 and Figure 1 As shown, a gate dielectric layer 56 and a gate material layer 58 can be formed sequentially, and the gate dielectric layer 56 and the gate material layer 58 can partially fill the trench TR. In some embodiments, another planarization process can be used to remove the gate dielectric layer 56 and the gate material layer 58 outside the trench TR to form a gate structure GS in the trench TR. The method for forming the gate structure GS in this embodiment may include, but is not limited to, the above. Figure 14 , Figure 15 as well as Figure 1 The steps are shown. In some embodiments, the gate structure GS may also be formed using other suitable methods depending on the fabrication process and / or design requirements.

[0116] The following description will focus on different embodiments of the present invention. For the sake of simplicity, the description will mainly focus on the differences between the embodiments, and will not repeat the same points. In addition, the same elements in the various embodiments of the present invention are identified by the same reference numerals to facilitate comparison between the embodiments.

[0117] Please see Figure 16 . Figure 16 The illustration shows a schematic diagram of a semiconductor device 102 according to a second embodiment of the present invention. Figure 16As shown, in the semiconductor device 102, the first transistor T1 and the second transistor T2 may be disposed on the same plane without overlapping each other in the first direction D1. In this case, the first transistor T1 may include a first gate structure GS1, and the second transistor T2 may include a second gate structure GS2. The first gate structure GS1 may surround each first semiconductor wafer 14P, and two first source / drain structures 34P may be disposed on opposite sides of the first gate structure GS1 in the horizontal direction (e.g., the second direction D2). The second gate structure GS2 may surround each second semiconductor wafer 16P, and two second source / drain structures 44P may be disposed on opposite sides of the second gate structure GS2 in the horizontal direction (e.g., the second direction D2). In some embodiments, the first gate structure GS1 and the second gate structure GS2 may be separated from each other, but this is not a limitation. In some embodiments, the first transistor T1 and the second transistor T2 may be disposed adjacently on a third direction D3, and the first gate structure GS1 and the second gate structure GS2 may be different portions of the same gate structure extending along the third direction D3, and the first gate structure GS1 and the second gate structure GS2 may therefore be electrically connected to each other, but are not limited thereto. Furthermore, the first gate structure GS1 may include a first gate material layer 58A, and the second gate structure GS2 may include a second gate material layer 58B, and the material composition of the first gate material layer 58A and the second gate material layer 58B may be similar to the material composition of the gate material layer in the first embodiment described above, but are not limited thereto. In some embodiments, the material composition of the first gate material layer 58A may be the same as or different from the material composition of the second gate material layer 58B depending on design requirements. For example, when the first transistor T1 and the second transistor T2 are transistors of different types (e.g., an n-type transistor and a p-type transistor respectively), the first gate material layer 58A and the second gate material layer 58B may each have different work function layers to meet the requirements of different types of transistors, but are not limited thereto.

[0118] Please see Figures 16 to 22 . Figures 17 to 22 The illustration shows a schematic diagram of a method for manufacturing a semiconductor device 102 according to a second embodiment of the present invention, wherein... Figure 18 It is illustrated Figure 17 A diagram illustrating the subsequent situation. Figure 19 It is illustrated Figure 18 A diagram illustrating the subsequent situation. Figure 20 It is illustrated Figure 19 A diagram illustrating the subsequent situation. Figure 21 It is illustrated Figure 20 A diagram illustrating the subsequent situation. Figure 22 It is illustrated Figure 21 The following is a diagram illustrating the situation, and Figure 16 It can be regarded as a drawing Figure 22A schematic diagram of the subsequent situation. The method for fabricating the semiconductor device 102 in this embodiment may include, but is not limited to, the following steps. First, as Figure 17 As shown, a first stacked structure FS1 is formed on the substrate 10, and the first stacked structure FS1 may include a plurality of first semiconductor stacked structures 14 and a sacrificial material 12. Each first semiconductor stacked structure 14 may include two first doped layers 14A and a second doped layer 14B sandwiched between the two first doped layers 14A in a first direction D1. The plurality of first semiconductor stacked structures 14 may be stacked on top of each other in the first direction D1, and the sacrificial material 12 may be disposed between the plurality of first semiconductor stacked structures 14 and between the first semiconductor stacked structures 14 and the substrate 10. In some embodiments, the first stacked structure FS1 may be regarded as a fin-like structure extending in a horizontal direction (e.g., the second direction D2), but is not limited thereto.

[0119] Then, as Figures 17 to 18 As shown, a first patterned mask layer 82 can be formed on the first stacked structure FS1, and an etching process is performed on the first stacked structure FS1 using the first patterned mask layer 82 as a mask to remove the first stacked structure FS1 not covered by the first patterned mask layer 82. After removing the portion of the first stacked structure FS1, a second patterned mask layer 84 can be formed to cover the first stacked structure FS1, the first patterned mask layer 82, and the substrate 10. Furthermore, the second patterned mask layer 84 may have an opening OP to expose a portion of the substrate 10. Then, as... Figures 18 to 19 As shown, a second stacked structure FS2 can be formed on the substrate 10 exposed by the opening OP, and the second stacked structure FS2 may include a plurality of second semiconductor stacked structures 16 and a sacrificial material 12. Each second semiconductor stacked structure 16 may include two third doped layers 16A and a fourth doped layer 16B sandwiched between the two third doped layers 16A in a first direction D1. The plurality of second semiconductor stacked structures 16 may be stacked on top of each other in the first direction D1, and the sacrificial material 12 may be disposed between the plurality of second semiconductor stacked structures 16 and between the second semiconductor stacked structures 16 and the substrate 10. In some embodiments, the second stacked structure FS2 may be further patterned into a fin-like structure extending in a horizontal direction (e.g., but not limited to the second direction D2), but is not limited thereto.

[0120] like Figures 19 to 20 As shown, the first patterned mask layer 82 and the second patterned mask layer 84 can be removed, and a dummy gate structure 20 and a spacer wall 28 can be formed on the first stacked structure FS1 and the second stacked structure FS2, respectively. Then, as... Figures 20 to 21As shown, the first semiconductor pieces 14P and the second semiconductor pieces 16P are respectively formed by performing a patterning process on the first stack structure FS1 and the second stack structure FS2 using the dummy gate structures 20 and the spacers 28 as masks. In addition, after the first semiconductor pieces 14P and the second semiconductor pieces 16P are formed, an etching process can be performed on the sacrificial material 12 to shorten the length of the sacrificial material 12 in the horizontal direction and further expose a portion of each first semiconductor piece 14P and a portion of each second semiconductor piece 16P. Then, as shown, Figures 21 to 22 As shown, the spacers 32 can be formed on the sidewalls of the sacrificial material 12, and the first source / drain structures 34P and the second source / drain structures 44P can be formed after the spacers 32 are formed. In some embodiments, the first source / drain structures 34P and the second source / drain structures 44P can be respectively formed by different fabrication processes (e.g., epitaxial growth fabrication processes), but the application is not limited in this way.

[0121] Then, as shown, Figure 22 and Figure 16 As shown, the etching stop layers 52 and the dielectric layers 54 can be formed, and the gate dielectric layers 56 and the first gate material layers 58A are used to replace the dummy gate structures 20 and the sacrificial material 12 corresponding to the first semiconductor pieces 14P to form the first gate structures GS1, and the gate dielectric layers 56 and the second gate material layers 58B are used to replace the dummy gate structures 20 and the sacrificial material 12 corresponding to the second semiconductor pieces 16P to form the second gate structures GS2. In other words, the first gate structures GS1 and the second gate structures GS2 can be respectively formed by a replacement gate fabrication process, and the fabrication method can be similar to the method of forming the gate structures in the first embodiment described above, but the application is not limited in this way.

[0122] It is worth noting that in the present application, the fabrication method of the first transistor T1 and the second transistor T2 which are arranged adjacent to each other and separated from each other in the horizontal direction is not limited to the above-mentioned Figures 16 to 22The first and second transistors T1 and T2 can be formed in other suitable manners as required by design, provided that the steps of forming the first and second semiconductor stacks 14 and 16, forming the dummy gate structures 20, and forming the spacers 28 are not changed. For example, in some embodiments, a plurality of first semiconductor stacks 14 and a plurality of second semiconductor stacks 16 can be formed on the substrate 10 in an alternating stack in the first direction D1, and after the stack is patterned with the dummy gate structures 20 and the spacers 28, different replacement gate fabrication processes can be performed on regions corresponding to the first transistors T1 and regions corresponding to the second transistors T2, respectively, to remove the second semiconductor pieces 16P in the regions corresponding to the first transistors T1 and remove the first semiconductor pieces 14P in the regions corresponding to the second transistors T2, respectively, to form the first transistors including the first semiconductor pieces 14P and the second transistors including the second semiconductor pieces 16P, respectively. In addition, in the semiconductor device formed by this fabrication method, the positions of the plurality of first semiconductor pieces 14P in the first direction D1 can be displaced from the positions of the plurality of second semiconductor pieces 16P in the first direction D1, but this is not a limitation.

[0123] In summary, in the semiconductor device and the fabrication method thereof according to the present application, each semiconductor piece can be formed by sandwiching another doped layer of a different conductivity type between two doped layers of the same conductivity type, thereby adjusting the channel region depletion condition or / and the electric field distribution of the transistor including the semiconductor piece when the transistor is operated, and thus improving the electrical performance of the semiconductor device.

[0124] The above description is only some preferred embodiments of the present application, and any equivalent changes and modifications made according to the claims of the present application should be covered by the present application.

Claims

1. A semiconductor device, characterized by comprising: Comprising: a substrate; and a first transistor disposed on the substrate, the first transistor comprising: a plurality of first semiconductor pieces stacked in a vertical direction and separated from each other, wherein each of the first semiconductor pieces comprises: two first doped layers; and a second doped layer disposed between the two first doped layers in the vertical direction, wherein a conductivity type of the second doped layer is complementary to a conductivity type of each of the first doped layers; and two first source / drain structures disposed on two opposite sides of each of the first semiconductor pieces in a horizontal direction, wherein the two first source / drain structures are connected to the plurality of first semiconductor pieces, wherein the second doped layer in each of the first semiconductor pieces is directly connected to the two first doped layers.

2. The semiconductor device of claim 1, wherein a conductivity type of each of the first source / drain structures is the same as the conductivity type of each of the first doped layers.

3. The semiconductor device of claim 2, wherein a dopant concentration of each of the first source / drain structures is equal to a dopant concentration of each of the first doped layers with a tolerance of ±10%.

4. The semiconductor device of claim 1, wherein each of the first source / drain structures is directly connected to the two first doped layers and the second doped layer of each of the first semiconductor pieces.

5. The semiconductor device of claim 1, wherein a thickness of each of the second doped layers is less than or equal to a thickness of each of the first doped layers.

6. The semiconductor device of claim 1, wherein the first transistor further comprises: a first gate structure surrounding each of the first semiconductor pieces, wherein the two first source / drain structures are disposed on two opposite sides of the first gate structure in the horizontal direction.

7. The semiconductor device of claim 1, further comprising: a second transistor disposed on the substrate, the second transistor comprising: a plurality of second semiconductor pieces stacked in the vertical direction and separated from each other, wherein each of the second semiconductor pieces comprises: two third doped layers; and a fourth doped layer disposed between the two third doped layers in the vertical direction, wherein a conductivity type of the fourth doped layer is complementary to a conductivity type of each of the third doped layers, and the conductivity type of each of the fourth doped layers is the same as the conductivity type of each of the first doped layers; and two second source / drain structures disposed on two opposite sides of each of the second semiconductor pieces in the horizontal direction, wherein the two second source / drain structures are connected to the plurality of second semiconductor pieces.

8. The semiconductor device of claim 7, wherein a conductivity type of each of the second source / drain structures is the same as the conductivity type of each of the third doped layers.

9. The semiconductor device of claim 8, wherein a dopant concentration of each of the second source / drain structures is equal to a dopant concentration of each of the third doped layers with a tolerance of ±10%.

10. The semiconductor device of claim 7, wherein each of the second source / drain structures is directly connected to the two third doped layers and the fourth doped layer of each of the second semiconductor pieces.

11. The semiconductor device of claim 7, wherein a thickness of each of the fourth doped layers is less than or equal to a thickness of each of the third doped layers.

12. The semiconductor device of claim 7, wherein the fourth doped layer in each of the second semiconductor pieces is directly connected to the two third doped layers.

13. The semiconductor device of claim 7, wherein the plurality of first semiconductor pieces are disposed between the substrate and the plurality of second semiconductor pieces in the vertical direction.

14. The semiconductor device of claim 13, wherein the first transistor further comprises a first portion of a gate structure surrounding each of the first semiconductor pieces, the second transistor further comprises a second portion of the gate structure, and the second portion surrounds each of the second semiconductor pieces, wherein the first portion of the gate structure is directly connected to the second portion of the gate structure, and the first portion of the gate structure is disposed between the substrate and the second portion of the gate structure in the vertical direction.

15. The semiconductor device of claim 13, wherein at least a portion of each of the first source / drain structures is disposed between the substrate and one of the two second source / drain structures in the vertical direction.

16. The semiconductor device of claim 7, wherein the second transistor further comprises: a second gate structure surrounding each of the second semiconductor pieces, wherein the two second source / drain structures are respectively disposed on two opposite sides of the second gate structure in the horizontal direction.

17. The semiconductor device of claim 1, wherein a thickness of each of the first semiconductor pieces is between 5 nanometers and 100 nanometers.

18. The semiconductor device of claim 1, wherein the first transistor is a junctionless transistor.

19. The semiconductor device of claim 1, wherein the first transistor is an n-type transistor, each of the first doped layers is an n-type doped semiconductor layer, and each of the second doped layers is a p-type doped semiconductor layer. ​

Images