Power drive circuit and control method thereof

Abstract

A power driving circuit includes a power conversion module, a plurality of gate drivers, a waveform processing unit, a control unit, a weight unit and a comparator. Each gate driver includes a driving resistance setting value. The waveform processing unit outputs an absolute value waveform of current of alternating current power. The weight unit generates a trigger voltage. When the comparator judges that the absolute value waveform of current is greater than the trigger voltage, a slew rate control signal is output to each gate driver. When each gate driver receives the slew rate control signal, the driving resistance setting value of each gate driver is respectively adjusted. The present invention also relates to a control method for a power driving circuit.

Description

Technical Field

[0001] The present invention relates to a power circuit and a control method thereof, and more particularly to a power circuit with a dynamic adjustment of a driving resistance setting value and a control method thereof. Background Art

[0002] Power switching elements such as MOSFETs, IGBTs, SiC-MOSFETs, and GaN are widely used in power electronics systems, such as front-end converters, automotive charging systems, and drive inverters. These power switching elements generate switching losses during the energy conversion process. To meet the trend toward lower losses and higher efficiency, the gate drive resistance of the power switching elements is adjusted and gradually reduced. This reduces the overlap area of ​​the power switching elements during switching, further minimizing losses and improving efficiency. However, blindly reducing the drive resistance increases the slope of the voltage change (dv / dt) and current change (di / dt) during switching, causing parasitic inductance and coupling capacitance in the circuit to oscillate and exceed EMI operating limits. Therefore, achieving optimal operating characteristics requires a trade-off between the two.

[0003] Figure 1A and Figure 1B The performance of Fuji model 2MBI1400VXB-IGBT module was verified using a dual pulse test platform. Figure 1A Display drive resistance R G-On The turn-on voltage slope dv / dt from 0Ω to 4.8Ω is Figure 1B Display drive resistance R G-On Switching loss E from 0Ω to 4.8Ω ON result.

[0004] Due to regulatory or circuit configuration restrictions, if the turn-on voltage slope dv / dt is designed to be lower than 9kV / s, then Figure 1A The results show that when using the 2MBI1400VXB-IGBT module, a drive resistance value equal to or higher than 2.4Ω is required. The selection of the drive resistance value also determines the turn-on voltage slope dv / dt and the switching loss E ON The operating behavior of the power switching element flows with the current I CE Gradually improve, E ON The loss also increases, while the turn-on voltage slope dv / dt begins to decrease. CE When the current is higher than 800A, the driving resistance is switched from 2.4Ω to 0Ω, which not only maintains the design requirement of the upper limit of the slope of 9kV / s, but also ONThe loss can also be greatly reduced. Based on this idea, the slew-rate control (SRC) driving mode is gradually replacing the traditional circuit architecture.

[0005] The traditional SRC function starting mode uses the flow current and temperature information of the power switch element as the judgment condition. The obtained information is controlled through hardware or firmware. The advantages and disadvantages of the two methods will be described below.

[0006] Using hardware circuit to detect current and temperature information to control EN SRC The signal example circuit is shown in Figure 2 The load current feedback information is compared with the preset current level through the signal processing circuit. When the load current is higher than the current level, the EN SRC signal is set to the starting state, and vice versa. In addition, temperature information can also be used for starting judgment. When the temperature exceeds the judgment point required by the SRC function to start, the EN SRC signal is set to the starting state, reducing switching loss and reducing the operating temperature of the power switch element. And Figure 2 for the operation example of single-phase output, if the line is a three-phase system, the same signal and comparison configuration need to be increased to three groups. The increase of components will affect the size of the circuit board manufacturing, and the temperature and current judgment circuit can be selected according to the actual demand.

[0007] Using firmware program to start the SRC function as shown in Figure 3 Compared with hardware settings, complex circuit elements and increased circuit board manufacturing space are needed to achieve. The microprocessor (control unit) itself can obtain the characteristics such as current and temperature information, and through the writing of flexible programs, the SRC driving mode can be realized.

[0008] However, using hardware or firmware to judge and control has its disadvantages. As shown in Figure 4 , the hardware circuit implementation method will need additional components, not only reducing the layout efficiency of the circuit board, but also because the components are selected, the SRC comparison level cannot be modified at will. But its fast response can respond to the rapid change of the comparison signal, achieving high accuracy of SRC function use; and the firmware program improves the circuit board layout and comparison level control problem, but limited by the microprocessor sampling of the sensing signal, there may be SRC function use malfunction when the sensing signal changes rapidly.

[0009] As shown in Figure 5As shown, using current information as a reference of SRC comparison level, in actual circuit operation, due to the problem of microprocessor signal sampling, the running characteristics of current ripple are ignored in the implementation of SRC method in firmware program, and then the start signal EN SRC In the incorrect case, the power switching element cannot act in accordance with the expected result.

[0010] Therefore, how to design a power driving circuit and its operation method, by using hardware circuit to sense the high response characteristics of the signal, and using the weight circuit to combine the firmware program to flexibly adjust the drive resistance setting value of the gate driver, so as to dynamically adjust the drive resistance setting value of the gate driver according to the optimal program in different use occasions, to have high correctness SRC function starting ability, is an important research topic of the present invention. SUMMARY

[0011] The purpose of the present application is to provide a power driving circuit to solve the problems of the prior art.

[0012] To achieve the above-mentioned purpose, the power driving circuit provided by the present application includes a power conversion module, a plurality of gate drivers, a waveform processing unit, a control unit, a weight unit and a comparator. The power conversion module includes a plurality of switches, and the power conversion module receives a direct current power supply to output an alternating current power. Each gate driver is connected to the control end of each switch, and each gate driver includes a drive resistance setting value. The waveform processing unit is coupled to the alternating current signal of the alternating current power to output the current absolute value waveform of the alternating current signal. The control unit adjusts the duty cycle of the first pulse width modulation signal according to the direct current power and the alternating voltage signal of the alternating current power to output the second pulse width modulation signal. The weight unit obtains the average voltage of the second pulse width modulation signal, and superimposes the average voltage and the trigger level signal to generate a trigger voltage. When the comparator determines that the current absolute value waveform is greater than the trigger voltage, the comparator outputs a slew rate control signal to each gate driver. When each gate driver receives the slew rate control signal, the drive resistance setting value of each gate driver is respectively reduced.

[0013] In an embodiment, when the comparator determines that the current absolute value waveform is not greater than the trigger voltage, the comparator stops outputting the slew rate control signal to respectively restore the drive resistance setting value of each gate driver.

[0014] In an embodiment, the control unit is further configured to detect the operating temperature of the power conversion module; when the control unit determines that the operating temperature is higher than a temperature threshold, the control unit adjusts the duty cycle of the first pulse width modulation signal to zero.

[0015] In one embodiment, the control unit controls the plurality of gate drivers to selectively turn on or turn off the plurality of switches according to the current absolute value waveform.

[0016] In one embodiment, the waveform processing unit includes a first operation unit and a second operation unit. The first operation unit receives a reference voltage, wherein the first operation unit inverts the AC current signal to generate a first processed waveform, and the first operation unit retains a portion of the first processed waveform that is lower than the reference voltage to form a second processed waveform. The second operation unit amplifies the second processed waveform to generate a third processed waveform, wherein the second operation unit superimposes the third processed waveform with the AC current signal to form a fourth processed waveform, wherein the second operation unit inverts the fourth processed waveform to output the current absolute value waveform.

[0017] In one embodiment, the first operation unit includes a first operational amplifier, a first resistor, a second resistor, a third resistor, a first diode, and a second diode. The first operational amplifier includes a negative input terminal, a positive input terminal, and an output terminal. A first end of the first resistor is coupled with the AC current signal, and a second end of the first resistor is connected to the negative input terminal of the first operational amplifier. A first end of the second resistor is coupled with the reference voltage, and a second end of the second resistor is connected to the positive input terminal of the first operational amplifier. A first end of the third resistor is connected to the second end of the first resistor. An anode of the first diode is connected to a second end of the third resistor. A cathode of the second diode is connected to the second end of the first resistor, and an anode of the second diode is connected to a cathode of the first diode and the output terminal of the first operational amplifier to generate the second processed waveform.

[0018] In one embodiment, the second operation unit includes a fourth resistor, a fifth resistor, a sixth resistor, a second operational amplifier, and a seventh resistor. A first end of the fourth resistor is connected to the second end of the third resistor. A first end of the fifth resistor is connected to the first end of the first resistor, and a second end of the fifth resistor is connected to a second end of the fourth resistor. A first end of the sixth resistor is connected to the second end of the fifth resistor and the second end of the fourth resistor. The second operational amplifier includes a negative input terminal, a positive input terminal, and an output terminal, wherein the negative input terminal of the second operational amplifier is connected to the first end of the sixth resistor, and the output terminal of the second operational amplifier is connected to a second end of the sixth resistor. A first end of the seventh resistor is connected to the first end of the second resistor, and a second end of the seventh resistor is connected to the positive input terminal of the second operational amplifier.

[0019] In one embodiment, the fourth resistor has a size that is half of a size of the sixth resistor.

[0020] In one embodiment, the weighting unit includes a low-pass filter, an eighth resistor, and a ninth resistor. The low-pass filter receives the second pulse-width modulated signal and outputs an average voltage of the second pulse-width modulated signal. A first end of the eighth resistor receives the average voltage. A first end of the ninth resistor is coupled to the trigger level signal, and a second end of the ninth resistor is connected to the second end of the eighth resistor to generate a trigger voltage.

[0021] In one embodiment, the relationship among the trigger voltage, the average voltage, and the trigger level signal is: Vx=(V1×R9) / (R8+R9)+(V2×R8) / (R8+R9).

[0022] The proposed power drive circuit utilizes the hardware circuit's high responsiveness to sensing signals and uses a weighting circuit combined with firmware to flexibly adjust the SRC comparison level. This allows the gate driver's drive resistance setting to be dynamically adjusted according to an optimization program in different usage scenarios, ensuring highly accurate SRC function activation.

[0023] Another object of the present invention is to provide an operating method of a power driving circuit to solve the problems of the prior art.

[0024] To achieve the aforementioned objectives, the present invention provides an operating method for a power drive circuit for controlling a power conversion module. The operating method includes: converting a DC power source into AC power via the power conversion module; executing an absolute value calculation program to obtain a current absolute value waveform of an AC current signal of the AC power; adjusting the duty cycle of a first pulse width modulation signal based on the DC power source and the AC voltage signal of the AC power to form a second pulse width modulation signal; obtaining an average voltage of the second pulse width modulation signal; superimposing the average voltage with a trigger level signal to generate a trigger voltage; and comparing the current absolute value waveform with the trigger voltage. When the current absolute value waveform is greater than the trigger voltage, a slew rate control signal is output to each gate driver. Upon receiving the slew rate control signal, each gate driver reduces the drive resistance setting value of each gate driver.

[0025] In one embodiment, when the absolute value of the current waveform is not greater than the trigger voltage, the output of the slew rate control signal is stopped to restore the driving resistance setting value of each gate driver.

[0026] In one embodiment, the operating method further comprises: detecting an operating temperature of the power conversion module, wherein when the operating temperature is higher than a temperature threshold, adjusting the duty cycle of the first pulse width modulation signal to zero.

[0027] In one embodiment, the operating method further includes: controlling a plurality of gate drivers according to the current absolute value waveform to adjust the plurality of switches to be selectively turned on or off.

[0028] In one embodiment, the absolute value calculation process includes: inverting the AC current signal to generate a first processed waveform; retaining a portion of the first processed waveform below a reference voltage to form a second processed waveform; amplifying the second processed waveform to generate a third processed waveform; superimposing the third processed waveform with the AC current signal to form a fourth processed waveform; and inverting the fourth processed waveform to output a current absolute value waveform.

[0029] The proposed power driver circuit operation method utilizes the hardware circuit's high responsiveness to sensing signals and utilizes a weighting circuit in conjunction with firmware to flexibly adjust the SRC comparison level. This allows the gate driver's drive resistance setting to be dynamically adjusted according to an optimization program in different usage scenarios, ensuring highly accurate SRC function activation.

[0030] In order to further understand the technologies, means and technical effects adopted by the present invention to achieve the intended objectives, please refer to the following detailed description of the present invention and the accompanying drawings. It is believed that the objectives, features and characteristics of the present invention can be understood in depth and in detail. However, the accompanying drawings are provided for reference and illustration only and are not intended to limit the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1A : A curve diagram of the turn-on voltage slope performance of the existing double-pulse test platform.

[0032] Figure 1B : A graph showing the switching loss performance of the existing double-pulse test platform.

[0033] Figure 2 : Block diagram of a circuit that generates a slew rate control signal for an existing hardware circuit.

[0034] Figure 3 : Block diagram of the circuit that generates the slew rate control signal for the existing firmware.

[0035] Figure 4 : A waveform diagram showing the misjudgment of an action caused by using existing hardware circuits.

[0036] Figure 5 : This is a waveform diagram showing the misjudgment caused by using the existing firmware.

[0037] Figure 6 : is a circuit block diagram of the power drive circuit of the present invention.

[0038] Figure 7 : is a circuit diagram of the waveform processing unit of the present invention.

[0039] Figure 8 : A waveform diagram of the waveform processing unit of the present invention.

[0040] Figure 9 : is a circuit diagram of the weight unit of the present invention.

[0041] Figure 10 : is a circuit block diagram of the weight unit of the present invention applied to a power drive circuit.

[0042] Figures 11A-11C : A waveform diagram of the trigger voltage generated by the present invention.

[0043] Figure 12 : A schematic diagram of the waveform of the slew rate control signal generated by the present invention.

[0044] Figure 13 : is a flow chart of the operating method of the power driving circuit of the present invention.

[0045] Description of reference numerals:

[0046] 10: Waveform processing unit

[0047] 12: Control unit

[0048] 14: Weight unit

[0049] 16: Comparator

[0050] 20: Power conversion module

[0051] 21: On switch

[0052] 22: Lower the switch

[0053] 23: Temperature sensor

[0054] 31: Gate Driver

[0055] 32: Gate driver

[0056] 141: Low-pass filter

[0057] 142: Voltage stabilization circuit

[0058] R1~R9:resistance

[0059] D1~D2:diodes

[0060] OPA1: First operational amplifier

[0061] OPA2: Second operational amplifier

[0062] V Drive : Driving voltage

[0063] R G-On ,R G-On1 ,R G-On2 ,R G-Off : Driving resistance setting value

[0064] ePWM: Second pulse width modulation signal

[0065] EN SRC : Slew rate control signal

[0066] Vo: AC voltage signal

[0067] iload: AC current signal

[0068] |Vc|: Current absolute value waveform

[0069] V T : Operating temperature

[0070] iload-level: trigger level signal

[0071] Vx: trigger voltage

[0072] ePWM-U: control signal

[0073] ePWM-N: control signal

[0074] V1: first input voltage

[0075] V2: Second input voltage

[0076] DC+, DC-: DC power supply

[0077] S11~S18: Steps DETAILED DESCRIPTION

[0078] The technical content and detailed description of the present invention are described as follows with reference to the accompanying drawings.

[0079] See Figure 6 , which is a circuit block diagram of a power drive circuit according to the present invention. The power drive circuit includes a power conversion module 20, a plurality of gate drivers 31, 32, a waveform processing unit 10, a control unit 12, a weighting unit, and a comparator 16. The power conversion module 20 includes a plurality of switches. In one embodiment, each switch is an insulated gate bipolar transistor (IGBT), but this is not limiting. The power conversion module 20 receives DC power sources DC+ and DC- and outputs AC power (including an AC voltage signal Vo and an AC current signal iload).

[0080] Each gate driver 31, 32 is connected to the control terminal of each switch (taking IGBT as an example, the control terminal is the gate terminal), and each gate driver 31, 32 includes a driving resistor setting value R G-On1 ,R G-Off1 ,R G-On2 ,RG-Off2 , which will be described in detail later.

[0081] The waveform processing unit 10 is coupled to the AC current signal iload of the AC power to output a current absolute value waveform |Vc| of the AC current signal iload. Figure 7 and Figure 8 As shown, it is divided into a circuit diagram of the waveform processing unit of the present invention and a waveform diagram of the waveform processing unit operation. The waveform processing unit 10 includes a first operation unit and a second operation unit. The first operation unit receives a reference voltage Vos, wherein the first operation unit inverts the AC current signal iload to generate a first processing waveform, and the first operation unit retains the portion of the first processing waveform below the reference voltage Vos to form a second processing waveform Va (coordinated with Figure 8 (b)). The second operation unit amplifies the second processing waveform Va to generate a third processing waveform, wherein the second operation unit superimposes the third processing waveform with the AC current signal iload to form a fourth processing waveform (coordinated with Figure 8 (c)), wherein the second operation unit inverts the fourth processing waveform to output the current absolute value waveform |Vc| (matching Figure 8 (d)).

[0082] In some embodiments, the control unit 12 adjusts the duty cycles of the control signals e-PWM-N and ePWM-U, respectively, based on the magnitude of the current absolute value waveform |Vc| output by the waveform processing unit 10 , to control the multiple gate drivers 31 , 32 to selectively turn on or off the multiple switches 21 , 22 .

[0083] In some embodiments, the waveform processing unit 10 is typically provided with a current sensor (not shown), such as a Hall sensor. Thus, the waveform processing unit 10 can detect and receive the AC current signal iload from the AC power signal. However, the present invention is not limited thereto.

[0084] Specifically, the first operation unit includes a first operational amplifier OPA1, a first resistor R1, a second resistor R2, a third resistor R3, a first diode D1, and a second diode D2. The first operational amplifier OPA1 includes a negative input terminal, a positive input terminal, and an output terminal. The first terminal of the first resistor R1 is coupled to the AC current signal iload, and the second terminal of the first resistor R1 is connected to the negative input terminal of the first operational amplifier OPA1. The first terminal of the second resistor R2 is coupled to the reference voltage Vos, and the second terminal of the second resistor R2 is connected to the positive input terminal of the first operational amplifier OPA1. The first terminal of the third resistor R3 is connected to the second terminal of the first resistor R1. The anode of the first diode D1 is connected to the second terminal of the third resistor R3. The cathode of the second diode D2 is connected to the second terminal of the first resistor R1, and the anode of the second diode D2 is connected to the cathode of the first diode D1 and the output terminal of the first operational amplifier OPA1 to generate the second processed waveform Va. In some embodiments, the first terminal of the first resistor R1 is connected to a current sensor (not shown) provided in the waveform processing unit 10 to receive the AC current signal iload, but the present invention is not limited to this.

[0085] The second operation unit includes a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a second operational amplifier OPA2, and a seventh resistor R7. The first end of the fourth resistor R4 is connected to the second end of the third resistor R3. The first end of the fifth resistor R5 is connected to the first end of the first resistor R1, and the second end of the fifth resistor R5 is connected to the second end of the fourth resistor R4. The first end of the sixth resistor R6 is connected to the second end of the fifth resistor R5 and the second end of the fourth resistor R4. The second operational amplifier OPA2 includes a negative input terminal, a positive input terminal, and an output terminal. The negative input terminal of the second operational amplifier OPA2 is connected to the first end of the sixth resistor R6, and the output terminal of the second operational amplifier OPA2 is connected to the second end of the sixth resistor R6. The first end of the seventh resistor R7 is connected to the first end of the second resistor R2, and the second end of the seventh resistor R7 is connected to the positive input terminal of the second operational amplifier OPA2. Figure 7 The waveform processing unit 10 shown is one of the implementable circuits, but the present invention is not limited to this implementation circuit. Any circuit that can perform signal absolute operation can be used as the waveform processing unit of the present invention.

[0086] In some embodiments, the fourth resistor R4 is half the size of the sixth resistor R6 , so the second operation unit amplifies the second processed waveform Va to twice the original second processed waveform Va to generate the third processed waveform 2Va, but the present invention is not limited thereto.

[0087] The control unit 12 receives DC power sources DC+ and DC- and an AC voltage signal Vo of the AC power, and adjusts the duty cycle of a first pulse-width modulation signal (not shown) based on the DC power sources DC+ and DC- and the AC voltage signal Vo to output a second pulse-width modulation signal ePWM. The second pulse-width modulation signal ePWM is a signal with an adjusted duty cycle compared to the first pulse-width modulation signal (not shown). In this embodiment, the control unit 12 may be a digital controller, i.e., one capable of digital signal processing, calculation, and control functions, and may be, but is not limited to, a microcontroller (MCU), a digital signal processor (DSP), a field-programmable gate array (FPGA), or an application-specific integrated circuit (ASIC).

[0088] In some other embodiments, the first pulse-width modulation signal (not shown) is a signal provided within the control unit 12. The control unit 12 typically adjusts the duty cycle of the first pulse-width modulation signal (not shown) to output the second pulse-width modulation signal ePWM based on the DC power sources DC+, DC- received by the power conversion module 20 and / or the AC power (including the AC voltage signal Vo and / or the AC current signal iload) output. Typically, the AC power includes the AC current signal iload and / or the AC voltage signal Vo, but the present invention is not limited thereto.

[0089] The weight unit 14 obtains the average voltage V1 of the second pulse width modulation signal ePWM, and superimposes the average voltage V1 and the trigger level signal iload-level to generate a trigger voltage Vx. This will be described in detail later. The comparator 16 couples the weight unit 14 and the waveform processing unit 10, receives the trigger voltage Vx and the current absolute value waveform |Vc|, and compares the trigger voltage Vx with the current absolute value waveform |Vc|. This will be described in detail later. When the comparator 16 determines that the current absolute value waveform |Vc| is greater than the trigger voltage Vx, the comparator 16 outputs the slew rate control signal EN SRC to each gate driver 31,32.

[0090] When each gate driver 31 , 32 does not receive the slew rate control signal EN SRC, and the control signal ePWM-U output by the control unit 12 turns on the upper switch 21 of the power conversion module 20, and the control signal ePWM-N output by the control unit 12 turns off the lower switch 22 of the power conversion module 20, the driving resistance setting value R of the gate driver 31 G-On1 With gate driver 32 R G-Off2 On the contrary, when the control signal ePWM-U output by the control unit 12 turns off the upper switch 21 and the control signal ePWM-N turns on the lower switch 22, the driving resistance setting value R of the gate driver 31 G-Off1 With gate driver 32 R G-On2 For parallel operation.

[0091] When each gate driver 31, 32 receives the slew rate control signal EN SRC When more resistors are connected in parallel, the driving resistance setting value R of each gate driver 31, 32 is reduced. G-On1 ,R G-Off1 ,R G-On2 ,R G-Off2 When each gate driver 31, 32 receives the slew rate control signal EN SRC When the driving resistance setting value of each gate driver 31, 32 is determined by the total driving resistance setting value R G-On1 ,R G-On2 and the drive resistance setting value R G-Off1 ,R G-Off2 Therefore, when all the drive resistors are set to R G-On1 ,R G-Off1 ,R G-On2 ,R G-Off2 When connected in parallel, the driving resistance setting value of each gate driver 31, 32 will be reduced.

[0092] For example, when each gate driver 31, 32 receives the slew rate control signal EN SRC When the control unit 12 outputs the control signals ePWM-U and ePWM-N to respectively turn on the upper switch 21 and turn off the lower switch 22, the driving resistance setting value R of the gate driver 31 is G-On1 and R G-On2 For parallel operation, the driving resistance setting value R of the gate driver 32 is G-Off1 and R G-Off2 Similarly, when each gate driver 31, 32 receives the slew rate control signal EN SRC When the control unit 12 outputs the control signals ePWM-U and ePWM-N to respectively turn off the upper switch 21 and turn on the lower switch 22, the driving resistance setting value R of the gate driver 31 is G-Off1 and RG-Off2 For parallel operation, the driving resistance setting value R of the gate driver 32 is G-On1 and R G-On2为 In this way, when each gate driver 31, 32 receives the slew rate control signal EN SRC When the driving resistance values ​​connected to the upper switch 21 and the lower switch 22 are both reduced, the switching losses of the upper switch 21 and the lower switch 22 are also reduced. Figure 1B shown.

[0093] See Figure 9 and Figure 10 As shown, it is divided into a circuit diagram of the weight unit of the present invention and a circuit block diagram of the weight unit applied to the power drive circuit. Figure 9 As shown, the weight unit 14 mainly has three terminals, including a first input terminal for receiving a first input voltage V1, a second input terminal for receiving a second input voltage V2, and an output terminal for providing a trigger voltage Vx. Figure 10 As shown, the weighting unit 14 includes a low-pass filter 141, an eighth resistor R8, and a ninth resistor R9. The low-pass filter 141 receives the second pulse-width modulation signal ePWM and outputs an average voltage V1 of the second pulse-width modulation signal ePWM. A first end of the eighth resistor R8 receives the average voltage V1. A first end of the ninth resistor R9 is coupled to the trigger level signal iload-level (i.e., voltage V2), and a second end of the ninth resistor R9 is connected to the second end of the eighth resistor R8 to generate a trigger voltage Vx.

[0094] The weight unit 14 includes an eighth resistor R8, a ninth resistor R9, and a capacitor Cw. One end of the eighth resistor R8, one end of the ninth resistor R9, and one end of the capacitor Cw are connected to the output terminal. The other end of the eighth resistor R8 is the first input terminal, the other end of the ninth resistor R9 is the second input terminal, and the other end of the capacitor Cw is connected to the ground terminal. Therefore, as shown in the figure, the relationship between the trigger voltage Vx output by the weight unit 14 and the first input voltage V1 and the second input voltage V2 is:

[0095] Vx=(V1×R9) / (R8+R9)+(V2×R8) / (R8+R9)

[0096] In the present invention, the first input voltage V1 is the average voltage V1 of the second pulse width modulation signal ePWM, and the second input voltage V2 is the trigger level signal iload-level.

[0097] As can be seen from the above equation, when the eighth resistor R8 and the ninth resistor R9 are fixed, the magnitude of the trigger voltage Vx is controlled by the first input voltage V1 and the second input voltage V2. When the first input voltage V1 and the second input voltage V2 increase simultaneously, the trigger voltage Vx rises. When the first input voltage V1 and the second input voltage V2 decrease simultaneously, the trigger voltage Vx decreases. If one of the first input voltage V1 and the second input voltage V2 increases and the other decreases, the trigger voltage Vx reacts based on the distribution (ratio) of the first input voltage V1 and the second input voltage V2, hence the term "weighted circuit."

[0098] When implemented in combination with a microcontroller (i.e., the control unit 12) and a hardware circuit, the weight unit 14 also includes a low-pass filter 141 and a voltage regulator circuit 142. The low-pass filter 141 is coupled to the eighth resistor R8, and receives the second pulse width modulation signal ePWM provided by the control unit 12, so as to convert the square wave high-frequency signal into a DC signal, that is, the average voltage of the second pulse width modulation signal ePWM obtained by the low-pass filter 141 is used as the first input voltage V1. The voltage regulator circuit 142 is coupled to the ninth resistor R9, and receives the trigger level signal iload-level, so as to perform a voltage regulation operation on the trigger level signal iload-level. Therefore, the voltage V2 can also be regarded as the trigger level signal iload-level after voltage regulation. Among them, the voltage regulator circuit 142 can be implemented in the form of a capacitor or a voltage follower.

[0099] It is worth mentioning that when using hardware circuits for SRC functions, it has the correct trigger level signal (such as a current trigger level signal or a temperature trigger level signal). However, because in the hardware circuit, the trigger level of the trigger signal usually generates an external fixed voltage signal, and this trigger signal needs to be corrected by replacing the components on the hardware circuit. In terms of adjusting the trigger level, the flexibility of the hardware circuit is poor. However, when using a firmware program with a microcontroller for the SRC function, the trigger level can be adjusted by reading the input voltage, output voltage, load command, or the selected model of the power switching component. In the completed program, the trigger level can be easily adjusted. However, the input information of the firmware program is limited by the sampling speed of the microcontroller. Therefore, in the correct slew rate control signal EN SRC In terms of action, its reaction speed is slow. Figure 10 It is to combine the hardware correct slew rate control signal EN SRC The trigger voltage Vx can be adjusted by the action and firmware program, and the results are presented with their respective advantages.

[0100] See Figures 11A-11CAs shown, it is a waveform diagram of the trigger voltage generated by the present invention. According to different duty cycles of the second pulse width modulation signal ePWM, different trigger voltages Vx can be obtained under a fixed (for convenience of explanation only, not to limit the present invention) trigger level signal iload-level. Among them, the average voltage of the second pulse width modulation signal ePWM serves as the first input voltage V1 of the weight unit 14, and the trigger level signal iload-level serves as the second input voltage V2 of the weight unit 14. In addition, the relationship between the output trigger voltage Vx and the input first input voltage V1 and second input voltage V2 is explained in conjunction with the aforementioned relationship formula.

[0101] by Figure 11A For example, the second pulse width modulation signal ePWM is output by the control unit 12 and is a square wave signal with a duty cycle of 50% and a voltage range of 0 to 3.3 volts. The trigger level signal iload-level is generated by the hardware circuit and is fixed at 1.65 volts. Furthermore, it is assumed that the eighth resistor R8 and the ninth resistor R9 are the same. Therefore, according to the above relationship, the trigger voltage Vx can be calculated:

[0102] Vx = (3.3 x 50% x R9) / (R8 + R9) + (1.65 x R8) / (R8 + R9) = 1.65 volts.

[0103] by Figure 11B For example, the second pulse width modulation signal ePWM has a duty cycle of 25% and a square wave signal with a magnitude of 0 to 3.3 volts. The trigger level signal iload-level is fixed at 1.65 volts. Furthermore, it is assumed that the eighth resistor R8 and the ninth resistor R9 are the same. Therefore, according to the above relationship, the trigger voltage Vx can be calculated as:

[0104] Vx = (3.3 x 25% x R9) / (R8 + R9) + (1.65 x R8) / (R8 + R9) = 1.2375 volts.

[0105] by Figure 11C For example, the second pulse width modulation signal ePWM is a square wave signal with an 80% duty cycle and a magnitude of 0 to 3.3 volts. The trigger level signal iload-level is fixed at 1.65 volts. Furthermore, it is assumed that the eighth resistor R8 and the ninth resistor R9 are the same. Therefore, according to the above relationship, the trigger voltage Vx can be calculated:

[0106] Vx = (3.3 x 80% x R9) / (R8 + R9) + (1.65 x R8) / (R8 + R9) = 2.145 volts.

[0107] Therefore, through Figures 11A-11CFrom the three examples, it can be seen that even if the voltage of the trigger level signal iload-level does not change, the firmware program can still cooperate with the control unit 12 to adjust the magnitude of the second pulse width modulation signal ePWM, thereby controlling the level of the trigger voltage Vx, thereby achieving a more flexible trigger level correction.

[0108] See Figure 12 As shown in FIG, it is a waveform diagram of the slew rate control signal generated by the present invention. The trigger voltage Vx obtained after the weight unit 14 performs weight calculation on the second pulse width modulation signal ePWM and the trigger level signal iload-level is compared with the current absolute value waveform |Vc| (via the comparator 16). Figure 6 When the current absolute value waveform |Vc| is greater than the trigger voltage Vx (but this is not a limitation, it can also be judged as greater than or equal to), the comparator 16 outputs the slew rate control signal EN SRC is high level, controlling the driving resistance value R of the gate driver 31 G-On1 With R G-On2 In parallel, and R G-Off1 With R G-Off2 In parallel, the gate driver 32 is also connected in the same way, so that the drive resistance setting value of the gate driver 31 and the gate driver 32 will be reduced. On the contrary, if the current absolute value waveform |Vc| is less than or equal to the trigger voltage Vx (but this is not a limitation, it can also be judged as less than), the slew rate control signal EN output by the comparator 16 SRC = is low level, so the driving resistance setting value of the gate driver 31 is determined by the state of the upper switch 21 being on or off and is only the driving resistance setting value R G-On1 operation or just drive the resistor setting value R G-Off1 operation, or the state of the lower switch 22 being on or off determines only the drive resistance setting value R G-On2 operation or just drive the resistor setting value R G-Off2 Similarly, the driving resistance setting value of the gate driver 32 is also restored. The driving resistance setting value R is determined by the state of the upper switch 21 being on or off. G-On1 operation or just drive the resistor setting value R G-Off1 operation, or the state of the lower switch 22 being on or off determines only the drive resistance setting value R G-On2 operation or just drive the resistor setting value R G-Off2 operate.

[0109] Please see again Figure 6 The power conversion module 20 further includes a temperature sensor 23 for detecting the operating temperature V of the power conversion module 20. T . And the operating temperature V TThe information is transmitted to the control unit 12. Therefore, when the control unit 12 determines the operating temperature V T When the temperature is higher than the threshold, the control unit 12 adjusts the duty cycle of the first pulse width modulation signal to zero. Thus, according to the relationship between the trigger voltage Vx and the first input voltage V1 and the second input voltage V2, once the duty cycle of the first pulse width modulation signal is zero, the trigger voltage Vx calculated according to the relationship will be significantly reduced. Therefore, the current absolute value waveform |Vc| is easily greater than the trigger voltage Vx, and it is possible to achieve the following when the operating temperature V T When it is too high, set the value R G-On1 With R G-On2 In parallel, and R G-Off1 With R G-Off 2 are connected in parallel to reduce the driving resistance setting value of each gate driver 31, 32.

[0110] See Figure 13 , which is a flow chart of the operating method of the power driving circuit of the present invention. The operating method of the power driving circuit is used for the power driving circuit. The operating method includes the following steps: first, the DC power supply DC+, DC- is converted into AC power Vo by the power conversion module 20 (S11). Then, an absolute value operation program is executed to obtain the current absolute value waveform |Vc| of the AC current signal of the AC power (S12). Then, the duty cycle of the first pulse width modulation signal is adjusted according to the DC power supply DC+, DC- and the AC voltage signal of the AC power to form a second pulse width modulation signal ePWM (S13). Then, the average voltage V1 of the second pulse width modulation signal ePWM is obtained (S14). Then, the average voltage V1 and the trigger level signal iload-level are superimposed to generate a trigger voltage Vx (S15). Then, the current absolute value waveform |Vc| is compared with the trigger voltage Vx (S16). When the current absolute value waveform |Vc| is greater than the trigger voltage Vx, the slew rate control signal EN is output. SRC To each gate driver 31, 32 (S17). When each gate driver 31, 32 receives the slew rate control signal EN SRC , respectively reduce the driving resistance setting value of each gate driver 31, 32 (S18), for example: the driving resistance setting value R G-On1 With R G-On2 In parallel, and R G-Off1 With R G-Off2 in parallel.

[0111] In summary, the present invention has the following features and advantages: It leverages the hardware circuit's high responsiveness to sensing signals and utilizes a weighting circuit in conjunction with firmware to flexibly adjust the gate driver's drive resistance setting. This allows for dynamic adjustment of the gate driver's drive resistance setting based on an optimization program in different application scenarios, ensuring highly accurate SRC function activation. Furthermore, the device allows for user-defined operations through a human-machine interface or communication methods, enhancing flexibility and versatility.

[0112] The above description is only a detailed description and drawings of preferred specific embodiments of the present invention, and the features of the present invention are not limited thereto and are not intended to limit the present invention. The full scope of the present invention shall be based on the claims. All embodiments that are consistent with the concepts of the claims of the present invention and similar variations thereof shall be included in the scope of the present invention. Any changes or modifications that can be easily conceived by any person skilled in the art within the field of the present invention shall be covered by the claims of this disclosure.

Claims

1. A power drive circuit comprising: A power conversion module comprising a plurality of switches, wherein the power conversion module receives a DC power source to output an AC power; a plurality of gate drivers, wherein each of the plurality of gate drivers is respectively connected to a control terminal of each of the plurality of switches, and each of the plurality of gate drivers includes a driving resistance setting value; a waveform processing unit coupled to an AC current signal of the AC power to output a current absolute value waveform of the AC current signal; a control unit, adjusting a duty cycle of a first pulse width modulation signal according to the DC power source and an AC voltage signal of the AC power to output a second pulse width modulation signal; a weighting unit, obtaining an average voltage of the second pulse width modulation signal, and superimposing the average voltage with a trigger level signal to generate a trigger voltage; as well as a comparator, wherein when the comparator determines that the current absolute value waveform is greater than the trigger voltage, the comparator outputs a slew rate control signal to each of the plurality of gate drivers; When each of the plurality of gate drivers receives the slew rate control signal, the driving resistance setting value of each of the plurality of gate drivers is respectively reduced.

2. The power driving circuit as claimed in claim 1, wherein when the comparator determines that the current absolute value waveform is not greater than the trigger voltage, the comparator stops outputting the slew rate control signal to restore the driving resistance setting value of each of the plurality of gate drivers.

3. The power driving circuit as claimed in claim 1 , wherein the control unit is further configured to detect an operating temperature of the power conversion module; when the control unit determines that the operating temperature is higher than a temperature threshold, the control unit adjusts the duty cycle of the first pulse width modulation signal to zero. 4 . The power driving circuit as claimed in claim 1 , wherein the control unit controls the plurality of gate drivers according to the current absolute value waveform to adjust the plurality of switches to be selectively turned on or off.

5. The power driving circuit as claimed in claim 1 , wherein the waveform processing unit comprises: a first operating unit receiving a reference voltage, wherein the first operating unit inverts the AC current signal to generate a first processing waveform, and the first operating unit retains a portion of the first processing waveform below the reference voltage to form a second processing waveform; as well as A second operation unit amplifies the second processing waveform to generate a third processing waveform, wherein the second operation unit superimposes the third processing waveform with the AC current signal to form a fourth processing waveform, wherein the second operation unit inverts the fourth processing waveform to output the current absolute value waveform.

6. The power driving circuit as claimed in claim 5, wherein the first operation unit comprises: a first operational amplifier comprising a negative input terminal, a positive input terminal, and an output terminal; a first resistor, wherein a first end of the first resistor is coupled to the AC current signal, and a second end of the first resistor is connected to the negative input terminal of the first operational amplifier; a second resistor, wherein a first end of the second resistor is coupled to the reference voltage, and a second end of the second resistor is connected to the positive input terminal of the first operational amplifier; a third resistor, wherein a first end of the third resistor is connected to the second end of the first resistor; a first diode, wherein an anode of the first diode is connected to a second end of the third resistor; and a second diode, wherein a cathode of the second diode is connected to the second end of the first resistor, and an anode of the second diode is connected to a cathode of the first diode and the output end of the first operational amplifier to generate the second processed waveform.

7. The power driving circuit as claimed in claim 6, wherein the second operation unit comprises: a fourth resistor, wherein a first end of the fourth resistor is connected to the second end of the third resistor; a fifth resistor, wherein a first end of the fifth resistor is connected to the first end of the first resistor, and a second end of the fifth resistor is connected to a second end of the fourth resistor; a sixth resistor, wherein a first end of the sixth resistor is connected to the second end of the fifth resistor and the second end of the fourth resistor; a second operational amplifier comprising a negative input terminal, a positive input terminal, and an output terminal, wherein the negative input terminal of the second operational amplifier is connected to the first terminal of the sixth resistor, and the output terminal of the second operational amplifier is connected to a second terminal of the sixth resistor; and a seventh resistor, wherein a first end of the seventh resistor is connected to the first end of the second resistor, and a second end of the seventh resistor is connected to the positive input end of the second operational amplifier. 8 . The power driving circuit as claimed in claim 7 , wherein a size of the fourth resistor is half a size of the sixth resistor.

9. The power driving circuit according to claim 1 , wherein the weight unit comprises: a low-pass filter, receiving the second pulse width modulation signal and outputting the average voltage of the second pulse width modulation signal; an eighth resistor, wherein a first terminal of the eighth resistor receives the average voltage; and a ninth resistor, wherein a first terminal of the ninth resistor is coupled to the trigger level signal, and a second terminal of the ninth resistor is connected to a second terminal of the eighth resistor to generate the trigger voltage.

10. The power driving circuit as claimed in claim 9, wherein the relationship among the trigger voltage, the average voltage and the trigger level signal is: Vx=(V1×R9) / (R8+R9)+(V2×R8) / (R8+R9), in, Vx is the trigger voltage, V1 is the average voltage of the second pulse width modulation signal, V2 is the trigger level signal, R8 is the eighth resistor, and R9 is the ninth resistor.

11. A control method for a power drive circuit, wherein the power drive circuit includes a power conversion module and a plurality of gate drivers, each of the plurality of gate drivers being connected to each of the plurality of switches in the power conversion module, and each of the plurality of gate drivers including a drive resistance setting value, wherein the control method comprises: Converting a DC power source into an AC power through the power conversion module; executing an absolute value calculation program to obtain a current absolute value waveform of an AC current signal of the AC power; Adjusting a duty cycle of a first pulse width modulation signal according to the DC power source and an AC voltage signal of the AC power to form a second pulse width modulation signal; obtaining an average voltage of the second pulse width modulation signal; superimposing the average voltage and a trigger level signal to generate a trigger voltage; as well as comparing the current absolute value waveform with the trigger voltage; When the current absolute value waveform is greater than the trigger voltage, a slew rate control signal is output to each of the plurality of gate drivers; When each of the plurality of gate drivers receives the slew rate control signal, the driving resistance setting value of each of the plurality of gate drivers is respectively reduced. 12 . The control method of claim 11 , wherein when the current absolute value waveform is not greater than the trigger voltage, the slew rate control signal is stopped from being output to restore the driving resistance setting value of each of the plurality of gate drivers.

13. The control method according to claim 11, further comprising: detecting an operating temperature of the power conversion module; When the operating temperature is higher than a temperature threshold, the duty cycle of the first pulse width modulation signal is adjusted to zero.

14. The control method according to claim 11, further comprising: The plurality of gate drivers are controlled according to the current absolute value waveform to adjust the plurality of switches to be selectively turned on or off.

15. The control method as claimed in claim 11, wherein the absolute value calculation process comprises: inverting the AC current signal to generate a first processed waveform; retaining a portion of the first processed waveform below a reference voltage to form a second processed waveform; amplifying the second processed waveform to generate a third processed waveform; superimposing the third processed waveform and the AC current signal to form a fourth processed waveform; as well as The fourth processed waveform is inverted to output the current absolute value waveform.

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