Processors and computing systems

Abstract

The present disclosure relates to a processor and a computing system. A processor is provided, comprising: a pipeline stage, the pipeline stage including a timing device; a first clock driving circuit for providing a clock signal to the pipeline stage, the clock driving circuit comprising: a plurality of first clock paths, each providing a corresponding clock signal; and a first selector for selecting a clock signal from the clock signals provided by the plurality of first clock paths for use in the pipeline stage.

Description

Technical Field

[0001] The present disclosure relates to processors and computing systems. Background Art

[0002] In recent years, digital currencies have received increasing attention, and in related fields, improved processors and computing systems are needed.

[0003] Mining processors typically use a pipeline architecture. Based on the algorithm, the computational logic is divided into several pipeline stages, each with similar functional design and computational structure. Each stage requires an input clock, often called a pulse clock.

[0004] As mining processors utilize more advanced manufacturing processes, their complexity and discreteness are increasing. This leads to significant discrepancies between the processor's actual operating conditions and the simulation environment used during the design phase. Even if the clock driver circuit meets the clock requirements under simulation conditions during the design phase, the actual processor often fails to meet the design requirements due to differences in the simulation environment.

[0005] Therefore, there is a need for improved processors and computing systems. Summary of the Invention

[0006] According to one aspect of the present disclosure, a processor is provided, comprising: a pipeline stage, the pipeline stage including a timing device; and a clock driving module for providing a clock signal to the pipeline stage, the clock driving module including a first clock driving circuit, the first clock driving circuit including: multiple first clock paths, respectively providing corresponding clock signals; and a first selector for selecting a clock signal from the clock signals provided by the multiple first clock paths for use in the pipeline stage.

[0007] In some embodiments, the processor includes one or more cores, and the pipeline stage and the clock driving module are set in the core.

[0008] In some embodiments, the clock driving module further includes: a second clock driving circuit for adjusting the pulse width of the clock signal selected by the selector and providing a pulse width adjusted clock signal for the pipeline stage.

[0009] In some embodiments, the second clock driving circuit includes: multiple second clock paths, which respectively receive the selected clock signals and provide clock signals of different phases on each second clock path based on the selected clock signals; a logic unit, which generates a pulse-width-adjusted clock signal for the pipeline stage based on at least a portion of the clock signals of different phases.

[0010] In some embodiments, the plurality of second clock paths include at least a first path and a second path, wherein the first path provides the selected clock signal to the logic unit, and the second path provides an inverted version or an inverted and delayed version of the selected clock signal to the logic unit.

[0011] In some embodiments, the logic unit is an AND gate or an OR gate.

[0012] In some embodiments, the second path includes: an inverter that receives the selected clock signal and generates a clock signal that is inverted to the selected clock signal; one or more sub-paths for respectively providing corresponding versions of the inverted clock signal to a second selector; and the second selector that selects from different versions of the inverted clock signal and provides the selected version to the logic unit.

[0013] In some embodiments, the one or more sub-paths respectively provide different delayed versions of the inverted clock signal to the second selector.

[0014] In some embodiments, the plurality of first clock paths receive a common clock input and respectively provide clock signals of different phases based on the clock input.

[0015] In some embodiments, the processor is a processor for digital currency.

[0016] In some embodiments, the sequential device includes one or more latches, and the selected clock signal is used for the one or more latches.

[0017] According to another aspect of the present disclosure, a computing system is provided, which includes the processor according to any embodiment of the present disclosure.

[0018] Other features and advantages of the present disclosure will become apparent from the following detailed description of exemplary embodiments of the present disclosure with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0020] The present disclosure can be more clearly understood from the following detailed description with reference to the accompanying drawings, in which:

[0021] Figure 1 A schematic diagram of an exemplary pipeline processor is shown;

[0022] Figure 2 A schematic diagram of a processor according to an embodiment of the present disclosure is shown;

[0023] Figure 3 A schematic diagram of a processor according to another embodiment of the present disclosure is shown;

[0024] Figure 4 A schematic diagram of a processor according to another embodiment of the present disclosure is shown;

[0025] Figure 5 An exemplary timing diagram illustrating a pipeline according to one embodiment of the present disclosure; and

[0026] Figure 6 A schematic diagram of a latch in a processor according to an embodiment of the present disclosure is shown.

[0027] Note that in the embodiments described below, the same reference numerals are sometimes used in common across different drawings to denote the same parts or parts having the same functions, and their repeated descriptions are omitted. In this specification, similar reference numerals and letters are used to denote similar items. Therefore, once an item is defined in one drawing, it need not be further discussed in subsequent drawings.

[0028] For ease of understanding, the positions, sizes, and ranges of various components shown in the drawings and the like may not represent actual positions, sizes, and ranges. Therefore, the disclosed invention is not limited to the positions, sizes, and ranges disclosed in the drawings and the like. DETAILED DESCRIPTION

[0029] Various exemplary embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. It should be noted that, unless otherwise specifically stated, the relative arrangement of components and steps, numerical expressions, and numerical values ​​set forth in these embodiments do not limit the scope of the present disclosure. Furthermore, techniques, methods, and apparatus known to those skilled in the art may not be discussed in detail, but, where appropriate, such techniques, methods, and apparatus should be considered part of the specification.

[0030] It should be understood that the following description of at least one exemplary embodiment is merely illustrative and does not limit the present disclosure, its application, or use. It should also be understood that any implementation described herein by way of example does not necessarily imply that it is preferred or advantageous over other implementations. The present disclosure is not intended to be limited by any expressed or implied theory presented in the foregoing technical field, background technology, summary of the invention, or detailed description.

[0031] In addition, certain terms may be used in the following description for reference purposes only and are not intended to be limiting. For example, the words "first," "second," and other numerical terms referring to structures or elements do not imply a sequence or order unless the context clearly indicates otherwise.

[0032] It should also be understood that when the term “include / comprises” is used in this document, it indicates the presence of the specified features, integers, steps, operations, units and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, units and / or components and / or their combinations.

[0033] Figure 1 A schematic diagram of an exemplary pipeline processor is shown. In a conventional pipeline processor, the operating clock of each pipeline stage usually comes from the same clock source and is transmitted between the pipeline stages through the clock driving circuits at each stage of the pipeline, such as Figure 1 shown.

[0034] On the other hand, processor pipeline stages often have one or more sequential devices, such as flip-flops. Choosing latches as sequential devices in the pipeline can effectively reduce power consumption and area overhead, improving the competitiveness of mining machine products.

[0035] For pipeline designs using latches, the clocks between adjacent pipelines must meet certain phase requirements to satisfy the latch's specific timing requirements, such as the latch hold timing requirements and the latch's minimum pulse width requirements. This places higher demands on the design and manufacturing process of clock-related circuits. However, with the use of advanced processes, process complexity and discreteness are increasing, resulting in a large deviation between the actual operating conditions of the processor and the simulation environment during the design phase. Even if the clock driver circuit meets the clock requirements under simulation conditions during the design phase, the actual processor often fails to meet the design requirements due to the difference with the simulation environment. This also limits the yield of the processor.

[0036] The inventors of the present application recognized one or more of the problems set forth above and have proposed the improved processor and computing system disclosed herein.

[0037] Figure 2 A schematic diagram of a processor according to an embodiment of the present disclosure is shown.

[0038] According to an embodiment of the present disclosure, a processor is provided. Figure 2 As shown, the processor may include a clock driving module (not shown) and a pipeline stage 120. The clock driving module may include a clock driving circuit (first clock driving circuit) 100. The pipeline stage 120 may include a timing device, such as a trigger or a latch. Preferably, the timing device is a latch. The clock driving circuit 100 may be used to provide a clock signal to the pipeline stage. Figure 2In the illustrated embodiment, the clock driving module may also be indicated by reference numeral 100. In other embodiments, as will be shown in subsequent figures, the clock driving module may further include other components in addition to the first clock driving circuit 100.

[0039] A latch is a storage unit circuit that is sensitive to pulse levels and is a sequential device. Figure 6 A schematic diagram of a latch in a processor according to one embodiment of the present disclosure is shown. The latch may include a tri-state gate and an inverter / buffer. The tri-state gate receives an input D, a clock signal, and an inverted clock signal. The output of the tri-state gate is connected to an inverter / buffer (INV / BUF). The output of the inverter / buffer (INV / BUF) serves as the output Q of the latch.

[0040] A key latch specification is the minimum pulse width of the clock pulse, or the length of time the high or low clock level must remain when the latch device is in the on state. In other words, the latch has certain requirements for the duty cycle of the high or low level. Another important latch specification is the latch hold timing, or the minimum time the signal at the latch input must remain unchanged after the clock latches in.

[0041] Back to Figure 2 ,like Figure 2 As shown, the clock driving circuit 100 may include multiple clock paths (first clock paths) 101 and 103, etc., which respectively provide corresponding clock signals to the selector MUX0. Figure 2 Only the clock paths 101 and 103 are exemplarily shown in FIG. 8 . However, in other embodiments, the clock driving circuit may include more clock paths (first clock paths).

[0042] In some embodiments, each clock path can receive the same input clock and perform various delays and / or inversions on the input clock to produce different versions of the clock signal. For example, in some embodiments, each clock path provides different delays and / or inversions to the input clock; in other embodiments, some clock paths may provide the same delay or inversion. At least some of the clock paths may include a clock adjustment unit 105, such as a buffer or inverter, to adjust properties of the clock signal, such as the phase. As shown in the figure, clock path 101 has a buffer (assuming a delay of τ) and an inverter (for inversion), while clock path 103 has two buffers (assuming a delay of τ) and an inverter (for inversion). These buffers delay the input clock differently, thereby providing a clock signal version that is inverted and delayed by τ and a clock signal version that is inverted and delayed by 2τ. In some cases, clock paths may also be provided without the adjustment unit 105. It should also be understood that the phase adjustment unit can be provided as needed.

[0043] The clock driving circuit 100 may include the selector (first selector) MUX0 107 for selecting a clock signal from the clock signals provided by the plurality of first clock paths for use in the corresponding pipeline stage 120. For example, the selector 107 may select a clock signal from the plurality of first clock paths based on a selection signal (e.g., selection signal 0) to provide the selected clock signal as a clock output 111 to the pipeline stage 120 or the next pipeline stage.

[0044] Under the actual working conditions of the processor, the clock signal can be selected (signal 0) to determine which clock signal is used as the output clock to meet the timing requirements of the pipeline stage, such as the hold timing of the latch and the minimum clock pulse width requirements.

[0045] like Figure 2 As shown, clocks with different delays on clock paths 101 and 103 arrive at the two inputs of MUX0. Select signal 0 can be set as needed to select one of the two clock paths as the clock output for the clock driver circuit of the current pipeline stage and / or the next pipeline stage. The clock phases in two adjacent pipeline stages can be adjusted separately (each with two (or more) different delays) to better meet the timing requirements of the latches in each pipeline stage.

[0046] In some other embodiments, the processor may have one or more cores, and the aforementioned pipeline stages and clock driving circuits may be arranged in the cores.

[0047] Figure 3 FIG2 shows a schematic diagram of a processor according to another embodiment of the present disclosure. Figure 2 The embodiment of the processor shown, Figure 3 The clock driving module in the processor in the illustrated embodiment further includes another clock driving circuit (second clock driving circuit) 200 , which receives the clock output provided from the clock driving circuit 100 and provides a further regulated clock output to the pipeline stage 120 .

[0048] Here, with Figure 2 The same parts in the embodiments are given the same numbers, and the above Figure 2 The contents described may be applied here identically or adaptively, and therefore repeated description thereof will be omitted.

[0049] In some embodiments, the second clock driving circuit 200 is configured to adjust the pulse width of the clock signal selected by the selector MUX0 107 and provide the pulse width adjusted clock signal for the pipeline stage.

[0050] It should be noted that, "a clock signal is used for the sequential device to be tested" is intended to mean that the clock signal can be directly used for (e.g., directly provided to) the sequential device to be tested, or the clock signal can be indirectly used for (e.g., indirectly rather than directly provided to) the sequential device to be tested. In other words, an intermediate module or device may exist between the clock signal and the sequential device to be tested, and the intermediate module or device may provide a clock to the sequential device to be tested based on the clock signal.

[0051] In a specific implementation, Figure 3 As shown, the second clock driving circuit 200 may include multiple second clock paths 201, 203, etc., which respectively receive the selected clock signal and provide clock signals of different phases to the logic unit 205 based on the selected clock signal on each second clock path. The logic unit 205 generates a pulse-width-modulated clock signal for the pipeline stage 120 based on at least a portion of the clock signals of different phases. In some specific embodiments, the logic unit 205 may be an AND gate or an OR gate; the present disclosure is not limited thereto.

[0052] The plurality of second clock paths include at least a first path and a second path. Figure 3 In the example shown, the first path 201 can be configured to directly provide the clock output received from MUX0 (i.e., the selected clock signal described above) to the logic unit 205. The second path 203 can be configured to provide a further conditioned version (e.g., an inverted version or an inverted and delayed version) of the clock output received from MUX0 to the logic unit 205.

[0053] As shown in the figure, the second path 203 may include an inverter 207. The inverter 207 receives the clock output (i.e., the selected clock signal) 111 of the first clock driving circuit 100 and generates a clock signal that is inverted with respect to the clock output (i.e., the selected clock signal) 111. The second path 203 may also include one or more sub-paths, such as the sub-paths 209 and 211 shown in the figure. The sub-paths 209 and 211 respectively provide corresponding versions of the inverted clock signal to the second selector 215. For example, in Figure 3 In the example shown, subpath 211 delays the inverted clock signal via a buffer, thereby providing a delayed version of the inverted clock signal, while subpath 209 provides the unprocessed inverted clock signal. Thus, the inverter output signal reaches the two input terminals of selector MUX1 via two clock transmission paths with different delays. It should also be understood that the presence of inverter 207 can be configured as needed, and its location and number can also be adjusted as needed.

[0054] The second selector MUX1 215 selects from different versions of the inverted clock signal and provides the selected version to the logic unit. MUX1 can select an appropriate clock path delay to meet the pulse width requirements of the timing devices (e.g., latches) in the current stage of the pipeline.

[0055] exist Figure 3 In the example shown, the clock provided to the current pipeline stage can be generated by the clock output signal of the first clock driver circuit 100 of the current pipeline stage and different inverted clock versions of the clock output signal through a logic unit (e.g., an OR gate or an AND gate logic). The pulse width of the clock provided to the current pipeline stage can be determined by the phase of the output signal of the first clock driver circuit of the current pipeline stage and its selected inverted clock version (i.e., the delay time of the inverted clock version relative to the clock output signal).

[0056] Selector MUX1 can select one of two (or more) sub-clock paths as one input to logic unit 205 based on selection signal 1, while the other input to logic unit 205 is the clock output signal of the first clock driver circuit of the current pipeline stage. In this way, the output signal of logic unit 205 serves as the clock signal for the current pipeline stage (especially the latch device therein), making the duty cycle width adjustable.

[0057] Figure 4 FIG. 1 shows a schematic diagram of a processor according to another embodiment of the present disclosure. Figure 4 In the embodiment shown, multiple pipeline stages and clock driver modules corresponding to each pipeline stage are illustrated. Each clock driver module shown may include the clock driver circuits 100 and / or 200 described in the previous embodiments. The contents described above for each embodiment are also applicable to this embodiment, and therefore no further details will be provided.

[0058] In addition, although Figure 4 In the example shown in FIG, the selection signals of each stage are shown as selection signal 0 and selection signal 1, but it should be understood that the selection signals of each stage can also be set independently.

[0059] Figure 5 An exemplary timing diagram of a pipeline according to one embodiment of the present disclosure is shown. Figure 5 The example shown in Figure 4 The three pipeline stages P1, P2, and P3 are shown in the figure. As shown in the figure, MUX0 in each pipeline stage can be used to control the delay of the clock provided to the pipeline stage, while MUX1 can be used to control the width of the clock pulse. This can meet the pipeline timing requirements, such as the latch hold timing requirements and the minimum latch pulse width requirements.

[0060] It should be understood that the above Figure 3 The second clock driving circuit described in the above and other embodiments may also be provided in the core of the processor together with the first clock driving circuit.

[0061] The processor according to the embodiment of the present disclosure can be used for digital currency processing or calculation. Examples of digital currencies include Bitcoin, Litecoin, Ethereum, and other digital currencies.

[0062] It should also be understood that the present disclosure also provides a computing system, which may include the processor as described in any embodiment.

[0063] According to the embodiments of the present disclosure, a novel processor and computing system are provided. The processor and computing system according to the present disclosure can be used for processing and computing digital currency or virtual currency. According to the embodiments of the present disclosure, a flexibly configurable clock path is provided, and multiple clock options are provided for pipeline stages. Figure 3 For example, the embodiment provides (number of input paths for MUX0 = 2) x (number of input paths for MUX1 = 2) = 4 clock options. The more paths, the more options are available. According to the disclosed embodiments, flexible clock configurations can be provided for each stage of the pipeline, greatly improving the design flexibility and product yield of mining processors.

[0064] Those skilled in the art will appreciate that the description of the boundaries between operations (or steps) in the above-described embodiments is merely illustrative. Multiple operations can be combined into a single operation, and a single operation can be distributed among additional operations, and operations can be performed at least partially overlapping in time. Moreover, alternative embodiments can include multiple instances of specific operations, and in other various embodiments, the order of operations can be changed. However, other modifications, variations, and replacements are possible as well. Therefore, this specification and accompanying drawings should be considered as illustrative, not restrictive.

[0065] Although some specific embodiments of the present disclosure have been described in detail by way of examples, it should be understood by those skilled in the art that the above examples are for illustration only and are not intended to limit the scope of the present disclosure. The various embodiments disclosed herein may be combined in any manner without departing from the spirit and scope of the present disclosure. It should also be understood by those skilled in the art that various modifications may be made to the embodiments without departing from the scope and spirit of the present disclosure. The scope of the present disclosure is defined by the appended claims.

Claims

1. A processor, characterized in that: include: a first pipeline stage, the first pipeline stage comprising a sequential device; as well as A clock driving module for the first pipeline stage, configured to provide a clock signal to the first pipeline stage, the clock driving module comprising: A first clock driving circuit, wherein the first clock driving circuit comprises: a plurality of first clock paths, configured to receive a common clock input and respectively provide corresponding clock signals, at least one of the plurality of first clock paths delaying or inverting the common clock input; and a first selector, configured to select a clock signal from the clock signals provided by the plurality of first clock paths; and The second clock driving circuit is used to adjust the pulse width of the clock signal selected by the selector and provide the pulse width adjusted clock signal for the first pipeline stage.

2. The processor according to claim 1, wherein: One of the corresponding clock signals has a different delay or phase inversion relative to the other.

3. The processor according to claim 1, wherein: The second clock driving circuit includes: a plurality of second clock paths, each receiving the selected clock signal and providing a clock signal of a different phase based on the selected clock signal on each second clock path; The logic unit generates a pulse width modulated clock signal for the first pipeline stage based on at least a portion of the clock signals of different phases.

4. The processor according to claim 3, wherein: wherein the plurality of second clock paths include at least a first path and a second path, The first path provides the selected clock signal to the logic unit, and The second path provides an inverted version or an inverted and delayed version of the selected clock signal to the logic unit.

5. The processor according to claim 3, wherein: The logic unit is an AND gate or an OR gate.

6. The processor according to claim 4, wherein: The second path includes: an inverter receiving the selected clock signal and generating a clock signal inverted with respect to the selected clock signal; one or more sub-paths for respectively providing corresponding versions of the inverted clock signal to the second selector; and The second selector selects from different versions of the inverted clock signal and provides the selected version to the logic unit.

7. The processor according to claim 6, wherein: The one or more sub-paths respectively provide different delayed versions of the inverted clock signal to the second selector.

8. The processor according to claim 1, wherein: comprising one or more cores, wherein the first pipeline stage and the clock driving module are disposed in the cores; The processor is a processor for digital currency.

9. The processor according to claim 1, wherein: The timing device includes one or more latches, and the selected clock signal is used for the one or more latches.

10. The processor according to claim 1, wherein: Also includes: a second pipeline stage, the second pipeline stage comprising a sequential device; as well as A clock driving module for the second pipeline stage is configured to receive the clock signal selected by the first selector and provide the clock signal to the second pipeline stage.

11. A computing system comprising the processor according to any one of claims 1 to 10.

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