A parasitic parameter extraction method based on target detection network

Abstract

This invention discloses a parasitic parameter extraction method based on a target detection network, belonging to the field of parasitic parameter extraction. The method includes the following steps: establishing a parasitic capacitance pattern library; creating a dataset that matches the characteristics of the layout interconnects; training the target detection network using the self-built dataset and optimizing the network by modifying the loss function; using the trained network to predict the layout image, and subsequently processing the network's prediction results to obtain parasitic parameter values. This invention aims to provide a simple, alternative solution for establishing parasitic parameter pattern libraries and pattern matching for digital integrated circuits.

Description

Technical Field

[0001] The present invention relates to the field of parasitic parameter extraction, and in particular to a parasitic parameter extraction method based on a target detection network. Background Art

[0002] Parasitic parameter extraction is a step in the back-end process of digital integrated circuit design. It extracts the parasitic resistance and capacitance of interconnects from a layout that has completed layout and routing. As the process node advances, the parasitic capacitance and resistance caused by interconnects will gradually increase the impact on circuit timing. At the same time, the larger the scale of the integrated circuit, the higher the requirements for the extraction capability and efficiency of parasitic parameter extraction tools. Common extraction methods can be divided into field solution and pattern matching. The pattern matching method establishes a pattern library in advance based on the geometric structure and geometric parameters. During extraction, the actual layout is compared with the pattern library to obtain the resistance and capacitance values. This method is more suitable for large-scale circuits, but it often causes errors due to pattern matching errors, and the establishment of the pattern library is time-consuming and labor-intensive.

[0003] The industrial application of artificial intelligence has opened up a new path for extraction tools. Clustering algorithms can automatically build pattern libraries, replacing the lengthy manual process. Furthermore, the application of neural networks for classification in the matching process can improve matching efficiency and accuracy. However, previous layout research has focused on cross-sections, dividing the three-dimensional layout structure into two-dimensional parasitic parameters per unit length and then accumulating them. In reality, if each layer of the layout is treated as an image, image processing methods can be applied to directly extract the planar information of that layer. Summary of the Invention

[0004] To address the shortcomings of the aforementioned existing technologies, the present invention proposes a parasitic parameter extraction method based on a target detection network. This method simplifies the creation of a pattern library and uses the target detection network to classify and locate the geometric structures of interconnects in the layout. The network output is then compared with the pattern library to achieve accurate pattern matching. This invention aims to provide a simple, alternative solution for establishing and matching parasitic parameter pattern libraries for digital integrated circuits.

[0005] To achieve the above objectives, the present invention adopts the following technical solutions: a parasitic parameter extraction method based on a target detection network, generating a set of pictures and labeling files of similar layouts, creating a training set, optimizing the loss function, training the target detection network, inputting other layout pictures into the trained network, the network will output pattern and coordinate information, compare the pattern library, locate the wires, and obtain the parasitic capacitance value.

[0006] The specific steps include:

[0007] Step 1: Create a parasitic capacitance model library;

[0008] Step 2: Generate images that conform to the characteristics of the layout interconnect lines and annotate them to build a dataset;

[0009] Step 3: Use the dataset to train the target detection network and optimize the target detection network by optimizing the loss function;

[0010] Step 4: Use the trained target detection network to predict the layout image, and then process the network's prediction results to obtain the parasitic parameter values.

[0011] Preferably, the specific steps of step 1 are: setting different colors to represent different wire layers or wire overlapping relationships, and separately listing the capacitance formula lookup table of the surface capacitance with respect to the geometric structure (including layer relationship, wire spacing range on the same layer), and the capacitance formula lookup table of the coupling capacitance with respect to the geometric structure (number of conductors on the same layer).

[0012] Preferably, the specific steps of step 2 are: using color blocks of different colors to represent different wire layers or wire overlapping relationships (the overlapping relationship of wires in different layers or the overlapping relationship of wires in the same layer), randomly generating some color blocks of different colors, sizes, vertical or horizontal colors in the central area of the picture as interference backgrounds, and on the interference backgrounds, randomly generating target color blocks representing the overlapping relationships of the wires according to the proportion of the overlapping parts of the actual layout to the wires, and exporting the categories and coordinate values of the target color blocks as annotations.

[0013] Preferably, in step 3, the loss function of the target detection network is optimized based on the specific application of area prediction. The specific steps are: adding an area loss to the loss function of the original target detection network, namely the target loss, category loss and prediction box loss; after pre-training, performing hyperparameter evolution on the coefficients before each loss to obtain the optimal coefficient of each loss.

[0014] Preferably, step 4 includes: visualizing the three-dimensional structure of the multi-layer wire described in the layout file as a picture according to three views, wherein the top view is used for surface capacitance extraction, the left view and the main view are used for coupling capacitance extraction, and the layout picture is divided into several smaller pictures according to the pattern size, which are used as input to the target detection network, and the target detection network makes predictions on the layout picture; the geometric structure is obtained by predicting the classification result, and compared with the pattern library to obtain a capacitance calculation formula, the wire is located by the center coordinates of the prediction box, and the geometric parameters (including the overlapping area, the length and width of the overlapping part) are obtained by the coordinates and size of the prediction box, and the parasitic capacitance value of each wire is calculated by substituting them into the formula.

[0015] Beneficial effects:

[0016] 1. The pattern matching process in the present invention uses a target detection network, which is a deep neural network for target detection and can classify and locate targets in pictures. Taking the overlapping structure of wires as the detection target and the layout picture containing only interconnected wires as the network input, the network can obtain the category of the wires, i.e., the pattern, and the geometric parameters such as the position of the wires in the layout, the overlapping area, the overlapping width, and the overlapping length can be obtained based on the prediction frame coordinates. Since the target detection network has developed to yolo v5, fast and accurate target detection can be achieved. The use of the network replaces complex matching algorithms and improves matching accuracy.

[0017] 2. The pattern library in the present invention classifies patterns according to the geometric structure that affects the conductor, and gives the parasitic surface capacitance value and the parasitic coupling capacitance value calculation formula according to the analytical method. The sum of the two is the parasitic capacitance value. The specific geometric parameters (such as conductor length, width, etc.) are only used as variables in the formula. Therefore, there is no need to further subdivide the pattern based on the geometric parameters, which can greatly reduce the scale of the pattern library. The pattern library established in this way is also applicable to various process sizes. In the matching process, the geometric parameters such as the overlap area value are substituted into the capacitance analytical formula of the corresponding pattern to calculate the parasitic capacitance value.

[0018] 3. In the present invention, different colors are used to distinguish different layers or overlapping relationships. This method, combined with graph neural networks, provides a simple and practical layer relationship recognition algorithm.

[0019] 4. Because this invention introduces object detection networks to the field of parasitic parameter extraction for the first time, there are no annotated layout image sets available for training. Therefore, this invention constructs a dataset based on the characteristics of layout interconnects. The dataset contains only interconnects, and based on the characteristics of interconnects in real layouts, an image set of the required size can be automatically generated. This method effectively simplifies the dataset while simulating layout images and eliminates the enormous workload of manual annotation. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 Design a flow chart for the parasitic capacitance extraction method;

[0021] Figure 2 A simplified parasitic surface capacitance model library;

[0022] Figure 3 Structural design for target detection network. DETAILED DESCRIPTION

[0023] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0024] Figure 1 To design a flow chart for the parasitic capacitance extraction method, first design a pattern library (such as Figure 2As shown) and network structure (as Figure 3 (a) and (b) in the figure), then proceed to algorithm design. The overall algorithm framework includes three parts: data set establishment, network training, and layout extraction:

[0025] (1) Dataset establishment

[0026] First, the dataset used by the target detection network needs to conform to the characteristics of the layout containing only interconnected lines. The layout containing only interconnected lines is reflected as some color blocks of different colors and lengths. At the same time, the ratio of target color blocks to interference color blocks, the length and width range of color blocks, and the distribution area of color blocks in the image need to be consistent with the real layout. Figure 1 To.

[0027] (2) Network training

[0028] Then use the data set to train and verify the network. If the test results are not ideal, modify the loss function. The modified loss function is:

[0029] loss = λ obj l obj +λ cls l cls +λ box l box +λ area l area #(1) The first three terms are the loss function of the original object detection network, namely the weighted sum of the target loss, category loss, and prediction box loss. The last term is the added area loss. Alternatively, redesign the dataset and change the length range of the color blocks to optimize the training results until the network test results meet expectations.

[0030] (3) Layout prediction

[0031] The trained network is used to predict the layout image, and the classification given is the pattern in the pattern library. Therefore, the network prediction process is also the pattern matching process. After the predicted value is matched with the wire, the overlapping area, overlapping width, overlapping length and other parameters are substituted into the calculation formula corresponding to the pattern for calculation, and other required wire geometry parameters (including wire spacing and wire width) are directly read from the original layout file to finally obtain the parasitic capacitance value.

[0032] Figure 2This is a simplified parasitic surface capacitance pattern library. The pattern library described in this figure is for illustration only. It only considers one wire per layer, a total of five metal layers from M0 to M4, and the surface capacitance is simplified to a flat plate capacitor. The actual pattern library will be more complex. Different RGB values are set to distinguish different layers and layer overlap relationships, and the expression of the unit capacitance value is written to obtain the pattern library. Each layer overlap relationship and its corresponding unit capacitance formula is a pattern. The layer spacing and dielectric constant values are input in advance, and then the overlap area and layer relationship output by the network are matched with the pattern library. Substituting them into the capacitance expression can calculate the capacitance value. This is the pattern matching process of the capacitor.

[0033] Figure 3 This is the structural design of the target detection network. Figure 3 Figure (a) shows the internal structure of the network, which uses the YOLO v5s network model. It consists of four parts: the input, backbone, neck, and prediction. The input performs some processing on the original image before feeding it into the network. The backbone, consisting of modules such as Convolution, Batch Normalization (BN), and Leaky ReLU activation, performs core computations on feature maps. The neck incorporates a cross-layer structure, enhancing the network's feature fusion capabilities. The prediction outputs the network's prediction results, including category information and predicted bounding boxes.

[0034] Figure 3 (b) shows the network's external structure, specifically its input and output design. The network's input and output can be divided into a training process and a layout extraction process. The training process uses a dataset as input. The output categories, prediction box size, and prediction box center coordinates are used to calculate parameters such as precision, recall, and mean average precision (mAP), which represent network accuracy. Furthermore, since the network is used to predict overlapping areas, the prediction box size is also used to calculate area accuracy. For the layout extraction process, the layout image is input. The output categories represent the layer relationship, i.e., which two metal layers overlap. The prediction box size represents the overlapping area, and the prediction box side length represents the width and length of the overlapping portion. The prediction box center coordinates can be used to locate the wire, i.e., the wire location, or the overlapping layer relationship of the wire. As can be seen, the coordinates and size of the prediction box determine many of the wire's geometric parameters, so the prediction box error must be minimal.

[0035] The above embodiments are only for illustrating the technical idea of the present invention and cannot be used to limit the protection scope of the present invention. Any changes made on the basis of the disclosed technical solutions in accordance with the technical idea proposed by the present invention shall fall within the protection scope of the present invention.

Claims

1. A parasitic parameter extraction method based on target detection network, characterized in that: The steps include: Step 1: Create a parasitic capacitance model library; Step 2: Generate images that conform to the characteristics of the layout interconnect lines and annotate them to build a dataset; Step 3: Use the dataset to train the target detection network and optimize the target detection network by optimizing the loss function; Step 4: Use the trained target detection network to predict the layout image, and then process the network's prediction results to obtain the parasitic parameter values; The specific steps of step 2 are as follows: using color blocks with different colors to represent different wire layers, randomly generate some color blocks of different colors, different sizes, vertical or horizontal as interference background in the image, randomly generate target color blocks representing different overlapping relationships on the interference background, and derive the pattern category and coordinate value of the target color block as a label.

2. The parasitic parameter extraction method based on target detection network according to claim 1, characterized in that: The specific steps of step 1 are: setting different colors to represent different wire layers, overlapping relationships of wires in different layers, or overlapping relationships of wires in the same layer, and listing a lookup table of geometric structures corresponding to capacitance formulas to build a parasitic capacitance pattern library.

3. The parasitic parameter extraction method based on target detection network according to claim 1, characterized in that: The ratio of the number of target color blocks to the number of interference color blocks is set close to the ratio value of the actual layout situation. The length and width range of the color blocks refer to the length and width range of the actual wire. The distribution of the color blocks in the figure is concentrated in the central area, and the color blocks are rectangular in shape.

4. The parasitic parameter extraction method based on target detection network according to claim 1, characterized in that: In step 3, the loss function of the target detection network is optimized based on the specific application of area prediction. The specific steps are as follows: an area loss is added to the loss function of the original target detection network, namely the target loss, category loss, and prediction box loss; after pre-training, the coefficients before each loss are hyperparameter evolved to obtain the optimal coefficient of each loss.

5. The parasitic parameter extraction method based on target detection network according to claim 1, characterized in that: Step 4 includes: visualizing the layout file as an image as the input of the target detection network, and the target detection network makes predictions on the layout image; comparing the predicted classification results with the pattern library to obtain the capacitance calculation formula, locating the wire by the center coordinates of the prediction box, and obtaining the overlapping area, overlapping width, and overlapping length by the prediction box coordinates and size, and substituting them into the formula to calculate the parasitic capacitance value of each wire.

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