Methods, system-on-chip integrated circuits, and non-transitory computer-readable media for performing memory calibration

Abstract

The present invention relates to a method and a system-on-chip integrated circuit for performing memory calibration. The method can include, during a power-up and initialization phase, controlling a physical layer circuit in the system-on-chip integrated circuit to apply power to a memory through a set of bond pads and to initialize the memory; during an impedance calibration related phase, triggering the memory to perform impedance calibration with respect to a set of data pins; during at least one subsequent phase, performing data access testing corresponding to a set of test points on a predetermined mask that is movable with respect to a data eye, during any one of a calibration for read and a calibration for write; and selectively ending the any one of the calibration depending on whether the data access testing is successful.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to external memory control of an integrated circuit (IC), and in particular, to a method for performing memory calibration, a related system on chip (SoC) integrated circuit (IC), and a non-transitory computer-readable medium. BACKGROUND

[0002] According to the related art, when an electronic device with a dynamic random access memory (DRAM) is powered on, the DRAM can need to go through a preparation operation corresponding to a plurality of preparation stages to be ready for use. For the ease of understanding, the plurality of preparation stages can include a first stage regarding initialization, another stage regarding resistance / impedance calibration, and one or more subsequent stages. However, some problems can occur. For example, the parameter calibration in the one or more subsequent stages can be quite time-consuming, such that the boot-up time of the electronic device is increased, which can bring about a poor user experience. However, if the parameter calibration is not performed, it is difficult to ensure the normal operation of the electronic device. Therefore, a novel method and related architecture are needed to implement an SoC IC with a reliable calibration mechanism without side effects or with less likely side effects. SUMMARY

[0003] It is an object of the present disclosure to provide a method for performing memory calibration, a related system on chip (SoC) integrated circuit, and a non-transitory computer-readable medium to solve the above problems.

[0004] It is another object of the present disclosure to provide a method for performing memory calibration, a related system on chip (SoC) integrated circuit, and a non-transitory computer-readable medium to shorten the boot-up time of an electronic device and bring about a better user experience.

[0005] At least one embodiment of the present invention provides a method for memory calibration, which is applicable to a system-on-chip integrated circuit. The method can include: during a power-up and initialization phase of the system-on-chip integrated circuit, controlling a physical layer circuit in the system-on-chip integrated circuit to apply power to a memory through a set of pads and to initialize the memory; during an impedance calibration related phase of the system-on-chip integrated circuit, triggering the memory to perform impedance calibration with respect to a set of data pins; during at least one subsequent phase of the system-on-chip integrated circuit, performing data access testing corresponding to a set of test points on a predetermined mask during any one of calibration for read and calibration for write, wherein the predetermined mask is movable with respect to a data eye; and selectively ending the any one of calibration depending on whether the data access testing is successful.

[0006] At least one embodiment of the present invention provides a system-on-chip integrated circuit with memory calibration functionality. The system-on-chip integrated circuit can include: a processing circuit to control operation of the system-on-chip integrated circuit; a physical layer circuit coupled to the processing circuit to communicate for the processing circuit and a memory; and a set of pads including a plurality of pads as terminals of the system-on-chip integrated circuit to couple the system-on-chip integrated circuit to at least one external element, wherein the at least one external element includes the memory. For example, during a power-up and initialization phase of the system-on-chip integrated circuit, the processing circuit controls the physical layer circuit to apply power to the memory through the set of pads and to initialize the memory; during an impedance calibration related phase of the system-on-chip integrated circuit, the processing circuit triggers the memory to perform impedance calibration with respect to a set of data pins; during at least one subsequent phase of the system-on-chip integrated circuit, the processing circuit performs data access testing corresponding to a set of test points on a predetermined mask during any one of calibration for read and calibration for write, wherein the predetermined mask is movable with respect to a data eye; and the processing circuit selectively ends the any one of calibration depending on whether the data access testing is successful.

[0007] At least one embodiment of the present disclosure provides a non-transitory computer readable medium storing code that, when executed by a system on chip integrated circuit, causes the system on chip integrated circuit to perform a memory calibration procedure, which can include: during a power up and initialization phase of the system on chip integrated circuit, controlling a physical layer circuit of the system on chip integrated circuit to apply power to a memory through a set of bond pads and to initialize the memory; during an impedance calibration related phase of the system on chip integrated circuit, triggering the memory to perform impedance calibration with respect to a set of data pins; during at least one subsequent phase of the system on chip integrated circuit, during either of a calibration for read and a calibration for write, performing data access testing corresponding to a set of test points on a predetermined mask, wherein the predetermined mask is movable with respect to a data eye; and selectively ending the either of the calibration for read and the calibration for write depending on whether the data access testing is successful.

[0008] One of the benefits of the present disclosure is that, by a carefully designed memory calibration mechanism, the present disclosure can efficiently perform memory calibration to shorten the boot up time of an electronic device and bring better user experience. Compared to the related art, the present disclosure can avoid using time-consuming scanning methods (e.g., testing with respect to all possible combinations of parameters) during calibration. In addition, the present disclosure can implement a system on chip integrated circuit with a reliable calibration mechanism without side effects or with less likely side effects. BRIEF DESCRIPTION OF DRAWINGS

[0009] Figure 1 A schematic diagram of a system on chip (SoC) integrated circuit (IC) according to an embodiment of the present disclosure.

[0010] Figure 2 A timing diagram of a system on chip integrated circuit according to an embodiment of the present disclosure. Figure 1 Details of the system on chip integrated circuit shown.

[0011] Figure 3 A timing diagram of a system on chip integrated circuit according to another embodiment of the present disclosure. Figure 1 Details of the system on chip integrated circuit shown.

[0012] Figure 4 A horizontal timing calibration control scheme for write of a method for performing memory calibration according to an embodiment of the present disclosure.

[0013] Figure 5 A horizontal timing and reference voltage calibration control scheme for write of the method according to an embodiment of the present disclosure.

[0014] Figure 6 This is a method for calibrating and controlling a horizontal time and reference voltage reading, as shown in an embodiment of the present invention.

[0015] Figure 7 It shows Figure 6 An example of the associated reference voltage for the predetermined shield is shown.

[0016] Figure 8 This is a method for calibrating and controlling a horizontal time and reference voltage for reading, according to another embodiment of the present invention.

[0017] Figure 9 The lower half of the diagram illustrates a rapid calibration control scheme according to an embodiment of the present invention, wherein, for ease of understanding, Figure 9 The upper part shows a scanning calibration control scheme.

[0018] Figure 10 The following describes the workflow of the method according to an embodiment of the present invention. Detailed Implementation

[0019] Figure 1 This is a schematic diagram of a System-on-Chip (SoC) integrated circuit (IC) 100 according to an embodiment of the present invention, wherein the SoC IC 100 may be located in an electronic device 10, and further, may be mounted on a main circuit board (e.g., a printed circuit board) of the electronic device 10, but the present invention is not limited thereto. Figure 1 As shown, in addition to the SoC IC 100, the electronic device 10 may include a Dynamic Random Access Memory (DRAM) 100D, for example, the DRAM 100D may also be mounted on the main circuit board. Furthermore, the SoC IC 100 may include a non-volatile memory (NVM) 100N, a processing circuit 110, a physical layer (PHY) circuit 120, a pad set 130, and a Static Random Access Memory (SRAM) 140. The processing circuit 110 may include at least one processor (e.g., one or more processors), and the pad set 130 may include multiple pads as terminals for coupling the SoC IC 100 to at least one external component (e.g., the DRAM 100D).

[0020] In Figure 1 In the illustrated architecture, the NVM 100N can be depicted in the SoC IC 100, but the present disclosure is not limited thereto. For example, the NVM 100N can be implemented outside the SoC IC 100. In addition, the NVM 100N can be implemented by way of an Electrically Erasable Programmable Read-Only Memory (EEPROM), a Flash memory, or the like, but the present disclosure is not limited thereto.

[0021] Regardless of whether the NVM 100N is implemented inside or outside the SoC IC 100, the NVM 100N can store data for the SoC IC 100, and can avoid the data from being lost during power-off, where the data can include code, control parameters, or the like. The processing circuit 110 can load the code described above to the at least one processor described above, and the code running on the at least one processor described above can control the operation of the electronic device 10. For example, a first code of the code described above can be executed on the at least one processor described above to control the electronic device 10 to provide a service to a user of the electronic device 10, but the present disclosure is not limited thereto. In some examples, a second code of the code described above can be executed on the at least one processor described above to control the SoC IC 100 to perform memory calibration for the DRAM 100D. In addition, the SRAM 140 and the DRAM 100D can be respectively regarded as an internal memory and an external memory of the SoC IC 100. Further, the processing circuit 110 (e.g., the at least one processor described above) can temporarily store data, respectively. For example, the PHY circuit 120 can allow the processing circuit 110 (e.g., the at least one processor described above) to communicate with the DRAM 100D through the pad set 130 to allow the processing circuit 110 (e.g., the at least one processor described above) to access (e.g., write or read) data in the DRAM 100D.

[0022] When the electronic device 10 is powered on, the SoC IC 100 (e.g., the processing circuit 110, further, the calibration control module 100C therein) can utilize the PHY circuit 120 to perform a pre- operation corresponding to a plurality of pre- phases on the DRAM 100D to bring the DRAM 100D into an idle state, further, to prepare the DRAM 100D for use. For example, the plurality of pre- phases can include a power-up and initialization phase PHASE_1 in which the processing circuit 110 (e.g., the calibration control module 100C therein) can control the PHY circuit 120 to apply power to the DRAM 100D through the pad set 130, and to perform a series of operations on the DRAM 100D regarding initialization, a ZQ calibration phase PHASE_2 in which the processing circuit 110 (e.g., the calibration control module 100C therein) can control the PHY circuit 120 to trigger the DRAM 100D to perform a resistance / impedance calibration regarding a set of data pins {DQ} through the pad set 130, for example, the DRAM 100D can perform the resistance / impedance calibration by means of a precision resistor having a predetermined resistance value connected to a pin ZQ thereof, and at least one subsequent phase, such as one or more subsequent phases. For certain implementation details regarding the first two phases of the plurality of pre- phases, reference can be made to existing DRAM related standards such as the DDR3 SDRAM standard (e.g., JESD79-3), the DDR4 SDRAM standard (e.g., JESD79-4), and the like.

[0023] After the pre-operations corresponding to the first two phases are completed, the DRAM 100D can be in the idle state, but can not yet be ready for use. In order to correctly access the DRAM 100D, the processing circuit 110 (e.g., the calibration control module 100C therein) can perform pre-operations corresponding to the at least one subsequent phase, and these pre-operations can include at least a portion (e.g., a portion or all) of the following operations:

[0024] (1) The processing circuit 110 (e.g., the calibration control module 100C therein) can attempt to configure the PHY circuit 120 and / or the DRAM 100D according to a plurality of control parameters read from the NVM 100N, further perform a read calibration (which can be regarded as a read training) and a write calibration (which can be regarded as a write training) for the PHY circuit 120, and perform a data access test using at least one of the test control units POK1 and POK2 (e.g., one or both of the test control units POK1 and POK2) to determine whether the configuration is completed;

[0025] (2) In case that the data access test is unsuccessful, the processing circuit 110 (e.g., the calibration control module 100C therein) can calibrate at least one control parameter (e.g., one or more control parameters) for controlling the PHY circuit 120 to access the DRAM 100D, such as at least a portion (e.g., a portion or all) of the plurality of control parameters, and perform the data access test using the at least one test control unit to determine whether the configuration is completed;

[0026] Wherein, the calibration operation can be performed multiple times until the data access test is successful to ensure that the SoC IC 100 can correctly access (e.g., read or write) the DRAM 100D through the PHY circuit 120 after the configuration is completed, but the present application is not limited thereto.

[0027] For ease of understanding, the data access test can include a read test and a write test, such as a read and a write test for predetermined data, and a correct read result and a correct write result can respectively indicate a successful read test and a successful write test. As Figure 1As shown, the receiving (Rx) direction and the transmitting (Tx) direction of the SoC IC 100 relative to the DRAM 100D can represent the direction of read and write, respectively. For example, the processing circuit 110 (e.g., a calibration control module 100C therein) can perform calibration for read, such as phase and / or reference voltage calibration, further, during the phase calibration, the processing circuit 110 controls the PHY circuit 120 to adjust an amount of read delay stored in a read delay register in a receiver (e.g., a read capture circuit to capture data as a read result) therein to correspondingly adjust the number of enabled delay taps in the receiver, so that the data capture time point at the SoC side (e.g., the receiver in the PHY circuit 120) is aligned to the center of a data eye in a read signal (e.g., a data signal through a data pin DQ) waveform. The correctness of the read result can indicate that the read test is successful, which can indicate that the calibration for read is completed. As another example, the processing circuit 110 (e.g., a calibration control module 100C therein) can perform calibration for write, such as phase and / or reference voltage calibration, further, during the phase calibration, the processing circuit 110 controls the PHY circuit 120 to adjust an amount of write delay stored in a write delay register in a transmitter therein to correspondingly adjust the number of enabled delay taps in the transmitter, so that the phase of a write signal (e.g., a data signal through a data pin DQ) relative to a data strobe signal is adjusted to be correct at the data capture time point at the DRAM side (e.g., a receiver in the DRAM 100D), which means that the center of a data eye in the write signal waveform is aligned to the edge of the data strobe signal at the DRAM side. The correctness of the write result can indicate that the write test is successful, which can indicate that the calibration for write is completed. Thus, the DRAM 100D is ready for use.

[0028] According to certain embodiments, the test control unit POK2 can perform the read test, and the test control unit POK1 can perform the write test, but the present disclosure is not limited thereto. In certain embodiments, the implementation of the test control unit POK1 and the test control unit POK2 can be varied. For example, the test control unit POK1 can be integrated into the test control unit POK2. As another example, the test control unit POK2 can be integrated into the test control unit POK1.

[0029] According to certain embodiments, the PHY circuit 120 (e.g., the test control unit POK2) can set a mode control register (not shown) in the DRAM 100D to cause the DRAM 100D to enter a test mode or a normal mode. In the test mode, the DRAM 100D can switch its internal access paths to cause a read or write data stream to be redirected from memory cells in the DRAM 100D to a set of multi-purpose registers (MPRs, for short) (not shown) in the DRAM 100D, which can be used to store data for the SoC IC 100 in the normal mode. The PHY circuit 120 (e.g., the test control unit POK2) can pre-write the predetermined data to the set of MPRs in advance for the read test. The PHY circuit 120 (e.g., the test control unit POK2) can trigger the DRAM 100D to continuously and / or repeatedly transmit the predetermined data back to the PHY circuit 120 in the SoC IC 100 during the read test. For example, the predetermined data can include a set of alternating bits (e.g., 01010101 or 10101010, instead of consecutive bits of 1 or consecutive bits of 0), and a data signal through a data pin DQ can carry a corresponding bit stream (e.g., {01010101, 01010101,...} or {10101010, 10101010,...}), such that a data eye in this data signal waveform can be detected, but the disclosure is not limited thereto. Since the predetermined data is known data to the SoC IC 100 (e.g., the processing circuit 110, the calibration control module 100C, and / or the PHY circuit 120), the PHY circuit 120 (e.g., the test control unit POK2) can read a read result from the DRAM 100D and compare this read result with the predetermined data to determine whether the read result is correct, and thus whether the calibration for read is complete. In addition, after the calibration for read is complete, since all read results are considered to be reliable, the processing circuit 110 (e.g., the calibration control module 100C therein) can perform the calibration for write. For example, since any write data, such as the predetermined data, is known data to the SoC IC 100 (e.g., the processing circuit 110, the calibration control module 100C, and / or the PHY circuit 120), the calibration control module 100C (e.g., the test control unit POK1) can control the PHY circuit 120 to write the any write data, read a read result from the DRAM 100D, and compare this read result with the any write data, such as the predetermined data, to determine whether the read result is correct, and thus whether the calibration for write is complete.

[0030] Figure 2An example of the architecture shown (such as SoC IC 100 and processing circuit 110, calibration control module 100C, etc.) is shown in FIG. 1. In this embodiment, the at least one processor can be collectively referred to as processor 111. In addition to processor 111, processing circuit 110 can also include bus 110B and DRAM controller 112, and can also include at least one additional controller, which can be collectively referred to as controller 113. DRAM controller 112 can control the operation of DRAM 100D through PHY circuit 120, and controller 113 can control certain other operations. In this embodiment, calibration control module 100C can be implemented by calibration control program 200C running on processor 111, etc. For example, the second of the above-mentioned codes can be loaded into processor 111 to become calibration control program 200C running on processor 111. For the sake of brevity, similar content in this embodiment will not be repeated here. Figure 1 Details of the implementation of SoC IC 100 shown. Figure 2 The architecture shown (such as SoC IC 200 and processing circuit 210, calibration control program 200C, etc.) can be considered as an example of the architecture shown (such as SoC IC 100 and processing circuit 110, calibration control module 100C, etc.). In this embodiment, the at least one processor can be collectively referred to as processor 211. In addition to processor 211, processing circuit 210 can also include bus 210B and DRAM controller 212, and can also include at least one additional controller, which can be collectively referred to as controller 213. DRAM controller 212 can control the operation of DRAM 100D through PHY circuit 120, and controller 213 can control certain other operations. In this embodiment, calibration control module 100C can be implemented by calibration control program 200C running on processor 211, etc. For example, the second of the above-mentioned codes can be loaded into processor 211 to become calibration control program 200C running on processor 211. For the sake of brevity, similar content in this embodiment will not be repeated here. Figure 1 Details of the implementation of SoC IC 100 shown.

[0031] Figure 3 An example of the architecture shown (such as SoC IC 300 and processing circuit 310, calibration control circuit 300C, etc.) is shown in FIG. 3. In this embodiment, the at least one processor can be collectively referred to as processor 311. In addition to processor 311, processing circuit 310 can also include bus 210B, DRAM controller 312, and controller 213. DRAM controller 312 can control the operation of DRAM 100D through PHY circuit 120. In this embodiment, calibration control module 100C can be implemented by hardware circuit, etc., and can be implemented as one of the sub-circuits of DRAM controller 312, such as calibration control circuit 300C. For the sake of brevity, similar content in this embodiment will not be repeated here. Figure 1 Details of the implementation of SoC IC 100 shown. Figure 3 The architecture shown (such as SoC IC 200 and processing circuit 210, calibration control program 200C, etc.) can be considered as an example of the architecture shown (such as SoC IC 100 and processing circuit 110, calibration control module 100C, etc.). In this embodiment, the at least one processor can be collectively referred to as processor 211. In addition to processor 211, processing circuit 210 can also include bus 210B and DRAM controller 212, and can also include at least one additional controller, which can be collectively referred to as controller 213. DRAM controller 212 can control the operation of DRAM 100D through PHY circuit 120, and controller 213 can control certain other operations. In this embodiment, calibration control module 100C can be implemented by calibration control program 200C running on processor 211, etc. For example, the second of the above-mentioned codes can be loaded into processor 211 to become calibration control program 200C running on processor 211. For the sake of brevity, similar content in this embodiment will not be repeated here. Figure 1 Details of the implementation of SoC IC 100 shown.

[0032] In some subsequent embodiments, the above-mentioned data eye can be illustrated as a hexagon for ease of understanding, wherein the hexagon illustrated as a multi-layer stack can represent a respective data eye of a set of data signals passing through a set of data pins {DQ}. Wherein, the PHY circuit 120 can include a plurality of slice sub-circuits (which include respective receivers and transmitters) corresponding to the set of data pins {DQ} respectively, the processing circuit 110 can selectively calibrate a single slice or multiple slices as needed, but the present application is not limited thereto. For example, the shape of a data eye in a typical eye diagram can look like a hexagon or some other shape. In addition, the set of data signals can carry a set of bits of any one of one or more bit groups. For example, the one or more bit groups can represent bit groups read from the DRAM 100D. For another example, the one or more bit groups can represent bit groups written into the DRAM 100D. Furthermore, for the above-mentioned reference voltage calibration, the processing circuit 110 (e.g., the calibration control module 100C therein) can calibrate a reference voltage Vref used to determine whether a data bit is bit 0 or bit 1. For example, the reference voltage Vref can represent a reference voltage of a data signal of a certain data pin DQ (e.g., any data pin of the set of data pins {DQ}, further, each data pin of the set of data pins {DQ}), and thus can be written as reference voltage VrefDQ for ease of understanding.

[0033] Figure 4 A horizontal time calibration control scheme for write of a method for performing memory calibration according to an embodiment of the present application is shown. When the DRAM 100D belongs to a DDR3 SDRAM, the reference voltage Vref (e.g., the reference voltage VrefDQ) for write can be equal to 750 millivolts (mV). Since the reference voltage Vref is fixed, the calibration for write can include horizontal time calibration, and can be performed in a per-slice calibration manner, and the above-mentioned at least one control parameter can include a horizontal time control parameter O_X, but the present application is not limited thereto. For example, the calibration for write can be performed in an all-slice calibration manner.

[0034] Under the control of the calibration control module 100C, the processing circuit 110 can perform calibration for write according to the horizontal time calibration control scheme, and further, can perform the following steps S31A-S37A:

[0035] (step S31A) The processing circuit 110 can read a preset value O_X0 of the horizontal time control parameter O_X from the NVM 100N for writing to the write delay register as the write delay amount. Wherein, for the horizontal coordinate, the preset value O_X0 can correspond to a center point O (e.g., a candidate position O1 among a plurality of candidate positions O1, O2, O3, O4, O5, etc.) of a predetermined mask MASK_AB to indicate a data retrieval time point at the DRAM side (e.g., a receiver within the DRAM 100D), and the predetermined mask MASK_AB can be defined with a mask coefficient n and a horizontal time (horizontal timing) interval HT (e.g., a delay amount of each delay branch of the plurality of delay branches of the transmitter);

[0036] (step S32A) The processing circuit 110 can determine a set of test values corresponding to the predetermined mask MASK_AB according to the preset value O_X0 of the horizontal time control parameter O_X. Wherein, the set of test values includes two test values represented by test points A and B on the predetermined mask MASK_AB, such as the horizontal coordinates of the test points, respectively. Such as by adjusting the horizontal time (e.g., in fixed or non-fixed multiples) to the left or right relative to the center point O corresponding to the preset value O_X0 to obtain the horizontal coordinates;

[0037] (step S33A) The processing circuit 110 can write the two test values (such as the above-mentioned horizontal coordinates) in step S32A to the write delay register as the write delay amount, respectively, to check whether the write test is passed, so as to determine whether to stop the calibration for writing. Wherein, if the write test is passed in both cases of using the two test values (such as the above-mentioned horizontal coordinates) as the write delay amount, respectively, the processing circuit 110 can stop the calibration for writing, otherwise, the processing circuit 110 can continue the subsequent operation to continue the calibration for writing at the next candidate position;

[0038] (step S34A) The processing circuit 110 can adjust the preset value O_X0 of the horizontal time control parameter O_X according to a predetermined adjustment sequence, such as a sequence of the plurality of candidate positions O1, O2, O3, O4, O5, etc., to generate a candidate value O_Xc of the horizontal time control parameter O_X for writing to the write delay register as the write delay amount. Wherein, for the horizontal coordinate, the candidate value O_Xc can correspond to a subsequent candidate position among the plurality of candidate positions O1, O2, O3, O4, O5, etc., such as one of the candidate positions O2, O3, O4, O5, etc., to indicate a data retrieval time point at the DRAM side (e.g., a receiver within the DRAM 100D);

[0039] (step S35A) The processing circuit 110 can determine a set of test values corresponding to the predetermined mask MASK_AB in accordance with the candidate value O_Xc of the horizontal time control parameter O_X. The set of test values includes two test values represented by the horizontal and vertical coordinates of the test points A and B on the predetermined mask MASK_AB, for example. The horizontal coordinates can be obtained, for example, by adjusting the horizontal time (e.g., n times of the horizontal time interval HT) to the left and right of the point corresponding to the candidate value O_Xc (in a similar manner to step S32A).

[0040] (step S36A) The processing circuit 110 can write the two test values (such as the above-mentioned horizontal coordinates) in step S35A into the write delay register as the write delay amount, respectively, to check whether the write test is passed, so as to determine whether to stop the calibration for writing. If the write test is passed in both cases where the two test values (such as the above-mentioned horizontal coordinates) are used as the write delay amount, respectively, the processing circuit 110 can stop the calibration for writing, otherwise, the processing circuit 110 can perform similar operations to continue the calibration for writing at the next candidate position until all candidate positions in the plurality of candidate positions O1, O2, O3, O4, O5, etc. are used up.

[0041] (step S37A) When it is determined to stop the calibration for writing, the processing circuit 110 can update the horizontal time control parameter O_X in the NVM 100N to the latest candidate value O_Xc, such as the last candidate value O_Xc obtained and used in the above-mentioned loop of steps S34A-S36A.

[0042] The success of the write test at the test points A and B indicates that the write test at all possible or available test points in the region enclosed by the predetermined mask MASK_AB is expected to be successful, but the present application is not limited thereto. For example, if the failure of the write test continues to occur until all candidate positions in the plurality of candidate positions O1, O2, O3, O4, O5, etc. are used up, the processing circuit 110 can issue an error message instead of performing step S37A. In addition, in the above-mentioned operations, the processing circuit 110 can selectively move the predetermined mask MASK_AB (together with the test points A and B thereon) in a plurality of rounds in accordance with the plurality of candidate positions O1, O2, O3, O4, O5, etc. to perform the write test corresponding to the predetermined mask MASK_AB. For the sake of brevity, similar contents in the present embodiment are not repeated here.

[0043] According to certain embodiments, the plurality of candidate positions O1, O2, O3, O4, O5, etc. of the predetermined mask MASK_AB can be varied. For example, the number and / or arrangement of the candidate positions of the predetermined mask MASK_AB can be varied.

[0044] Figure 5 This is a method for calibrating and controlling the writing of a horizontal time and reference voltage according to an embodiment of the present invention. Compared to... Figure 4 The illustrated horizontal time calibration control scheme provides one-dimensional calibration, while the horizontal time and reference voltage calibration control scheme provides two-dimensional calibration. For example, when DRAM 100D is a DDR4 SDRAM, the write reference voltage Vref (e.g., reference voltage VrefDQ) is adjustable. Write calibration may include horizontal time calibration and reference voltage calibration, and can be performed using all-chip calibration methods. The aforementioned at least one control parameter may include a horizontal time control parameter O_X and a reference voltage parameter O_Y, where the reference voltage parameter O_Y may indicate a predetermined voltage level for the write reference voltage Vref, but the invention is not limited thereto. In some embodiments, for ease of understanding, the reference voltage parameter O_Y may be represented as the reference voltage Vref.

[0045] Under the control of the calibration control module 100C, the processing circuit 110 can perform calibration for the write operation according to the horizontal time and reference voltage calibration control scheme, and further perform the following steps S31B to S37B:

[0046] (Step S31B) In addition to reading the preset value O_X0 of the horizontal time control parameter O_X from the NVM 100N for writing to the write delay register as the write delay amount, the processing circuit 110 can also read a preset value O_Y0 of the reference voltage parameter O_Y from the NVM 100N for writing to a reference voltage control register as the predetermined voltage level of the reference voltage Vref. Specifically, for the horizontal and vertical coordinates, the preset values ​​(O_X0, O_Y0) can correspond to the center point O of a predetermined mask MASK_A2D_Tx (e.g., candidate position O1 among its multiple candidate positions O1, O2, O3, O4, O5, O6, O7, O8, O9, O10, O11, etc.) to indicate the data acquisition time point on the DRAM side (e.g., the receiver in DRAM100D) and the predetermined voltage level of the reference voltage Vref. The predetermined mask MASK_A2D_Tx can be defined by masking coefficients m and n and the horizontal time interval HT.

[0047] (Step S32B) The processing circuit 110 can determine a set of test values corresponding to the predetermined mask MASK_A2D_Tx in accordance with the preset values (O_X0, O_Y0), wherein the set of test values comprises a series of test values represented by the test points A, B, C and D on the predetermined mask MASK_A2D_Tx. For example, the horizontal and vertical coordinates of each of the test points can be determined in a manner similar to Figure 4 that the horizontal coordinate is determined by a horizontal adjustment (e.g., by n times of the horizontal time interval HT) with respect to the center point O corresponding to the preset value O_X0, and the vertical coordinate is determined by a vertical adjustment (e.g., by a fixed ratio of m%) or no adjustment upwards and downwards with respect to the center point O corresponding to the preset value O_Y0;

[0048] (Step S33B) The processing circuit 110 can write the series of test values (such as the above-mentioned coordinates) in step S32B into the write delay register (as the write delay amount) and the reference voltage control register (as the predetermined voltage level) respectively to check whether the write test is passed, so as to determine whether to stop the calibration for write. If the write test is passed in all of the four cases where the series of test values (such as the above-mentioned coordinates) are used as the write delay amount and the predetermined voltage level respectively, the processing circuit 110 can stop the calibration for write, otherwise, the processing circuit 110 can continue the subsequent operations to continue the calibration for write at the next candidate position;

[0049] (Step S34B) The processing circuit 110 can adjust the preset values O_X0 and O_Y0 of the horizontal time control parameter O_X and the reference voltage parameter O_Y respectively in accordance with a predetermined adjustment sequence, such as the sequence of the candidate positions O1, O2, O3, O4, O5, O6, O7, O8, O9, O10, O11, etc., to generate the candidate values O_Xc and O_Yc of the horizontal time control parameter O_X and the reference voltage parameter O_Y respectively for writing into the write delay register (as the write delay amount) and the reference voltage control register (as the predetermined voltage level). For the horizontal and vertical coordinates, the candidate values (O_Xc, O_Yc) can correspond to a subsequent candidate position in the candidate positions O1, O2, O3, O4, O5, O6, O7, O8, O9, O10, O11, etc., such as one of the candidate positions O2, O3, O4, O5, O6, O7, O8, O9, O10, O11, etc., to indicate the data retrieval time point at the DRAM side (e.g., the receiver within the DRAM 100D) and the predetermined voltage level of the reference voltage Vref;

[0050] (step S35B) The processing circuit 110 can determine a set of test values corresponding to the predetermined mask MASK_A2D_Tx in accordance with the candidate values (O_Xc, O_Yc), wherein the set of test values comprises a series of test values represented by the test points A, B, C and D on the predetermined mask MASK_A2D_Tx, such as the horizontal and vertical coordinates of the test points respectively. The coordinates of the series of test values are obtained in a similar manner as step S32B (with the preset values (O_X0, O_Y0) being replaced by the candidate values (O_Xc, O_Yc)), which will not be repeated here;

[0051] (step S36B) The processing circuit 110 can write the series of test values (such as the above-mentioned coordinates) in step S35B into the write delay register (as the write delay amount) and the reference voltage control register (as the predetermined voltage level) respectively to check whether the write test is passed, so as to determine whether to stop the calibration for writing. If the write test is passed in all four cases of using the series of test values (such as the above-mentioned coordinates) as the write delay amount and the predetermined voltage level respectively, the processing circuit 110 can stop the calibration for writing, otherwise, the processing circuit 110 can perform similar operations to continue the calibration for writing at the next candidate position until all the candidate positions O1, O2, O3, O4, O5, O6, O7, O8, O9, O10, O11, etc. are used up;

[0052] (step S37B) When it is determined to stop the calibration for writing, the processing circuit 110 can update the horizontal time control parameter O_X and the reference voltage parameter O_Y in the NVM 100N to their respective latest candidate values (O_Xc, O_Yc), such as the last candidate values (O_Xc, O_Yc) obtained and used in the loop of steps S34B-S36B above;

[0053] The success of the write test at test points A, B, C, and D can indicate that the write test at all possible or available test points within the area enclosed by predetermined mask MASK_A2D_Tx is expected to be successful, but the present application is not limited thereto. For example, if the failure of the write test continues to occur until all of the candidate locations O1, O2, O3, O4, O5, O6, O7, O8, O9, O10, O11, etc. are exhausted, processing circuit 110 can issue an error message instead of performing step S37B. In addition, in the above operation, processing circuit 110 can selectively move predetermined mask MASK_A2D_Tx (together with test points A, B, C, and D thereon) in multiple rounds according to the candidate locations O1, O2, O3, O4, O5, O6, O7, O8, O9, O10, O11, etc. respectively to perform the write test corresponding to predetermined mask MASK_A2D_Tx. For the sake of brevity, similar content in this embodiment will not be repeated here.

[0054] According to certain embodiments, the candidate locations O1, O2, O3, O4, O5, O6, O7, O8, O9, O10, O11, etc. of predetermined mask MASK_A2D_Tx can be varied. For example, the number and / or arrangement of the candidate locations of predetermined mask MASK_A2D_Tx can be varied.

[0055] Figure 6 A level time and reference voltage calibration control scheme for read according to the method shown in one embodiment of the present application. Compared to the embodiment shown in Figure 5 the embodiment, the level time and reference voltage calibration control scheme in this embodiment will replace predetermined mask MASK_A2D_Tx corresponding to write with predetermined mask MASK_A2D_Rx corresponding to read, and can also provide two-dimensional calibration. For example, the reference voltage Vref (e.g. reference voltage VrefDQ) for read is adjustable regardless of whether DRAM 100D belongs to DDR3 SDRAM, DDR4 SDRAM, etc. The calibration for read can include level time calibration and reference voltage calibration, and can be performed in an all-chip calibration manner, and the at least one control parameter can include another level time control parameter O_X and another reference voltage parameter O_Y, but the present application is not limited thereto. For example, related symbols such as Vref (e.g. VrefDQ), O, A, B, C, D, O_X, O_Y, O_X0, O_Y0, O_Xc, O_Yc, etc. can be as shown in Figure 4 or Figure 5The embodiments shown in the middle are suffixed with "(1)" to be rewritten as Vref(1) (e.g., VrefDQ(1)), O(1), A(1), B(1), C(1), D(1), O_X(1), O_Y(1), O_X0(1), O_Y0(1), O_Xc(1), O_Yc(1), etc., or can be suffixed with "(0)" to be rewritten as Vref(0) (e.g., VrefDQ(0)), O(0), A(0), B(0), C(0), D(0), O_X(0), O_Y(0), O_X0(0), O_Y0(0), O_Xc(0), O_Yc(0), etc. in the present embodiments. For simplicity, the following description uses the symbols without suffix "(0)".

[0056] Under the control of the calibration control module 100C, the processing circuit 110 can perform calibration for reading according to the horizontal time and reference voltage calibration control scheme of the present embodiment, and further, can perform the following steps S31C-S37C:

[0057] (Step S31C) In addition to reading the preset value O_X0 of the horizontal time control parameter O_X from the NVM 100N for writing to the read delay register as the read delay amount, the processing circuit 110 can also read the preset value O_Y0 of the reference voltage parameter O_Y from the NVM 100N for writing to another reference voltage control register as a predetermined voltage level of the reference voltage Vref. Wherein, for horizontal and vertical coordinates, the preset values (O_X0, O_Y0) can correspond to the center point O (e.g., the candidate position O1 among the plurality of candidate positions O1, O2, O3, O4, O5, etc.) of the predetermined mask MASK_A2D_Rx to indicate the data capture time point on the SoC side (e.g., the receiver within the PHY circuit 120) and the predetermined voltage level of the reference voltage Vref, and the predetermined mask MASK_A2D_Rx can be defined with mask coefficients x and y and an inter-tap period IP (e.g., the delay amount of each delay tap in the plurality of delay taps of the receiver);

[0058] (Step S32C) The processing circuit 110 can determine a set of test values corresponding to the predetermined mask MASK_A2D_Rx according to the preset values (O_X0, O_Y0), wherein the set of test values includes a series of test values represented by the test points A, B, C, and D on the predetermined mask MASK_A2D_Rx. For example, the horizontal and vertical coordinates of each of these test points, such as by (similarly Figure 5horizontal adjustment (e.g., by y times of the inter-branch period IP) relative to a center point O corresponding to a preset value O_X0 to obtain a horizontal coordinate, and a fixed (e.g., x%) or non-fixed ratio vertical adjustment relative to the center point O corresponding to a preset value O_Y0 upward and downward to obtain a vertical coordinate;

[0059] (step S33C) The processing circuit 110 can write the series of test values (such as the above listed coordinates) in step S32C into the read latency register (as the read latency) and the other reference voltage control register (as the predetermined voltage level) respectively to check whether the read test is passed, so as to determine whether to stop the calibration for read. If the read test is passed in all four cases of using the series of test values (such as the above listed coordinates) as the read latency and the predetermined voltage level respectively, the processing circuit 110 can stop the calibration for read, otherwise, the processing circuit 110 can continue the subsequent operation to continue the calibration for read at the next candidate position;

[0060] (step S34C) The processing circuit 110 can adjust the preset values O_X0 and O_Y0 of the horizontal time control parameter O_X and the reference voltage parameter O_Y respectively according to a predetermined adjustment sequence, such as the sequence of the plurality of candidate positions O1, O2, O3, O4, O5, etc., to generate candidate values O_Xc and O_Yc of the horizontal time control parameter O_X and the reference voltage parameter O_Y respectively for writing into the read latency register (as the read latency) and the other reference voltage control register (as the predetermined voltage level). The candidate values (O_Xc, O_Yc) can correspond to a subsequent candidate position in the plurality of candidate positions O1, O2, O3, O4, O5, etc., such as one of the candidate positions O2, O3, O4, O5, etc., for indicating the data capture time point at the SoC side (e.g., the receiver within the PHY circuit 120) and the predetermined voltage level of the reference voltage Vref for the horizontal and vertical coordinates;

[0061] (step S35C) The processing circuit 110 can determine a set of test values corresponding to the predetermined mask MASK_A2D_Rx according to the candidate values (O_Xc, O_Yc), wherein the set of test values includes a series of test values represented by the test points A, B, C and D on the predetermined mask MASK_A2D_Rx. For example, the horizontal and vertical coordinates of the test points are obtained in a similar manner as step S32C (with the preset values (O_X0, O_Y0) being replaced by the candidate values (O_Xc, O_Yc)), which will not be described herein again;

[0062] (step S36C) The processing circuit 110 can write the series of test values (such as the above-listed coordinates) in step S35C into the read latency register (as the read latency amount) and the other reference voltage control register (as the predetermined voltage level) respectively to check whether the read test is passed, so as to determine whether to stop the calibration for read, wherein if the read test is passed in all of the four cases respectively employing the series of test values (such as the above-listed coordinates) as the read latency amount and the predetermined voltage level, the processing circuit 110 can stop the calibration for read, otherwise, the processing circuit 110 can perform similar operations to continue the calibration for read at the next candidate position until all of the candidate positions O1, O2, O3, O4, O5, etc. in the plurality of candidate positions O1, O2, O3, O4, O5, etc. are used up;

[0063] (step S37C) When it is determined to stop the calibration for read, the processing circuit 110 can update the horizontal time control parameter O_X and the reference voltage parameter O_Y in the NVM 100N to their respective latest candidate values (O_Xc, O_Yc), such as the last candidate values (O_Xc, O_Yc) obtained and used in the above-listed loop of steps S34C-S36C;

[0064] Wherein the success of the read test at the test points A, B, C and D can indicate that the write test at all possible or available test points within the region enclosed by the predetermined mask MASK_A2D_Rx is expected to be successful, but the present application is not limited thereto. For example, if the failure of the read test continues to occur until all of the candidate positions O1, O2, O3, O4, O5, etc. in the plurality of candidate positions O1, O2, O3, O4, O5, etc. are used up, the processing circuit 110 can issue an error message instead of performing step S37C. In addition, in the above-listed operations, the processing circuit 110 can selectively move the predetermined mask MASK_A2D_Rx (together with the test points A, B, C and D thereon) in a plurality of rounds according to the plurality of candidate positions O1, O2, O3, O4, O5, etc. to perform the read test corresponding to the predetermined mask MASK_A2D_Rx. For the sake of simplicity, similar contents in the present embodiment are not repeated here.

[0065] According to certain embodiments, the plurality of candidate positions O1, O2, O3, O4, O5, etc. of the predetermined mask MASK_A2D_Rx can be varied. For example, the number and / or arrangement of the candidate positions of the predetermined mask MASK_A2D_Rx can be varied. Further, Figure 6 The illustrated candidate positions O1, O2, O3, O4, O5, etc. can be regarded as one-dimensionally arranged candidate positions, but the present application is not limited thereto. When necessary, two-dimensionally arranged candidate positions (for example Figure 5The candidate positions O1, O2, O3, O4, O5, O6, O7, O8, O9, O10, O11, etc. shown are candidate positions for the predetermined mask MASK_A2D_Rx.

[0066] According to certain embodiments, the read test involving the predetermined mask MASK_A2D_Rx can be varied. For example, the read test can be implemented by a horizontal timing margin test, etc.

[0067] Figure 7 An example of the associated reference voltages for the predetermined mask MASK_A2D_Rx is shown. For the reference voltage Vref_P through test points A and B and the reference voltage Vref_N through test points C and D, the reference voltage Vref (e.g., reference voltage Vref(0)) through the center point O can be represented as follows: Figure 6 Vref_P = Vref * (1 + x%);

[0068] Vref_N = Vref * (1 - x%);

[0069] where the reference points E and F on the predetermined mask MASK_A2D_Rx can represent the intersection of the predetermined mask MASK_A2D_Rx and a center vertical line (e.g., a vertical line through the center point O) and can be used in the horizontal timing margin test described above.

[0070]

[0071] Figure 8 ​For the read level time and reference voltage calibration control scheme of the method shown in another embodiment of the present application, the read test can be implemented by the level time margin test. For the case that the center point O of the predetermined mask MASK_A2D_Rx is at a candidate position (e.g., one of the candidate positions O1, O2, O3, O4, O5, etc.), the processing circuit 110 can calculate three time differences TD, TD_P and TD_N represented by three horizontal line segments cut by the data eye from a center horizontal line (e.g., the horizontal line passing through the center point O), an upper horizontal line (e.g., the horizontal line passing through the reference point E) and a lower horizontal line (e.g., the horizontal line passing through the reference point F) of the predetermined mask MASK_A2D_Rx, respectively, and determine whether the read test is successful or not according to whether the three time differences TD, TD_P and TD_N are all greater than the width (2*(y*(IP))) of the predetermined mask MASK_A2D_Rx. If the three time differences TD, TD_P and TD_N are all greater than a predetermined level time margin, such as the width (2*(y*(IP))) of the predetermined mask MASK_A2D_Rx, which can indicate that the predetermined mask MASK_A2D_Rx is located entirely within the data eye, the processing circuit 110 can determine that the read test is successful, otherwise (e.g., when the boundary of the predetermined mask MASK_A2D_Rx exceeds the data eye), the processing circuit 110 can determine that the read test is failed. For the sake of brevity, similar contents in this embodiment are not repeated here.

[0072] Figure 9 The lower half of FIG. 1 shows a fast calibration control scheme of the method shown in an embodiment of the present application, wherein for the sake of brevity, Figure 9 The upper half of FIG. 1 shows a scan calibration control scheme (e.g., test with respect to all possible parameter combinations). The predetermined mask can represent one of the predetermined masks MASK_A2D_Rx, MASK_A2D_Tx, MASK_AB, etc. described above, and the fast calibration control scheme can represent the corresponding control scheme in the above embodiments. Since the fast calibration control scheme does not need to test with respect to all possible parameter combinations, the architecture of the present application can efficiently perform memory calibration to shorten the boot-up time of the electronic device 10 and bring better user experience. For the sake of brevity, similar contents in this embodiment are not repeated here.

[0073] Figure 10The following is an example of a workflow of the method according to an embodiment of the application. The processing circuit 110 (e.g., the calibration control module 100C therein) can perform the operations of step S10, step S20, and steps S31-S38 at the power-up and initialization phase PHASE_1, the ZQ calibration phase PHASE_2, and at least one subsequent phase such as the phase and / or reference voltage calibration phase PHASE_3, respectively. For ease of understanding, steps S31A-S37A, steps S31B-S37B, and steps S31C-S37C in some embodiments above can be examples of steps S31-S37 in the workflow, but the application is not limited thereto. For example, in a case where the preset values of all the control parameters are sufficiently accurate such that the respective candidate position numbers for read and for write are sufficient to handle any possible parameter drift in the calibration for read and in the calibration for write, the processing circuit 110 (e.g., the calibration control module 100C therein) can perform at least a portion (e.g., a portion or all) of steps S31-S37 to perform and complete the calibration for read, then perform step S38 to determine that the calibration for read is not yet completed, and perform at least a portion (e.g., a portion or all) of steps S31-S37 to perform and complete the calibration for write, and subsequently perform step S38 to determine that the calibration for write is not yet completed.

[0074] In step S10, the processing circuit 110 (e.g., the calibration control module 100C) can control the PHY circuit 120 to apply power to the DRAM 100D through the pad set 130 and to perform the initialization (e.g., the series of operations thereof) on the DRAM 100D.

[0075] In step S20, the processing circuit 110 (e.g., the calibration control module 100C) can control the PHY circuit 120 to trigger the DRAM 100D to perform the resistance / impedance calibration through the pad set 130.

[0076] In step S31, the processing circuit 110 (e.g., the calibration control module 100C) can read at least one preset value of at least one control parameter (e.g., the horizontal time control parameter O_X and / or the reference voltage parameter O_Y) from the NVM 100N. For example, when the processing circuit 110 is performing calibration for read, the at least one control parameter can include the horizontal time control parameter O_X(0) and the reference voltage parameter O_Y(0), and the at least one preset value can include the preset values (O_X0(0), O_Y0(0)). When the processing circuit 110 is performing calibration for write, for example, in the case where the DRAM 100D belongs to DDR4 SDRAM, the at least one control parameter can include the horizontal time control parameter O_X(1) and the reference voltage parameter O_Y(1), and the at least one preset value can include the preset values (O_X0(1), O_Y0(1)); for another example, in the case where the DRAM 100D belongs to DDR3 SDRAM, the at least one control parameter can include the horizontal time control parameter O_X(1), and the at least one preset value can include the preset value O_X0(1).

[0077] In step S32, the processing circuit 110 (e.g., the calibration control module 100C) can determine a set of test values corresponding to a predetermined mask MASK according to the at least one preset value of the at least one control parameter. For example, when the processing circuit 110 is performing calibration for read, the predetermined mask MASK can represent the predetermined mask MASK_A2D_Rx. When the processing circuit 110 is performing calibration for write, for example, in the case where the DRAM 100D belongs to DDR4 SDRAM, the predetermined mask MASK can represent the mask MASK_A2D_Tx; for another example, in the case where the DRAM 100D belongs to DDR3 SDRAM, the predetermined mask MASK can represent the predetermined mask MASK_AB.

[0078] In step S33, the processing circuit 110 (e.g., the calibration control module 100C) can check whether the test (e.g., a read test such as the horizontal time margin test for calibration for read, or a write test for calibration for write) is passed. If yes, proceed to step S38; if no, proceed to step S34.

[0079] In step S34, the processing circuit 110 (e.g., the calibration control module 100C) can adjust the preset values of the at least one control parameter according to a predetermined adjustment sequence to generate at least one candidate value of the at least one control parameter. For example, when the processing circuit 110 is performing calibration for read, the at least one control parameter can include the horizontal time control parameter O_X(0) and the reference voltage parameter O_Y(0), and the at least one candidate value can include the preset values (O_Xc(0), O_Yc(0)). When the processing circuit 110 is performing calibration for write, for example, in the case where the DRAM 100D belongs to DDR4 SDRAM, the at least one control parameter can include the horizontal time control parameter O_X(1) and the reference voltage parameter O_Y(1), and the at least one candidate value can include the preset values (O_Xc(1), O_Yc(1)); for another example, in the case where the DRAM 100D belongs to DDR3 SDRAM, the at least one control parameter can include the horizontal time control parameter O_X(1), and the at least one candidate value can include the preset value O_Xc(1).

[0080] In step S35, the processing circuit 110 (e.g., the calibration control module 100C) can determine a set of test values corresponding to the predetermined mask MASK (e.g., one of the predetermined masks MASK_A2D_Rx, MASK_A2D_Tx, MASK_AB, etc., as described in step S32) according to the at least one candidate value of the at least one control parameter.

[0081] In step S36, the processing circuit 110 (e.g., the calibration control module 100C) can check whether the test (e.g., a read test, such as the horizontal time margin test, for calibration for read, or a write test, for calibration for write) is passed. If yes, proceed to step S37; if no, proceed to step S34.

[0082] In step S37, the processing circuit 110 (e.g., the calibration control module 100C) can update the at least one control parameter in the NVM 100N to its latest candidate value.

[0083] In step S38, the processing circuit 110 (e.g., the calibration control module 100C) can check whether the overall calibration is completed. If yes, the workflow is ended; if no, step S31 is entered to perform the next calibration. For example, the overall calibration can include the calibration for reading and the calibration for writing, and the processing circuit 110 can perform and complete the calibration for reading first. When step S38 is performed for the first time, the processing circuit 110 can determine that the overall calibration is not completed. In this case, the next calibration can represent the calibration for writing. Thus, the processing circuit 110 can subsequently perform and complete the calibration for writing. When step S38 is performed for the second time, the processing circuit 110 can determine that the overall calibration is completed. For the sake of brevity, similar contents in the embodiments are not repeated here.

[0084] For better understanding, the method can be illustrated by the workflow shown in Figure 10 but the present application is not limited thereto. According to certain embodiments, one or more steps can be added, deleted or modified in the workflow shown in Figure 10 For example, one or more error handling steps can be inserted in the partial workflow from step S36 to step S34 (e.g., when the determination result of step S36 is "no") for performing error handling. In the one or more error handling steps, the processing circuit 110 can first check whether the loop including steps S34, S35 and S36 has used up all the candidate positions in the plurality of candidate positions of the mask center point O. Among them, if the loop has used up all the candidate positions (which means that the failure of the reading test continues to occur until all the candidate positions are used up), the processing circuit 110 can issue an error message and then perform step S38, otherwise, the processing circuit 110 can perform step S34 to continue the operation of the loop. For the sake of brevity, similar contents in the embodiments are not repeated here.

[0085] The above only describes the preferred embodiments of the present application, and any equivalent changes and modifications made according to the protection scope required by the present application shall fall within the scope of the present application.

[0086] Legend of reference signs:

[0087] 10: electronic device

[0088] 100, 200, 300: system on chip (SoC) integrated circuit (IC)

[0089] 100C: calibration control module

[0090] 100D: dynamic random access memory (DRAM)

[0091] 100N: non-volatile memory (NVM)

[0092] 110, 210, 310: processing circuitry

[0093] 120: physical layer (PHY) circuitry

[0094] 130: pad group

[0095] 140: static random access memory (SRAM)

[0096] POK1, POK2: test control unit

[0097] DQ: data pin

[0098] 200C: calibration control program

[0099] 210B: bus

[0100] 211, 311: processor

[0101] 212, 312: dynamic random access memory (DRAM) controller

[0102] 213: controller

[0103] 300C: calibration control circuitry

[0104] MASK_AB, MASK_A2D_Tx, MASK_A2D_Rx, MASK: predetermined mask

[0105] O: center point

[0106] O1-O11: candidate position

[0107] A, B, C, D: test point

[0108] HT: horizontal time pitch

[0109] IP: inter-branch period

[0110] m, n, x, y: mask coefficient

[0111] Vref, Vref_P, Vref_N: reference voltage

[0112] E, F: reference point

[0113] TD, TD_P, TD_N: time difference

[0114] PHASE_1: power-up and initialization phase

[0115] PHASE_2: ZQ calibration phase

[0116] PHASE_3: phase and / or reference voltage calibration phase

[0117] S31-S38: Steps

Claims

1. A method for memory calibration applicable to a system-on-chip integrated circuit, the method comprising: controlling, in a power-up and initialization phase of the system-on-chip integrated circuit, a physical layer circuit of the system-on-chip integrated circuit to apply power to a memory through a set of pads and to initialize the memory; triggering, in an impedance calibration related phase of the system-on-chip integrated circuit, the memory to perform impedance calibration with respect to a set of data pins; performing, in at least one subsequent phase of the system-on-chip integrated circuit, data access testing corresponding to a set of test points on a predetermined mask that is movable with respect to a data eye, during any one of a calibration for read and a calibration for write; and selectively ending the any one of the calibration depending on whether the data access testing is successful; wherein possible positions of the predetermined mask with respect to the data eye correspond to a plurality of candidate positions of a center point of the predetermined mask, and the any one of the calibration is performed for at least one round, wherein the one or more rounds correspond to at least one candidate position of the plurality of candidate positions.

2. The method of claim 1, wherein, selectively ending the any one of the calibration depending on whether the data access testing is successful, further comprises: selectively ending the any one of the calibration depending on whether the data access testing is successful, to reduce a total time of all calibrations in the at least one subsequent phase.

3. The method of claim 1, wherein, selectively ending the any one of the calibration depending on whether the data access testing is successful, further comprises: ending the any one of the calibration in response to the data access testing being successful.

4. The method of claim 1, wherein, selectively ending the any one of the calibration depending on whether the data access testing is successful, further comprises: triggering to continue the any one of the calibration with the predetermined mask moved in response to the data access testing being unsuccessful.

5. The method of claim 1, wherein, selectively ending the any one of the calibration depending on whether the data access testing is successful, further comprises: ending the any one of the calibration for a current round in response to the data access testing being successful, or triggering another round of the any one of the calibration in response to the data access testing being unsuccessful.

6. The method of claim 1, wherein, Success of the data access testing on the set of test points indicates that the data access testing on all possible test points within an area enclosed by the predetermined mask is expected to be successful.

7. A system-on-chip integrated circuit having a memory calibration function, the system-on-chip integrated circuit comprising: a processing circuit to control operation of the system-on-chip integrated circuit; a physical layer circuit coupled to the processing circuit to communicate for the processing circuit and a memory; and a set of pads comprising a plurality of pads as terminals of the system-on-chip integrated circuit to couple the system-on-chip integrated circuit to at least one external element, wherein the at least one external element comprises the memory; wherein: in a power-up and initialization phase of the system-on-chip integrated circuit, the processing circuit controls the physical layer circuit to apply power to the memory through the set of pads and to initialize the memory; in a phase related to impedance calibration of the system-on-chip integrated circuit, the processing circuitry triggers the memory to perform impedance calibration with respect to a set of data pins; in at least one subsequent phase of the system-on-chip integrated circuit, during performance of either of calibration for read and calibration for write, the processing circuitry performs data access testing corresponding to a set of test points on a predetermined mask, wherein the predetermined mask is movable with respect to a data eye; and in accordance with whether the data access testing is successful, the processing circuitry selectively ends the either of calibration; wherein possible positions of the predetermined mask with respect to the data eye correspond to a plurality of candidate positions of a center point of the predetermined mask, the either of calibration is performed for one or more rounds, wherein the one or more rounds correspond to at least one candidate position of the plurality of candidate positions.

8. A non-transitory computer-readable medium storing code to cause a system-on-chip integrated circuit to perform a memory calibration procedure when the code is executed by the system-on-chip integrated circuit, the memory calibration procedure comprising: in a power-up and initialization phase of the system-on-chip integrated circuit, controlling a physical layer circuitry in the system-on-chip integrated circuit to apply power to a memory through a set of bond pads and to initialize the memory; in a phase related to impedance calibration of the system-on-chip integrated circuit, triggering the memory to perform impedance calibration with respect to a set of data pins; in at least one subsequent phase of the system-on-chip integrated circuit, during performance of either of calibration for read and calibration for write, performing data access testing corresponding to a set of test points on a predetermined mask, wherein the predetermined mask is movable with respect to a data eye; and in accordance with whether the data access testing is successful, selectively ending the either of calibration; wherein possible positions of the predetermined mask with respect to the data eye correspond to a plurality of candidate positions of a center point of the predetermined mask, the either of calibration is performed for one or more rounds, wherein the one or more rounds correspond to at least one candidate position of the plurality of candidate positions. ​

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