Method for screening weak bits in a memory array

Abstract

Embodiments of the invention provide a method of screening for weak bits in a memory array, comprising: storing a first set of data in a first memory array of a memory array having a first set of memory cells; at least one of applying a first bake process to the first memory array or applying a first magnetic field to the first memory array; determining whether a portion of the first set of data stored in the first memory array is changed by the first bake process or the first magnetic field; and if a first memory cell of the first set of memory cells stores the changed data, tracking an address of at least the first memory cell of the first set of memory cells, and at least one of: (1) replacing the first memory cell of the first set of memory cells storing the changed data with a corresponding memory cell in a second memory array of the memory array, and (2) discarding the first memory cell of the first set of memory cells storing the changed data.

Description

[0001] Divisional Application

[0002] This application is a divisional application of patent application number 202010288375.8, filed on June 28, 2017, entitled “Error Correction Method in Memory Array”. TECHNICAL FIELD

[0003] Embodiments of the present invention relate generally to the field of semiconductor technology, and more particularly to a method of screening weak bits in a memory array. BACKGROUND

[0004] The semiconductor integrated circuit (IC) industry has produced a variety of digital devices to solve problems in a number of different fields. Some of these digital devices, such as memory arrays, are configured to store data. During the manufacturing process of a memory array, portions of the memory array are destroyed or contain corrupted data. SUMMARY

[0005] According to an aspect of the present invention, there is provided a method of correcting errors in a memory array, the method comprising: configuring a first memory array having a first error correcting code (ECC) to provide error correction of data stored in the first memory array, the first memory array comprising a first set of memory cells arranged in a plurality of rows and a plurality of columns, a row of memory cells of the first set of memory cells comprising a first set of memory words, each word of the first set of memory words comprising a first set of bits; configuring a second memory array having a second ECC to provide error correction of data stored in the first memory array, the second memory array comprising a second set of memory cells arranged in a plurality of rows and a plurality of columns, a row of memory cells of the second set of memory cells comprising a second set of memory words, each word of the second set of memory words comprising a second set of bits; subjecting the first memory array and the second memory array to a reflow process; and correcting data stored in the first memory array based at least on the first ECC or the second ECC.

[0006] According to another aspect of the present disclosure, there is provided a method of correcting errors in a memory array, the method comprising: configuring a first memory array having a first error correcting code (ECC) to provide error correction of data stored in the first memory array, the first memory array comprising a first set of memory cells arranged in a plurality of rows and a plurality of columns, a row of memory cells in the first set of memory cells comprising a first set of memory words, each word in the first set of memory words comprising a first set of bits; configuring a first portion of a second memory array having a first parity configured to provide error detection of the data stored in rows of the first memory array, the first portion of the second memory array comprising a second set of memory cells storing a first set of data; configuring a second portion of the second memory array having a second parity configured to provide error detection of data stored in columns of the first memory array, the second portion of the second memory array comprising a third set of memory cells storing a second set of data; configuring the second portion of the second memory array having a second ECC to provide error correction of the second set of data stored in the second portion of the second memory array; subjecting the first memory array and the second memory array to a reflow process; correcting at least a portion of the data stored in the first memory array based on at least (1) the first ECC or (2) the first parity and the second parity; and correcting the second set of data stored in the second portion of the second memory array based on the second ECC.

[0007] According to yet another aspect of the present disclosure, there is provided a method of correcting errors in a memory array, the method comprising: configuring a first memory array having a first error correcting code (ECC) to provide error correction of a set of data stored in the first memory array, thereby generating a first set of data, the first memory array comprising a first set of memory cells arranged in a plurality of rows and a plurality of columns, a row of memory cells in the first set of memory cells comprising a first set of memory words, each word in the first set of memory words comprising a first set of bits; storing a second set of data in a second memory array, the second set of data comprising at least a copy of the first set of data, the second memory array comprising a second set of memory cells arranged in a plurality of rows and a plurality of columns; subjecting the first memory array and the second memory array to a reflow process; recovering at least a portion of the first set of data based on the first set of data and the second set of data; and correcting errors in the recovered first set of data based on the ECC.

[0008] According to yet another aspect of the present application, there is provided a method of screening for weak bits in a memory array, the method comprising: storing a first set of data in a first memory array of the memory array, the first memory array having a first set of memory cells; at least one of applying a first bake process to the first memory array or applying a first magnetic field to the first memory array; determining whether a portion of the first set of data stored in the first memory array is changed by the first bake process or the first magnetic field; and if the first memory cell of the first set of memory cells stores the changed data, tracking an address of at least the first memory cell of the first set of memory cells, and at least one of (1) replacing the first memory cell of the first set of memory cells storing the changed data with a corresponding memory cell in a second memory array of the memory array, or (2) discarding the first memory cell of the first set of memory cells storing the changed data.

[0009] According to yet another aspect of the present application, there is provided a method of correcting errors in a memory array, the method comprising: screening for weak bits in a first memory array of the memory array, the first memory array comprising a first set of memory cells arranged in a plurality of rows and a plurality of columns, a row of memory cells of the first set of memory cells comprising a first set of memory words, each word of the first set of memory words comprising a first set of bits; storing a set of data in the first memory array; configuring the first memory array with a first error correcting code (ECC) to provide error correction of the set of data stored in the first memory array, thereby generating a first set of data; storing a second set of data in a second memory array, the second set of data comprising an even number of copies of the first set of data, the second memory array comprising a second set of memory cells arranged in a plurality of rows and a plurality of columns; applying a reflow process to the first memory array and the second memory array; recovering at least a portion of the first set of data based on the first set of data and the second set of data; and correcting errors in the recovered first set of data based on the ECC.

[0010] According to yet another aspect of the present application, there is provided a memory system, comprising: a first memory array configured with a first error correcting code (ECC) to provide error correction of data stored in the first memory array, the first memory array comprising a first set of memory cells arranged in a plurality of rows and a plurality of columns, a row of memory cells of the first set of memory cells comprising a first set of memory words, each word of the first set of memory words comprising a first set of bits; a second memory array configured with a second ECC to provide error correction of data stored in the first memory array, the second memory array comprising a second set of memory cells arranged in a plurality of rows and a plurality of columns, a row of memory cells of the second set of memory cells comprising a second set of memory words, each word of the second set of memory words comprising a second set of bits, the first memory array and the second memory array being portions of a same memory array; and a configuration system connected to the first memory array and the second memory array, the configuration system configuring the first memory array with the first ECC and configuring the second memory array with the second ECC. BRIEF DESCRIPTION OF DRAWINGS

[0011] Various aspects of the application can be best understood from the following detailed description when read with the accompanying drawings. It is noted that, in accordance with the standard practice in the industry, various components are not drawn to scale. In fact, the dimensions of the various components can be arbitrarily increased or decreased for the sake of a discussion of clarity.

[0012] Figure 1 is a block diagram of a memory system according to some embodiments.

[0013] Figure 2 is a flowchart of a method of correcting errors in a memory system according to some embodiments.

[0014] Figure 3A is a diagram of a portion of a memory array according to some embodiments.

[0015] Figure 3B is a flowchart of a method of correcting errors in a memory array according to some embodiments.

[0016] Figure 4A is a diagram of a portion of a memory array according to some embodiments.

[0017] Figure 4B is a diagram of a portion of a memory array according to some embodiments.

[0018] Figure 4C is a flowchart of a method of correcting errors in a memory array according to some embodiments.

[0019] Figure 5Ais a diagram of a portion of a memory array according to some embodiments.

[0020] Figure 5B is a flowchart of a method of correcting errors in a memory array according to some embodiments.

[0021] Figure 5C is a block diagram of a system according to some embodiments.

[0022] Figure 6 is a flowchart of a method of correcting errors of a memory array according to some embodiments.

[0023] Figure 7 is a block diagram of a system for configuring a memory array according to some embodiments. DETAILED DESCRIPTION

[0024] The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components, materials, values, steps, arrangements, etc. are described herein to simplify the present disclosure. Of course, such are merely examples and are not intended to limit the present application in any way. Other components, materials, values, steps, arrangements, etc. are contemplated. For instance, in the following description, forming a first component over or on a second component can include embodiments in which the first component and the second component are formed in direct contact, and can also include embodiments in which additional components can be formed between the first component and the second component, such that the first component and the second component can not be in direct contact. Furthermore, the present application can be repeated with various example reference numerals and / or characters in various instances. This repetition is for simplicity and clarity and does not itself dictate a relationship between the various embodiments and / or configurations discussed.

[0025] Also, spatially relative terms, such as "beneath", "below", "lower", "above", "upper" and the like, can be used herein for ease of description to describe one element or component's relationship to another element(s) or component(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The devices can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0026] According to some embodiments, the memory array is subjected to a reflow process. According to some embodiments, the reflow process is a process in which at least one electrical component in the memory array is temporarily attached to at least one contact pad using solder paste. Thereafter, the entire device is subjected to controlled heating, thereby melting the solder and providing a permanent connection between the at least one electrical component and the at least one contact pad. However, the reflow process can damage data contained in the memory array or can damage memory cells within the memory array.

[0027] According to some embodiments, a method of correcting errors in a memory array includes configuring a first memory array with a first error correcting code (ECC) to provide error correction of data stored in the first memory array, configuring a second memory array with a second ECC to provide error correction of data stored in the first memory array, subjecting the first memory array and the second memory array to a reflow process, and correcting data stored in the first memory array based on at least the first ECC or the second ECC. According to some embodiments, the first memory array and the second memory array are portions of a memory array. According to some embodiments, the first ECC or the second ECC is used to correct bit errors introduced by the reflow process.

[0028] Figure 1 is a block diagram of a memory system 100 according to some embodiments.

[0029] The memory system 100 includes an integrated circuit (IC) 102 electrically connected to a configuration system 104. The IC 102 includes a memory array 102a configured to store data. In some embodiments, the IC 102 includes other circuitry or is configured to store or execute software, which is not shown for simplicity. In some embodiments, the IC 102 is configured to repair or detect errors in data stored in the memory array 102a. Repairing errors includes overwriting data with correct data provided by an error correcting code (ECC) or flipping a logical value of existing data in a faulty location of the memory array 102a.

[0030] The memory array 102a includes a plurality of banks of memory cells. Each bank includes a plurality of rows, a plurality of columns, and associated circuitry such as sense amplifiers, word lines, bit lines, etc. The size of the memory 102a includes, for example, 1, 2, 4 megabytes (Mb), etc., depending on the application. Other memory sizes are within the scope of various embodiments. In some embodiments, a row of memory cells is referred to as a data bit. Various embodiments of the present invention provide mechanisms for repairing errors that occur in the memory array 102a using one or more ECCs. The memory array 102a is a non-volatile memory. In some embodiments, the memory array 102a includes resistive random access memory (RRAM), magnetoresistive RAM (MRAM), phase change RAM (PRAM), ferroelectric RAM (FRAM), or other suitable memory types. Other memory types are within the scope of various embodiments.

[0031] The configuration system 104 interfaces with the integrated circuit 102 to configure the memory array 102a with one or more ECC configurations or error detection configurations. In some embodiments, the configuration system 104 includes a hardware processor and a non-transitory computer-readable storage medium encoded with (i.e., storing) a set of executable instructions. Embodiments of the configuration system 104 are shown in Figure 7 FIG. 8 as system 700. The configuration system 104 is separate from the IC 102. In some embodiments, the configuration system 104 is part of the IC 102.

[0032] Figure 2 is a flowchart of a method 200 of correcting errors in a memory system 100 according to some embodiments. It should be understood that additional operations can be implemented before, during, and / or after the method 200 shown, and thus some other operations are only briefly described herein. In some embodiments, the method 200 can be used to configure an IC 102 with ECC (as in Figure 2 ), and to correct errors in the memory array 102a based at least on the ECC. Figure 1

[0033] In operation 202 of the method 200, the memory array 102a is configured. In some embodiments, the memory array 102a is configured with error correction to be able to correct one or more errors in data stored in the memory array 102a. For example, in some embodiments, the memory array 102a is configured with ECC to correct one or more errors in data stored in the memory array 102a. In some embodiments, the ECC includes Hamming ECC, Reed-Solomon ECC, BCH codes, etc. In some embodiments, the memory array 102a is configured with error correction to be able to detect one or more errors in data stored in the memory array 102a. In some embodiments, the error detection includes parity to detect one or more bit errors (also referred to as errors) in data stored in the memory array 102a. Other ECC or error detection methods are within the scope of various embodiments.

[0034] The method 200 continues with operation 204, in which a reflow process is implemented on the memory array 102a. In some embodiments, the reflow process of operation 204 includes placing the memory array 102a into a reflow oven, and heating the reflow oven at a first temperature T1 for a first duration D1. In some embodiments, the reflow process of operation 204 includes exposing the memory array 102a to an infrared lamp, and heating the memory array 102a at a first temperature T1 for a first duration D1 by the infrared lamp.

[0035] ​Method 200 continues with operation 206, recovering data in memory array 102a. In some embodiments, ECC is used by IC 102 to recover data in memory array 102a. In some embodiments, the ECC includes at least the first ECC, the second ECC, or the third ECC. In some embodiments, the first parity and the second parity are used by IC 102 to recover data in memory array 102a.

[0036] Figure 3A is a diagram of a portion of a memory array 300 according to some embodiments.

[0037] Memory array 300 is Figure 1 an embodiment of memory array 102a of FIG. 1. Memory array 300 includes a first memory array 302 and a second memory array 304.

[0038] First memory array 302 is directly adjacent to second memory array 304. In some embodiments, first memory array 302 is separated from second memory array 304 by another region (not shown). First memory array 302 and second memory array 304 are portions of the same memory array 300. In some embodiments, first memory array 302 and second memory array 304 are corresponding portions of different memory arrays.

[0039] First memory array 302 includes a first set of memory cells arranged in a plurality of rows and a plurality of columns. Each row of memory cells in the first set of memory cells includes a first set of memory words. For illustration, a row 315 of memory cells is shown, but the teachings of row 315 are applicable to each row of memory cells in first memory array 302. Row 315 of memory cells in the first set of memory cells includes a first set of memory words W[l], W[2], W[3], or W[4] (collectively, words "W"). A common number of words W in a row includes 8, 16, 32, 64, etc. Different numbers of words W in a row of memory cells of the first set of memory cells are within the scope of various embodiments. Each word of the first set of memory words W includes a plurality of memory cells or a plurality of memory bits. Word W[3] includes a first set of bits 315a and a second set of bits 315b. For simplicity, memory bits in words W[l], W[2], and W[4] are not shown.

[0040] First set of bits 315a includes bits Al,..., AX, where X is a positive integer corresponding to a number of data bits in first set of bits 315a in word W[3].

[0041] The second set of bits 315b includes bits B1...BZ, where Z is a positive integer corresponding to a number of bits in the second set of bits 315b. The second set of bits 315b is referred to as a first ECC 330, which is configured to provide N-bit error correction in the first set of bits 315a of the word W[3], where N is a positive integer.

[0042] The second memory array 304 is configured with a second ECC 332, which is configured to provide data error correction stored in the first memory array 302. The second memory array 304 includes a second set of memory cells arranged in a plurality of rows and a plurality of columns. Each row of memory cells in the second set of memory cells includes a second set of memory words. For illustration, a row 325 of memory cells is shown, but the teachings of the row 325 are applicable to each row of memory cells in the second memory array 304. The row 325 of memory cells in the second set of memory cells includes a second set of memory words SW[1], SW[2], SW[3], or SW[4] (collectively referred to as words “SW”). In some embodiments, each row of memory cells in the second set of memory cells has a corresponding row of memory cells in the first set of memory cells. A common number of words SW in a row includes 8, 16, 32, 64, etc. Different numbers of words SW in a row of memory cells of the second set of memory cells are within the scope of various embodiments. Each word of the second set of memory words SW includes a plurality of memory cells or a plurality of memory bits. The word SW[3] includes the first set of bits 325a. For brevity, the memory bits in the words SW[1], SW[2], and SW[4] are not shown. Each word in the first set of words W has a corresponding word in the second set of words SW. Each word in the second set of words SW is configured with the second ECC 332 to provide error correction for at least a corresponding portion of the word in the first set of words W. For brevity, the second ECC 332 in each word SW[1], SW[2], and SW[4] is not shown.

[0043] The first set of bits 325a includes bits C1, C2..., CZ’, where Z’ is a positive integer corresponding to a number of data bits in the first set of bits 325a in the word SW[3]. The first set of bits 325a is referred to as the second ECC 332, which is configured to provide M1-bit error correction in the first set of bits 315a of the word W[3]. In some embodiments, the second ECC 332 is configured to provide M1-bit error correction in the first set of bits 315a and the second set of bits 315b of the word W[3]. M1 is a positive integer greater than the integer N.

[0044] The integer M1 is represented by Equation 1:

[0045] M1 = N + M (1)

[0046] where M is a positive integer corresponding to the number of extra protected bits provided by the second ECC 332 to the word W[3] compared to the first ECC 330.

[0047] In some embodiments, the first memory array 302 and the second memory array 304 have the same number of rows or columns of memory cells. In some embodiments, the first memory array 302 and the second memory array 304 have different numbers of rows or columns of memory cells. In some embodiments, the second memory array 304 is a backup memory array configured to store temporary data. Different locations of the first memory array 302 and the second memory array 304 are within the scope of various embodiments. Different locations of the first set of words W or the first ECC 330 in the first memory array 302 and the second set of words SW or the second ECC 332 in the second memory array 304 are within the scope of various embodiments. Different locations of the rows 315 in the first memory array 302 and the rows 325 in the second memory array 304 are within the scope of various embodiments.

[0048] Figure 3B is a flowchart of a method 300' of correcting errors in a memory array 300 according to some embodiments.

[0049] The method 300' is an embodiment of the method 200 with similar elements. Figure 2 The method 300' is applied to the words W[3] and the words SW[3] in Figure 3A but in some embodiments, the method 300' can be applied to each row of memory cells in the first memory array 302 or the second memory array 304.

[0050] In operation 302' of the method 300', the memory array 300 Figure 3A is divided into the first memory array 302 and the second memory array 304.

[0051] The method 300' continues with operation 304' in which data is stored in the first memory array 302. In some embodiments, the data stored in the first memory array 302 is the first set of bits 315a. In some embodiments, the data stored in the first memory array 302 is a portion of the word W[3]. In some embodiments, the IC 102 is configured to store the data in the first memory array 302. In some embodiments, the configuration system 104 is configured to store the data in the first memory array 302.

[0052] Method 300' continues with operation 306', in which the first memory array 302 is configured with a first ECC 330 to provide error correction for data stored in the first memory array 302. In some embodiments, the first ECC 330 is configured to provide error correction for data (e.g., the first set of bits 315a) stored in the first memory array 302. The first ECC 330 is stored in the first memory array 302 as a second set of bits 315b.

[0053] Method 300' continues with operation 308', in which the second memory array 304 is configured with a second ECC 332 to provide error correction for at least a portion of the data (e.g., the first set of bits 315a) stored in the first memory array 302. In some embodiments, the first ECC 330 or the second ECC 332 includes a Hamming ECC, a Reed-Solomon ECC, or a BCH code, among others. Other ECCs are within the scope of various embodiments. In some embodiments, the system 104 is configured at least with the first memory array 302 having the first ECC 330 or the second memory array 304 having the second ECC 332 (e.g., the second set of bits 325a). Operations 304', 306', and 308' are embodiments of operation 202( Figure 2 ) of method 300.

[0054] Method 300' continues with operation 310', in which a reflow process is performed on the first memory array 302 and the second memory array 304. The reflow process of operation 310' is similar to the reflow process of operation 204( Figure 2 ) of method 300.

[0055] In some embodiments, the reflow process of operation 310' damages a portion of the data stored in the first memory array 302. In some embodiments, the portion of the data stored in the first memory array 302 is damaged prior to the reflow process. In some embodiments, the reflow process of operation 310' damages a memory cell in the first memory array 302 such that the damaged memory cell does not function properly.

[0056] Method 300' continues with operation 312', in which the data (e.g., the first set of bits 315a of word W[3]) stored in the first memory array 302 is corrected based at least on the first ECC 330 or the second ECC 332. In some embodiments, the second ECC 332 corrects the first set of bits 315a and the second set of bits 315b, and thus, the correcting data of operation 312' includes the first set of bits 315a and the second set of bits 315b.

[0057] In some embodiments, if the number of bit errors in at least a portion of a word of the first set of words W in the first memory array 302 is less than or equal to N bits, data stored at the word of the first set of words W in the first memory array 302 is corrected based on the first ECC 330 (e.g., the first set of bits 315a). For example, in some embodiments, if the number of bit errors in the word W[3] of the first set of words W in the first memory array 302 is less than or equal to N bits, at least a portion of data stored at the word W[3] in the first memory array 302 (e.g., the first set of bits 315a) is corrected based on the first ECC 330.

[0058] In some embodiments, if the number of bit errors in at least a portion of a word of the first set of words W in the first memory array 302 is greater than N bits and less than or equal to Ml bits, data stored at the word of the first set of words in the first memory array 302 (e.g., the first set of bits 315a or the second set of bits 315b) is corrected based on the second ECC 332. For example, in some embodiments, if the number of bit errors in the word W[3] of the first set of words W in the first memory array 302 is greater than N bits and less than or equal to Ml bits, data stored at the word W[3] in the first memory array 302 (e.g., the first set of bits 315a or the second set of bits 315b) is corrected based on the second ECC 332. Operation 312’ is an embodiment of operation 206( Figure 2 ) of FIG. 2.

[0059] Method 300’ continues with operation 314’, in which at least a portion of the second memory array 304 is released. In some embodiments, operation 314’ includes designating at least a portion of the second memory array 304 as available memory cells for writing by the IC 102 or other circuitry. In some embodiments, operation 302’ or 314’ is optional.

[0060] Using at least one of the presently disclosed methods, a memory array (e.g., memory array 102a, Figure 3A memory array 300 of FIG. 3, Figure 4A memory array 400A of FIG. 4A, Figure 4B memory array 400B of FIG. 4B, or Figure 5AThe error correction capability of the memory array (e.g., memory array 102a, 300, 400A, 400B, or 500) using at least one of the presently disclosed methods is greater than other methods, resulting in a memory array (e.g., memory array 102a, 300, 400A, 400B, or 500) having a lower bit error rate (BER) and a lower field return rate than other methods. In some embodiments, the field return rate is a failure rate of a memory array die in an integrated circuit after a reflow process. Using at least one of the presently disclosed methods, an ECC (e.g., first ECC 330, second ECC 332, 432, 434, 530, or third ECC 532) or a parity (e.g., first parity 420 or 424 or second parity 422) is used to correct bit errors introduced into a memory array (e.g., memory array 102a, 300, 400A, 400B, or 500) by a reflow process, a bake process, or an applied magnetic field.

[0061] Figure 4A is a diagram of a memory array 400A in accordance with some embodiments.

[0062] Memory array 400A is Figure 1 an embodiment of memory array 102a. Memory array 400A is Figure 3A a variation of memory array 300. Memory array 400A includes a first memory array 402 in place of first memory array 302 and a second memory array 404 in place of second memory array 304.

[0063] First memory array 402 is a first memory array 302 Figure 3A ). Second memory array 404 is a variation of second memory array 304 Figure 3A ).

[0064] Second memory array 404 includes a first portion 404a and a second portion 404b.

[0065] First portion 404a includes a second set of memory cells arranged in columns. The columns of memory cells are configured to store a first set of data P1, P2,..., PY (collectively referred to as first set of data “P”), where Y is a positive integer corresponding to a number of bits of the first set of data P or corresponding to a number of rows of memory cells in first memory array 402.

[0066] The first set of data P is configured as a first set of parity bits in a first parity 420. The first parity 420 is configured to provide parity error detection for data stored in each row of the first memory array 402 (e.g., row 315, first set of bits 315a, or second set of bits 315b). The first parity 420 is an even parity or an odd parity. Each row of parity data in the first set of data P corresponds to a parity of data for a corresponding row in the first memory array 402.

[0067] A second portion 404b of the second memory array 404 is configured with a second parity 422 and a second ECC 432. The second portion 404b includes a third set of memory cells arranged in a plurality of rows and a plurality of columns. Each row of memory cells in the third set of memory cells includes a second set of memory words. For illustration, a row of memory cells 425 is shown, but the teachings of row 425 are applicable to each row of memory cells in the second portion 404b of the second memory array 404. The row of memory cells 425 in the third set of memory cells includes a second set of memory words SW[1]’, SW[2]’, SW[3]’, or SW[4]’ (collectively, words “SW’”). In some embodiments, each row of memory cells in the third set of memory cells has a corresponding row of memory cells in the first set of memory cells of the first memory array 402. A common number of words SW’ in a row includes 8, 16, 32, 64, etc. Different numbers of words SW’ in a row of memory cells of the third set of memory cells are within the scope of various embodiments. Each word of the second set of memory words SW’ includes a plurality of memory cells or a plurality of memory bits. Word SW[3]’ includes a first set of bits 425a and a second set of bits 425b. For brevity, bits in words SW[1]’, SW[2]’, and SW[4]’ are not shown. Each word in the second set of words SW’ has a corresponding word in the first set of words W.

[0068] The first set of bits 425a includes bits P1’,..., PX’, where X’ is a positive integer corresponding to a number of data bits in the first set of bits 425a in word SW[3]’. The first set of bits 425a is configured as a second set of parity bits of the second parity 422. The second parity 422 is configured to provide parity error detection for data stored in each column of the first memory array 402. The second parity 422 is an even parity or an odd parity. In some embodiments, each word in the second set of words SW’ is associated with memory cells of a corresponding column in the first memory array 402. In some embodiments, a portion of each word in the second set of words SW’ is a second parity of memory cells of a corresponding column in the first memory array 402.

[0069] The second set of bits 425b includes bits D1,..., DZ', where Z' is a positive integer corresponding to the number of bits in the second set of bits 425b. The second set of bits 425b is referred to as a second ECC 432 configured to provide N1-bit error correction in the first set 425a of words SW[3]'. N1 is a positive integer. Each word in the second set of words SW' is configured with the second ECC 432 to provide partial error correction of the word in the second set of words SW'. For brevity, the second ECC in each of the words SW[1]', SW[2]', and SW[4]' is not shown.

[0070] In some embodiments, the first memory array 402 and the second memory array 404 have the same number of rows or columns of memory cells. In some embodiments, the first memory array 402 and the second memory array 404 have different numbers of rows or columns of memory cells. In some embodiments, the second memory array 404 is a backup memory array configured to store temporary data. Different locations of the first memory array 402 and the second memory array 404 are within the scope of various embodiments. Different locations of the first portion 404a or the second portion 404b are within the scope of various embodiments. Different locations of the first set of words W or the first ECC 330 in the first memory array 402 and the second set of words SW' or the second ECC 432 in the second memory array 404 are within the scope of various embodiments. Different locations of the rows 315 in the first memory array 402 and the rows 425 in the second memory array 404 are within the scope of various embodiments. In some embodiments, the first ECC 330 is optional, thus, the first memory array 402 does not include the first ECC 330, and the word W[3] does not include the second set of bits 315b.

[0071] Figure 4B is a diagram of a memory array 400B according to some embodiments.

[0072] The memory array 400B is an embodiment of the memory array 102a of Figure 1 The memory array 400B is a variant of the memory array 400A of Figure 4A The memory array 400B includes a first memory array 402 and a second memory array 406. In comparison to Figure 4A the memory array 400A of Figure 4B the second memory array 406 of replaces the second memory array 404.

[0073] The second memory array 406 is a variant of the second memory array 404 Figure 4A ) of

[0074] The second memory array 406 includes a first portion 406a and a second portion 406b. The second portion 406b isFigure 4A The first portion 406a is a variation of the first portion 404a. Figure 4A

[0075] The first portion 406a includes a fourth set of memory cells arranged in multiple rows and multiple columns. The first portion 406a is configured with a first parity 424 and a third ECC 434.

[0076] Each row of memory cells in the fourth set of memory cells includes a third set of memory words. For illustration, a row 435 of memory cells is shown, but the teachings of the row 435 are applicable to each row of memory cells in the first portion 406a of the second memory array 406. The row 435 of memory cells in the fourth set of memory cells includes a third set of memory words S[l], S[2], S[3], or S[4] (collectively, words “S”). In some embodiments, each row of memory cells in the fourth set of memory cells has a corresponding row of memory cells in the first set of memory cells of the first memory array 402 or in the third set of memory cells in the second portion 406b of the second memory array 406.

[0077] A common number of words S in a row includes 8, 16, 32, 64, and so on. Different numbers of words S in a row of memory cells in the fourth set of memory cells are within the scope of various embodiments. Each word of the third set of memory words S includes a plurality of memory cells or a plurality of memory bits. The word S[3] includes a first set of bits 435a and a second set of bits 435b. For simplicity, the memory bits in the words S[l], S[2], and S[4] are not shown. In some embodiments, each word in the third set of words S has a corresponding word in the first set of words W or the second set of words W’.

[0078] The first set of bits 435a is a first set of data P in the word S[3]. Figure 4B The first set of bits 435a includes bits P1’,..., PY’, where Y’ is a positive integer corresponding to a number of data bits in the first set of bits 435a of the word S[3]. The first set of bits 435a is configured as a first set of parity bits in the first parity 424. The first parity 424 is configured to provide parity error detection of data stored in the row 315 of the first memory array 402. The first parity 424 is an even parity or an odd parity.

[0079] ​In some embodiments, each word in the third set of words S is associated with a corresponding row of memory cells in the first memory array 402. In some embodiments, a portion of each word in the third set of words S is a first parity of the corresponding row of memory cells in the first memory array 402. For example, in these embodiments, the first parity 424 is configured to provide a parity error detection of the data stored in the row 315 of the first memory array 402.

[0080] The second set of bits 435b includes bits E1,..., EZ”, where Z” is a positive integer corresponding to the number of bits in the second set of bits 435b. The second set of bits 435b is referred to as a third ECC 434, which is configured to provide an N2-bit error correction in the first set of bits 435a of the word S[3], where N2 is a positive integer. Each word in the third set of words S is configured with the third ECC 434 to provide a partial error correction of the word in the third set of words S. For simplicity, the third ECC in each word S[1], S[2], and S[4] is not shown. In some embodiments, the integer N, N1, or N2 is different from the other one of the integers N, N1, or N2.

[0081] Different locations of the first portion 406a or the second portion 406b are within the scope of various embodiments. Different locations of the first set of words W in the first memory array 402 or the first ECC 330, the second set of words SW’ in the second memory array 404 or the second ECC 432, or the third set of words S in the second memory array 404 or the third ECC 434 are within the scope of various embodiments. Different locations of the row 315 in the first memory array 402 and the row 425 or the row 435 in the second memory array 406 are within the scope of various embodiments. In some embodiments, the first ECC 330 is optional, and thus, the first memory array 402 does not include the first ECC 330 and the word W[3] does not include the second set of bits 315b.

[0082] Figure 4C is a flowchart of a method 400C of correcting errors in a memory array 400A or 400B in accordance with some embodiments.

[0083] The method 400C is an embodiment of the method 200 with similar elements. Figure 2 The method 400C is an embodiment of the method 200 with similar elements. For simplicity, the method 400C is applied to the word W[3] and the words SW[3]’ and S[3] in Figure 4A - Figure 4B The method 400C is an embodiment of the method 200 with similar elements. For simplicity, the method 400C is applied to the word W[3] and the words SW[3]’ and S[3] in

[0084] In operation 402’ of the method 400C, the memory array 400A Figure 4A) is divided into a first memory array 402 and a second memory array 404. In some embodiments, the memory array 400B Figure 4B ) is divided into a first memory array 402 and a second memory array 406.

[0085] The method 400C continues with operation 404', in which data is stored in the first memory array 402. In some embodiments, the data stored in the first memory array 402 is the first set of bits 315a. In some embodiments, the data stored in the first memory array 402 is the portion of the word W[3]. In some embodiments, the IC 102 is configured to store the data in the first memory array 402. In some embodiments, the configuration system 104 is configured to store the data in the first memory array 402.

[0086] The method 400C continues with operation 406', in which the first memory array 402 is configured with a first ECC 330 to provide error correction for the data stored in the first memory array 402. In some embodiments, the first ECC 330 is configured to provide error correction for the data (e.g., the first set of bits 315a) stored in the first memory array 402. In some embodiments, the configuration system 104 is configured with the first memory array 402 having the first ECC 330. The first ECC 330 is stored in the first memory array 402 as a second set of bits 315b.

[0087] The method 400C continues with operation 408', in which a first portion 404a of the second memory array 404 Figure 4A ) is configured with a first parity 420. The first parity 420 is configured to provide error detection for the data stored in the row of the first memory array 402. In some embodiments, the operation 408' is applied to the memory array 400B Figure 4B of FIG. 4B, in which a first portion 406a of the second memory array 406 is configured with a first parity 424. In some embodiments, the first portion 404a of the second memory array 404 includes a second set of memory cells configured to store a first set of data P (e.g., the first parity 420). In some embodiments, the first portion 406a of the second memory array 406 includes a second set of memory cells configured to store a first set of data (e.g., the first set of bits 435a for the word W[3]).

[0088] The method 400C continues with operation 410', in which a second portion 404b of the second memory array 404 is configured with a second parity 422. The second parity 422 is configured to provide error detection for the data stored in the column of the first memory array 402. In some embodiments, the operation 410' is applied to the memory array 400B Figure 4Bthe second portion 406b of the second memory array 406 is configured with a second parity 422. In some embodiments, the second portion 404b of the second memory array 404 or the second portion 406b of the second memory array 406 includes a third set of memory cells configured to store a second set of data (e.g., the first set of bits 425a for the word SW[3]’).

[0089] The method 400C continues with operation 412’, in which, Figure 4B the second portion 404b of the second memory array 404 is configured with a second ECC 432 to provide error correction for data (e.g., the first set of bits 425a) stored in the second memory array 404. In some embodiments, the configuration system 104 configures the second memory array 404 with the second ECC 432 (e.g., the second set of bits 425b). In some embodiments, operation 412’ is applied to Figure 4B the second portion 406b of the second memory array 406 is configured with a second ECC 432 to provide error correction for data (e.g., the first set of bits 425a) stored in the second memory array 406.

[0090] The method 400C continues with operation 414’, in which, Figure 4B the first portion 406a of the second memory array 406 is configured with a third ECC 434 to provide error correction for a first set of data (e.g., the first set of bits 435a) stored in the first portion 406a of the second memory array 406. In some embodiments, the first set of bits 435a is a set of parity bits.

[0091] In some embodiments, the first ECC 330, the second ECC 432, or the third ECC 434 includes a Hamming ECC, a Reed-Solomon ECC, a BCH code, etc. Other ECCs are within the scope of various embodiments. In some embodiments, the configuration system 104 configures the second memory array 406 with the third ECC 434 (e.g., the second set of bits 435b). Operations 404’, 406’, 408’, 410’, 412’, and 414’ are embodiments of operation 202( Figure 2 ) of the method 400A.

[0092] The method 400C continues with operation 416’, in which, a reflow process is performed on the first memory array 402 and the second memory array 404 or 406. The reflow process of operation 416’ is operation 204( Figure 2the reflow process of operation 416'. In some embodiments, the portion of the data stored in the first memory array 402 is damaged prior to the reflow process of operation 416'. In some embodiments, the reflow process of operation 416' damages memory cells in the first memory array 402 such that the damaged memory cells do not function properly.

[0093] The method 400C continues with operation 418', in which at least a portion of the data stored in the first memory array 402 (e.g., the word W[3] or the first set of bits 315a) is corrected based on at least (1) the first ECC 330 or (2) the first parity 420 and the second parity 422. In some embodiments, the correction of the data of operation 418' includes the first set of bits 315a and the second set of bits 315b.

[0094] In some embodiments, the first ECC 330 is an N-bit ECC, where N is a positive integer corresponding to a number of bits in at least one word of the first set of memory words W that are provided error protection by the first ECC 330. In some embodiments, operation 418' includes correcting N-bit errors in the words of the first set of words W based on the first ECC 330 and correcting single-bit errors in the words of the first set of words W based on a combination of the first parity 420 (or the first parity 424 in the first set of words W) and the second parity 422. In some embodiments, the first parity 420 (or the first parity 424 in the first set of words W) and the second parity 422 collectively provide 1-bit-5-bit error protection. Figure 4B Figure 4B In some embodiments, the first parity 420 (or the first parity 424 in the first set of words W) and the second parity 422 collectively provide 1-bit-5-bit error protection.

[0095] In some embodiments, if a number of errors in at least a portion of the words of the first set of words W in the first memory array 402 is less than or equal to N bits, the data stored at the words of the first set of words W in the first memory array 402 (e.g., the first set of bits 315a) is corrected based on the first ECC 330. For example, in some embodiments, if a number of errors in the words W[3] of the first set of words W in the first memory array 302 is less than or equal to N bits, at least a portion of the data stored at the words W[3] (e.g., the first set of bits 315a) in the first memory array 402 is corrected based on the first ECC 330.

[0096] In some embodiments, if a number of errors in at least a portion of the words of the first set of words W in the first memory array 402 is greater than N bits and less than or equal to N+1 bits, the first ECC corrects N-bit errors in the words of the first set of words in the first memory array 402 and the first parity 420 (or the first parity 424 in the first set of words W) and the second parity 422 corrects the single-bit error in the words of the first set of words in the first memory array 402. Figure 4B ​The combination of the first parity check (424) and the second parity check (422) in the first memory array 402 corrects bit errors in the first group of words.

[0097] Method 400C continues with operation 420', wherein the first set of data (e.g., the first set of bits 435a) stored in the first portion 406a of the second memory array 406 is corrected based on the third ECC 434. In some embodiments, operations 414' and 420' are not applied. Figure 4A The memory array 400A.

[0098] Method 400C continues operation 422', wherein the correction based on the second ECC 432 is stored Figure 4A The second set of data (e.g., the first set of bits 425a) in the second portion 404b of the second memory array 404. In some embodiments, operation 422' is applied to... Figure 4B The memory array 400B, wherein, based on the second ECC 432 correction, is stored in... Figure 4B The second set of data (e.g., the first set of bits 425a) in the second part 406b of the second memory array 406.

[0099] Method 400C continues with operation 424', wherein at least a portion of the second memory array 404 or the second memory array 406 is released. In some embodiments, operation 424' includes designating at least a portion of the second memory array 404 or the second memory array 406 as memory cells writable by IC 102 or other circuitry. In some embodiments, one or more of operations 402', 406', 414', 420', 422', or 424' are optional.

[0100] Figure 5A This is a diagram of a memory array 500 according to some embodiments.

[0101] Memory Array 500 is Figure 1 An embodiment of memory array 102a. Memory array 500A is... Figure 3A A variation of the memory array 300. The memory array 500A includes a first memory array 502 replacing the first memory array 302 and a second memory array 504 replacing the second memory array 304.

[0102] The first memory array 502 is the first memory array 302 ( Figure 3A The second memory array 504 is the second memory array 304. Figure 3A A variant of ). The second memory array 504 includes a first part 504a and a second part 504b.

[0103] In some embodiments, the first portion 504a or the second portion 504b is a copy of the first memory array 502. In some embodiments, the first portion 504a is a copy of the second portion 504b. In some embodiments, the second memory array 504 includes an even number (e.g., integer K is even) of copies of the first memory array 502. In some embodiments, the data stored in the second memory array 504 includes an even number (e.g., integer K is even) of copies of the data in the first memory array 502.

[0104] The first portion 504a includes a second set of memory cells arranged in a plurality of rows and a plurality of columns. Each row of memory cells in the second set of memory cells includes a second set of memory words. To illustrate, a row 525 of memory cells is shown, but the teachings of the row 525 are applicable to each row of memory cells in the first portion 504a of the second memory array 504. The row 525 of memory cells in the second set of memory cells includes second set of memory words W[1]’, W[2]’, W[3]’, or W[4]’ (collectively, words “W’”). In some embodiments, each row of memory cells in the second set of memory cells has a corresponding row of memory cells in the first set of memory cells in the first memory array 502. A common number of words W’ in a row includes 8, 16, 32, or 64, etc. Different numbers of words W’ in a row of memory cells of the second set of memory cells are within the scope of various embodiments. Each word of the second set of memory words W’ includes a plurality of memory cells or a plurality of memory bits. The word W[3]’ includes a first set of bits 525a and a second set of bits 525b. For brevity, the memory bits in the words W[1]’, W[2]’, and W[4]’ are not shown. Each word in the second set of words W’ has a corresponding word in the first set of words W.

[0105] In some embodiments, each word in the second set of words W’ is configured with a second ECC 530 to provide error correction of at least a corresponding portion of the word in the second set of words W’. For brevity, the second ECC 530 in each W[1]’, W[2]’, and W[4]’ is not shown.

[0106] The first set of bits 525a includes bits F1,..., FX, where X is a positive integer corresponding to a number of data bits in the first set of bits 525a of the word W[3]’.

[0107] The second set of bits 525b includes bits G1,..., GZ, where Z is a positive integer corresponding to the number of bits in the second set of bits 525b. The second set of bits 525b is referred to as a second ECC 530 configured to provide N-bit error correction in the first set of bits 525a of the word W[3]’, where N is a positive integer. In some embodiments, the first memory array 502 is not configured with the first ECC 330 and the first portion 504a is not configured with the second ECC 530. In some embodiments, each word in the first set of words W does not include the second set of bits 525b and each word in the second set of words W’ does not include the second set of bits 525b.

[0108] In some embodiments, the second portion 504b is a copy of the first portion 504a. The second portion 504b includes a third set of memory cells arranged in a plurality of rows and a plurality of columns. Each row of memory cells in the third set of memory cells includes a third set of memory words. To illustrate, a row 535 of memory cells is shown, but the teachings of the row 535 are applicable to each row of memory cells in the second portion 504b of the second memory array 504. The row 535 of memory cells in the third set of memory cells includes a third set of memory words W[1]”, W[2]”, W[3]”, or W[4]” (collectively referred to as words “W”). In some embodiments, each row of memory cells in the third set of memory cells has a corresponding row of memory cells in the first set of memory cells of the first memory array 502 or in the second set of memory cells in the first portion 504a of the second memory array 504. A common number of words W” in a row includes 8, 16, 32, 64, etc. Different numbers of words W” in a row of memory cells of the third set of memory cells are within the scope of various embodiments. Each word of the third set of memory words W” includes a plurality of memory cells or a plurality of memory bits. The word W[3]” includes a first set of bits 535a and a second set of bits 535b. For simplicity, the memory bits in the words W[1]”, W[2]”, and W[4]” are not shown. Each word in the third set of words W” has a corresponding word in the first set of words W or the second set of words W’.

[0109] The first set of bits 535a includes bits F1’,..., FX’, where X’ is a positive integer corresponding to the number of data bits in the first set of bits 535a of the word W[3]”.

[0110] The second set of bits 535b includes bits G1’... GZ’, where Z’ is a positive integer corresponding to the number of bits in the second set of bits 535b. The second set of bits 535b is referred to as a third ECC 530 configured to provide N-bit error correction of the first set of bits 535a of the word W[3]”. N is a positive integer. In some embodiments, the first portion 504a and the second portion 504b are copies of the first memory array 502. In some embodiments, the first memory array 502 is not configured with the first ECC 330, at least the first portion 504b is not configured with the second ECC 530, or the second portion 504b is not configured with the third ECC 532. In some embodiments, each word in the first set of words W does not include a second set of bits 315b, at least each word in the second set of words W’ does not include a second set of bits 525b, or each word in the third set of words W” does not include a second set of bits 535b.

[0111] In some embodiments, the row 525 or 535 is a copy of the row 315. In some embodiments, the word W[3]’ or W[3]” is a copy of the word W[3]. In some embodiments, the first set of bits 525a or 535a is a copy of the first set of bits 315a. In some embodiments, the second set of bits 525b or 535b is a copy of the second set of bits 315b.

[0112] In some embodiments, at least one of the first ECC 330, the second ECC 530, or the third ECC 532 is the same type of ECC as another one of the first ECC 330, the second ECC 530, or the third ECC 532. In some embodiments, at least one of the first ECC 330, the second ECC 530, or the third ECC 532 is a different type of ECC than another one of the first ECC 330, the second ECC 530, or the third ECC 532. In some embodiments, the second ECC 530 or the third ECC 532 includes a Hamming ECC, a Reed-Solomon ECC, a BCH code, etc. Other ECCs are within the scope of various embodiments. In some embodiments, the size of the second memory array 504 is at least 66% larger than the size of the first memory array 502.

[0113] Figure 5B is a flowchart of a method 500’ of correcting errors in a memory array 500 according to some embodiments.

[0114] The method 500’ is an embodiment of the method 200 having similar elements. Figure 2 The method 500’ is applied to the memory array 500 in some embodiments. For brevity, the method 500’ is applied to the memory array 500 in some embodiments. Figure 5Aword W[3], word W[3]' and word W[3]". However, the method 500' can be applied to each row of memory cells in the first memory array 502 or the second memory array 504.

[0115] In operation 502' of the method 500', the memory array 500( Figure 5A ) is divided into a first memory array 502 and a second memory array 504. In some embodiments, the operation 502' includes dividing the second memory array 504 into an even number (e.g., even number K) of portions (e.g., in Figure 5A - Figure 5C the first portion 504a and the second portion 504b where K equals 2). In some embodiments, the size of the first memory array 502 is less than or equal to 1 / K of the size of the second memory array 504 th .

[0116] The method 500' continues with operation 504', where a set of data (e.g., the first set of bits 315a) is stored in the first memory array 502. In some embodiments, the set of data (e.g., the first set of bits 315a) stored in the first memory array 502 is a portion of the word W[3]. In some embodiments, the IC 102 is configured to store the set of data (e.g., the first set of bits 315a) in the first memory array 502. In some embodiments, the configuration system 104 is configured to store the set of data (e.g., the first set of bits 315a) in the first memory array 502.

[0117] In some embodiments, the set of data (e.g., the first set of bits 315a) includes an address of a memory cell in the first memory array 502.

[0118] The method 500' continues with operation 506', where the first memory array 502 is configured with a first ECC 330 to provide error correction for the set of data (e.g., the first set of bits 315a) stored in the first memory array 502, thereby generating a first set of data (e.g., the first set of bits 315a and the second set of bits 315b). In some embodiments, the configuration system 104 configures the first memory array 502 with the first ECC 330. The first ECC 330 is stored in the first memory array 502 as the second set of bits 315b. In some embodiments, the first set of data includes the first set of bits 315a and 315b. In some embodiments, the operation 506' is optional. For example, in some embodiments, the first memory array 502 is not configured with the first ECC 330, and thus, the first set of data of the method 500' corresponds to the set of data.

[0119] Method 500' continues with operation 508', in which a second set of data is stored in the second memory array 504. In some embodiments, the second set of data includes at least a copy of the first set of data (class, first set of bits 315a and second set of bits 315b).

[0120] In some embodiments, the second set of data includes at least the first set of bits 525a or the first set of bits 535a. In some embodiments, at least the first memory array 502 is configured with the first ECC 330, and the first portion 504a or the second portion 504b of the second memory array is configured with ECC protection (e.g., the second ECC 530 or the third ECC 532). In some embodiments, if the first portion 504a or the second portion 504b of the second memory array is configured with ECC protection, then the second set of data includes at least the first set of bits 525a, the first set of bits 535a, the second set of bits 525b, or the second set of bits 535b. In some embodiments, the first memory array 502 is not configured with the first ECC 330, and thus, in these embodiments, the second set of data of method 500' is not protected by ECC. In some embodiments, if the second set of data is not configured with ECC protection, then the second set of data does not include one or more of the second set of bits 525b or 535b.

[0121] In some embodiments, a relationship between the size S2 of the second memory array 504 and the size S1 of the first memory array 502 is represented by equation 2 or 3 below:

[0122] S2< 2 * S1 (2)

[0123] S2≥ K * S1 (3)

[0124] where k is an even number.

[0125] In some embodiments, if the size S2 of the second memory array 504 satisfies equation 2, then operation 508' includes storing a copy of the first set of data as the second set of data in the second memory array 504. In some embodiments, if the size S2 of the second memory array 504 satisfies equation 3, then operation 508' includes dividing the second memory array 504 into an even number (e.g., even number K) of portions (e.g., in the first portion 504a and the second portion 504b). Figure 5A to 5CIn the second memory array 504, an even number of parts 504a and 504b are stored in each corresponding part of the first set of data (e.g., the first part 504a and the second part 504b), where the even number K is equal to 3. In some embodiments, the second set of data includes an even number (e.g., an even number of K) copies of the first set of data (e.g., the first set of bits 315a). In some embodiments, the second set of data includes an even number (e.g., an even number of K) copies of data stored in at least word W[3].

[0126] Method 500' continues with operation 510', where (i) a reflow process is performed on the first memory array 502 and the second memory array 504. The reflow process of operation 510' is... Figure 2 Operation 204 Figure 3B Operation 310' or Figure 4C The reflow process of operation 416'. In some embodiments, the reflow process of operation 510' damages a portion of the data stored in the first memory array 502 or the second memory array 504. In some embodiments, the reflow process of operation 510' damages memory cells in the first memory array 502 or the second memory array 504 such that the damaged memory cells cannot properly store data.

[0127] Method 500' continues operation 512', wherein a portion of a first set of data (e.g., first set of bits 315a and second set of bits 315b) stored in the first memory array 502 is recovered. In some embodiments, the recovered first set of data is the output signal OUT_F ( Figure 5C In some embodiments, the recovered first set of data has a recovered ECC (if available). In some embodiments, the recovered first set of data for operation 512' is generated based on a majority voting circuit of the first set of data (e.g., first set of bits 315a and second set of bits 315b) and the second set of data (e.g., first set of bits 525a or 535a or second set of bits 525b or 535b). (e.g., output signal OUT_F) Figure 5C In the first embodiment, the recovered first set of data includes at least a portion of the first set of data. In some embodiments, the recovered first set of data includes at least a corrected version of the first set of bits 315a or a corrected version of the first ECC 330.

[0128] In some embodiments, the first array 502 and the second array 504 are configured in an L- module redundancy system implementing the multi-bit voting of operation 512’, where L is a positive integer corresponding to a number of redundant elements in the L-module redundancy system. For example, in some embodiments, if the integer L is equal to 3, the first array 502 and the second array 504 are configured in a three-module redundancy system 550 (shown) implementing the multi-bit voting of operation 512’. Figure 5C In some embodiments, the integer L is equal to the integer K+1 of operation 502’ or 508’. In some embodiments, in the L-module redundancy system, for each bit of data, if the data from one of the L systems (e.g., the first memory array 502 and the second memory array 504) is incorrect, the data from the remaining L-1 systems (e.g., the first memory array 502 and the second memory array 504) is used to correct the incorrect data. In some embodiments, the multi-bit voting of operation 512’ is implemented bit-wise for the first set of data and the second set of data.

[0129] In some embodiments, operation 512’ includes generating a first set of output signals by implementing at least one AND operation between the first set of data and the second set of data for each bit of data, and implementing an OR operation on the first set of output signals.

[0130] In some embodiments, the first ECC 330 of the first set of data or the second ECC 530 of the second set of data does not contain any errors and is not recovered or corrected. In some embodiments, the first ECC 330 of the first set of data or the second ECC 530 of the second set of data contains errors and is recovered or corrected by an ECC engine (not shown) in the IC 102. In some embodiments, if the size S2 of the second memory array 504 satisfies equation 2, the first set of data and the second set of data contain one or more errors (if they contain different data). In these embodiments, if the number of errors in the second set of data is less than the number of errors in the first set of data, the second set of data (e.g., the first set of bits 525a and the recovered ECC 530) is copied into the first memory cell array 502 as the recovered first set of data. In these embodiments, if the number of errors of the first set of data is less than the number of errors of the second set of data, the first set of data (e.g., the first set of bits 325a and the recovered first ECC 530) corresponds to the recovered first set of data. In these embodiments, if no ECC is recovered, the first ECC 330 or the second ECC 530 replaces the recovered ECC.

[0131] Method 500 continues operation 514, wherein the recovered first set of data stored in the first memory array 502 is corrected based on ECC (e.g., first ECC 330, second ECC 530, or third ECC 532) (e.g., output signal OUT_F). Figure 5C In some embodiments, the ECC of operation 514' is a recovered ECC. In some embodiments, if the first ECC 330 is not corrected in operation 512', the first set of data (e.g., the output signal OUT_F) is recovered or corrected based on the first ECC 330. Figure 5C )) part.

[0132] In some embodiments, the first set of data recovered in operation 514' includes at least a portion of the first set of bits 315a and a portion of the second set of bits 315b. In some embodiments, the recovered first set of data includes words in the first set of words W in the first memory array 502. In some embodiments, if the number of errors in at least a portion of the words in the first set of words W of the first memory array 502 is less than or equal to N bits, the data at the words in the first set of words W of the first memory array 502 (e.g., the first set of bits 315a) is corrected based on the recovered first ECC 330. In some embodiments, if the number of errors in at least a portion of the words in the first set of words W of the first memory array 502 is greater than N bits, the data at the words in the first set of words W of the first memory array 502 (e.g., the first set of bits 315a or the second set of bits 315b) is not corrected based on the recovered first ECC 330.

[0133] Method 500' continues operation 524', wherein at least a portion of the second memory array 504 is released. In some embodiments, operation 524' includes designating at least a portion of the second memory array 504 as memory cells writable by IC 102 or other circuitry.

[0134] In some embodiments, one or more of operations 502', 506'-514' or 516' are optional.

[0135] It should be understood that it is possible Figure 3B The method shown is 300'. Figure 4C Method 400' shown Figure 5B The method shown is 500' or Figure 6 Additional operations are performed before, during, and / or after Method 600, and therefore this document only briefly describes some of these other operations.

[0136] Figure 5C This is a block diagram of system 550 according to some embodiments.

[0137] System 550 includes a majority voting circuit 560 electrically connected to each of the first memory array 502, the first portion 504a of the second memory array 504, and the second portion 504b of the second memory array 504. In some embodiments, system 550 includes other circuitry or is configured to store or execute software, which is not shown for simplicity. System 550 is part of IC 102 of Figure 1 In some embodiments, system 550 is part of configuration system 104. Figure 1

[0138] When the integers K and L are equal to 3, system 550 is a three-mode redundant system configured to implement the multi-bit voting of operation 520’. Figure 5B In some embodiments, system 550 is configured to repair or detect errors in data stored in the first memory array 502.

[0139] The first memory array 502 is configured to store input data IN1. In some embodiments, input data IN1 is the first set of data of operation 504’.

[0140] The first portion 504a of the second memory array 504 is configured to store a first copy IN2 of input data IN1. The second portion 504b of the second memory array 504 is configured to store a second copy IN3 of input data IN1. In some embodiments, the first copy IN2 and the second copy IN3 are the second set of data of operation 508’.

[0141] A read operation is performed by system 550 on data stored in the first memory array 502 and the first portion 504a and the second portion 504b. In some embodiments, the majority voting circuit 560 is configured to perform the read operation on the first memory array 502, the first portion 504a, and the second portion 504b.

[0142] The majority voting circuit 560 is configured to receive signals OUT1, OUT2, and OUT3. Signals OUT1, OUT2, and OUT3 are data read from the corresponding first memory array 502, first portion 504a, and second portion 504b. The majority voting circuit 560 is configured to generate an output signal OUT F based on the input signals OUT1, OUT2, and OUT3. The majority voting circuit 560 is a logic circuit that is configured to determine (or correct) bit-by-bit if there is an error in the data stored in the first memory array 502, the first portion 504a, and the second portion 504b. The output signal OUT F is a low logic value represented by “0” or a high logic value represented by “1”.

[0143] ​In some embodiments, the majority voting circuit 560 is configured to compare each bit of data in the first memory array 502 and the second memory array 504 to determine if there is an error in the data stored in the first memory array 502, the first portion 504a, and the second portion 504b. In some embodiments, for each bit of data, if the bit of data stored in the first memory array 502 and the second memory array 504 is corrupted or inconsistent with each other, the inconsistency or error is corrected with the correct data in the other two memory arrays.

[0144] In some embodiments, the majority voting circuit 560 is an AND-OR logic circuit configured to generate an output signal OUT F. In these embodiments, the output signal OUT F is equal to the expression of Equation 4:

[0145] OUT F = (OUT1 and OUT2) OR (OUT2 and OUT3) OR (OUT1 and OUT3) (4)

[0146] In these embodiments, for each bit of input data IN1 stored in the first memory array 502, the majority voting circuit 560 detects and corrects single-bit errors in the input data IN1, the first copy IN2, or the second copy IN3. In some embodiments, for a bit of data stored in the first memory array 502, the output signal OUT F of the majority voting circuit 560 is a logic “1” if two or more of the signals OUT1, OUT2, or OUT3 are a logic “1”. In some embodiments, for a bit of data stored in the first memory array 502, the output signal OUT F of the majority voting circuit 560 is a logic “0” if two or more of the signals OUT1, OUT2, or OUT3 are a logic “0”. For example, in these embodiments, if the input data IN1, the first copy IN2, the second copy IN2, OUT1, OUT2, and OUT3 are equal to each other, the output signal OUT F is equal to the signal OUT1, OUT2, or OUT3, and there is no error in the signals OUT1, OUT2, or OUT3. In these embodiments, if there is a single-bit error in the input data IN1, the first copy IN2, the second copy IN2, OUT1, OUT2, or OUT3, one of the signals OUT1, OUT2, or OUT3 will have a different value than the other one of the signals OUT1, OUT2, or OUT3, but the majority voting circuit 560 will correct the single error based on the AND-OR logic operation represented by Equation 4.

[0147] Figure 6 is a flowchart of a method 600 of correcting errors in a memory array 500 according to some embodiments.

[0148] Operation 600 is an embodiment of method 200 with similar elements Figure 2 of method 500’. For brevity, method 600 applies to word W[3], word W[3]’, and word W[3]” in Figure 5A some embodiments, method 600 can apply to each row of memory cells in first memory array 502 or second memory array 504. Method 600 is a variation of method 500’. Figure 5B

[0149] In operation 602 of method 600, a set of data (e.g., first set of bits 315a) is stored in first memory array 502 of memory array 500. In some embodiments, the set of data (e.g., first set of bits 315a) stored in first memory array 502 is part of word W[3]. In some embodiments, IC 102 is configured to store a set of data (e.g., first set of bits 315a) in first memory array 502. In some embodiments, configuration system 104 is configured to store a set of data (e.g., first set of bits 315a) in first memory array 502. In some embodiments, the set of data (e.g., first set of bits 315a) stored in first memory array 502 is a first data type. In some embodiments, the first data type is a set of high logic values or “1”. In some embodiments, the first data type is a set of low logic values or “0”.

[0150] Method 600 continues with operation 604, in which (i) a bake process is performed on memory array 500, or (ii) a magnetic field is applied to memory array 500.

[0151] In some embodiments, the bake process includes placing memory array 500 into an oven, and heating the oven at temperature T2 for duration D2. In some embodiments, heating the oven at temperature T2 for duration D2 includes heating memory array 500 at temperature T2. In some embodiments, temperature T2 of the bake process of operation 606 is greater than or equal to temperature T1 of the reflow process of operation 510’ of method 500’. In some embodiments, duration D2 of the bake process of operation 606 is greater than or equal to duration D1 of the reflow process of operation 510’ of method 500’.

[0152] In some embodiments, the magnetic field applied to memory array 500 has a strength in a range from about 500 Oersteds (Oe) to about 2000 Oe. In some embodiments, the duration D2 of the magnetic field applied to memory array 500 is in a range from about 1 second to about 10 seconds.

[0153] ​Method 600 continues with operation 606, in which it is determined whether at least a portion of the set of data (e.g., first set of bits 315a) was changed by the baking process or the applied magnetic field of operation 604. If at least a portion of the set of data (e.g., first set of bits 315a) is determined to have been changed by the baking process or the applied magnetic field, method 600 proceeds to operation 608. If it is determined that the set of data (e.g., first set of bits 315a) was not changed by the baking process or the applied magnetic field, method 600 proceeds to operation 612. In some embodiments, the one or more memory cells that include the changed data are referred to as a first set of memory cells of first memory array 502.

[0154] In some embodiments, the changed set of data includes a set of bits having opposite logic values from the logic values of the bits in the set of data. For example, in some embodiments, if the set of data corresponds to a set of high logic values, the changed set of data includes a set of bits having low logic values. Similarly, in some embodiments, if the set of data corresponds to a set of low logic values, the changed set of data includes a set of bits having high logic values.

[0155] Method 600 continues with operation 608, in which the addresses of the memory cells in the first set of memory cells storing the changed data are tracked. In some embodiments, the addresses of the tracked memory cells are recorded in a database (e.g., memory 704 of system 700 Figure 7 ) in some embodiments, the memory cells that include the changed data are referred to as “weak bits.”

[0156] Method 600 continues with operation 610, in which the memory cells in the first set of memory cells storing the changed data are replaced with corresponding memory cells in a second memory array, or the memory cells in the first set of memory cells storing the changed data are discarded. In some embodiments, the discarded memory cells are memory cells that are not used in first memory array 502. In some embodiments, the discarded memory cells are memory cells that are removed from IC 102. In some embodiments, operations 606, 608, and 610 are repeated for each memory cell in the first set of memory cells storing the changed data.

[0157] In some embodiments, operations 602-610 are used to screen out memory cells in the first memory array 502 that are described as "weak bits." In some embodiments, operations 602-610 are repeated. For example, in some embodiments, operations 602-610 are applied to the memory array 500 when the set of data corresponds to a set of high logic values to screen out memory cells in the first memory array 502 that are susceptible to transitioning from a high logic value to a low logic value by the bake process or the magnetic field of operation 604. In these embodiments, operations 602-610 are again applied to the memory array 500, but the set of data corresponds to a set of low logic values to screen out memory cells that are susceptible to transitioning from a low logic value to a high logic value by the bake process or the magnetic field of operation 604. Other configurations of the set of data are within the scope of the present disclosure.

[0158] In some embodiments, when operations 602-610 are repeated, the bake process of the first repetition is the same as the bake process of the second repetition. In some embodiments, when operations 602-610 are repeated, the bake process of the first repetition is different than the bake process of the second repetition. In some embodiments, when operations 602-610 are repeated, the magnetic field applied of the first repetition is the same as the magnetic field applied of the second repetition. In some embodiments, when operations 602-610 are repeated, the magnetic field applied of the first repetition is different than the magnetic field applied of the second repetition. Other configurations of the bake process or the applied magnetic field are within the scope of the present disclosure.

[0159] Method 600 continues with operation 612. In some embodiments, operation 612 of method 600 corresponds to Figure 5B Method 500' of correcting errors in the memory array 500.

[0160] Method 600 can identify and screen out weak bits in the memory array 500 that result in the memory array 500 having a lower BER and a lower field failure rate than other methods.

[0161] The order of the operations of methods 200, 300', 400C, 500', or 600 is for illustration only; the operations of 200, 300', 400C, 500', or 600 can be performed in an order different than the order shown in corresponding Figure 2 , Figure 3B , Figure 4C , Figure 5B or Figure 6 In some embodiments, operations prior to, during, and / or after the operations shown in Figure 2 , Figure 3B , Figure 4C , Figure 5B or Figure 6 may be implemented in addition to Figure 2 , Figure 3B , Figure 4C, Figure 5B or Figure 6 operations other than those shown.

[0162] Figure 7 is a block diagram of a system 700 for configuring a memory array 102a according to some embodiments. The system 700 includes a hardware processor 702 and a non-transitory computer-readable storage medium 704 encoded with (i.e., storing) computer program code 706 (i.e., a set of executable instructions). The computer program code 706 is configured to interface with the integrated circuit 102 for configuring the memory array 102a with various ECC configurations. The processor 702 is electrically connected to the computer-readable storage medium 704 through a bus 708. The processor 702 is also electrically connected to an I / O interface 710 through the bus 708. A network interface 712 is also electrically connected to the processor 702 through the bus 708. The network interface 612 is connected to a network 714, thereby enabling the processor 702 and the computer-readable storage medium 704 to connect to external elements through the network 714. The processor 702 is configured to execute the computer program code 706 encoded in the computer-readable storage medium 704, such that the system 700 is operable to implement some or all of the operations described in the methods 200, 300', 400C, 500' or 600. In some embodiments, the system 700 is a system 550. Figure 5C

[0163] In some embodiments, the processor 702 is a central processing unit (CPU), a multi-processor, a distributed processing system, an application specific integrated circuit (ASIC), and / or a suitable processing unit.

[0164] In some embodiments, the computer-readable storage medium 704 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or apparatus or device). For example, the computer-readable storage medium 704 includes semiconductor or solid-state memory, magnetic tape, a removable computer diskette, a random access memory (RAM), a read-only memory (ROM), a rigid magnetic disc, and / or an optical disc. In some embodiments using optical discs, the computer-readable storage medium 704 includes a compact disc - read only memory (CD-ROM), a compact disc - read / write (CD-R / W) and / or a digital video disc (DVD).

[0165] ​In some embodiments, the storage medium 704 stores computer program code 706 configured to cause the system 700 to implement the method 200, 300', 400C, 500' or 600. In some embodiments, the storage medium 604 also stores information required for implementing the method 200, 300', 400C, 500' or 600 and information generated during the implementation of the method 200, 300', 400C, 500' or 600, such as the first ECC 716, the second ECC 718, the third ECC 720, the first parity 722, the second parity 724 and the configuration 726 and / or information of a set of executable instructions for implementing the operations of the method 200, 300', 400C, 500' or 600.

[0166] In some embodiments, the storage medium 704 stores computer program code 706 for connecting memory devices. The computer program code 706 enables the processor 702 to generate instructions readable by the integrated circuit 102 to effectively implement the method 200, 300', 400C, 500' or 600 during a memory configuration process.

[0167] The system 700 includes an I / O interface 710. The I / O interface 710 is connected to external circuits. In some embodiments, the I / O interface 710 includes a keyboard, a keypad, a mouse, a trackball, a touchpad and / or cursor direction keys for transmitting information and commands to the processor 702.

[0168] The system 700 also includes a network interface 712 connected to the processor 702. The network interface 712 allows the system 700 to communicate with a network 714 to which one or more other computer systems are connected. The network interface 712 includes a wireless network interface such as Bluetooth, WIFI, WIMAX, GPRS or WCDMA; or a wired network interface such as ETHERNET, USB or IEEE- 1394. In some embodiments, the method 200, 300', 400C, 500' or 600 is implemented in two or more systems 700, and information such as the first ECC, the second ECC, the third ECC, the first parity, the second parity and the configuration is exchanged between the different systems 700 through the network 714.

[0169] The system 700 is configured to receive information related to a first ECC through the I / O interface 710 or the network interface 712. The information is communicated through the bus 708 to the processor 702 to determine the first ECC for configuring the integrated circuit 102. The first ECC is then stored in the computer readable medium 704 as the first ECC 716. The system 700 is configured to receive information related to a second ECC through the I / O interface 710 or the network interface 712. The information is stored in the computer readable medium 704 as the second ECC 718. The system 700 is configured to receive information related to a third ECC through the I / O interface 710 or the network interface 712. The information is stored in the computer readable medium 704 as the third ECC 720. The system 700 is configured to receive information related to a first parity through the I / O interface 710 or the network interface 712. The information is stored in the computer readable medium 704 as the first parity 722. The system 700 is configured to receive information related to a second parity through the I / O interface 710 or the network interface 712. The information is stored in the computer medium 704 as the second parity 724. The system 700 is configured to receive information related to a memory configuration through the I / O interface 710 or the network interface 712. The information is stored in the computer readable medium 704 as the configuration 726.

[0170] One aspect of the present disclosure relates to a method of correcting errors in a memory array. The method includes configuring a first memory array with a first ECC to provide error correction for data stored in the first memory array, configuring a second memory array with a second ECC to provide error correction for data stored in the first memory array, subjecting the first memory array and the second memory array to a reflow process, and correcting data stored in the first memory array based on at least the first ECC or the second ECC. The first memory array includes a first set of memory cells arranged in a plurality of rows and a plurality of columns. A row of memory cells in the first set of memory cells includes a first set of memory words. Each word in the first set of memory words includes a first set of bits. The second memory array includes a second set of memory cells arranged in a plurality of rows and a plurality of columns. A row of memory cells in the second set of memory cells includes a second set of memory words. Each word in the second set of memory words includes a second set of bits.

[0171] In an embodiment, the first memory cells are a first portion of the memory array; and the second memory cells are a second portion of the memory array.

[0172] In an embodiment, the first ECC is an N-bit ECC, where N is a positive integer corresponding to a number of bits of error protection provided by the first ECC in at least one word of the first set of memory words.

[0173] In an embodiment, the second ECC is an Ml-bit ECC, where Ml is a positive integer corresponding to a number of bits of error protection provided by the second ECC in at least one word of the first set of memory words in the first memory array, and Ml is greater than N.

[0174] In an embodiment, correcting data stored in the first memory array based on at least the first ECC or the second ECC includes correcting data stored in the first memory array based on the first ECC if a number of errors in at least one word of the first set of words in the first memory array is less than or equal to N bits.

[0175] In an embodiment, correcting data stored in the first memory array based on at least the first ECC or the second ECC includes correcting data stored in the first memory array based on the second ECC if a number of errors in at least one word of the first set of words in the first memory array is greater than N bits and less than or equal to Ml bits.

[0176] In an embodiment, the first ECC or the second ECC is a Hamming ECC, a Reed-Solomon ECC, or a BCH ECC.

[0177] In an embodiment, the method of correcting errors in a memory array further includes storing the data in the first memory array; and

[0178] dividing the memory array into the first memory array and the second memory array.

[0179] In an embodiment, the first memory array is a portion of the memory array and the second memory array is a portion of another memory array, where the other memory array is different from the memory array.

[0180] In an embodiment, the method of correcting errors in a memory array further includes releasing the second memory array after correcting errors in the first memory array.

[0181] Another aspect of the present disclosure relates to a method of correcting errors in a memory array. The method includes configuring a first memory array having a first ECC to provide error correction for data stored in the first memory array, configuring a first portion of a second memory array having a first parity configured to provide error detection for data stored in a row of the first memory array, configuring a second portion of the second memory array having a second parity configured to provide error detection for data stored in a column of the first memory array, configuring the second portion of the second memory array having a second ECC to provide error correction for a second set of data stored in the second portion of the second memory array, subjecting the first memory array and the second memory array to a reflow process, correcting at least a portion of the data stored in the first memory array based on at least (1) the first ECC or (2) the first parity and the second parity, and correcting the second set of data stored in the second portion of the second memory array based on the second ECC. The first memory array includes a first set of memory cells arranged in a plurality of rows and a plurality of columns. A row of the first set of memory cells includes a first set of memory words. Each word of the first set of memory words includes a first set of bits. The first portion of the second memory array includes a second set of memory cells storing a first set of data. The second portion of the second memory array includes a third set of memory cells storing a second set of data.

[0182] In an embodiment, the method of correcting errors in a memory array further includes configuring the first portion of the second memory array having a third ECC to provide error correction for the first set of data stored in the first portion of the second memory array, the first set of data having a first set of parity bits.

[0183] In an embodiment, the method of correcting errors in a memory array further includes correcting the first set of data stored in the first portion of the second memory array based on the third ECC.

[0184] In an embodiment, the first ECC is an N-bit ECC, where N is a positive integer corresponding to a number of bits of error protection provided by the first ECC in at least one word of the first set of memory words; and the second ECC is an Nl-bit ECC, where Nl is a positive integer corresponding to a number of bits of error protection provided by the second ECC in the second set of data, the second set of data having a second set of parity bits.

[0185] In an embodiment, the third ECC is an N2-bit ECC, where N2 is a positive integer corresponding to a number of bits of error protection provided by the third ECC in the first set of data.

[0186] In an embodiment, correcting data stored in the first memory array based on (1) the first ECC or (2) the first parity and the second parity includes correcting N-bit errors in a word of the first set of words based on the first ECC and correcting single-bit errors in a word of the first set of words based on a combination of the first parity and the second parity.

[0187] Yet another aspect of the present disclosure relates to a method of correcting errors in a memory array. The method includes configuring a first memory array having a first error-correcting code (ECC) to provide error correction for a first set of data stored in the first memory array, storing a second set of data in a second memory array, subjecting the first memory array and the second memory array to a reflow process, correcting the first set of data to generate a third set of data based on a majority vote of the first set of data and the second set of data, and correcting errors in the third set of data based on the first ECC. The first memory array includes a first set of memory cells arranged in a plurality of rows and a plurality of columns. A row of memory cells of the first set of memory cells includes a first set of memory words. Each word of the first set of memory words includes a first set of bits. The second set of data includes an even number of copies of the first set of data. The second memory array includes a second set of memory cells arranged in a plurality of rows and a plurality of columns.

[0188] In an embodiment, recovering at least a portion of the first set of data based on the first set of data and the second set of data includes recovering the first set of data based on a majority vote of the first set of data and the second set of data includes generating a first set of output signals by performing at least one AND operation between the first set of data and the second set of data for each bit of data and performing an OR operation on the first set of output signals.

[0189] In an embodiment, the second set of data further includes an even number of copies of the first set of data.

[0190] In an embodiment, the second set of data further includes a single copy of the first set of data.

[0191] In an embodiment, the method of screening for weak bits in a memory array further comprises: storing a second set of data in the first memory array; performing at least a second bake process on the first memory array or applying a second magnetic field to the first memory array; determining whether a portion of the second set of data stored in the second memory array is changed by the second bake process or the second magnetic field; and if a second memory cell of the first set of memory cells stores changed data, tracking an address of at least the second memory cell of the first set of memory cells and performing at least one of: (1) replacing the second memory cell of the first set of memory cells storing the changed data with a corresponding memory cell in the second memory array of the memory array, or (2) discarding the second memory cell of the first set of memory cells storing the changed data.

[0192] In an embodiment, the first set of data is logically opposite the second set of data.

[0193] In an embodiment, each member of the first set of data is a low logic value or a high logic value.

[0194] In an embodiment, performing the first bake process comprises placing the memory array into an oven and heating the oven at a first temperature for a first duration of time; performing the second bake process comprises placing the memory array into the oven and heating the oven at a second temperature for a second duration of time, and at least one of: (1) the first temperature is equal to the second temperature; or (2) the first duration of time is equal to the second duration of time.

[0195] In an embodiment, applying the first magnetic field comprises applying the first magnetic field having a first strength for a first duration of time, and applying the second magnetic field comprises applying the second magnetic field having a second strength for a second duration of time, and at least one of: (1) the first strength is equal to the second strength; or (2) the first duration of time is equal to the second duration of time.

[0196] In an embodiment, recovering at least the portion of the first set of data based on the first set of data and the second set of data comprises: recovering the first set of data based on a majority vote of bits of the first set of data and the second set of data.

[0197] In an embodiment, recovering the first set of data based on the majority voting of the first set of data and the second set of data includes, for each bit of data, generating a first set of output signals by performing at least one AND operation between the first set of data and the second set of data, and performing an OR operation on the first set of output signals.

[0198] The foregoing summary of a few embodiments will so fully disclose the general nature of the invention that others can better understand how to make and use the invention. Those skilled in the art will appreciate that they can readily apply the conception of the invention as further set forth in the disclosure that follows to the full extent required by the prior art to which this invention is relevant by way of many different embodiments. It is therefore contemplated that the following disclosure and examples be considered in a descriptive sense only and not for purposes of limiting the true scope of such improvements, as they can be applied in a multitude of ways beyond those explicitly described.

Claims

1. A method for filtering weak bits in a memory array, the method comprising: The memory array is divided into a first memory array and a second memory array; The first set of data is stored in the first memory array of the memory array, the first memory array having a first set of memory cells; At least a first baking process is performed on the first memory array, or at least a first magnetic field is applied to the first memory array; Determine whether a portion of the first set of data stored in the first memory array is altered by the first baking process or the first magnetic field; as well as If the first memory cell of the first group of memory cells stores changed data, then the address of at least the first memory cell of the first group of memory cells is tracked, and at least one of the following operations is performed: (1) Replace the first memory cell in the first group of memory cells storing the changed data with the corresponding memory cell in the second memory array of the memory array, and (2) Discard the first memory cell in the first group of memory cells that stores the changed data.

2. The method for filtering weak bits in a memory array according to claim 1, further comprising: The second set of data is stored in the first memory array; At least a second baking process is performed on the first memory array, or at least a second magnetic field is applied to the first memory array; Determine whether a portion of the second set of data stored in the first memory array is altered by the second baking process or the second magnetic field; as well as If the second memory cell in the first group of memory cells stores changed data, then the address of at least the second memory cell in the first group of memory cells is tracked, and at least one of the following operations is performed: (1) Replace the second memory cell in the first group of memory cells storing the changed data with the corresponding memory cell in the second memory array of the memory array, and (2) Discard the second memory cell in the first set of memory cells that stores the changed data.

3. The method for filtering weak bits in a memory array according to claim 2, wherein, The first set of data is logically the opposite of the second set of data.

4. The method for filtering weak bits in a memory array according to claim 2, wherein, Implementing the first baking process includes: The memory array is placed in an oven, and the oven is heated at a first temperature for a first duration.

5. The method for filtering weak bits in a memory array according to claim 4, wherein, Performing the second baking process includes placing the memory array into the oven and heating the oven at a second temperature for a second duration, and meeting at least one of the following conditions: (1) The first temperature is equal to the second temperature; and (2) The first duration is equal to the second duration.

6. The method for filtering weak bits in a memory array according to claim 2, wherein, Applying the first magnetic field includes applying the first magnetic field having a first strength for a first duration.

7. The method for filtering weak bits in a memory array according to claim 6, wherein, Applying the second magnetic field includes applying the second magnetic field with a second strength for a second duration, and meeting at least one of the following conditions: (1) The first strength is equal to the second strength; and (2) The first duration is equal to the second duration.

8. The method for filtering weak bits in a memory array according to claim 6, wherein, The first strength is in the range of 500 to 2000 Oersted.

9. The method for filtering weak bits in a memory array according to claim 8, wherein, The first duration is from 1 second to 10 seconds.

10. The method for filtering weak bits in a memory array according to claim 1, wherein, Each member of the first group of data is either a low logic value or a high logic value.

11. The method for filtering weak bits in a memory array according to claim 1, wherein, The system is configured to store the first set of data in the first memory array.

12. The method for filtering weak bits in a memory array according to claim 1, wherein, The first set of data is stored in the first memory array via an integrated circuit.

13. The method for filtering weak bits in a memory array according to claim 1, further comprising: The addresses of at least the first memory cell that are tracked are recorded in the database.

14. The method for filtering weak bits in a memory array according to claim 1, wherein, In the case of discarding the first memory cell in the first group of memory cells that stores the changed data, the first memory cell is an unused memory cell in the first memory array.

15. The method for filtering weak bits in a memory array according to claim 1, wherein, In the case of discarding the first memory cell in the first group of memory cells storing the changed data, the first memory cell is a memory cell removed from the integrated circuit.

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