A plastic packaging structure and processing method thereof

Abstract

The present invention relates to the field of semiconductor plastic encapsulation technology, and specifically discloses a plastic encapsulation structure comprising: a substrate and a silicon chip disposed on the substrate; a drainage groove is provided on the surface of the silicon chip facing away from the substrate; the silicon chip is bonded to the substrate via a bonding wire, one end of the bonding wire being located within the drainage groove and the other end being located on the substrate; the drainage groove is capable of draining plastic encapsulation material to the periphery of the silicon chip to form a plastic encapsulation material layer disposed around the silicon chip. The present invention also discloses a method for processing the plastic encapsulation structure. The plastic encapsulation structure provided by the present invention can effectively prevent displacement of the silicon chip due to the impact of the plastic encapsulation material.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor plastic packaging technology, and in particular to a plastic packaging structure and a processing method of the plastic packaging structure. Background Art

[0002] Plastic-encapsulated devices offer advantages such as low cost, small size, light weight, and mass production. However, during the encapsulation process, the encapsulation compound can impact and squeeze the chip and the bonding wires at the edge of the substrate, causing a certain degree of displacement between the positioning chip and the bonding wires, leading to bond wire breakage. Summary of the Invention

[0003] The present invention provides a plastic packaging structure and a processing method of the plastic packaging structure, which solves the problem of welding wire being broken in the related art.

[0004] As a first aspect of the present invention, a plastic encapsulation structure is provided, which includes: a substrate and a silicon chip arranged on the substrate, a drainage groove is provided on the surface of the silicon chip facing away from the substrate, the silicon chip is bonded to the substrate through a bonding wire, one end of the bonding wire is located in the drainage groove, and the other end is located on the substrate, the drainage groove can drain the plastic encapsulation material to the four sides of the silicon chip to form a plastic encapsulation material layer arranged around the silicon chip.

[0005] Furthermore, the drainage groove includes a cross-shaped slot structure.

[0006] Furthermore, the drainage groove includes a groove structure arranged along the diagonal line of the silicon chip and in a cross shape.

[0007] Furthermore, the bonding wire includes lead segments arranged at each diagonal position of the silicon chip, one end of each lead segment is located in the drainage groove, and the other end is connected to the substrate.

[0008] Furthermore, the diameter of each lead segment is between 5 μm and 50 μm, and the length of each lead segment is between 1 mm and 10 mm.

[0009] Furthermore, the bonding wire includes any one of a gold wire, a copper wire, an alloy wire and a polymer conductive wire.

[0010] Furthermore, the substrate includes any one of a multi-layer substrate, an embedded substrate and a flexible substrate.

[0011] As another aspect of the present invention, a method for processing a plastic package structure is provided, for processing the plastic package structure described above, wherein the processing method comprises:

[0012] Providing a substrate and a silicon chip, wherein the substrate includes multiple pins, the top solder resist layer of the substrate is a chip bonding area, and the bottom solder resist layer of the substrate is a BGA pad area;

[0013] Processing the upper surface of the silicon chip to form a drainage groove;

[0014] Thinning the lower surface of the silicon chip to reach a preset thickness;

[0015] Performing metal plating on the lower surface of the silicon chip to form a back gold;

[0016] Soldering the back gold of the silicon chip to the surface of the substrate;

[0017] Slicing the silicon chip to obtain separate packaging structures with independent electrical performance;

[0018] Bonding the silicon chip on the separate package structure to the substrate;

[0019] The bonded individual packaging structures are plastic-encapsulated, and the plastic encapsulation material is drained to the periphery of the silicon chip through the drainage groove to form a plastic encapsulation material layer arranged around the silicon chip.

[0020] As another aspect of the present invention, a method for processing a plastic package structure is provided, for processing the plastic package structure described above, wherein the processing method comprises:

[0021] Providing a substrate and a silicon chip, wherein the substrate includes multiple pins, the top solder resist layer of the substrate is a chip bonding area, and the bottom solder resist layer of the substrate is a BGA pad area;

[0022] Thinning the lower surface of the silicon chip to reach a preset thickness, and metal-plating the lower surface of the silicon chip to form a back-gold coating;

[0023] Soldering the back gold of the silicon chip to the surface of the substrate;

[0024] Slicing the silicon chip to obtain separate packaging structures with independent electrical performance;

[0025] Processing the upper surface of the silicon chip on the individual packaging structure to form a drainage groove;

[0026] Bonding the silicon chip on the separate package structure to the substrate;

[0027] The bonded individual packaging structures are plastic-encapsulated, and the plastic encapsulation material is drained to the periphery of the silicon chip through the drainage groove to form a plastic encapsulation material layer arranged around the silicon chip.

[0028] The packaging structure provided by the present invention, by providing drainage grooves, can guide the encapsulating material around the silicon chip during the encapsulation process, effectively preventing the silicon chip from being displaced by the impact of the encapsulating material. Furthermore, based on factors such as the viscosity variation of the encapsulating material and the time the silicon chip is packaged, the bonding wires of the chip are subjected to minimal force when the encapsulating material is diverted, effectively preventing the bonding wires from being broken by the encapsulating material and improving the reliability of the encapsulated product. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The accompanying drawings are used to provide a further understanding of the present invention and constitute a part of the specification. Together with the following detailed description, they are used to explain the present invention but do not constitute a limitation of the present invention. In the accompanying drawings:

[0030] Figure 1A A top view of a plastic package structure according to an embodiment of the present invention.

[0031] Figure 1B This is a structural cross-sectional view of the plastic packaging structure provided by the present invention.

[0032] Figure 1C A top view of the plastic package structure according to another embodiment of the present invention.

[0033] Figure 2A for Figure 1A A top view of a substrate according to an embodiment of the present invention.

[0034] Figure 2B for Figure 1A A top view of a silicon chip forming a drainage groove according to an embodiment of the present invention.

[0035] Figure 2C for Figure 1A A top view of a silicon chip and a substrate after being welded in accordance with an embodiment of the present invention.

[0036] Figure 2D for Figure 1A A top view of a silicon chip bonded to a substrate according to an embodiment of the present invention.

[0037] Figure 2E for Figure 1A A top view of forming a molding compound layer according to an embodiment of the present invention.

[0038] Figure 3A for Figure 1A A top view of a substrate according to another embodiment of the present invention.

[0039] Figure 3B for Figure 1A A top view of a silicon chip formed on a substrate according to another embodiment.

[0040] Figure 3C for Figure 1AA top view of a drain groove formed on a silicon chip according to another embodiment of the present invention.

[0041] Figure 3D for Figure 1A A top view of a silicon chip bonded to a substrate according to another embodiment of the present invention.

[0042] Figure 3E for Figure 1A A top view of forming a molding compound layer according to another embodiment of the present invention. DETAILED DESCRIPTION

[0043] It should be noted that, in the absence of conflict, the embodiments and features of the embodiments of the present invention may be combined with each other. The present invention will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0044] In order to enable those skilled in the art to better understand the solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present invention.

[0045] It should be noted that the terms "first," "second," and the like in the specification and claims of the present invention and the accompanying drawings are used to distinguish similar objects and are not necessarily used to describe a particular order or precedence. It should be understood that the terms used in this manner are interchangeable where appropriate for the embodiments of the present invention described herein. In addition, the terms "including," "having," and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or apparatus comprising a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units that are not explicitly listed or that are inherent to these processes, methods, products, or apparatuses.

[0046] In this embodiment, a plastic packaging structure is provided. Figure 1A is a top view of a plastic package structure provided according to an embodiment of the present invention, Figure 1B is a cross-sectional view of a plastic package structure provided according to an embodiment of the present invention. Figure 1A and Figure 1B Shown, including:

[0047] A substrate 103 and a silicon chip 101 arranged on the substrate 103, a drainage groove 102 is set on the surface of the silicon chip 101 facing away from the substrate 103, and the silicon chip 101 is bonded to the substrate 103 through a bonding wire 104, one end of the bonding wire 104 is located in the drainage groove 102, and the other end is located on the substrate 103, and the drainage groove 102 can drain the molding compound to the four sides of the silicon chip 101 to form a molding compound layer 105 arranged around the silicon chip 101.

[0048] Specifically, in order to solve the problem of the bonding wires being broken by the bonding material during the bonding process, a drainage groove 102 is formed on the upper surface of the silicon chip 101 to drain the bonding material to the surrounding areas of the silicon chip 101, thereby preventing the bonding wires from being broken by the bonding material.

[0049] Specifically, the substrate 103 is provided with BGA pads and solder balls. The substrate is connected to the chip in the slot via conductive glue. The solder joints on the chip are connected to the BGA (Ball Grid Array) pads on the substrate / lead frame via bonding wires. The chip, bonding wires, solder balls, and substrate constitute the power supply and signal channels of the circuit. The plastic encapsulation compound encapsulates the substrate, chip, and bonding wires.

[0050] Therefore, the packaging structure provided by the embodiments of the present invention, by providing drainage grooves, can direct the encapsulating material around the silicon chip during the encapsulation process, effectively preventing displacement of the silicon chip due to the impact of the encapsulating material. Furthermore, based on factors such as the viscosity variation of the encapsulating material and the time the silicon chip is packaged, the bonding wires of the chip are subjected to minimal force when the encapsulating material is diverted, effectively preventing the bonding wires from being broken by the encapsulating material and improving the reliability of the encapsulated product.

[0051] It should be noted that when manufacturing the drainage groove 102, any one of laser grooving, wet etching and deep silicon etching can be used. Of course, other methods that can manufacture the drainage groove 102 can also be used, which is not limited here.

[0052] The specific processing method can be summarized as follows: forming drainage grooves on the upper surface of the silicon chip → thinning the lower surface of the silicon chip → metallizing the lower surface of the silicon chip → dicing and sorting → silicon chip mounting → bonding → plastic encapsulation. Alternatively, the process can be as follows: thinning the silicon chip → metallizing the lower surface of the silicon chip → dicing and sorting → silicon chip mounting → forming drainage grooves on the upper surface of the silicon chip → bonding → plastic encapsulation.

[0053] Specifically, in the embodiment of the present invention, in order to improve the drainage effect, the drainage groove 102 includes a cross-shaped slot structure.

[0054] More specifically, Figure 1AAs shown, the drainage groove 102 includes a grooving structure arranged in a cross shape along the diagonal of the silicon chip 101.

[0055] Further specifically, as Figure 1C shown, the drainage groove 102 includes a grooving structure arranged in a cross shape like a Chinese character '田' (field).

[0056] It should be understood that through the structure of the drainage groove 102 shown in Figure 1A and Figure 1C when encapsulating with molding compound, the molding compound can be effectively drained along the grooves to the four corners, thereby effectively preventing the silicon chip 101 from being displaced due to the impact of the molding compound, and at the same time effectively avoiding the bonding wires from being broken.

[0057] Specifically, the bonding wire 104 includes lead segments arranged at each diagonal position of the silicon chip 101. One end of each lead segment is located in the drainage groove 102, and the other end is connected to the substrate 103.

[0058] In the embodiment of the present invention, as Figure 1A and Figure 1C shown, it may specifically include 4 lead segments located at the four corners of the silicon chip 101, and each lead segment can achieve the bonding between the silicon chip 101 and the substrate 103.

[0059] Further specifically, the diameter of each lead segment is between 5 μm and 50 μm, and the length of each lead segment is between 1 mm and 10 mm.

[0060] In the embodiment of the present invention, the bonding wire 104 includes any one of gold wire, copper wire, alloy wire, and polymer conductive wire.

[0061] In the embodiment of the present invention, the substrate 103 includes any one of a multi-layer substrate, a buried substrate, and a flexible substrate.

[0062] It should be noted that in the embodiment of the present invention, the multi-layer substrate specifically refers to a substrate with the number of layers between 1 and 30, a line width greater than or equal to 5 μm, a line pitch greater than or equal to 5 μm, and the number of pins between 1 and 10000.

[0063] As another embodiment of the present invention, a processing method for a plastic encapsulation structure is provided, which is used to process the plastic encapsulation structure shown in the foregoing Figure 1A wherein, as Figures 2A to 2E shown, the processing method includes:

[0064] Step S110, as Figure 2AAs shown, a substrate 103 and a silicon chip 101 are provided, wherein the substrate 103 includes multiple pins, and the top solder mask (TSM) layer of the substrate 103 is the chip bonding area, and the bottom solder mask (BSM) layer of the substrate is the BGA pad area; it should be understood that the substrate 103 can specifically be a high-density substrate, and the substrate and the silicon chip are both treated with nickel palladium gold.

[0065] Step S120: Figure 2B As shown, the upper surface of the silicon chip 101 is processed to form a drainage groove 102; for example, the upper surface of the silicon chip can be processed by high-precision laser or etching to prepare a groove structure of a certain width and depth along the diagonal direction to form the drainage groove 102.

[0066] Step S130: Thinning the lower surface of the silicon chip 101 to reach a preset thickness. In an embodiment of the present invention, a fully automatic thinning machine is used to thin the back of the silicon chip 101 to reach the desired thickness.

[0067] Step S140: Metal plating is performed on the lower surface of the silicon chip 101 to form back gold; it should be understood that this method can match the stresses among the chip, solder, and base, while improving the bonding strength between the silicon chip and the base and reducing the contact resistance and contact thermal resistance.

[0068] Step S150: Figure 2C As shown, the back metal of the silicon chip 101 is welded to the surface of the substrate 103;

[0069] Step S160: Slicing the silicon chip 101 to obtain a separate package structure with independent electrical performance;

[0070] It should be understood that each chip with independent electrical performance is separated one by one along the scribe groove.

[0071] Step S170: Figure 2D As shown, the silicon chip 101 on the separate package structure is bonded to the substrate 103; specifically, gold wires can be welded to the surface of the silicon chip 101 and the substrate 103 through thermal ultrasound to achieve electrical connections between the silicon chip and the external circuit, and between the silicon chips.

[0072] Step S180: Figure 2E As shown, the bonded individual package structures are plastic-encapsulated, and the plastic encapsulation material is drained to the periphery of the silicon chip 101 through the drainage groove 102 to form a plastic encapsulation material layer 105 disposed around the silicon chip 101 .

[0073] It should be understood that the final step is plastic encapsulation, where the slotted silicon chip or the slotted silicon chip and the gold wire are sealed with molten plastic encapsulation material to prevent them from being affected by external factors and becoming ineffective, thereby obtaining a plastic encapsulated device with high reliability.

[0074] As another embodiment of the present invention, a method for processing a plastic package structure is provided, which is used to process the plastic package structure described above, wherein: Figures 3A to 3E As shown, the processing method includes:

[0075] Step S210: Figure 3A As shown, a substrate 103 and a silicon chip 101 are provided, wherein the substrate 103 includes multiple pins, and the TSM layer of the substrate is the chip bonding area, and the BSM layer of the substrate is the BGA pad area; it should be understood that the substrate 103 can specifically be a high-density substrate, and the substrate and the silicon chip are both treated with nickel palladium gold.

[0076] Step S220: thinning the lower surface of the silicon chip 101 to reach a preset thickness, and metal-plating the lower surface of the silicon chip 101 to form a back-gold coating;

[0077] In an embodiment of the present invention, a fully automatic thinning machine is used to thin the back of the silicon chip to achieve the desired thickness, and vacuum metal coating is performed on the thinned surface to form back gold, so that the stresses between the chip, solder, and base are matched, while the bonding strength between the chip and the base is improved, and the contact resistance and contact thermal resistance are reduced.

[0078] Step S230: welding the back metal of the silicon chip 101 to the surface of the substrate 103;

[0079] Step S240: Slicing the silicon chip 101 to obtain a separate package structure with independent electrical performance;

[0080] Specifically, the silicon chip 101 is diced, and each chip with independent electrical performance is separated one by one along the dicing grooves.

[0081] Step S250: processing the upper surface of the silicon chip 101 on the individual package structure to form a drainage groove 102;

[0082] The upper surface of the silicon chip is formed into a groove structure with a certain width and depth along the diagonal direction by high-precision laser or etching to form the drainage groove 102.

[0083] Step S260: bonding the silicon chip 101 on the separate package structure to the substrate 103;

[0084] Specifically, gold wires are welded to the silicon chip 101 and the surface of the substrate 103 by thermosonic action, thereby achieving electrical connections between the silicon chip 101 and the external circuit, and between the silicon chips 101 and the silicon chips 101 .

[0085] Step S270 , performing plastic encapsulation on the bonded individual package structures, and draining the plastic encapsulation material to the periphery of the silicon chip 101 through the drainage groove 102 to form a plastic encapsulation material layer 105 disposed around the silicon chip 101 .

[0086] Specifically, during the plastic packaging, the slotted silicon chip and the gold wire are sealed with molten plastic packaging material to prevent them from being damaged by external influences, thereby obtaining a plastic-packaged device with high reliability.

[0087] In summary, the processing method for the encapsulated structure provided by the embodiments of the present invention, by providing a drainage groove, can direct the encapsulating material to the periphery of the silicon chip during the encapsulation process, effectively preventing the silicon chip from being displaced by the impact of the encapsulating material. Furthermore, based on factors such as the viscosity variation characteristics of the encapsulating material and the time the silicon chip is wrapped, the bonding wires of the chip are subjected to minimal force when the encapsulating material is diverted, thereby effectively preventing the bonding wires from being broken by the encapsulating material and improving the reliability of the encapsulated product.

[0088] It will be understood that the above embodiments are merely exemplary embodiments for illustrating the principles of the present invention, and the present invention is not limited thereto. Those skilled in the art will appreciate that various modifications and improvements can be made without departing from the spirit and substance of the present invention, and such modifications and improvements are also considered to be within the scope of protection of the present invention.

Claims

1. A plastic packaging structure, characterized in that: include: A substrate and a silicon chip disposed on the substrate, wherein a drainage groove is disposed on a surface of the silicon chip facing away from the substrate, the silicon chip is bonded to the substrate via a bonding wire, one end of the bonding wire being located in the drainage groove and the other end being located on the substrate, the drainage groove being capable of draining a molding compound to the periphery of the silicon chip to form a molding compound layer disposed around the silicon chip; The drainage groove includes a groove structure arranged in a cross pattern.

2. The plastic packaging structure according to claim 1, characterized in that: The drainage groove includes a groove structure arranged along the diagonal line of the silicon chip and in a cross shape.

3. The plastic packaging structure according to claim 2, characterized in that: The bonding wire includes a lead segment arranged at each diagonal position of the silicon chip, one end of each lead segment is located in the drainage groove, and the other end is connected to the substrate.

4. The plastic packaging structure according to claim 3, characterized in that: The diameter of each lead segment is between 5 μm and 50 μm, and the length of each lead segment is between 1 mm and 10 mm.

5. The plastic packaging structure according to claim 1, characterized in that: The bonding wire includes any one of a gold wire, a copper wire, an alloy wire and a polymer conductive wire.

6. The plastic packaging structure according to claim 1, characterized in that: The substrate includes any one of a multi-layer substrate, an embedded substrate and a flexible substrate.

7. A method for processing a plastic package structure, for processing the plastic package structure according to any one of claims 1 to 6, characterized in that: The processing method comprises: Providing a substrate and a silicon chip, wherein the substrate includes multiple pins, the top solder resist layer of the substrate is a chip bonding area, and the bottom solder resist layer of the substrate is a BGA pad area; Processing the upper surface of the silicon chip to form a drainage groove; Thinning the lower surface of the silicon chip to reach a preset thickness; Performing metal plating on the lower surface of the silicon chip to form a back gold; Soldering the back gold of the silicon chip to the surface of the substrate; Slicing the silicon chip to obtain separate packaging structures with independent electrical performance; Bonding the silicon chip on the separate package structure to the substrate; The bonded individual packaging structures are plastic-encapsulated, and the plastic encapsulation material is drained to the periphery of the silicon chip through the drainage groove to form a plastic encapsulation material layer arranged around the silicon chip.

8. A method for processing a plastic package structure, for processing the plastic package structure according to any one of claims 1 to 6, characterized in that: The processing method comprises: Providing a substrate and a silicon chip, wherein the substrate includes multiple pins, the top solder resist layer of the substrate is a chip bonding area, and the bottom solder resist layer of the substrate is a BGA pad area; Thinning the lower surface of the silicon chip to reach a preset thickness, and metal-plating the lower surface of the silicon chip to form a back-gold coating; Soldering the back gold of the silicon chip to the surface of the substrate; Slicing the silicon chip to obtain separate packaging structures with independent electrical performance; Processing the upper surface of the silicon chip on the individual packaging structure to form a drainage groove; Bonding the silicon chip on the separate package structure to the substrate; The bonded individual packaging structures are plastic-encapsulated, and the plastic encapsulation material is drained to the periphery of the silicon chip through the drainage groove to form a plastic encapsulation material layer arranged around the silicon chip.

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