A metal oxide semiconductor field effect transistor

Abstract

The present invention discloses a metal oxide semiconductor field effect transistor, which relates to the technical field of semiconductor field effect transistors. It includes a frame, inside which a first P-shaped semiconductor is installed. On one side of the top of the first P-shaped semiconductor, a first N-shaped semiconductor is installed. On the other side of the top of the first P-shaped semiconductor, a second N-shaped semiconductor is installed. On one side of the bottom of the first P-shaped semiconductor, a third N-shaped semiconductor is installed. On the other side of the bottom of the first P-shaped semiconductor, a fourth N-shaped semiconductor is installed. An N-shaped semiconductor channel is installed between the third N-shaped semiconductor and the fourth N-shaped semiconductor. Through the setting of the interaction between the enhancement-type metal oxide semiconductor field and the depletion-type metal oxide semiconductor field, the device of the present invention also has the function of controlling the operation of two devices that cannot work simultaneously. This design ensures that the above two working devices do not interfere with each other and ensures the normal operation of the machine.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor field effect transistors, and specifically to a metal oxide semiconductor field effect transistor. Background Art

[0002] A metal oxide semiconductor field effect transistor is a field effect transistor that can be widely used in analog circuits and digital circuits.

[0003] At present, some metal oxide semiconductor field effect transistors have the function of controlling the on-off of the current between two pins, or controlling the magnitude of the current between two pins by the amount of charge on the gate metal plate. The functions of this type of effect transistor are too single, so a metal oxide semiconductor field effect transistor is proposed. Summary of the Invention

[0004] The purpose of the present invention is to provide a metal oxide semiconductor field effect transistor to solve the problems raised in the above background art.

[0005] To achieve the above purpose, the present invention provides the following technical solution: A metal oxide semiconductor field effect transistor includes a frame. An electric field effect is installed inside the frame. A first P-type semiconductor is installed inside the electric field effect. On one side of the top of the first P-type semiconductor, a first N-type semiconductor is installed. On the other side of the top of the first P-type semiconductor, a second N-type semiconductor is installed. On one side of the bottom of the first P-type semiconductor, a third N-type semiconductor is installed. On the other side of the bottom of the first P-type semiconductor, a fourth N-type semiconductor is installed. An N-type semiconductor channel is installed between the third N-type semiconductor and the fourth N-type semiconductor. An enhancement-mode metal oxide semiconductor field is installed at the top of the first P-type semiconductor. A depletion-mode metal oxide semiconductor field is installed at the bottom of the first P-type semiconductor. A first oxide layer is fixedly connected to the top of the first P-type semiconductor. A second oxide layer is fixedly connected to the bottom of the first P-type semiconductor. A first metal plate is installed on the top of the first oxide layer. A second metal plate is installed on the bottom of the second oxide layer. Both the first metal plate and the second metal plate are electrically connected to a gate G.

[0006] Furthermore, the enhancement-mode metal oxide semiconductor field includes a first source G plate and a first drain D plate. The bottom of the first source G plate is fixed to the top of the first oxide layer. The bottom of the first drain D plate is fixed to the top of the first oxide layer. The bottom of the first source G plate penetrates through the first oxide layer and contacts the first N-type semiconductor. The bottom of the first drain D plate penetrates through the first oxide layer and contacts the second N-type semiconductor. The top of the first source G plate is electrically connected to a first source G wire. The top of the first drain D plate is electrically connected to a first drain D wire. The first source G wire is electrically connected to a first working field. The first drain D wire is electrically connected to a first working field.

[0007] Further, the depletion-type metal oxide semiconductor field includes a second source G plate and a second drain D plate. The top of the second source G plate is fixed to the bottom of the second oxide layer, and the top of the second drain D plate is fixed to the bottom of the first oxide layer. The top of the second source G plate penetrates through the second oxide layer and contacts the third N-type semiconductor, and the top of the second drain D plate penetrates through the first oxide layer and contacts the fourth N-type semiconductor. The top of the second source G plate is electrically connected to a second source G wire, and the top of the second drain D plate is electrically connected to a second drain D wire. The second source G wire is electrically connected to a second working field, and the second drain D wire is electrically connected to a second working field.

[0008] Further, the first working field includes a first power supply, a second P-type semiconductor, a fifth N-type semiconductor, a switch, and a first working device. The first power supply, the second P-type semiconductor, the fifth N-type semiconductor, the switch, and the first working device are electrically connected in sequence, and one side of the second P-type semiconductor is fixed to one side of the fifth N-type semiconductor.

[0009] Further, the second working field includes a third power supply, a light bulb, and a second working device. The third power supply, the light bulb, and the second working device are electrically connected in sequence.

[0010] Further, the gate G includes a second power supply. The positive pole of the second power supply is electrically connected to a first wire and a second wire. The first wire is electrically connected to a first metal plate, and the second wire is electrically connected to a second metal plate. The negative pole of the second power supply is electrically connected to a third wire, and the third wire is electrically connected to the first source G wire.

[0011] Compared with the prior art, the beneficial effects of the present invention are:

[0012] In this metal oxide semiconductor field effect transistor, through the setting of the interaction between the enhancement-type metal oxide semiconductor field and the depletion-type metal oxide semiconductor field, the device can also control the operation of two devices that cannot work simultaneously. This design ensures that the above two working devices do not interfere with each other and guarantees the normal operation of the machine.

[0013] In this metal oxide semiconductor field effect transistor, through the setting of the light bulb on the depletion-type metal oxide semiconductor field, workers can directly observe whether the field effect transistor is operating normally. When the enhancement-type metal oxide semiconductor field is operating, the light bulb should be off, and when the enhancement-type metal oxide semiconductor field stops, the light bulb lights up. In this way, it is convenient for workers to observe whether the field effect transistor is faulty and prevents mechanical damage caused by the fault. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 Isometric view of the present invention;

[0015] Figure 2 is the internal isometric view of the present invention;

[0016] Figure 3 is the sectional view of the present invention;

[0017] Figure 4 is the sectional view of the electric effect field of the present invention;

[0018] Figure 5 is the simplified circuit diagram of the present invention;

[0019] Figure 6 is Figure 5 the simplified circuit diagram when the switch is closed.

[0020] In the figure: 1, the first N-shaped semiconductor; 2, the second N-shaped semiconductor; 3, the third N-shaped semiconductor; 4, the fourth N-shaped semiconductor; 5, the first P-shaped semiconductor; 6, the first oxide layer; 7, the second oxide layer; 8, the N-shaped semiconductor channel; 9, the first metal plate; 10, the second metal plate; 11, the first source G plate; 12, the first drain D plate; 13, the second source G plate; 14, the second drain D plate; 15, the first source G wire; 16, the first drain D wire; 17, the second source G wire; 18, the second drain D wire; 19, the first power supply; 20, the second P-shaped semiconductor; 21, the fifth N-shaped semiconductor; 22, the switch; 23, the first working device; 24, the second power supply; 25, the first wire; 26, the second wire; 27, the third wire; 28, the third power supply; 29, the light bulb; 30, the second working device; 31, the frame; 32, the electric effect field. Detailed implementation manners

[0021] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without making creative efforts shall fall within the protection scope of the present invention.

[0022] It should be noted that in the description of the present invention, the orientation or positional relationship indicated by the terms "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. is based on the orientation or positional relationship shown in the accompanying drawings. It is only for the convenience of describing the present invention and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation to the present invention.

[0023] In addition, it should be understood that, for the sake of convenience of description, the dimensions of the various components shown in the drawings are not drawn in accordance with actual proportional relationships. For example, the thickness or width of certain layers may be exaggerated relative to other layers.

[0024] It should be noted that like reference numerals and letters denote like items in the following drawings. Therefore, once an item is defined or described in one drawing, it will not be necessary to give further specific discussion and description thereof in the description of the subsequent drawings.

[0025] As Figures 1-6 shown, the present invention provides a technical solution: a metal oxide semiconductor field effect transistor, including a frame 31, an electric effect field 32 is installed inside the frame 31, a first P-shaped semiconductor is installed inside the electric effect field 32, a first N-shaped semiconductor 1 is installed on one side of the top of the first P-shaped semiconductor 5, a second N-shaped semiconductor 2 is installed on the other side of the top of the first P-shaped semiconductor 5, a third N-shaped semiconductor 3 is installed on one side of the bottom of the first P-shaped semiconductor 5, a fourth N-shaped semiconductor 4 is installed on the other side of the bottom of the first P-shaped semiconductor 5, an N-shaped semiconductor channel 8 is installed between the third N-shaped semiconductor 3 and the fourth N-shaped semiconductor 4, an enhancement-mode metal oxide semiconductor field is installed on the top of the first P-shaped semiconductor 5, a depletion-mode metal oxide semiconductor field is installed on the bottom of the first P-shaped semiconductor 5, a first oxide layer 6 is fixedly connected to the top of the first P-shaped semiconductor 5, a second oxide layer 7 is fixedly connected to the bottom of the first P-shaped semiconductor 5, a first metal plate 9 is installed on the top of the first oxide layer 6, a second metal plate 10 is installed on the bottom of the second oxide layer 7, and both the first metal plate 9 and the second metal plate 10 are electrically connected to a gate G.

[0026] As Figure 3 shown, the enhancement-mode metal oxide semiconductor field includes a first source G plate 11 and a first drain D plate 12. The bottom of the first source G plate 11 is fixed to the top of the first oxide layer 6, the bottom of the first drain D plate 12 is fixed to the top of the first oxide layer 6, the bottom of the first source G plate 11 penetrates through the first oxide layer 6 and contacts the first N-shaped semiconductor 1, the bottom of the first drain D plate 12 penetrates through the first oxide layer 6 and contacts the second N-shaped semiconductor 2, the top of the first source G plate 11 is electrically connected to a first source G wire 15, the top of the first drain D plate 12 is electrically connected to a first drain D wire 16, the first source G wire 15 is electrically connected to a first working field, and the first drain D wire 16 is electrically connected to a first working field.

[0027] As Figure 3As shown, the depletion-type metal oxide semiconductor field includes the second source G plate 13 and the second drain D plate 14. The top of the second source G plate 13 is fixed to the bottom of the second oxide layer 7, and the top of the second drain D plate 14 is fixed to the bottom of the first oxide layer 6. The top of the second source G plate 13 penetrates through the second oxide layer 7 and contacts the third N-type semiconductor 3. The top of the second drain D plate 14 penetrates through the first oxide layer 6 and contacts the fourth N-type semiconductor 4. The top of the second source G plate 13 is electrically connected to the second source G wire 17, and the top of the second drain D plate 14 is electrically connected to the second drain D wire 18. The second source G wire 17 is electrically connected to the second working field, and the second drain D wire 18 is electrically connected to the second working field.

[0028] As Figure 1 shown, the first working field includes a first power supply 19, a second P-type semiconductor 20, a fifth N-type semiconductor 21, a switch 22, and a first working device 23. The first power supply 19, the second P-type semiconductor 20, the fifth N-type semiconductor 21, the switch 22, and the first working device 23 are electrically connected in sequence. One side of the second P-type semiconductor 20 is fixed to one side of the fifth N-type semiconductor 21. The second working field includes a third power supply 28, a light bulb 29, and a second working device 30. The third power supply 28, the light bulb 29, and the second working device 30 are electrically connected in sequence.

[0029] As Figure 2 shown, the gate G includes a second power supply 24. The positive pole of the second power supply 24 is electrically connected to a first wire 25 and a second wire 26. The first wire 25 is electrically connected to the first metal plate 9, and the second wire 26 is electrically connected to the second metal plate 10. The negative pole of the second power supply 24 is electrically connected to a third wire 27, and the third wire 27 is electrically connected to the first source G wire 15 by wire.

[0030] Working principle: As Figure 5 and Figure 6As shown, when the third power supply 28 starts to work properly, due to electrical connection, the light bulb 29 and the second working device 30 start to work properly. Electrons flow from the second drain D wire 18 through the second drain D plate 14, the fourth N-type semiconductor 4, the N-type semiconductor channel 8, the third N-type semiconductor 3, the second source G plate 13 and the second source G wire 17 to the positive pole of the third power supply 28. At this time, the normal working process of the depletion-type metal oxide semiconductor field is completed. At this time, since the switch 22 is in the open state, the enhancement-type metal oxide semiconductor field is not in the working state. When the switch 22 is closed, the first power supply 19 supplies power. When the first power supply 19 supplies power, the first power supply 19 will cause the second power supply 24 to make the ions in the first metal plate 9 and the second metal plate 10 flow to the positive pole of the second power supply 24 through the first wire 25 and the second wire 26, making the first metal plate 9 and the second metal plate 10 positively charged. At this time, the positive charges on the positively charged first metal plate 9 will attract the negatively charged electrons on the first P-type semiconductor 5, the first N-type semiconductor 1 and the second N-type semiconductor 2, and the positive charges on the second metal plate 10 will attract the negatively charged electrons on the third N-type semiconductor 3, the fourth N-type semiconductor 4, the first P-type semiconductor 5 and the N-type semiconductor channel 8. Therefore, in the region near the first oxide layer 6 between the first N-type semiconductor 1 and the second N-type semiconductor 2, the first P-type semiconductor 5 is transformed into a new N-type semiconductor channel 8 containing free electrons. On the contrary, since the third N-type semiconductor 3 and the fourth N-type semiconductor 4 are located in the N-type semiconductor channel 8, the N-type semiconductor channel 8 disappears, and the ions between the third N-type semiconductor 3 and the fourth N-type semiconductor 4 cannot flow, making the depletion-type metal oxide semiconductor field in the off state. However, due to the generation of the new N-type semiconductor channel 8, the ions between the first N-type semiconductor 1 and the second N-type semiconductor 2 can flow, and the electron flow direction in the enhancement-type metal oxide semiconductor field is similar to that in the depletion-type metal oxide semiconductor field, making the enhancement-type metal oxide semiconductor field operate normally, and the first working device 23 starts to work. To ensure the normal operation of the enhancement-type metal oxide semiconductor field, a second P-type semiconductor 20 and a fifth N-type semiconductor 21 are installed in the enhancement-type metal oxide semiconductor field. The second P-type semiconductor 20 and the fifth N-type semiconductor 21 can form a semiconductor, making the current of the device flow in only one direction. If it is necessary to turn on the depletion-type metal oxide semiconductor field again, the switch 22 is turned off, and the first power supply 19 stops supplying power, making the first metal plate 9 and the second metal plate 10 no longer positively charged, resulting in the disappearance of the new N-type semiconductor channel 8 and the appearance of the original N-type semiconductor channel 8, making the depletion-type metal oxide semiconductor field start to work properly.

[0031] Although embodiments of the present invention have been shown and described, it will be understood by those of ordinary skill in the art that various changes, modifications, substitutions and variations can be made to these embodiments without departing from the principles and spirit of the present invention, and the scope of the present invention is defined by the appended claims and their equivalents.

Claims

1. A metal oxide semiconductor field effect transistor, comprising a frame (31), characterized in that: Inside the frame (31), an electric effect field (32) is installed. Inside the electric effect field (32), a first P-type semiconductor (5) is installed. On one side of the top of the first P-type semiconductor (5), a first N-type semiconductor (1) is installed. On the other side of the top of the first P-type semiconductor (5), a second N-type semiconductor (2) is installed. On one side of the bottom of the first P-type semiconductor (5), a third N-type semiconductor (3) is installed. On the other side of the bottom of the first P-type semiconductor (5), a fourth N-type semiconductor (4) is installed. Between the third N-type semiconductor (3) and the fourth N-type semiconductor (4), an N-type semiconductor channel (8) is installed. At the top of the first P-type semiconductor (5), an enhanced metal oxide semiconductor field is installed. At the bottom of the first P-type semiconductor (5), a depletion metal oxide semiconductor field is installed. At the top of the first P-type semiconductor (5), a first oxide layer (6) is fixedly connected. At the bottom of the first P-type semiconductor (5), a second oxide layer (7) is fixedly connected. At the top of the first oxide layer (6), a first metal plate (9) is installed. At the bottom of the second oxide layer (7), a second metal plate (10) is installed. Both the first metal plate (9) and the second metal plate (10) are electrically connected to the gate G; The enhanced metal oxide semiconductor field includes a first source G plate (11) and a first drain D plate (12). The bottom of the first source G plate (11) is fixed to the top of the first oxide layer (6), and the bottom of the first drain D plate (12) is fixed to the top of the first oxide layer (6). The top of the first source G plate (11) is electrically connected to a first source G wire (15), and the first source G wire (15) is electrically connected to a first working field; The depletion metal oxide semiconductor field includes a second source G plate (13) and a second drain D plate (14). The top of the second source G plate (13) is fixed to the bottom of the second oxide layer (7), and the top of the second drain D plate (14) is fixed to the bottom of the first oxide layer (6). The top of the second source G plate (13) is electrically connected to a second source G wire (17), and the top of the second drain D plate (14) is electrically connected to a second drain D wire (18). The second source G wire (17) is electrically connected to a second working field, and the second drain D wire (18) is electrically connected to a second working field; The first working field includes a first power supply (19), a second P-type semiconductor (20), a fifth N-type semiconductor (21), a switch (22), and a first working device (23). The first power supply (19), the second P-type semiconductor (20), the fifth N-type semiconductor (21), the switch (22), and the first working device (23) are electrically connected in sequence. One side of the second P-type semiconductor (20) is fixed to one side of the fifth N-type semiconductor (21); The second working field includes a third power supply (28), a light bulb (29), and a second working device (30). The third power supply (28), the light bulb (29), and the second working device (30) are electrically connected in sequence; The gate G includes a second power supply (24). The positive electrode of the second power supply (24) is electrically connected to a first wire (25) and a second wire (26). The first wire (25) is electrically connected to a first metal plate (9), and the second wire (26) is electrically connected to a second metal plate (10). The negative electrode of the second power supply (24) is electrically connected to a third wire (27), and the third wire (27) is connected to a first source G wire.

2. The metal oxide semiconductor field effect transistor according to claim 1, wherein: The bottom end of the first source G plate (11) penetrates through the first oxide layer (6) and contacts the first N-type semiconductor (1). The bottom end of the first drain D plate (12) penetrates through the first oxide layer (6) and contacts the second N-type semiconductor (2). The top end of the first drain D plate (12) is electrically connected to a first drain D wire (16), and the first drain D wire (16) is electrically connected to a first working field.

3. The metal oxide semiconductor field effect transistor according to claim 1, wherein: The top end of the second source G plate (13) penetrates through the second oxide layer (7) and contacts the third N-type semiconductor (3). The top end of the second drain D plate (14) penetrates through the first oxide layer (6) and contacts the fourth N-type semiconductor (4).

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