A power output circuit, a power output device and a smart door lock

Abstract

The application belongs to the technical field of power supply, and provides a power supply output circuit, a power supply output device and an intelligent door lock, wherein the first power supply input end is connected with the first power supply signal, the second power supply input end is connected with the second power supply signal, the normally-off anti-backflow switch module is turned on within the first preset time when the first power supply input end is connected with the first power supply signal, so as to output the first power supply signal to the combining output end; the normally-on anti-backflow switch module is turned off within the second preset time when the first power supply input end is connected with the first power supply signal, and is kept on when the first power supply input end is powered off and the second power supply input end is connected with the second power supply signal, so as to output the second power supply signal to the combining output end. By setting the first preset time to be greater than the second preset time, the on and off time of the two power supply signals is staggered, the two power supply signals are completely isolated, the mutual influence of the two power supplies is avoided, and stable power supply output is realized.

Description

Technical Field

[0001] This application belongs to the field of power supply technology, and in particular relates to a power output circuit, a power output device, and a smart door lock. Background Technology

[0002] Smart door locks typically use dry cell batteries or lithium batteries for power. When the batteries are completely depleted, an external 5V power source can be connected via USB for emergency power to open the door, which is also one of the industry standard requirements. Therefore, there will be a design for a combined circuit of the two power sources. As a battery-powered smart door lock is a power-sensitive electronic product, the design of this combined circuit must not only prevent backflow between the two power sources, but also meet the requirements of low leakage current and low on-state voltage drop.

[0003] However, existing dual-power-supply combining circuits suffer from power loss issues in applications. Summary of the Invention

[0004] To achieve the above objectives, embodiments of this application provide a power output circuit, a power output device, and a smart door lock, aiming to solve the power loss problem existing in the application of existing dual-power combination circuits.

[0005] A first aspect of this application provides a power output circuit, the power output circuit comprising:

[0006] The first power input terminal is used to connect the first power signal;

[0007] The second power input terminal is used to connect the second power signal;

[0008] Combined output terminal;

[0009] The normally disconnected backflow prevention switch module is connected to the first power input terminal and the combined output terminal, and is used to conduct within a first preset time when the first power signal is connected to the first power input terminal, so as to output the first power signal to the combined output terminal.

[0010] A normally conducting anti-backflow switch module is connected to the first power input terminal and the second power input terminal. It is used to turn off within a second preset time when the first power input terminal is connected to the first power signal, and to remain conducting when the first power input terminal is powered off and the second power input terminal is connected to the second power signal, so as to output the second power signal to the combined output terminal.

[0011] Wherein, the first preset time is greater than the second preset time.

[0012] In one embodiment, the normally conducting anti-backflow switch module is further configured to conduct for a third preset time when the first power input terminal is powered off, so as to output the second power signal to the combined output terminal; the normally disconnected anti-backflow switch module is further configured to disconnect for a fourth preset time when the first power input terminal is powered off.

[0013] The third preset time is greater than the fourth preset time.

[0014] In one embodiment, the normally disconnect anti-backflow switch module includes:

[0015] The first pre-charge unit is connected to the first power input terminal and is used to generate a first pre-charge signal when the first power input terminal is powered on.

[0016] The first switching unit is connected to the first power input terminal and the combined output terminal respectively, and is used to keep the first power input terminal and the combined output terminal off, and to prevent the current from the combined output terminal from flowing back to the first power output terminal.

[0017] A first control unit, connected to the first pre-charge unit, is used to receive the first pre-charge signal and generate a first switch control signal based on the first pre-charge signal.

[0018] The first switching unit is further configured to control the connection between the first power input terminal and the combined output terminal according to the first switching control signal.

[0019] In one embodiment, the normally conducting anti-backflow switch module includes:

[0020] The second pre-charge unit is connected to the first power input terminal and is used to generate a second pre-charge signal when the first power input terminal is powered on.

[0021] The second switching unit is connected to the second power input terminal and the combined output terminal respectively, and is used to maintain the conduction between the second power input terminal and the combined output terminal, and to prevent the current from flowing back from the combined output terminal to the second power input terminal.

[0022] The second control unit, connected to the second pre-charge unit and the second switch unit, is used to receive the second pre-charge signal and generate a second switch control signal based on the second pre-charge signal to ground the second power input terminal and the combined output terminal.

[0023] In one embodiment, the second pre-charge unit includes: a first resistor, a first capacitor, and a first NMOS transistor;

[0024] The gate of the first NMOS transistor is connected to the first power input terminal. The drain of the first NMOS transistor, the first end of the first resistor, and the first end of the first capacitor are all connected to the second control unit. The source of the first NMOS transistor is grounded, and the second end of the first resistor is connected to the second switching unit.

[0025] In one embodiment, the second switching unit includes: a second PMOS transistor, a third PMOS transistor, and a second resistor;

[0026] The drain of the second PMOS transistor is connected to the second power input terminal. The source of the second PMOS transistor and the source of the third PMOS transistor are both connected to the second control unit. The drain of the third PMOS transistor is connected to the combined output terminal. The gate of the second PMOS transistor and the gate of the third PMOS transistor are both connected to the first end of the second resistor. The second end of the second resistor is grounded.

[0027] In one embodiment, the second control unit includes: a first PMOS transistor;

[0028] The gate of the first PMOS transistor is connected to the second precharge unit, the source of the first PMOS transistor is connected to the second switching unit, and the drain of the first PMOS transistor is connected to the first terminal of the second resistor.

[0029] In one embodiment, the first switching unit includes a fourth PMOS transistor and a fifth PMOS transistor;

[0030] The drain of the fourth PMOS transistor is connected to the first power input terminal, the source of the fourth PMOS transistor and the source of the fifth PMOS transistor are both connected to the first control unit, and the gate of the fourth PMOS transistor and the gate of the fifth PMOS transistor are both connected to the first control unit.

[0031] A second aspect of this application provides a power output device, the power output device comprising:

[0032] Energy storage modules, and

[0033] The power output circuit as described in any of the above is connected to the energy storage module.

[0034] A third aspect of this application provides a smart door lock, including: a door lock body; and a power output circuit as described in any of the preceding claims, the power output circuit being used to supply power to the door lock body.

[0035] This application provides a power output circuit, a power output device, and a smart door lock. A first power input terminal receives a first power signal, and a second power input terminal receives a second power signal. A normally open anti-backflow switch module conducts for a first preset time when the first power input terminal receives the first power signal, outputting the first power signal to the combined output terminal. A normally closed anti-backflow switch module is turned off for a second preset time when the first power input terminal receives the first power signal, and remains open when the first power input terminal is powered off and the second power input terminal receives the second power signal, outputting the second power signal to the combined output terminal. By setting the first preset time to be greater than the second preset time, the on and off times of the two power signals are staggered, completely isolating the two power signals and preventing mutual interference, thus achieving stable power output. Attached Figure Description

[0036] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0037] Figure 1 A schematic diagram of a power output circuit provided in an embodiment of this application. Figure 1 ;

[0038] Figure 2 A schematic diagram of a power output circuit provided in an embodiment of this application. Figure 2 ;

[0039] Figure 3 A schematic diagram of a power output circuit provided in an embodiment of this application. Figure 3 ;

[0040] Figure 4 A schematic diagram of the structure of a normally conducting anti-backflow switch module provided in this application embodiment. Figure 1 ;

[0041] Figure 5 A schematic diagram of the structure of a normally conducting anti-backflow switch module provided in this application embodiment. Figure 2 ;

[0042] Figure 6 A schematic diagram of the structure of a normally conducting anti-backflow switch module provided in this application embodiment. Figure 3 ;

[0043] Figure 7 A schematic diagram of the structure of a normally open anti-backflow switch module provided in this application embodiment. Figure 1 ;

[0044] Figure 8 A schematic diagram of the structure of a normally open anti-backflow switch module provided in this application embodiment. Figure 2 . Detailed Implementation

[0045] To enable those skilled in the art to better understand the present invention, the technical solutions of the embodiments of the present invention will be clearly described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0046] The term "comprising," and any variations thereof, in the specification, claims, and accompanying drawings of this invention are intended to cover a non-exclusive inclusion. For example, a process, method, system, product, or apparatus that comprises a series of steps or units is not limited to the steps or units listed, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to such processes, methods, products, or apparatus. Furthermore, the terms "first," "second," and "third," etc., are used to distinguish different objects, not to describe a particular order.

[0047] This application provides a power output circuit, see [link to relevant documentation] Figure 1 As shown, the power output circuit includes: a first power input terminal 110, a second power input terminal 120, a combined output terminal 300, a normally open anti-backflow switch module, and a normally closed anti-backflow switch module.

[0048] Specifically, the first power input terminal 110 is used to receive the first power signal, and the second power input terminal 120 is used to receive the second power signal. The first power input terminal 110 and the second power input terminal 120 are respectively connected to two power sources, and the two power sources output power signals to the combined output terminal 300, so as to realize the switching of the two power sources to supply power to external devices and avoid power outages of external devices. For example, the second power input terminal 120 can be connected to an energy storage module to receive the second power signal provided by the energy storage module, and the first power input terminal 110 can be connected to a charging port or a USB input port.

[0049] In this embodiment, the normally open anti-backflow switch module 210 is connected to the first power input terminal 110 and the combined output terminal 300, and is used to conduct within a first preset time when the first power input terminal 110 is connected to the first power signal, so as to output the first power signal to the combined output terminal 300; the normally closed anti-backflow switch module 220 is connected to the first power input terminal 110 and the second power input terminal 120, and is used to turn off within a second preset time when the first power input terminal 110 is connected to the first power signal, and remain open when the first power input terminal 110 is powered off and the second power input terminal 120 is connected to the second power signal, so as to output the second power signal to the combined output terminal 300, wherein the first preset time is greater than the second preset time.

[0050] In this embodiment, the normally conducting anti-backflow switch module 220 remains conducting when no external signal is connected, while the normally disconnected anti-backflow switch module 210 remains disconnected when no external signal is connected. Therefore, when no external signal is connected, the combined output terminal 300 is normally electrically connected to the second power input terminal 120, while remaining insulated from the first power input terminal 110. When an external signal is connected, if the first power input terminal 110 is connected to a first power signal, the normally disconnected anti-backflow switch module 210 conducts for a first preset time, while the normally conducting anti-backflow switch module 220 is disconnected for a second preset time. The first preset time is longer than the second preset time. By setting the normally conducting anti-backflow switch module 220 and the normally disconnected anti-backflow switch module 210 to open slowly and close quickly, the on and off times of the two power supplies connected to the first power input terminal 110 and the second power input terminal 120 are staggered, completely isolating the two power supplies and avoiding interference during power switching.

[0051] Furthermore, when the first power input terminal 110 is powered off, the normally conducting anti-backflow switch module 220 is turned on within a third preset time, and the normally disconnected anti-backflow switch module 210 is turned off within a fourth preset time. Since the third preset time is longer than the fourth preset time, the second power input terminal 120 receives the second power signal and outputs it through the combined output terminal 300 to supply power to external devices.

[0052] In a specific application embodiment, the second power input terminal 120 can be connected to a backup power supply, while the first power input terminal 110 can be connected to a main power supply. When the main power supply is de-energized, the normally conducting anti-backflow switch module 220 is turned on, and the second power input terminal 120 outputs a second power signal through the combined output terminal 300 to supply power to the outside.

[0053] In one embodiment, the normally-conducting anti-backflow switch module 220 is also used to conduct for a third preset time when the first power input terminal 110 is powered off, so as to output a second power signal to the combined output terminal 300.

[0054] In one embodiment, the normally disconnected backflow prevention switch module 210 is also used to turn off within a fourth preset time when the first power input terminal 110 loses power.

[0055] In a specific application embodiment, when the backup power supply of the second power input terminal 120 is normally powered, the normally conducting anti-backflow switch module 220 remains in the conducting state, and the normal power supply (e.g., USB interface) is connected to the first power input terminal 110. The normally conducting anti-backflow switch module 220 is quickly turned off (turned off within a second preset time), and the normally disconnected anti-backflow switch module 210 is slowly turned on (turned on within a first preset time). At this time, the external device is powered through the combined output terminal 300 connected to the normal power supply.

[0056] When the power supply interface of the first power input terminal 110 is unplugged, the normally disconnected backflow prevention switch module 210 is quickly turned off, and the normally connected backflow prevention switch module 220 is slowly turned on, restoring the power supply from the backup power supply of the second power input terminal 120. In this application embodiment, under normal circumstances, the backup power supply of the second power input terminal 120 can be set, while the first power input terminal 110 is used as an emergency port.

[0057] In one embodiment, see Figure 2 As shown, the normally disconnected backflow prevention switch module includes: a first pre-charging unit 212, a first switching unit 211, and a first control unit 213.

[0058] The first pre-charging unit 212 is connected to the first power input terminal 110. The first pre-charging unit 212 is used to generate a first pre-charging signal when the first power input terminal 110 is powered on. The voltage of the first pre-charging signal is determined by the power-on time of the first power input terminal 110 and the voltage of the first power signal connected to the first power input terminal 110.

[0059] The first switching unit 211 is connected to the first power input terminal 110 and the combined output terminal 300, respectively, to keep the first power input terminal 110 and the combined output terminal 300 off and to prevent the current from the combined output terminal 300 from flowing back to the first power output terminal 110. In this embodiment, by setting the normally closed first switching unit 211 at the first power input terminal 110 and the combined output terminal 300, the combined output terminal 300 is insulated from the first power input terminal 110 when no external voltage signal is connected, thus preventing the current from the combined output terminal 300 from flowing back to the first power input terminal 110.

[0060] The first control unit 213 is connected to the first pre-charge unit 212. The first control unit 213 is used to receive the first pre-charge signal and generate a first switch control signal according to the first pre-charge signal. The first switch unit 211 controls the connection between the first power input terminal 110 and the combined output terminal 300 according to the first switch control signal.

[0061] In this embodiment, when the first power input terminal 110 is connected to the first power signal, the first pre-charging unit charges based on the first power signal. After the voltage of the first pre-charging signal reaches the first target voltage after a first preset time, the first control unit 213 controls the first power input terminal 110 and the combined output terminal 300 to conduct based on the first pre-charging signal of the first target voltage, thereby outputting the first power signal of the first power input terminal 110 to the combined output terminal 300, so as to realize the purpose of powering external devices by the first power input terminal 110.

[0062] In one embodiment, see Figure 2 As shown, the normally conducting anti-backflow switch module 220 includes: a second pre-charging unit 222, a second switching unit 221, and a second control unit 223.

[0063] The second pre-charge unit 222 is connected to the first power input terminal 110. The second pre-charge unit 222 is used to generate a second pre-charge signal when the first power input terminal 110 is powered on. The second switch unit 221 is connected to the second power input terminal 120 and the combined output terminal 300 respectively. The second switch unit 221 is used to maintain the conduction between the second power input terminal 120 and the combined output terminal 300 and to prevent the current of the combined output terminal 300 from flowing back to the second power input terminal 120.

[0064] The second control unit 223 is connected to the second pre-charge unit 222 and the second switch unit 221. The second control unit 223 is used to receive the second pre-charge signal and generate a second switch control signal according to the second pre-charge signal to ground the second power input terminal 120 and the combined output terminal 300.

[0065] In this embodiment, the second switch unit 221 is in a normally conducting state. Since the second switch unit 221 is located between the second power input terminal 120 and the combined output terminal 300, when no external voltage signal is connected, the combined output terminal 300 is connected to the second power input terminal 110, and the second power input terminal 120 provides a second power signal to the combined output terminal 300 to supply power to external devices.

[0066] When the first power input terminal 110 is connected to the first power signal, the second pre-charging unit 222 charges based on the first power signal and generates a second pre-charging signal. After a second preset time, the voltage of the second pre-charging signal reaches the second target voltage. At this time, the second control unit 223 controls the second switching unit 221 to turn off based on the second pre-charging signal of the second target voltage, and the second power input terminal 120 and the combined output terminal 300 are disconnected, thereby outputting the first power signal of the first power input terminal 110 to the combined output terminal 300, so as to achieve the purpose of switching to the first power input terminal 110 to supply power to external devices when the first power input terminal 110 is powered on.

[0067] In one embodiment, see Figure 3 As shown, the second pre-charge unit 222 includes: a first resistor R1, a first capacitor C1, and a first NMOS transistor N1.

[0068] Specifically, the gate of the first NMOS transistor N1 is connected to the first power input terminal 110, the drain of the first NMOS transistor N1, the first end of the first resistor R1, and the first end of the first capacitor C1 are all connected to the second control unit 223, the source of the first NMOS transistor N1 is grounded, and the second end of the first resistor R1 is connected to the second switching unit 221.

[0069] In this embodiment, the gate of the first NMOS transistor N1 can be directly connected to the first power input terminal 110, or it can be indirectly connected to the first power input terminal 110 through a voltage divider circuit. The voltage divider circuit divides the first power signal of the first power input terminal 110. When the first power input terminal 110 is powered on, the first NMOS transistor is turned on. The control terminal of the second control unit 223 is grounded. The first resistor R1 and the first capacitor C1 form an RC circuit. At this time, the second control unit 223 controls the MOS transistor in the second switching unit 221 to be turned off, and the second power input terminal 120 is disconnected from the combined output terminal 300.

[0070] In one embodiment, see Figure 3 As shown, the second switching unit 221 includes: a second PMOS transistor P2, a third PMOS transistor P3, and a second resistor R2.

[0071] Specifically, the drain of the second PMOS transistor P2 is connected to the second power input terminal 120, the source of the second PMOS transistor P2 and the source of the third PMOS transistor P3 are connected to the second control unit 223, the drain of the third PMOS transistor P3 is connected to the combined output terminal 300, the gate of the second PMOS transistor P2 and the gate of the third PMOS transistor P3 are connected to the first terminal of the second resistor R2, and the second terminal of the second resistor R2 is grounded.

[0072] In this embodiment, if the first PMOS transistor is turned on, the gate voltages of the second PMOS transistor P2 and the third PMOS transistor P3 are pulled up, and the second PMOS transistor P2 and the third PMOS transistor P3 are turned off. If the first PMOS transistor P1 is turned off, the gate voltages of the second PMOS transistor P2 and the third PMOS transistor P3 are pulled down, and the second PMOS transistor P2 and the third PMOS transistor P3 are turned on. In one embodiment, see... Figure 3 As shown, the second control unit 223 includes: a first PMOS transistor P1.

[0073] Specifically, the gate of the first PMOS transistor P1 is connected to the second precharge unit 222, the source of the first PMOS transistor P1 is connected to the second switch unit 221, the drain of the first PMOS transistor P1 is connected to the first end of the second resistor R2, and the second end of the second resistor R2 is grounded.

[0074] In this embodiment, after the first power input terminal 110 is powered on, the first capacitor C1 discharges, and the gate voltage of the first PMOS transistor is pulled down to a preset voltage within a second preset time. At this time, the first PMOS transistor is turned on, thereby controlling the second switching unit 221 to turn off. After the first power input terminal 110 is powered off, the first NMOS transistor N1 is turned off, and the gate voltage of the first PMOS transistor P1 is pulled up within a third preset time. The first PMOS transistor P1 is turned off, controlling the second switching unit 221 to turn on.

[0075] In one embodiment, see Figure 3 As shown, the first pre-charge unit 212 includes: a third resistor R3, a fourth resistor R4, a fifth resistor R5, a first diode D1, and a second capacitor C2.

[0076] Specifically, the first end of the third resistor R3 is connected to the first power input terminal 110, the second end of the third resistor R3, the first end of the fourth resistor R4, the first end of the fifth resistor R5 and the cathode of the first diode D1 are connected to the second pre-charge unit 222, the anode of the first diode D1, the second end of the fifth resistor R5 and the first end of the second capacitor C2 are connected to the first control unit 213, and the second end of the fourth resistor R4 and the second end of the second capacitor C2 are grounded.

[0077] In one embodiment, see Figure 3 As shown, the first control unit 213 includes: a second NMOS transistor N2 and a sixth resistor R6.

[0078] Specifically, the gate of the second NMOS transistor N2 is connected to the first precharge unit 212, the drain of the second NMOS transistor N2 and the first end of the sixth resistor R6 are connected to the first switch unit 211, the second end of the sixth resistor R6 is connected to the first switch unit 211, and the source of the second NMOS transistor N2 is grounded.

[0079] In one embodiment, see Figure 3 As shown, the first switching unit 211 includes a fourth PMOS transistor P4 and a fifth PMOS transistor P5.

[0080] In this embodiment, when the first power input terminal 110 is powered on, the voltage of the gate of the second NMOS transistor is pulled up to a high level, the second NMOS transistor is turned on, the gates of the fourth PMOS transistor and the fifth PMOS transistor are grounded, the fourth PMOS transistor and the fifth PMOS transistor are turned on, and at this time the first power input terminal 110 is connected to the combined output terminal 300.

[0081] Specifically, the drain of the fourth PMOS transistor P4 is connected to the first power input terminal 110, the source of the fourth PMOS transistor P4 and the source of the fifth PMOS transistor P5 are connected to the second terminal of the sixth resistor R6, and the gate of the fourth PMOS transistor P4 and the gate of the fifth PMOS transistor P5 are connected to the drain of the second NMOS transistor N2.

[0082] In practical applications, combined with Figure 3 To explain the principle, if the second power input 120 is connected to the battery and the first power input 110 is connected to the USB interface, when the battery is normally connected, the first power input 110 is inserted into the USB interface. At this time, the gate voltage of the first NMOS transistor N1 is VN1 = R4 * V_USB / (R3 + R4), where V_USB is the voltage of the first power signal connected to the first power input 110. The first NMOS transistor N1 is turned on, and the drain voltage of the first NMOS transistor N1 is pulled low, that is, the gate voltage of the first PMOS transistor P1 is 0V. The first PMOS transistor P1 is turned on, and the drain voltage of the first PMOS transistor P1 is pulled high, that is, the gate voltages of the second PMOS transistor P2 and the third PMOS transistor P3 are pulled high. At this time, the second PMOS transistor P2 and the third PMOS transistor P3 are turned off, and the battery power supply circuit is disconnected.

[0083] Since the gates of the first PMOS transistor P1 in the normally-on anti-backflow switch module 220 (battery output circuit) and the second NMOS transistor N2 in the normally-off anti-backflow switch module 210 (USB interface output circuit) are both designed with capacitor charging and discharging circuits, after the normally-on anti-backflow switch module 220 is quickly turned off, the gate voltage of the second NMOS transistor N2 in the normally-off anti-backflow switch module 210 is charged to VN2 = R4 * V_USB / (R3 + R4), and the second NMOS transistor N2 is turned on. The drain voltage of the second NMOS transistor N2 is pulled low, that is, the gate voltages of the fourth PMOS transistor P4 and the fifth PMOS transistor P5 are 0. At this time, the fourth PMOS transistor P4 is turned on by its body diode. The source voltages of the fourth PMOS transistor P4 and the fifth PMOS transistor P5 are equal to the power supply voltage of the USB interface. Therefore, the fifth PMOS transistor P5 is also turned on, and the USB channel provides normal power supply.

[0084] When the USB port is unplugged, the gate voltage of the second NMOS transistor N2 in the USB port path discharges rapidly through the diode, causing the second NMOS transistor N2 to turn off quickly. The drain voltage of the second NMOS transistor N2 is pulled high, which in turn pulls up the gate voltages of the fourth PMOS transistor P4 and the fifth PMOS transistor P5, turning them off. The USB port path is then turned off. At the same time, the gate voltage of the first NMOS transistor N1 in the battery port path is pulled low, turning it off. The drain voltage of the first NMOS transistor N1 is pulled high, which in turn pulls up the gate voltage of the first PMOS transistor P1, turning it off. The drain voltage of the first PMOS transistor P1 is pulled low, meaning the gate voltages of the second PMOS transistor P2 and the third PMOS transistor P3 are 0. The second PMOS transistor P2 turns on through its body diode. The source voltages of the second PMOS transistor P2 and the third PMOS transistor P3 are equal to the battery voltage, so the third PMOS transistor P3 also turns on, and the battery port path resumes normal power supply.

[0085] In one specific application embodiment, combined with Figure 4 As shown, the second pre-charge unit 222 includes: a seventh resistor R7, an eighth resistor R8, and a third NMOS transistor N3.

[0086] Specifically, the first end of the eighth resistor R8 is connected to the first power input terminal 110, the second end of the eighth resistor R8 is connected to the gate of the third NMOS transistor N3, the drain of the third NMOS transistor N3 and the first end of the seventh resistor R7 are connected to the gate of the first PMOS transistor P1, the second end of the seventh resistor R7 is connected to the source of the second PMOS transistor P2 and the third PMOS transistor P2, and the source of the third NMOS transistor N3 is grounded.

[0087] In this embodiment, the first end of the eighth resistor R8 is connected to the first power input terminal 110 and is used to receive the first power signal when the first power input terminal 110 is powered on. The gate of the third NMOS transistor N3 is turned on when the first power signal is connected and powered on. At this time, the seventh resistor R7 is grounded, the voltage of the gate of the first PMOS transistor P1 is pulled low, the first PMOS transistor P1 is turned on, the gate voltages of the second PMOS transistor P2 and the third PMOS transistor P3 are pulled up, the second PMOS transistor P2 and the third PMOS transistor P3 are turned off, and the first PMOS transistor P1 is turned off.

[0088] In one specific application embodiment, combined with Figure 5 As shown, the second switching unit 221 includes a sixth PMOS transistor P6 and a seventh PMOS transistor P7. The source of the sixth PMOS transistor P6 is connected to the second power input terminal 120, the drain of the sixth PMOS transistor P6 is connected to the drain of the seventh PMOS transistor P7, the source of the seventh PMOS transistor P7 is connected to the combined output terminal 300, the gate of the seventh PMOS transistor P7 is connected to the first power input terminal 110, and the gate of the sixth PMOS transistor P6 is connected to the second pre-charge unit 222.

[0089] In this embodiment, the drains of the sixth PMOS transistor P6 and the seventh PMOS transistor P7 are connected together. When the first power input terminal 110 is powered on, the voltage of the gate of the seventh PMOS transistor P7 is pulled up, and the seventh PMOS transistor P7 is turned off.

[0090] In one specific application embodiment, combined with Figure 5 As shown, the second control unit 223 includes: an eighth PMOS transistor P8, a fifth NMOS transistor N5, a tenth resistor R10, an eleventh resistor R11, and a third capacitor C3. Specifically, the source of the eighth PMOS transistor P8 is connected to the second power input terminal 120, and the gate of the eighth PMOS transistor P8 is connected to the second pre-charge unit 222. The drain of the eighth PMOS transistor P8, the first end of the tenth resistor R10, the first end of the eleventh resistor R11, and the first end of the third capacitor C3 are all connected to the gate of the sixth PMOS transistor P6. The second end of the third capacitor C3 is grounded. The second end of the eleventh resistor R11 is connected to the drain of the fifth NMOS transistor N5. The source of the fifth NMOS transistor N5 is grounded, and the gate of the fifth NMOS transistor N5 is connected to the second pre-charge unit 222.

[0091] In this embodiment, the eighth PMOS transistor P8, the fifth NMOS transistor N5, the tenth resistor R10, the eleventh resistor R11, and the third capacitor C3 form a switch control circuit. When the first power input terminal 110 is powered on, the gate voltage of the eighth PMOS transistor P8 and the gate voltage of the fifth NMOS transistor N5 are pulled down to a preset voltage (e.g., 0V) within a second preset time. At this time, the eighth PMOS transistor P8 is turned on and the fifth NMOS transistor N5 is turned off, thereby controlling the gate voltage of the sixth PMOS transistor to rise. When the gate voltage of the sixth PMOS transistor rises to its cutoff voltage, the sixth PMOS transistor is turned off. At this time, the second switch unit 221 is turned off. The third capacitor C3 is used as a charging and discharging device to determine that the gate voltage of the sixth PMOS transistor is pulled up to the cutoff voltage of the sixth PMOS transistor within a third preset time.

[0092] In one specific application embodiment, the gate of the seventh PMOS transistor P7 can be connected to the first terminal of the third capacitor C3 along with the gate of the sixth PMOS transistor.

[0093] In one specific application embodiment, combined with Figure 5 As shown, the second pre-charge unit 222 includes a fourth NMOS transistor N4 and a ninth resistor R9. Specifically, the gate of the fourth NMOS transistor N4 is connected to the first power input terminal, the source of the fourth NMOS transistor N4 is grounded, the drain of the fourth NMOS transistor N4 and the first end of the ninth resistor R9 are connected to the gate of the eighth PMOS transistor P8 and the gate of the fifth NMOS transistor N5, and the second end of the ninth resistor R9 is connected to the second power input terminal.

[0094] In one specific application embodiment, combined with Figure 6 As shown, the second control unit 223 includes a ninth PMOS transistor P9 and a twelfth resistor R12. Specifically, the gate of the ninth PMOS transistor P9 is connected to the first terminal of the ninth resistor R9, the source of the ninth PMOS transistor P9 is connected to the second power input terminal, the drain of the ninth PMOS transistor P9 and the first terminal of the twelfth resistor R12 are connected to the gate of the sixth PMOS transistor P6, and the second terminal of the twelfth resistor R12 is grounded.

[0095] In this embodiment, when the first power input terminal 110 is powered on, the gate voltage of the fourth NMOS transistor is pulled up to a high level, and the fourth NMOS transistor is turned on. At this time, the gate voltage of the ninth PMOS transistor P9 is pulled down to a low level, and the ninth PMOS transistor P9 is turned on. The second power input terminal 120 is electrically connected to the gate of the sixth PMOS transistor P6, and the gate voltage of the sixth PMOS transistor P6 is pulled up to a high level, and the sixth PMOS transistor P6 is turned off. The second switching unit 221 is turned off.

[0096] In one specific application embodiment, combined with Figure 7As shown, the first pre-charge unit 212 includes: a thirteenth resistor R13, a fourteenth resistor R14, and a fifteenth resistor R15. Specifically, the first end of the thirteenth resistor R13 is connected to the first power input terminal 110, the second end of the thirteenth resistor R13, the first end of the fourteenth resistor R14, and the first end of the fifteenth resistor R15 are all connected together, the second end of the fourteenth resistor R14 is grounded, and the second end of the fifteenth resistor R15 is connected to the gate of the second NMOS transistor.

[0097] In this embodiment, the thirteenth resistor R13, the fourteenth resistor R14, and the fifteenth resistor R15 form a voltage divider circuit. When the first power input terminal 110 is powered on, the gate voltage of the second NMOS transistor is pulled up to a high level, and the second NMOS transistor is turned on. The gates of the fourth PMOS transistor and the fifth PMOS transistor are grounded, and the fourth PMOS transistor and the fifth PMOS transistor are turned on. At this time, the first power input terminal 110 and the combined output terminal 300 are connected.

[0098] In one specific application embodiment, combined with Figure 8 As shown, the first switching unit 211 includes an eighth PMOS transistor P8, a ninth PMOS transistor P9, a sixteenth resistor R16, and a seventeenth resistor R17. Specifically, the first end of the sixteenth resistor R16 is connected to the source of the eighth PMOS transistor P8 and connected to the first power input terminal 110. The second end of the sixteenth resistor R16 is connected to the gate of the eighth PMOS transistor P8 and connected to the first pre-charge unit 212. The drain of the eighth PMOS transistor P8 is connected to the drain of the ninth PMOS transistor P9. The source of the ninth PMOS transistor P9 and the first end of the seventeenth resistor R17 are connected to the combined output terminal 300. The gate of the ninth PMOS transistor P9 and the second end of the seventeenth resistor R17 are connected to the first pre-charge unit 212.

[0099] In one specific application embodiment, combined with Figure 8 As shown, the first control unit 213 includes a sixth NMOS transistor N6 and a seventh NMOS transistor N7. Specifically, the drain of the sixth NMOS transistor N6 is connected to the gate of the eighth PMOS transistor P8, the drain of the seventh NMOS transistor N7 is connected to the gate of the ninth PMOS transistor P9, the source of the sixth PMOS transistor P6 is grounded, the source of the seventh NMOS transistor N7 is grounded, and the gates of the sixth NMOS transistor N6 and the seventh NMOS transistor N7 are connected to the second terminal of the fifteenth resistor R15.

[0100] In this embodiment, the gate of the eighth PMOS transistor P8 is connected to the first power input terminal 110 through the sixteenth resistor R16, and the gate of the ninth PMOS transistor P9 is connected to the combined output terminal 300 through the seventeenth resistor R17. When the first power input terminal 110 is powered on, the gate level of the eighth PMOS transistor P8 is pulled up to a high level, and the eighth PMOS transistor P8 is turned off. Only when the gate voltage of the sixth NMOS transistor N6 gradually rises to the turn-on voltage will the sixth NMOS transistor N6 turn on and ground the gate of the eighth PMOS transistor P8, thus turning on the eighth PMOS transistor P8. Similarly, only when the gate voltage of the seventh NMOS transistor N7 gradually rises to the turn-on voltage will the seventh NMOS transistor N7 turn on and ground the gate of the ninth PMOS transistor P9, thus turning on the ninth PMOS transistor P9. This application embodiment provides a power output device, which includes: an energy storage module, and a power output circuit as described in any of the above claims, connected to the energy storage module.

[0101] This application provides an intelligent door lock, including: a door lock body; and a power output circuit as described in any of the above claims, the power output circuit being used to supply power to the door lock body.

[0102] This application provides a power output circuit, a power output device, and a smart door lock. A first power input terminal receives a first power signal, and a second power input terminal receives a second power signal. A normally open anti-backflow switch module conducts for a first preset time when the first power input terminal receives the first power signal, outputting the first power signal to the combined output terminal. A normally closed anti-backflow switch module is turned off for a second preset time when the first power input terminal receives the first power signal, and remains open when the first power input terminal is powered off and the second power input terminal receives the second power signal, outputting the second power signal to the combined output terminal. By setting the first preset time to be greater than the second preset time, the on and off times of the two power signals are staggered, completely isolating the two power signals and preventing mutual interference, thus achieving stable power output.

[0103] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units and modules is merely an example. In practical applications, the above functions can be assigned to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiments can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit. Furthermore, the specific names of the functional units and modules are only for easy differentiation and are not intended to limit the scope of protection of this application. The specific working process of the units and modules in the above system can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0104] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0105] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0106] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0107] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A power supply output circuit, characterized by comprising: The power supply output circuit comprises: a first power supply input end for connecting a first power supply signal; a second power supply input end for connecting a second power supply signal; a combination output end; a normally-off anti-backflow switch module connected with the first power supply input end and the combination output end, for conducting in a first preset time when the first power supply input end connects the first power supply signal, so as to output the first power supply signal to the combination output end; a normally-on anti-backflow switch module connected with the first power supply input end and the second power supply input end, for being turned off in a second preset time when the first power supply input end connects the first power supply signal, and being kept on when the first power supply input end is powered off and the second power supply input end connects the second power supply signal, so as to output the second power supply signal to the combination output end; wherein the first preset time is greater than the second preset time; the normally-off anti-backflow switch module comprises: a first pre-charge unit connected with the first power supply input end, for generating a first pre-charge signal when the first power supply input end is powered on; a first switch unit connected with the first power supply input end and the combination output end, for keeping the first power supply input end and the combination output end off, and preventing the current of the combination output end from flowing back to the first power supply input end; a first control unit connected with the first pre-charge unit, for receiving the first pre-charge signal and generating a first switch control signal according to the first pre-charge signal; wherein the first switch unit is further used for controlling the first power supply input end and the combination output end to be on according to the first switch control signal; the normally-on anti-backflow switch module comprises: a second pre-charge unit connected with the first power supply input end, for generating a second pre-charge signal when the first power supply input end is powered on; a second switch unit connected with the second power supply input end and the combination output end, for keeping the second power supply input end and the combination output end on, and preventing the current of the combination output end from flowing back to the second power supply input end; a second control unit connected with the second pre-charge unit and the second switch unit, for receiving the second pre-charge signal and generating a second switch control signal according to the second pre-charge signal, so as to ground the second power supply input end and the combination output end.

2. The power supply output circuit according to claim 1, wherein The normally-on anti-backflow switch module is further used for conducting in a third preset time when the first power supply input end is powered off, so as to output the second power supply signal to the combination output end; the normally-off anti-backflow switch module is further used for being turned off in a fourth preset time when the first power supply input end is powered off; wherein the third preset time is greater than the fourth preset time.

3. The power supply output circuit of claim 1, wherein, The second pre-charge unit comprises: a first resistor, a first capacitor, and a first NMOS tube; The gate of the first NMOS tube is connected with the first power input end, the drain of the first NMOS tube, the first end of the first resistor and the first end of the first capacitor are commonly connected with the second control unit, the source of the first NMOS tube is grounded, and the second end of the first resistor is connected with the second switch unit.

4. The power supply output circuit of claim 1, wherein, The second switch unit comprises a second PMOS tube, a third PMOS tube and a second resistor. The drain of the second PMOS tube is connected with the second power input end, the source of the second PMOS tube and the source of the third PMOS tube are commonly connected with the second control unit, the drain of the third PMOS tube is connected with the combining output end, the gate of the second PMOS tube and the gate of the third PMOS tube are commonly connected with the first end of the second resistor, and the second end of the second resistor is grounded.

5. The power supply output circuit according to claim 4, wherein The second control unit comprises a first PMOS tube. The gate of the first PMOS tube is connected with the second pre-charging unit, the source of the first PMOS tube is connected with the second switch unit, and the drain of the first PMOS tube is connected with the first end of the second resistor.

6. The power supply output circuit of claim 1, wherein, The first switch unit comprises a fourth PMOS tube and a fifth PMOS tube. The drain of the fourth PMOS tube is connected with the first power input end, the source of the fourth PMOS tube and the source of the fifth PMOS tube are commonly connected with the first control unit, and the gate of the fourth PMOS tube and the gate of the fifth PMOS tube are commonly connected with the first control unit.

7. A power output device characterized by comprising: The power output device comprises: an energy storage module, and a power output circuit according to any one of claims 1-6, which is connected with the energy storage module.

8. A smart door lock comprising: a door lock body; and a power output circuit according to any one of claims 1-6, which is used for supplying power to the door lock body.

Images