High-voltage integrated circuit, counting method, and semiconductor circuit

Abstract

The present invention provides a high-voltage integrated circuit, a counting method and a semiconductor circuit. The high-voltage integrated circuit includes an over-current protection circuit and a driving circuit. The input end of the over-current protection circuit is used to receive an external current signal, and the output end of the over-current protection circuit is connected to the driving circuit. The over-current protection circuit is used to judge the current signal according to a preset judgment rule to generate an over-current signal. The preset judgment rule is whether the number of times the current value of the current signal is greater than a preset current threshold within a preset time period exceeds a preset value. If so, the output of the over-current protection circuit is turned off. If not, an over-current signal is generated. The over-current protection circuit includes a timer and a counter. The timer is used to set the preset time period, and the counter is used to set the preset value and count the number of times the current value of the current signal is greater than the preset current threshold. The driving circuit drives an external switching transistor according to the over-current signal. The technical solution of the present invention can filter interference signals and has high reliability.

Description

Technical Field

[0001] The present invention relates to the technical field of electronic circuits, and particularly to a high-voltage integrated circuit, a counting method, and a semiconductor circuit. Background Art

[0002] A high-voltage integrated circuit, namely HVIC (High Voltage Integrated Circuit), is an integrated circuit product used to convert MCU signals into drive signals for switching devices such as IGBTs. Generally, a high-voltage integrated circuit integrates basic devices such as various switching devices, diodes, voltage regulators, resistors, and capacitors to form a drive circuit, a pulse generation circuit, a delay circuit, a filtering circuit, an overcurrent protection circuit, an overheat protection circuit, an undervoltage protection circuit, a bootstrap circuit, etc. When the high-voltage integrated circuit is working, on the one hand, it receives the control signals of an external processor to drive the subsequent switching devices to work, and on the other hand, it also sends relevant working state detection signals back to the external processor to achieve the control of the circuit working conditions.

[0003] In the related art, an overcurrent protection circuit is integrated inside the high-voltage integrated circuit. In the event of various overcurrent situations, the circuit function of the overcurrent protection circuit is single, and it cannot flexibly exert the function of overcurrent protection. When the overcurrent signal reaches the threshold value, the overcurrent protection circuit enters the overcurrent protection function, and it cannot intelligently judge whether the overcurrent signal is a real overcurrent or an interference signal, which may cause the high-voltage integrated circuit to malfunction and affect its normal operation. Summary of the Invention

[0004] The purpose of the present invention is to provide a high-voltage integrated circuit for the deficiencies in the prior art, which can effectively filter interference signals and has high reliability.

[0005] To achieve this purpose, the present invention adopts the following technical solutions:

[0006] In the first aspect, the present invention provides a high-voltage integrated circuit, which includes an overcurrent protection circuit and a drive circuit; the input end of the overcurrent protection circuit is used to receive an external current signal, the output end of the overcurrent protection circuit is connected to the drive circuit, and the overcurrent protection circuit is used to judge the current signal according to a preset judgment rule to generate an overcurrent signal; wherein, the preset judgment rule is whether the number of current values of the current signal greater than a preset current threshold within a preset time period exceeds a preset value. If so, the output of the overcurrent protection circuit is turned off. If not, an overcurrent signal is generated; the overcurrent protection circuit includes a timer and a counter. The timer is used to set the preset time period, and the counter is used to set the preset value and count the number of current values of the current signal greater than the preset current threshold; the drive circuit drives an external switching device according to the overcurrent signal.

[0007] Further, the driving circuit includes a high-side driving circuit, an interlock circuit, and a low-side driving circuit, and the high-side driving circuit is connected to the low-side driving circuit through the interlock circuit.

[0008] Further, the high-side driving circuit has 3 channels. The high-side driving circuit includes a high-side undervoltage protection circuit and a bootstrap circuit. The high-side undervoltage protection circuit is used to implement the high-side driving undervoltage protection function, and the bootstrap circuit is used to implement the bootstrap power supply function; the low-side driving circuit has 3 channels.

[0009] Further, the high-voltage integrated circuit further includes an overvoltage protection circuit, an enable circuit, an overtemperature protection circuit, and an error reporting circuit;

[0010] The output end of the overcurrent protection circuit is connected to the first input end of the error reporting circuit;

[0011] The output end of the overvoltage protection circuit is connected to the second input end of the error reporting circuit;

[0012] The output end of the enable circuit is connected to the third input end of the error reporting circuit;

[0013] The output end of the overtemperature protection circuit is connected to the fourth input end of the error reporting circuit;

[0014] The first output end of the error reporting circuit is connected to the input end of the driving circuit;

[0015] The first output end of the error reporting circuit is used to connect to an external processor.

[0016] Further, the high-voltage integrated circuit further includes a power supply circuit, and the output end of the power supply circuit is connected to the input end of the overvoltage protection circuit.

[0017] Further, the overcurrent protection circuit further includes a first comparator, a first voltage-dividing resistor, a second voltage-dividing resistor, a third voltage-dividing resistor, an NMOS transistor, an OR gate, and a logic circuit,

[0018] The positive input end of the first comparator serves as the input end of the overcurrent protection circuit;

[0019] The negative input end of the first comparator is respectively connected to the second end of the first voltage-dividing resistor and the first end of the second voltage-dividing resistor;

[0020] The first end of the first voltage-dividing resistor is used to connect to a reference voltage. The second end of the second voltage-dividing resistor is respectively connected to the first end of the third voltage-dividing resistor and the drain of the NMOS transistor, and the second end of the third voltage-dividing resistor is connected to ground;

[0021] The gate of the NMOS transistor is connected to the signal control terminal of the logic circuit, and the source of the NMOS transistor is connected to the ground;

[0022] The output terminals of the first comparator are respectively connected to the first input terminal of the counter and the first input terminal of the OR gate;

[0023] The output terminal of the timer is connected to the second input terminal of the counter, and the output terminal of the counter is connected to the second input terminal of the OR gate;

[0024] The output terminal of the OR gate is connected to the input terminal of the logic circuit;

[0025] The output terminal of the logic circuit serves as the output terminal of the overcurrent protection circuit.

[0026] Further, the timer includes a pulse circuit, a first capacitor, a second capacitor, a third capacitor, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a diode, a second comparator, a third comparator, a first NAND gate, a second NAND gate, a third NAND gate, an inverter, and a bipolar junction transistor.

[0027] The output terminal of the pulse circuit is connected to the first end of the second capacitor;

[0028] The second end of the second capacitor is respectively connected to the positive electrode of the diode, the second end of the sixth resistor, and the positive electrode of the third comparator. The negative electrode of the diode and the first end of the sixth resistor are both connected to the power supply voltage;

[0029] The negative electrode of the third comparator is respectively connected to the second end of the second resistor and the first end of the third resistor. The second end of the third resistor is connected to the ground;

[0030] The output terminal of the third comparator is connected to the first input terminal of the second NAND gate;

[0031] The positive electrode of the second comparator is respectively connected to the second end of the first resistor, the first end of the second resistor, and the first end of the first capacitor. The first end of the first resistor is connected to the power supply voltage, and the second end of the first capacitor is connected to the ground;

[0032] The negative electrode of the second comparator is respectively connected to the second end of the fifth resistor, the first end of the third capacitor, and the collector of the bipolar junction transistor. The fifth resistor is connected to the power supply voltage. The second end of the third capacitor and the emitter of the bipolar junction transistor are both connected to the ground;

[0033] The base of the bipolar junction transistor is connected to the second end of the fourth resistor;

[0034] The output terminal of the second comparator is connected to the first input terminal of the first NAND gate;

[0035] The second input terminal of the first NAND gate is connected to the power supply voltage, and the third input terminal of the first NAND gate is respectively connected to the output terminal of the second NAND gate and the first input terminal of the third NAND gate;

[0036] The second input terminal of the third NAND gate is connected to the power supply voltage;

[0037] The output terminal of the first NAND gate is connected to the second input terminal of the second NAND gate;

[0038] The output terminal of the third NAND gate is respectively connected to the first end of the fourth resistor and the input terminal of the inverter, and the output terminal of the inverter serves as the output terminal of the timer.

[0039] Furthermore, the counter includes a time input circuit, a counting control circuit, a clearing circuit, a counting circuit, and a carry circuit.

[0040] The input terminal of the time input circuit serves as the time input terminal of the counter, the first output terminal of the time input circuit is connected to the input terminal of the counting control circuit, and the second output terminal of the time input circuit is connected to the input terminal of the clearing circuit;

[0041] The output terminal of the counting control circuit is connected to the first input terminal of the counting circuit, the output terminal of the clearing circuit is connected to the second input terminal of the counting circuit, and the third input terminal of the counting circuit serves as the signal input terminal to be counted of the counter;

[0042] The output terminal of the counting circuit is connected to the input terminal of the carry circuit;

[0043] The output terminal of the carry circuit serves as the output terminal of the counter.

[0044] In a second aspect, the present invention further provides a counting method, which is applied to the high-voltage integrated circuit provided by the present invention. The method includes the following steps:

[0045] Step S1, set the timing time in the time input circuit;

[0046] Step S2, start the counting control circuit and issue a start counting instruction;

[0047] Step S3, receive the signal to be counted into the counting circuit, and the counting circuit performs counting;

[0048] Step S4: Determine whether the counting circuit reaches a counting carry. If so, send a carry signal and proceed to Step S5; if not, return to Step S3.

[0049] Step S5: Clear the counting circuit and then return to Step S3.

[0050] In a third aspect, the present invention further provides a semiconductor circuit, which includes a switching transistor and the above-mentioned high-voltage integrated circuit provided by the present invention; the high-voltage integrated circuit is connected to the switching transistor, and the high-voltage integrated circuit is used to drive the switching transistor.

[0051] Advantages of the present invention: In the present invention, a timer and a counter are provided in the overcurrent protection circuit of the high-voltage integrated circuit. The timer is used to set the preset time period, the counter is used to set the preset count value and count the number of times the current value of the current signal is greater than the preset current threshold, and the overcurrent protection circuit judges the current signal according to the preset judgment rule to generate an overcurrent signal. This circuit setting enables the high-voltage integrated circuit to determine whether the current signal is a true overcurrent or a problem of interference signal. Thus, it avoids the triggering of the drive circuit caused by interference signals, thereby improving the reliability. Description of the Drawings

[0052] Figure 1 is the module structure diagram of the high-voltage integrated circuit provided by the embodiment of the present invention;

[0053] Figure 2 is the circuit schematic diagram of a specific implementation of the high-voltage integrated circuit provided by the embodiment of the present invention;

[0054] Figure 3 is the circuit schematic diagram of a specific implementation of the overcurrent protection circuit provided by the embodiment of the present invention;

[0055] Figure 4 is the circuit schematic diagram of the timer of the high-voltage integrated circuit provided by the embodiment of the present invention;

[0056] Figure 5 is Figure 4 the voltage-time relationship diagram of the timer in

[0057] Figure 6 is the module structure diagram of the counter of the high-voltage integrated circuit provided by the embodiment of the present invention;

[0058] Figure 7 is the flowchart of the counting method of the present invention;

[0059] Figure 8 is the structural schematic diagram of the semiconductor circuit provided by the embodiment of the present invention. Detailed Embodiments

[0060] The present invention will be described in detail below in conjunction with specific embodiments.

[0061] A high-voltage integrated circuit 100 of the present invention. Referring also to Figure 1-2 , Figure 1 is a module structure diagram of the high-voltage integrated circuit 100 provided by an embodiment of the present invention; Figure 2 is a circuit schematic diagram of a specific implementation of the high-voltage integrated circuit 100 provided by an embodiment of the present invention.

[0062] The high-voltage integrated circuit 100 includes an overcurrent protection circuit 10, a drive circuit 20, an overvoltage protection circuit 30, an enable circuit 40, an overtemperature protection circuit 50, an error reporting circuit 60, and a power supply circuit 70.

[0063] The circuit connection relationship of the high-voltage integrated circuit 100 is as follows:

[0064] The output end of the overcurrent protection circuit 10 is connected to the drive circuit 20. The output end of the overcurrent protection circuit 10 is connected to the first input end of the error reporting circuit 60. The output end of the overvoltage protection circuit 30 is connected to the second input end of the error reporting circuit 60. The output end of the enable circuit 40 is connected to the third input end of the error reporting circuit 60. The output end of the overtemperature protection circuit 50 is connected to the fourth input end of the error reporting circuit 60. The first output end of the error reporting circuit 60 is connected to the input end of the drive circuit 20. The first output end of the error reporting circuit 60 is used to connect to an external processor. The output end of the power supply circuit 70 is connected to the input end of the overvoltage protection circuit 30. Among them,

[0065] The power supply circuit 70 includes a 5V LDO circuit and a 1.2V BANDGAP circuit, which supply 5V power and 15V voltage to all internal circuits of the HVIC and supply external 5V power, and provide a stable 1.2V voltage reference for the HVIC and external circuits.

[0066] The input end of the overcurrent protection circuit 10 is used to receive an external current signal ITRIP, and the overcurrent protection circuit 10 is used to judge the current signal ITRIP according to a preset judgment rule to generate an overcurrent signal. Among them, the preset judgment rule is whether the number of times the current value of the current signal ITRIP is greater than a preset current threshold within a preset time period exceeds a preset value. If so, the overcurrent protection circuit 10 outputs a shutdown. If not, an overcurrent signal is generated.

[0067] Referring to Figure 3 , Figure 3It is a circuit schematic diagram of a specific implementation of the overcurrent protection circuit 10 provided by an embodiment of the present invention. Specifically, the overcurrent protection circuit 10 includes a timer 101, a counter 102, a first comparator CMP, a first voltage-dividing resistor RV1, a second voltage-dividing resistor RV2, a third voltage-dividing resistor RV3, an NMOS transistor Q1, an OR gate OR, and a logic circuit 103.

[0068] The circuit connection relationship of the overcurrent protection circuit 10 is as follows:

[0069] The positive input terminal of the first comparator CMP serves as the input terminal of the overcurrent protection circuit 10.

[0070] The negative input terminal of the first comparator CMP is respectively connected to the second terminal of the first voltage-dividing resistor RV1 and the first terminal of the second voltage-dividing resistor RV2.

[0071] The first terminal of the first voltage-dividing resistor RV1 is used to connect to a reference voltage of 620. The second terminal of the second voltage-dividing resistor RV2 is respectively connected to the first terminal of the third voltage-dividing resistor RV3 and the drain of the NMOS transistor Q1. The second terminal of the third voltage-dividing resistor RV3 is connected to the ground GND.

[0072] The gate of the NMOS transistor Q1 is connected to the signal control terminal of the logic circuit 103, and the source of the NMOS transistor Q1 is connected to the ground GND.

[0073] The output terminal of the first comparator CMP is respectively connected to the first input terminal of the counter 102 and the first input terminal of the OR gate OR.

[0074] The output terminal of the timer 101 is connected to the second input terminal of the counter 102, and the output terminal of the counter 102 is connected to the second input terminal of the OR gate OR.

[0075] The output terminal of the OR gate OR is connected to the input terminal of the logic circuit 103.

[0076] The output terminal of the logic circuit 103 serves as the output terminal of the overcurrent protection circuit 10.

[0077] The working principle of the overcurrent protection circuit 10 is as follows: The timer 101 sets an M time. When the current signal ITRIP exceeds the voltage signal at the voltage dividing point 0504 N times within this M time, that is, when the counter 102 counts that there are N times the current signal ITRIP exceeds the voltage signal at the voltage dividing point (the connection point of the second voltage dividing resistor RV2 and the third voltage dividing resistor RV3) within the M time, the carry output port of the counter 102 outputs a high potential. At this time, the output end of the time comparison is at a low potential, and the output port of the OR gate OR outputs a high potential to shield the current signal ITRIP. The logic circuit 103 will consider that there is no overcurrent phenomenon in the application circuit of the high-voltage integrated circuit 100 (or it is said that the current signal ITRIP at present is an interference signal and overcurrent protection is not required), and the high-voltage integrated circuit 100 continues to work normally. At the same time, when the counter 102 starts to clear, it will also clear the N times of signals recorded in the count, and the timer 101 will also start a new timing and repeat the work.

[0078] Within this M time, when the current signal ITRIP exceeds the voltage signal at the voltage dividing point less than N times, that is, when the counter 102 counts that the current signal ITRIP exceeds the voltage signal at the voltage dividing point less than N times within the M time, the carry output port of the counter 102 outputs a low potential. When the current signal ITRIP exceeds the threshold value, the comparator CMP outputs a low potential, and the output port of the OR gate OR outputs a low potential, entering the overcurrent protection; when the current signal ITRIP does not exceed the threshold value, the comparator CMP outputs a high potential, and the output port of the OR gate OR outputs a high potential, and the high-voltage integrated circuit 100 works normally.

[0079] See Figure 4 , Figure 4 is the circuit schematic diagram of the timer 101 of the high-voltage integrated circuit 100 provided by the embodiment of the present invention.

[0080] The timer 101 is used to set the preset time period.

[0081] Specifically, the timer 101 includes a pulse circuit 101a, a first capacitor C1, a second capacitor C2, a third capacitor C3, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a diode D1, a second comparator A1, a third comparator A2, a first NAND gate G1, a second NAND gate G2, a third NAND gate G3, an inverter G4, and a bipolar junction transistor Q2.

[0082] The circuit connection relationship of the timer 101 is as follows:

[0083] The output end of the pulse circuit 101a is connected to the first end of the second capacitor C2.

[0084] The second terminal of the second capacitor C2 is respectively connected to the positive terminal of the diode D1, the second terminal of the sixth resistor R6, and the positive terminal of the third comparator A2. The negative terminal of the diode D1 and the first terminal of the sixth resistor R6 are both connected to the power supply voltage.

[0085] The negative terminal of the third comparator A2 is respectively connected to the second terminal of the second resistor R2 and the first terminal of the third resistor R3. The second terminal of the third resistor R3 is connected to the ground GND.

[0086] The output terminal of the third comparator A2 is connected to the first input terminal of the second NAND gate G2.

[0087] The positive terminal of the second comparator A1 is respectively connected to the second terminal of the first resistor R1, the first terminal of the second resistor R2, and the first terminal of the first capacitor C1. The first terminal of the first resistor R1 is connected to the power supply voltage. The second terminal of the first capacitor C1 is connected to the ground GND.

[0088] The negative terminal of the second comparator A1 is respectively connected to the second terminal of the fifth resistor R5, the first terminal of the third capacitor C3, and the collector of the bipolar junction transistor Q2. The fifth resistor R5 is connected to the power supply voltage. The second terminal of the third capacitor C3 and the emitter of the bipolar junction transistor Q2 are both connected to the ground GND.

[0089] The base of the bipolar junction transistor Q2 is connected to the second terminal of the fourth resistor R4.

[0090] The output terminal of the second comparator A1 is connected to the first input terminal of the first NAND gate G1.

[0091] The second input terminal of the first NAND gate G1 is connected to the power supply voltage. The third input terminal of the first NAND gate G1 is respectively connected to the output terminal of the second NAND gate G2 and the first input terminal of the third NAND gate G3.

[0092] The second input terminal of the third NAND gate G3 is connected to the power supply voltage.

[0093] The output terminal of the first NAND gate G1 is connected to the second input terminal of the second NAND gate G2.

[0094] The output terminal of the third NAND gate G3 is respectively connected to the first terminal of the fourth resistor R4 and the input terminal of the inverter G4. The output terminal of the inverter G4 serves as the output terminal of the timer 101.

[0095] The working principle of the timer 101 is as follows:

[0096] The diode D1 is a clamping diode. In the steady state, the input end of the circuit is at the power supply level and discharges internally. The bipolar junction transistor Q2 is a switching MOS transistor. When the bipolar junction transistor Q2 conducts, the output end Vo outputs a low level. When the pulse circuit 101a outputs a pulse signal and makes the potential of V1 instantaneously lower than 1 / 3Vcc, the low-level comparator operates, and the monostable circuit starts a steady-state process. The second capacitor C2 starts to charge, and Vc increases according to an exponential law. When Vc charges to 2 / 3Vcc, the high-level comparator operates, the second comparator A1 flips, the output Vo returns from a high level to a low level, the bipolar junction transistor Q2 conducts again, and the charge on the second capacitor C2 quickly discharges through the bipolar junction transistor Q2. The transient state ends and returns to stability, preparing for the arrival of the next trigger pulse.

[0097] Refer to Figure 5 , Figure 5 is Figure 4 the voltage-time relationship diagram of the timer 101 during operation. The duration Tw of the quasi-steady state of the timer 101 (i.e., the delay time) is determined by the magnitudes of the resistor R and the capacitor C in the external components. Tw = 1.1RC. By changing the magnitudes of the resistor R and the capacitor C, the delay time can be varied between several microseconds and dozens of minutes.

[0098] The counter 102 is used to set the preset value and count the number of times the current value of the current signal ITRIP is greater than the preset current threshold.

[0099] Refer to Figure 6 , Figure 6 is the module structure diagram of the counter 102 of the high-voltage integrated circuit 100 provided by the embodiment of the present invention.

[0100] Specifically, the counter 102 includes a time input circuit 1021, a counting control circuit 1022, a clearing circuit 1023, a counting circuit 1024, and a carry circuit 1025.

[0101] The input end of the time input circuit 1021 serves as the time input end TIN of the counter 102. The first output end of the time input circuit 1021 is connected to the input end of the counting control circuit 1022, and the second output end of the time input circuit 1021 is connected to the input end of the clearing circuit 1023.

[0102] The output end of the counting control circuit 1022 is connected to the first input end of the counting circuit 1024. The output end of the clearing circuit 1023 is connected to the second input end of the counting circuit 1024. The third input end of the counting circuit 1024 serves as the counted signal input end IN of the counter 102.

[0103] The output terminal of the counting circuit 1024 is connected to the input terminal of the carry circuit 1025.

[0104] The output terminal of the carry circuit 1025 serves as the output terminal OUT1 of the counter 102.

[0105] The working process of the counter 102 is as follows:

[0106] The time input circuit 1021 receives the timing signal from TIN. The time input circuit 1021 notifies that the counting control circuit 1022 starts counting until the required carry output is reached. After completing a cycle of counting, the clearing circuit 1023 clears the counting circuit 1024 and the carry circuit 1025 to prepare for the next counting.

[0107] The driving circuit 20 drives an external switching transistor according to the overcurrent signal.

[0108] The driving circuit 20 includes a high-side driving circuit 201, an interlock circuit 202, and a low-side driving circuit 203. The high-side driving circuit 201 is connected through the interlock circuit 202 and the low-side driving circuit 203.

[0109] In this embodiment, the high-side driving circuit 201 has 3 channels. The high-side driving circuit 201 includes a high-side undervoltage protection circuit 201a and a bootstrap circuit 201b. The high-side undervoltage protection circuit 201a is used to implement the high-side driving undervoltage protection function. The bootstrap circuit 201b is used to implement the bootstrap power supply function. The low-side driving circuit 203 has 3 channels.

[0110] The present invention also provides a counting method, which is applied to the high-voltage integrated circuit 100 and specifically applied to the counter 102.

[0111] Refer to Figure 7 , Figure 7 which is the flowchart of the counting method of the present invention.

[0112] Specifically, the counting method includes the following steps:

[0113] Step S1: Set the timing time in the time input circuit 1021.

[0114] Step S2: Start the counting control circuit 1022 and issue a start counting instruction.

[0115] Step S3: Receive the signal to be counted into the counting circuit 1024, and the counting circuit 1024 performs counting.

[0116] Step S4: Determine whether the counting circuit 1024 reaches the counting carry. If so, send a carry signal and proceed to step S5; if not, return to the said step S3.

[0117] Step S5: Clear the counting circuit 1024 and then return to the said step S3.

[0118] The present invention also provides a semiconductor circuit 300.

[0119] Refer to Figure 8 , Figure 8 which is the structural schematic diagram of the semiconductor circuit provided by the embodiment of the present invention.

[0120] The semiconductor circuit 300 includes a switching transistor 200 and the high-voltage integrated circuit 100 as described above. The high-voltage integrated circuit 100 is connected to the switching transistor 200, and the high-voltage integrated circuit 100 is used to drive the switching transistor 200.

[0121] It can be understood that the content in the above embodiments of the high-voltage integrated circuit is applicable to the embodiment of this semiconductor circuit 300. The functions specifically implemented by the embodiment of this semiconductor circuit 300 are the same as those of the above embodiment of the high-voltage integrated circuit 100, and the beneficial effects achieved are also the same as those of the above embodiment of the high-voltage integrated circuit 100.

[0122] In the present invention, a timer 101 and a counter 102 are provided in the overcurrent protection circuit 10 of the high-voltage integrated circuit 100. The timer 101 is used to set the preset time period, the counter 102 is used to set the preset count value and count the number of times the current value of the current signal is greater than the preset current threshold, and the overcurrent protection circuit 10 judges the current signal according to a preset judgment rule to generate an overcurrent signal. This circuit setting enables the high-voltage integrated circuit 100 to determine whether the current signal is a real overcurrent or a problem of interference signal. Thus, it avoids the triggering of the drive circuit 20 caused by interference signals, thereby improving the reliability.

[0123] The above content is only a preferred embodiment of the present invention. For those of ordinary skill in the art, according to the idea of the present invention, there will be changes in the specific implementation manners and application scopes. The content of this specification should not be construed as a limitation to the present invention.

Claims

1. A high-voltage integrated circuit, characterized in that, The high-voltage integrated circuit includes an overcurrent protection circuit and a drive circuit; The input end of the overcurrent protection circuit is used to receive an external current signal, the output end of the overcurrent protection circuit is connected to the drive circuit, and the overcurrent protection circuit is used to judge the current signal according to a preset judgment rule to generate an overcurrent signal; wherein, the preset judgment rule is whether the number of current values of the current signal greater than a preset current threshold within a preset time period exceeds a preset value. If so, the output of the overcurrent protection circuit is turned off. If not, an overcurrent signal is generated; The overcurrent protection circuit includes a timer and a counter. The timer is used to set the preset time period, and the counter is used to set the preset value and count the number of current values of the current signal greater than the preset current threshold; The drive circuit drives an external switching transistor according to the overcurrent signal; The overcurrent protection circuit further includes a first comparator, a first voltage-dividing resistor, a second voltage-dividing resistor, a third voltage-dividing resistor, an NMOS transistor, an OR gate, and a logic circuit, The positive input end of the first comparator serves as the input end of the overcurrent protection circuit; The negative input end of the first comparator is respectively connected to the second end of the first voltage-dividing resistor and the first end of the second voltage-dividing resistor; The first end of the first voltage-dividing resistor is used to connect to a reference voltage. The second end of the second voltage-dividing resistor is respectively connected to the first end of the third voltage-dividing resistor and the drain of the NMOS transistor. The second end of the third voltage-dividing resistor is connected to the ground; The gate of the NMOS transistor is connected to the signal control end of the logic circuit, and the source of the NMOS transistor is connected to the ground; The output end of the first comparator is respectively connected to the first input end of the counter and the first input end of the OR gate; The output end of the timer is connected to the second input end of the counter, and the output end of the counter is connected to the second input end of the OR gate; The output end of the OR gate is connected to the input end of the logic circuit; The output end of the logic circuit serves as the output end of the overcurrent protection circuit.

2. The high-voltage integrated circuit according to claim 1, wherein The drive circuit includes a high-side drive circuit, an interlock circuit, and a low-side drive circuit. The high-side drive circuit is connected through the interlock circuit and the low-side drive circuit.

3. The high-voltage integrated circuit according to claim 2, characterized in that, The high-side drive circuit has 3 channels. The high-side drive circuit includes a high-side undervoltage protection circuit and a bootstrap circuit. The high-side undervoltage protection circuit is used to implement the high-side drive undervoltage protection function, and the bootstrap circuit is used to implement the bootstrap power supply function; the low-side drive circuit has 3 channels.

4. The high-voltage integrated circuit according to claim 1, wherein The high-voltage integrated circuit further includes an overvoltage protection circuit, an enable circuit, an overtemperature protection circuit, and an error reporting circuit; The output end of the overcurrent protection circuit is connected to the first input end of the error reporting circuit; The output end of the overvoltage protection circuit is connected to the second input end of the error reporting circuit; The output end of the enable circuit is connected to the third input end of the error reporting circuit; The output end of the overtemperature protection circuit is connected to the fourth input end of the error reporting circuit; The first output end of the error reporting circuit is connected to the input end of the drive circuit; The first output terminal of the error reporting circuit is used to connect to an external processor.

5. The high-voltage integrated circuit according to claim 4, wherein The high-voltage integrated circuit further includes a power supply circuit, and the output terminal of the power supply circuit is connected to the input terminal of the overvoltage protection circuit.

6. The high-voltage integrated circuit according to claim 1, characterized in that, The timer includes a pulse circuit, a first capacitor, a second capacitor, a third capacitor, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a diode, a second comparator, a third comparator, a first NAND gate, a second NAND gate, a third NAND gate, an inverter, and a bipolar junction transistor. The output terminal of the pulse circuit is connected to the first terminal of the second capacitor. The second terminal of the second capacitor is respectively connected to the positive terminal of the diode, the second terminal of the sixth resistor, and the positive terminal of the third comparator. The negative terminal of the diode and the first terminal of the sixth resistor are both connected to the power supply voltage. The negative terminal of the third comparator is respectively connected to the second terminal of the second resistor and the first terminal of the third resistor. The second terminal of the third resistor is connected to ground. The output terminal of the third comparator is connected to the first input terminal of the second NAND gate. The positive terminal of the second comparator is respectively connected to the second terminal of the first resistor, the first terminal of the second resistor, and the first terminal of the first capacitor. The first terminal of the first resistor is connected to the power supply voltage. The second terminal of the first capacitor is connected to ground. The negative terminal of the second comparator is respectively connected to the second terminal of the fifth resistor, the first terminal of the third capacitor, and the collector of the bipolar junction transistor. The fifth resistor is connected to the power supply voltage. The second terminal of the third capacitor and the emitter of the bipolar junction transistor are both connected to ground. The base of the bipolar junction transistor is connected to the second terminal of the fourth resistor. The output terminal of the second comparator is connected to the first input terminal of the first NAND gate. The second input terminal of the first NAND gate is connected to the power supply voltage. The third input terminal of the first NAND gate is respectively connected to the output terminal of the second NAND gate and the first input terminal of the third NAND gate. The second input terminal of the third NAND gate is connected to the power supply voltage. The output terminal of the first NAND gate is connected to the second input terminal of the second NAND gate. The output terminal of the third NAND gate is respectively connected to the first terminal of the fourth resistor and the input terminal of the inverter. The output terminal of the inverter serves as the output terminal of the timer.

7. The high-voltage integrated circuit according to claim 1, wherein The counter includes a time input circuit, a counting control circuit, a clearing circuit, a counting circuit, and a carry circuit. The input terminal of the time input circuit serves as the time input terminal of the counter. The first output terminal of the time input circuit is connected to the input terminal of the counting control circuit. The second output terminal of the time input circuit is connected to the input terminal of the clearing circuit. The output terminal of the counting control circuit is connected to the first input terminal of the counting circuit. The output terminal of the clearing circuit is connected to the second input terminal of the counting circuit. The third input terminal of the counting circuit serves as the input terminal of the signal to be counted of the counter. The output terminal of the counting circuit is connected to the input terminal of the carry circuit. The output terminal of the carry circuit serves as the output terminal of the counter.

8. A counting method, characterized in that, The counting method is applied to the high-voltage integrated circuit as described in claim 7, and the method includes the following steps: Step S1: Set the timing time in the time input circuit; Step S2: Start the counting control circuit and issue a start counting instruction; Step S3: Receive the signal to be counted into the counting circuit, and the counting circuit performs counting; Step S4: Determine whether the counting circuit reaches the counting carry. If so, issue a carry signal and proceed to step S5. If not, return to step S3; Step S5: Clear the counting circuit and then return to step S3.

9. A semiconductor circuit, characterized in that, The semiconductor circuit includes a switching transistor and the high-voltage integrated circuit as described in any one of claims 1-7; the high-voltage integrated circuit is connected to the switching transistor, and the high-voltage integrated circuit is used to drive the switching transistor.

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