Low complexity multi-ary LDPC check node update method for fifo architecture

Abstract

The application provides a low-complexity multi-ary LDPC check node update method of FIFO architecture, which comprises the following steps: obtaining check node input data, processing the input data to obtain an extended sum matrix and a matrix, the input data being two groups of log-likelihood values and Galois field numbers in ascending order with a length of N; dividing the extended sum matrix and the matrix into four regions; storing the four regions into first-in-first-out memories (FIFOs) respectively, and directly connecting FIFO ports with value comparators; configuring a 1-bit register as a flag bit for each FIFO, using the flag bit register to control the reading of the FIFO to enter the value comparator for comparison, retaining the current minimum value, and updating the flag bit register; and repeating the operation until N minimum log-likelihood values without repetition are obtained. 2 ) to O(N 2 ) in space complexity. The application has important value for promoting the wide application of high-throughput and low-resource multi-ary LDPC decoders.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of high-performance communication channel coding and decoding, and in particular to a method for updating check nodes of a multi-ary LDPC based on a FIFO structure. BACKGROUND

[0002] Binary LDPC codes are widely used due to their close-to-Shannon-limit coding efficiency, low encoding and decoding complexity, and low performance and power consumption requirements for chips. However, in the free-space laser communication scenario, errors generated in the middle are often bursty, so the channel code not only needs good error correction capability, but also needs burst error resistance. Related studies have shown that multi-ary LDPC can combine multiple errors into fewer symbol errors, has significantly improved burst error resistance and stronger error correction capability, but the decoding complexity of multi-ary LDPC is much higher than that of binary LDPC, which is not conducive to high throughput and occupies too much hardware resources, so it is difficult to promote in practical applications.

[0003] The multi-ary LDPC decoder generally uses the extended minimum sum (EMS) algorithm, and the most complex part of the algorithm is the check node update link, which needs to sort all the extended sums and select a certain number of minimum values. The existing sorting algorithm can use the temporary addition method to obtain the data to be sorted to save storage resources, but this will cause the throughput to decrease; or the matrix after addition is stored in the register in advance to save clock ticks, but this will consume a large amount of storage resources; therefore, there is a defect that the throughput and storage resources are mutually restricted, which is not conducive to hardware implementation. SUMMARY

[0004] The present application aims to at least solve one of the technical problems in the related art to some extent.

[0005] To this end, a first object of the present application is to provide a low-complexity multi-ary LDPC check node update method based on a FIFO architecture, which overcomes the defect that the throughput and storage resources are mutually restricted.

[0006] A second object of the present application is to provide a low-complexity multi-ary LDPC check node update device based on a FIFO architecture.

[0007] To achieve the above object, a low-complexity multi-ary LDPC check node update method based on a FIFO architecture is provided in an embodiment of the first aspect of the present application, comprising:

[0008] obtaining check node input data, processing the input data to obtain an extended sum matrix, the input data being two groups of log-likelihood values and Galois field numbers arranged in ascending order with a length of N;

[0009] The extension and matrix are divided into four regions;

[0010] The four regions are respectively stored in first-in first-out memories (FIFOs), and the FIFO ports are directly connected with the value comparator ports;

[0011] A register with a size of 1 bit is configured as a flag bit for each FIFO, the flag bit register is used to control the FIFO reading to enter the value comparator for comparison, to reserve the current minimum value, and to update the flag bit register; the operation is repeated until N Galois field numbers without repetition are obtained. In addition, the low-complexity multi-ary LDPC check node updating method based on the FIFO architecture according to the above embodiment of the application can further have the following additional technical features:

[0012] Further, in an embodiment of the application, the extension and matrix are represented as:

[0013]

[0014] Each extension and matrix element SD x,y includes two parts of data, an addition result s x,y and an exclusive OR result d x,y , wherein, s x,y = U x + V y , represents bit-by-bit exclusive OR, + represents decimal addition, (UB, U) and (VB, V) are two groups of input data with a length of N of the check node updating module, U and V are two groups of log-likelihood values arranged in ascending order, and UB and VB are two groups of Galois field numbers irrelevant to the value size.

[0015] Further, in an embodiment of the application, the extension and matrix are divided into four regions, including:

[0016] The four regions are M1, M2, M3 and M4, the division criteria are M1 = {M | 0 ≤ x ≤ n-1, 0 ≤ y ≤ n-1}, M2 = {M | n ≤ x ≤ N-1, 0 ≤ y ≤ n-1}, M3 = {M | 0 ≤ x ≤ n-1, n ≤ y ≤ N-1}, and M4 = {M | n ≤ x ≤ N-1, n ≤ y ≤ N-1}, n is a region division boundary value, the symbol represents upward rounding.

[0017] Further, in an embodiment of the application, the storing of the four regions into FIFOs includes:

[0018] Discard M4 region, store {M1, M2} and {M1, M3} into n FIFOs respectively, the FIFO depth is N.

[0019] Further, in one embodiment of the present application, the FIFO flag bit controls the FIFO reading into the comparator, including:

[0020] Update the FIFO flag bit xf x and yf y When the current minimum value coordinate is (x, y), the second minimum value coordinate can be (x+1, y) and (x, y+1), wherein the update flag bit step is as follows:

[0021] If xf x+1 =1, yf y+1 =1, then xf x =0, yf y =0, and no FIFO is read;

[0022] If xf x+1 =1, yf y+1 =0, then yf y =0, yf y+1 =1, and the FIFO containing the (x, y+1) position data is read;

[0023] If xf x+1 =0, yf y+1 =1, then xf x =0, xf x+1 =1, and the FIFO containing the (x+1, y) position data is read;

[0024] If xf x+1 =0, yf y+1 =0, then xf x+1 =1, yf y+1 =1, and the FIFO containing the (x+1, y) and (x, y+1) position data is read;

[0025] The specific way of the flag bit register controlling the FIFO reading is that when the flag bit register is 1, the FIFO corresponding to the coordinate is read, otherwise it is not read.

[0026] Further, in one embodiment of the present application, it further includes:

[0027] Each FIFO reading port is configured with a register, and the FIFO stores the original port data in the register after reading out one number; when the value comparator selects the data to be compared, if the flag register is 1, the data on the FIFO reading port is selected; if the flag register is 0, the data in the cache register of the FIFO reading port is selected.

[0028] Further, in one embodiment of the present application, further comprising:

[0029] If the currently read data coordinate belongs to the M1 region, the two FIFOs corresponding to the coordinate are read simultaneously; if the currently read data coordinate belongs to the M2 region, only the FIFO storing the data of the {M1, M2} region corresponding to the coordinate is read; if the currently read data coordinate belongs to the M3 region, only the FIFO storing the data of the {M1, M3} region corresponding to the coordinate is read.

[0030] To achieve the above object, the second aspect of the present application provides a low-complexity multi-ary LDPC check node update device with FIFO architecture, characterized in that it comprises the following modules:

[0031] The acquisition module is configured to acquire check node input data, and process the input data to obtain an extended and matrix, wherein the input data is two groups of log-likelihood values and Galois field numbers arranged in ascending order with a length of N;

[0032] The division module is configured to divide the extended and matrix into four regions;

[0033] The storage module is configured to store the four regions into FIFOs respectively, and directly connect the FIFO ports with the value comparator ports;

[0034] The comparison module is configured to configure a 1-bit register as a flag for each FIFO, control the FIFO reading data to enter the value comparator for comparison by using the flag register, retain the current minimum value, and update the flag register; and repeat the operation until N Galois field numbers of the minimum log-likelihood values are obtained without repetition.

[0035] The low-complexity multi-ary LDPC check node update method with FIFO architecture provided by the present application utilizes the feature that smaller values are concentrated in the upper left corner region of the extended and matrix, adopts FIFO storage to store the row and column data related to the upper left corner region for subsequent sorting, reduces the storage resources; adopts a specific data space of the FIFO output port to extract the minimum value, reduces the calculation complexity of sorting, and saves the calculation resources. Compared with the classic bubble algorithm, the time complexity is reduced from O(N 2 ) to O(N The space complexity is reduced from O(N2 ) falls to It is of great value to promote the wide application of the high-throughput and low-resource multi-ary LDPC decoder. BRIEF DESCRIPTION OF DRAWINGS

[0036] The above and / or additional aspects and advantages of the present application will become apparent and be readily understood from the following description, taken in conjunction with the accompanying drawings, in which:

[0037] Figure 1 A flowchart of a low-complexity multi-ary LDPC check node update method of a FIFO architecture provided by an embodiment of the present application.

[0038] Figure 2 A schematic diagram of the overall structure of the low-complexity multi-ary LDPC check node update method of a FIFO architecture provided by an embodiment of the present application.

[0039] Figure 3 A schematic diagram of the hardware structure of the check node update method provided by an embodiment of the present application.

[0040] Figure 4 A schematic diagram of the flag filtering principle provided by an embodiment of the present application.

[0041] Figure 5 A flowchart of a low-complexity multi-ary LDPC check node update device of a FIFO architecture provided by an embodiment of the present application. DETAILED DESCRIPTION

[0042] Embodiments of the present application are described in detail below with reference to examples illustrated in the accompanying drawings, in which the same or similar reference numerals are used throughout to represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to explain the present application, and should not be understood as limiting the present application.

[0043] The low-complexity multi-ary LDPC check node update method and device of a FIFO architecture of an embodiment of the present application are described below with reference to the accompanying drawings.

[0044] Figure 1 A flowchart of a low-complexity multi-ary LDPC check node update method of a FIFO architecture provided by an embodiment of the present application.

[0045] As shown in the flowchart, the low-complexity multi-ary LDPC check node update method of a FIFO architecture includes the following steps: Figure 1

[0046] ​S101: Obtain check node input data, process the input data to obtain a syndrome matrix and a parity check matrix, the input data being two groups of log-likelihood ratios and Galois field numbers in ascending order with a length of N;

[0047] S102: Divide the syndrome matrix and the parity check matrix into four regions;

[0048] S103: Store the four regions in first-in-first-out memories (FIFOs) respectively, and directly connect FIFO ports with a value comparator port;

[0049] S104: Configure a 1-bit register as a flag bit for each FIFO, control the reading of the FIFO into the value comparator for comparison by using the flag bit register, reserve the current minimum value, and update the flag bit register; repeat the operation until N Galois field numbers of minimum log-likelihood values are obtained without repetition.

[0050] Further, in an embodiment of the present application, the syndrome matrix and the parity check matrix are represented as:

[0051]

[0052] Each element SD of the syndrome matrix and the parity check matrix x,y includes two parts of data, an addition result s x,y and an exclusive OR result d x,y , wherein, s x,y = U x + V y , represents bit-by-bit exclusive OR, + represents decimal addition, (UB, U) and (VB, V) are two groups of input data of the check node update module with a length of N, U and V are two groups of log-likelihood values in ascending order, and UB and VB are two groups of Galois field numbers irrelevant to the value size.

[0053] Figure 2 FIG. 1 is a schematic diagram of the overall structure of a low-complexity multi-ary LDPC check node update method provided by the FIFO architecture of an embodiment of the present application.

[0054] As shown in FIG. 2, in an embodiment of the present application, the syndrome matrix and the parity check matrix are divided into four regions, including: Figure 2

[0055] The four regions are M1, M2, M3 and M4, the division criteria are M1 = {M | 0≤x≤n-1, 0≤y≤n-1}, M2 = {M | n≤x≤N-1, 0≤y≤n-1}, M3 = {M | 0≤x≤n-1, n≤y≤N-1}, and M4 = {M | n≤x≤N-1, n≤y≤N-1}, n being a region division boundary value, symbol​ Indicates rounding up.

[0056] like Figure 2 As shown, in one embodiment of the present invention, four areas are stored in FIFO respectively, including:

[0057] The M4 area is discarded, and {M1, M2} and {M1, M3} are stored in n FIFOs respectively, and the FIFO depth is N.

[0058] Furthermore, in one embodiment of the present invention, controlling the FIFO reading to enter the comparator through the FIFO flag bit includes:

[0059] Update the FIFO flag xf used to control the FIFO reading x and yf y When , the current minimum coordinate is (x, y), and the next minimum coordinate may be (x+1, y) and (x, y+1). The steps to update the flag are as follows:

[0060] If xf x+1 =1,yf y+1 =1, then xf x =0,yf y =0, do not read FIFO at the same time;

[0061] If xf x+1 =1,yf y+1 =0, then yf y =0,yf y+1 =1, read the FIFO containing the (x, y+1) position data at the same time;

[0062] If xf x+1 =0,yf y+1 =1, then xf x =0,xf x+1 =1, read the FIFO containing the (x+1,y) position data at the same time;

[0063] If xf x+1 =0,yf y+1 =0, then xf x+1 =1,yf y+1 =1, read the FIFO containing the position data of (x+1,y) and (x,y+1) at the same time;

[0064] The specific way in which the flag register controls FIFO reading is that when the flag register is 1, the FIFO of the corresponding coordinate is read, otherwise it is not read.

[0065] Furthermore, in one embodiment of the present invention, it further comprises:

[0066] Each FIFO reading port is configured with a register, and the FIFO stores the data of the original port in the register every time it reads a number; when the value comparator selects the data to be compared, if the flag bit register is 1, the data on the FIFO reading port is selected; if the flag bit register is 0, the data in the cache register of the FIFO reading port is selected.

[0067] Further, in an embodiment of the present application, further comprising:

[0068] If the currently read data coordinates belong to the M1 region, the two FIFOs corresponding to the coordinates are read at the same time; if the currently read data coordinates belong to the M2 region, only the FIFO storing the data of the {M1, M2} region corresponding to the coordinates is read; if the currently read data coordinates belong to the M3 region, only the FIFO storing the data of the {M1, M3} region corresponding to the coordinates is read.

[0069] Embodiment 1

[0070] Taking a Galois field GF(64) located on the check node update input data length N as an example, the specific steps are as follows:

[0071] S201: Calculate a check node extension set:

[0072]

[0073] Its flag bit is:

[0074]

[0075] Wherein, X flag and Y flag mark the row and column ordering of the set M, s x,y = U x + V y , (UB, U) and (VB, V) are two groups of input data of the check node update module, the data length is N, x [0, 31], y [0, 31], U and V are two groups of ascendingly arranged log-likelihood values, UB and VB are two groups of Galois field GF(64) numbers, 64 = 2 6 , UB [0, 63], VB [0, 63], Indicates bit-by-bit XOR, + indicates decimal addition. T = [(dm0, sm0), …, (dm 31 , sm 31 )], which represents the smallest 32 log-likelihood values and Galois field numbers after the check node extension set is sorted; T flag = [tf0, …, tf 63] is the flag of the Galois field number in T; num represents the number of minimum values ​​currently found, and iter represents the number of times the minimum value is currently searched.

[0076] S202: Divide M into 4 regions and sort them, namely M1, M2, M3, M4, symbol Indicates rounding up, so the region division boundary value n = 4, and the divided regions are:

[0077] M1={M|0≤x≤3,0≤y≤3},

[0078] M2={M|4≤x≤31,4≤y≤31},

[0079] M3={M|0≤x≤3,4≤y≤31},

[0080] M4={M|4≤x≤31,4≤y≤31},

[0081] According to the boundary value 4, such as Figure 3 As shown, set up 8 FIFOs, place n along the X direction and Y direction respectively, remove area M4, and then send M1 and M2 to FIFOX0 to FIFOX in the X direction. n-1 , send M1 and M3 into FIFOY0 to FIFOY in the Y direction n-1 .

[0082] S203: Initialization. Initialize the data to be compared and take the log-likelihood value s at the (0,0) coordinate of M. 0,0 Put it into the comparator, the rest of the data to be compared in the comparator is 0; initialize the flag bit X flag =[1,0,…,0],Y flag =[1,0,…,0]; initialize the minimum value set T = [(0,0),…,(0,0)], initialize the Galois field number flag T in T flag =[0,…,0]; initialize the number of minimum values ​​currently found num = 0; initialize the number of times the current minimum value is searched iter = 0.

[0083] S204: Find the minimum value. If the current comparator finishes the comparison and obtains the minimum value s x,y The corresponding Galois field number already exists in T, that is, T flag (d x,y )=1, then discard the minimum value; otherwise, x,y and its Galois field number d x,y Added to T, while T flag (d x,y) is set to 1, num = num + 1. When the comparison is completed, iter = iter + 1. If iter reaches the preset value at this time, the process proceeds to S206; otherwise, the process proceeds to S205.

[0084] S205: Add new data to be compared. According to the latest minimum coordinate (x, y), combined with the flag X flag and Y flag , add the data in M1 or M2 or M3 into the comparator for the next data comparison, and update the flag X according to the data addition situation flag and Y flag , assuming that the minimum coordinate obtained by the current comparison is (x, y), the next minimum coordinates to be added may be (x+1, y) and (x, y+1), such as Figure 4 As shown, the star represents the position (x, y), the No. 1 triangle represents the position (x+1, y), and the No. 2 triangle represents the position (x, y+1): If xf x+1 =1 and yf y+1 =1, do not add data, xf x Set to 0, yf y Set to 0; if xf x+1 =1 and yf y+1 =0, add data at (x,y+1), yf y Set to 0, yf y+1 Set to 1; if xf x+1 =0 and yf y+1 =1, add the data at (x+1,y), xf x Set to 0, xf x+1 Set to 1; if xf x+1 =0 and yf y+1 =0, add data at (x+1,y) and (x,y+1), xf x+1 Set to 1, yf y+1 Set to 1.

[0085] Each FIFO read port is configured with a register. Every time the FIFO reads a number, the original port data is cached in the register. Set n binary comparators and connect the two ports of each comparator to a single FIFO in the X and Y directions respectively. The structure is as follows: Figure 3 As shown, use X flag and Y flag The corresponding flag bit controls the MUX selector to select the port data for the comparator. When the flag bit is 1, the FIFO read port data is selected. When the flag bit is 0, the FIFO read port register data is selected. After a clock cycle, the current minimum value is obtained.

[0086] X flag and Y flagThe flag is used as read enable control of the FIFO reading at the end of each comparison within one clock, and provides data source for the next data addition. If the current read number belongs to M1, the two FIFOs corresponding to the number coordinate are read simultaneously; if the current read number belongs to M2, only the FIFOY corresponding to the number coordinate is read; if the current read number belongs to M3, only the FIFOX corresponding to the number coordinate is read.

[0087] If the added data belongs to M1, the X flag and Y flag flag is recovered by using the cache value when the next data is added, otherwise the cache and the recovered flag are not used.

[0088] Then S204 is entered.

[0089] S206: If the current num is 32, the process is ended to obtain the check node update result T; otherwise, T is filled to 32 data with specific log-likelihood value and Galois field number, and then the process is ended. The specific method is that the numerical part is filled with the maximum log-likelihood value in T before filling, and the index part is filled with the Galois field number that does not exist in T before filling, to obtain the check node update result T.

[0090] Embodiment 2

[0091] The following is the simulation and engineering implementation of the multinary LDPC decoder with Galois field GF(64), check matrix size 100*200 and check node update input data length N of 32. The FPGA uses Xilinx-xc7vx690tffg1927-2 type board, the clock frequency is 200 Hz, the resource occupancy and throughput of the decoder using the present application and the decoder using the bubble detection algorithm are compared, and it is verified that the multinary LDPC check node update method of the present application can overcome the defects of the low complexity bubble detection algorithm that the throughput and the storage resource are mutually restricted, and can simultaneously reduce the time complexity from O(N 2 ) to O(N The space complexity is reduced from O(N 2 ) to O(N It has important value for realizing the multinary LDPC decoder with high throughput and low resource.

[0092] Table 1 is a comparison table of resource occupation ratio and clock ticks of two decoders adopting the present application and the bubble-checking algorithm under the same time complexity, at this time, the bubble-checking algorithm adopts the scheme of completing addition in advance and storing the obtained expansion and matrix in the register in order to save clock ticks. The LUT resource occupation ratio of the single check node update module adopting the present application is 0.69%, which is reduced by 73.5% compared with the check node update module adopting the bubble-checking algorithm, and at the same time, the register with an occupation ratio of 0.37% and the BRAM with an occupation ratio of 0.54% replace the register resource with an occupation ratio of 4.52% in the bubble-checking algorithm; the clock ticks are both 182 clk, so the throughput is consistent.

[0093] Table 2 is a comparison table of resource occupation ratio and clock ticks of two decoders adopting the present application and the bubble-checking algorithm under the same space complexity, at this time, the bubble-checking algorithm adopts the scheme of temporarily completing addition to obtain a single data to be sorted in order to save storage resources. The clock ticks of the single check node update module adopting the present application are 182 clk, which is 32 clk less than the bubble-checking algorithm, so the throughput is improved by 17.6%; the hardware storage resources of the two are almost the same, but in the LUT resource, the present application is reduced by 16.9% compared with the bubble-checking algorithm.

[0094]

[0095] Table 1 is a comparison table of resource occupation ratio and clock ticks of two decoders (same time complexity)

[0096]

[0097] Table 2 is a comparison table of resource occupation ratio and clock ticks of two decoders (same space complexity)

[0098] The low-complexity multi-ary LDPC check node update method of the FIFO architecture provided by the present application effectively reduces the hardware resources required for multi-ary LDPC decoder check node update by storing and sorting the expansion and set division area, and can simultaneously reduce the time complexity from O(N 2 ) to O(N The space complexity is reduced from O(N 2 ) to O(N It has important value to promote the wide application of high-throughput and low-resource multi-ary LDPC decoder.

[0099] In order to realize the above-mentioned embodiments, the present application further provides a low-complexity multi-ary LDPC check node update device of FIFO architecture.

[0100] Figure 5A schematic structural diagram of a low-complexity multi-ary LDPC check node updating device with a FIFO architecture is provided in an embodiment of the present invention.

[0101] like Figure 5 As shown, the low-complexity multi-ary LDPC check node update device of the FIFO architecture includes: an acquisition module 10, a division module 20, a storage module 30, and a comparison module 40;

[0102] The acquisition module is used to obtain the check node input data and process the input data to obtain the extended sum matrix. The input data is two sets of log-likelihood values ​​and their Galois field numbers arranged in ascending order with a length of N.

[0103] A partitioning module for dividing the expansion and matrix into four areas;

[0104] A storage module is used to store the four areas into FIFOs respectively, and directly connect the FIFO ports to the value comparator ports;

[0105] The comparison module is used to configure a 1-bit register as a flag bit for each FIFO, use the flag bit register to control the FIFO reading to enter the numerical comparator for comparison, retain the current minimum value, and mark the register; loop this operation until the minimum log-likelihood value of N non-repeating Galois field numbers is obtained.

[0106] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art can combine and combine different embodiments or examples described in this specification and features of different embodiments or examples without contradiction.

[0107] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of such features. Throughout the description of this application, "plurality" means at least two, for example, two, three, etc., unless otherwise specifically defined.

[0108] Any processes or methods described in the flow charts or otherwise described herein can be understood as representing modules, segments, or portions of code that include one or more executable instructions for implementing the specified logical functions or steps, and the preferred embodiments of the application include additional or fewer steps, in other orders, with other functionality, in implementations of these preferred embodiments of the application. Thus, any of the steps, options, aspects, components, etc. discussed herein can be included or deleted in other embodiments of the application, and yet still be deemed to fall within the scope of the present application.

[0109] Although the embodiments of the present application have been shown and described above, it should be understood by those ordinary skilled in the art that the above embodiments are exemplary and cannot be construed as limiting the present application, and those ordinary skilled in the art can make changes, modifications, replacements and variations to the above embodiments within the scope of the present application.

Claims

1. A low-complexity multi-ary LDPC check node update method based on a FIFO architecture, characterized in that: The following steps are involved: Obtain check node input data, and process the input data to obtain an extended sum matrix, wherein the input data is two sets of log-likelihood values ​​and their Galois field numbers arranged in ascending order and having a length of N, wherein the extended sum matrix is ​​expressed as: Each expansion and matrix element SD x,y Includes two parts of data, the addition result s x,y and XOR result d x,y , where d x,y =UB x ⊕VB y , s x,y =U x +V y , ⊕ represents bitwise XOR, + represents decimal addition, (UB, U) and (VB, V) are two sets of input data of length N for the check node update module, U and V are two sets of log-likelihood values ​​arranged in ascending order, and UB and VB are two sets of Galois field numbers that are independent of the value size; Dividing the expansion matrix into four regions, wherein the four regions are M1, M2, M3 and M4; Abandon the M4 area, store {M1, M2} and {M1, M3} into n FIFOs respectively, the FIFO depth is N, and directly connect the FIFO ports to the numerical comparator ports; Each FIFO is configured with a register of 1 bit as a flag bit, and the flag bit register is used to control the FIFO reading to enter the numerical comparator for comparison, retain the current minimum value, and update the flag bit register; this operation is repeated until the minimum log-likelihood value of N non-repeating Galois field numbers is obtained, wherein the FIFO flag xf used to control the FIFO reading is updated x and yf y When the current minimum value is (x, y), the next minimum value may be (x+1, y) and (x, y+1). The steps to update the flag are as follows: If xf x+1 =1,yf y+1 =1, then xf x =0,yf y =0, do not read FIFO at the same time; If xf x+1 =1,yf y+1 =0, then yf y =0,yf y+1 =1, read the FIFO containing the (x, y+1) position data at the same time; If xf x+1 =0,yf y+1 =1, then xf x =0,xf x+1 =1, read the FIFO containing the (x+1,y) position data at the same time; If xf x+1 =0,yf y+1 =0, then xf x+1 =1,yf y+1 =1, read the FIFO containing the position data of (x+1,y) and (x,y+1) at the same time; The specific way in which the flag register controls FIFO reading is that when the flag register is 1, the FIFO of the corresponding coordinate is read, otherwise it is not read.

2. The method according to claim 1, characterized in that The expansion matrix is ​​divided into four areas, including: The division criteria are M1 = {M|0≤x≤n-1,0≤y≤n-1}, M2 = {M|n≤x≤N-1,0≤y≤n-1}, M3 = {M|0≤x≤n-1,n≤y≤N-1}, M4 = {M|n≤x≤N-1,n≤y≤N-1}, where n is the boundary value of the region division. symbol Indicates rounding up.

3. The method according to claim 1, characterized in that Also includes: Each FIFO read port is configured with a register. Every time the FIFO reads a number, the original port data is cached in the register. When the flag register is used to select the data to be compared for the numerical comparator, if the flag register is 1, the data on the FIFO read port is selected; if the flag register is 0, the data in the cache register of the FIFO read port is selected.

4. The method according to claim 1, wherein Also includes: If the coordinates of the data currently being read belong to the M1 area, the two FIFOs corresponding to the coordinates are read at the same time; if the coordinates of the data currently being read belong to the M2 area, only the FIFO corresponding to the coordinates containing the data of the {M1, M2} area is read; if the coordinates of the data currently being read belong to the M3 area, only the FIFO corresponding to the coordinates containing the data of the {M1, M3} area is read.

5. A low-complexity multi-ary LDPC check node update device with a FIFO architecture, characterized in that: Includes the following modules: An acquisition module is used to obtain check node input data and process the input data to obtain an extended sum matrix. The input data is two sets of log-likelihood values ​​and their Galois field numbers arranged in ascending order with a length of N. The extended sum matrix is ​​represented as follows: Each expansion and matrix element SD x,y Includes two parts of data, the addition result s x,y and XOR result d x,y , where d x,y =UB x ⊕VB y , s x,y =U x +V y , ⊕ represents bitwise XOR, + represents decimal addition, (UB, U) and (VB, V) are two sets of input data of length N for the check node update module, U and V are two sets of log-likelihood values ​​arranged in ascending order, and UB and VB are two sets of Galois field numbers that are independent of the value size; A division module, configured to divide the expansion matrix into four regions, wherein the four regions are M1, M2, M3 and M4; A storage module is used to discard the M4 area, store {M1, M2} and {M1, M3} into n FIFOs respectively, the FIFO depth is N, and directly connect the FIFO ports to the numerical comparator ports; A comparison module is configured to configure a 1-bit register as a flag bit for each FIFO, use the flag bit register to control the FIFO reading to enter the numerical comparator for comparison, retain the current minimum value, and update the flag bit register; loop this operation until the minimum log-likelihood value of N non-repeating Galois field numbers is obtained, wherein the FIFO flag xf used to control the FIFO reading is updated x and yf y When the current minimum value is (x, y), the next minimum value may be (x+1, y) and (x, y+1). The steps to update the flag are as follows: If xf x+1 =1,yf y+1 =1, then xf x =0,yf y =0, do not read FIFO at the same time; If xf x+1 =1,yf y+1 =0, then yf y =0,yf y+1 =1, read the FIFO containing the (x, y+1) position data at the same time; If xf x+1 =0,yf y+1 =1, then xf x =0,xf x+1 =1, read the FIFO containing the (x+1,y) position data at the same time; If xf x+1 =0,yf y+1 =0, then xf x+1 =1,yf y+1 =1, read the FIFO containing the position data of (x+1,y) and (x,y+1) at the same time; The specific way in which the flag register controls FIFO reading is that when the flag register is 1, the FIFO of the corresponding coordinate is read, otherwise it is not read.

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