Optical receiver including monolithically integrated photodiode and transimpedance amplifier

Abstract

An optical receiver includes a monolithically integrated pin-shaped photodiode (PIN) and a transimpedance amplifier (TIA). The TIA includes an InP heterojunction bipolar transistor (HBT) made of a first plurality of layers of an epitaxial layer stack grown on an Si:InP substrate; the PIN is made of a second plurality of layers of the epitaxial layer stack. The p-type contact of the PIN is vertically connected to the input of the TIA to reduce the PIN capacitance C. PIN The TIA capacitor C TIA Can be etched to C PIN The thickness of the absorption layer, the window area and the optional mirror thickness of the PIN, the device capacitance C PIN +C TIA and the TIA’s feedback resistor R F The device parameters are optimized to specific performance specifications including sensitivity and responsivity at the operating wavelength. This design approach enables cost-effective manufacturing of integrated PIN‑TIAs for applications such as 1577 nm receivers in 10G‑PON ONUs.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to U.S. Provisional Patent Application No. 62 / 950,479, filed December 19, 2019, which is incorporated herein by reference. Technical Field

[0003] The present invention relates to an optical receiver including a photodiode detector and a transimpedance amplifier (TIA) for use in applications such as Gigabit Passive Optical Network (GPON). Background Art

[0004] A passive optical network (PON) is a point-to-multipoint, fiber-to-the-home network architecture. A PON network uses passive splitters and combiners to distribute optical signals without the need for active components such as optical amplifiers. An optical line terminal (OLT) at the service provider's central office communicates with an optical network unit (ONU) at each customer premises. The ONU includes an optical receiver that converts the received optical signal into an electrical output.

[0005] For example, a 10G passive optical network may be referred to as 10G-PON or XG-PON. ITU-T G.987 is a set of documents that defines the access network standard. Wavelength division multiplexing (WDM) enables simultaneous upstream and downstream transmission over the same optical fiber. This technology allows one PON wavelength to be used for upstream transmission and another for downstream transmission. For example, 10G-PON uses 1577nm for downstream transmission and 1270nm for upstream transmission.

[0006] The optical receiver of an ONU consists of a photodiode detector and a transimpedance amplifier. The performance of the optical receiver depends on several factors, such as:

[0007] Optical and electrical properties of the photodiode, such as responsivity, carrier transit time, and RC electrical characteristics;

[0008] Transimpedance amplifier semiconductor performance, such as gain, noise, overload, and bandwidth;

[0009] Mixed integration parasitics and packaging parasitics, such as series input inductance and stray capacitance.

[0010] Photodiode technology places physical limits on the receiver's sensitivity and bandwidth performance. The choice of TIA technology and design methodology significantly determines the overall receiver performance.

[0011] For 10G PON, 1577nm optical receivers typically use a hybrid arrangement of an avalanche photodiode (APD) and a transimpedance amplifier (TIA), i.e., discrete components. Currently, commercial semiconductor lasers emitting in the 1577nm wavelength range have limited output power, and InGaAs needle photodiodes (needle PDs) do not have sufficient sensitivity to be used as ONU optical detectors at 1577nm (1575-1581nm). Therefore, it is necessary to use more expensive APDs to obtain the required performance, such as responsivity and sensitivity. In addition to the high cost, other disadvantages of APDs are the need for a high-voltage power supply, additional circuitry for the control loop, poor reliability over a long life, or a limited operating life.

[0012] Receiver sensitivity is defined as the signal optical power required for the receiver to achieve a target bit error rate (BER). For 10GPON, according to ITU-T G.987, achieving a BER of 10⁻³ or better requires a sensitivity of -28.5dBm, which is unattainable with existing InGaAs vertical needle photodiodes. APDs can exceed the sensitivity of discrete needle photodiodes by, for example, 3 to 5dB, making them sufficiently sensitive for this application.

[0013] On the other hand, the performance of optical receivers, which include hybrid integrated photodiodes (PDs or APDs) and TIAs, is limited by parasitic effects such as pad capacitance, wire bonding inductance, and impedance matching requirements for interconnects between the APD and TIA. These issues are particularly concerning as data rates increase from 10 Gb / s to 25 Gb / s and 50 Gb / s, and beyond.

[0014] Therefore, there is a need for an optical receiver including a photodiode detector for 10G-PON and next-generation PON, for example, a 1577 nm photodiode detector for an ONU, or a 1270 nm photodiode detector for an OLT, that provides one or more of performance improvement, cost reduction, or alternative solutions to replace conventional hybrid APD-TIA modules. Summary of the Invention

[0015] The present invention is directed to obviating or alleviating one or more of the above-mentioned disadvantages of known devices and systems incorporating hybrid photodiode detectors and TIAs, or at least providing an alternative.

[0016] Aspects of the present invention provide optical receivers including monolithically integrated photodiodes and transimpedance amplifiers, and methods of optimizing the performance of monolithically integrated photodiodes and transimpedance amplifiers to meet performance specifications, such as those of next generation PONs.

[0017] On the one hand, the optical receiver includes a monolithically integrated photodiode (PD) and a transimpedance amplifier (TIA), wherein:

[0018] The TIA includes an InP heterojunction bipolar transistor (HBT) formed by a first plurality of layers of an epitaxial layer stack grown on an SI (semi-insulating) InP substrate; the PD includes a pin-shaped diode (PIN) formed by a second plurality of semiconductor layers of an epitaxial layer stack, the epitaxial layer stack including an n-layer, an i-layer, and a p-layer; the p-type contact of the PIN diode is directly interconnected to the input of the TIA through a conductive trace to reduce the device capacitance C of the PIN PIN , the input capacitance of the TIA is C TIA ;and

[0019] Select the device parameters that include the following values: C PIN 、C TIA , PIN area A or window diameter The thickness of the i-layer of PIN is t i and the TIA's transimpedance feedback resistor R F , to provide an integrated PIN-TIA that meets performance specifications including specified sensitivity and responsivity at the operating wavelength.

[0020] For example, the device parameters are selected through an optimization process to provide an integrated PIN-TIA that meets the desired performance specifications, such as sensitivity, responsivity, bandwidth, transimpedance gain, etc. In some embodiments, C PIN with C TIA match.

[0021] In an exemplary embodiment, for example, for the operating wavelength of 10G PON, the i-layer (i.e., the absorption layer) of the PIN comprises InGaAs. In other embodiments, instead of a PIN comprising an i-layer of InGaAs, other absorption materials within the InGaAlAsPpenternary system that are lattice-matched to InP can be used. The i-layer or absorption layer can comprise a single layer or a multilayer structure. The n-layer and p-layer can be n-doped InP and p-doped InP, or any other suitable lattice-matched semiconductor material. Each of the n-layer and p-layer can also comprise a single layer or a multilayer structure.

[0022] Notably, when the PIN diode is directly interconnected to the TIA input via photolithographically defined conductive traces, the parasitic capacitance and inductance of the pads and wire bonds required for hybrid integration of the PD and TIA are eliminated. Furthermore, the photolithographically defined interconnect traces between the PIN diode and TIA provide a more defined and reproducible interconnect, which avoids the variability and inconsistency issues associated with wire-bond interconnects of hybrid components.

[0023] For example, using the described design approach, a monolithic PIN-TIA can be fabricated with sensitivity and responsivity that meets the performance specifications for 10G PON receivers, 1577nm receivers for 10G PON optical network units (ONUs), or 1270nm receivers for optical line terminals (OLTs). InGaAs PINs are well-suited for operation at these wavelengths. That is, a monolithic InGaAs PIN-TIA can be configured to have, for example, sensitivity and responsivity better than -28dBm or better than -30dBm, comparable to conventional hybrid APD-TIAs for 1577nm ONU receivers. In initial prototypes, a responsivity of ~0.7A / W was achieved at 1550nm. By further optimizing PIN-TIA parameters, as described herein, it is expected that, for example, responsivities of ≥0.8A / W, ≥0.9A / W, or ≥1.0A / W can be achieved at 1577nm, approaching the quantum efficiency limit of 1.28A / W.

[0024] In some embodiments, the quantum efficiency (QE) is improved by including a mirror (i.e., a light reflector) that creates a dual path through the thickness t i of the first layer. For example, the mirror includes a multilayer quarter-wavelength stack of alternating high-refractive index (e.g., semiconductor) and low-refractive index (e.g., dielectric) lattice-matched materials to create a dual path through the i layer, effectively providing an absorption length in the i layer that is twice that of t i . The n layer of the mirror acts as the n layer of the PIN. In some embodiments, the quantum efficiency can be ≥85% or ≥90%.

[0025] In some embodiments, to reduce optical losses, the window or aperture includes an antireflective coating optimized for the operating wavelength, and the p+ cap layer is selected to be substantially transparent at the operating wavelength, for example, the p+ cap layer is made thinner and made of a material that reduces optical losses, rather than minimizing the sheet resistance and contact resistance of the p-type contact.

[0026] In an example embodiment of an optical receiver comprising a monolithically integrated PIN-TIA for operation at 1577 nm, the HBT is characterized by f T ≥100GHz, TIA has a bandwidth (BW) of 7.5GHz, C PIN ≤50fF, C TIA ≤50fF, R F =1500Ω. In another embodiment, a C of 14￡F has been achieved PIN It is beneficial to combine the capacitor (C PIN +C TIA ) is minimized, and C TIA Designed to be close to C PIN , or match C PINFor example, to improve sensitivity, if C can be sufficiently reduced by designing the PIN PIN , it may be desirable to use shorter gate length InP HBTs for the TIA, i.e., to reduce C TIA On the other hand, if we reduce C PIN is a limiting factor, then choose PIN Matching C TIA It is sufficient to use lower cost manufacturing, that is, the monolithic integrated PIN-TIA can be realized using cheaper and larger gate length technologies to manufacture the InP HBT circuit of the TIA. For example, if CPIN is about 50fF or 30fF, C TIA with C PIN Match. If C PIN If the gate width is reduced to ≤30fF or ≤15fF, a smaller gate width HBT can be used to reduce C TIA .

[0027] In some embodiments, an optical receiver for an OLT (Optical Line Terminal) or ONU (Optical Network Unit) of a 10G Passive Optical Network (PON) includes:

[0028] Monolithically integrated photodiode (PD) and transimpedance amplifier (TIA), where:

[0029] The TIA includes an InP (indium phosphide) heterojunction bipolar transistor (HBT) formed from a first plurality of layers of an epitaxial layer stack grown on an SI (semi-insulating) InP substrate;

[0030] The PD includes a pin diode (PIN) formed from a second plurality of semiconductor layers of an epitaxial layer stack, the epitaxial layer stack including an n-layer, an i-layer, and a p-layer;

[0031] The p-type contact of the PIN diode is directly interconnected to the input of the TIA through a conductive trace; and

[0032] The i-layer comprises an absorbing material selected for the operating wavelength of the OLT or ONU.

[0033] For optical receivers in optical nuclei (ONUs), the i-layer comprises a single or multilayer structure containing a material that absorbs at 1577 nm. For optical receivers in optical tertiary cellular (OLTs), the i-layer comprises a single or multilayer structure containing a material that absorbs at 1270 nm. For example, the i-layer is selected from a group of absorbing materials including InGaAs and other absorbing materials in the InGaAlAsP material system that are lattice-matched to InP. In the case of a circular PIN geometry, i.e., for normal incidence, the PIN can include a mirror (light reflector) below the i-layer to create a dual path through the i-layer.

[0034] Although the exemplary embodiment of the monolithically integrated PIN-TIA is described with reference to an implementation using an InGaAs PIN and a TIA circuit fabricated with InP HBTs, the design approach can be extended to other forms of PD implemented using InGaAs / InP process technology, for example, where the PD is an APD or a waveguide PIN (side window) rather than a vertical PIN (top window). The design parameters of the latter can be optimized to provide an integrated PD-TIA that meets the performance specifications of an optical receiver for an ONU or OLT for 10GPON, or for other applications requiring high data rate photodetectors.

[0035] For example, other applications may include 5G and database technology, although the operating wavelength may be slightly different from PON.

[0036] More generally, another aspect of the present invention provides an optical receiver comprising a monolithically integrated photodiode (PD) and a transimpedance amplifier (TIA), wherein:

[0037] The TIA includes a heterojunction bipolar transistor (HBT) formed from a first plurality of layers of an epitaxial layer stack formed on a substrate;

[0038] The PD is formed by the second plurality of semiconductor layers of the epitaxial layer stack; the p-type contact of the PD is directly interconnected to the input of the TIA through a conductive trace to provide the capacitance C of the PD. PD and the TIA capacitor C TIA ;and

[0039] Select device parameters, including: the C TIA and C PD ;Thickness of PD's absorption layer t i ;Window diameter or the area A of the PIN; and the transimpedance feedback resistor R of the TIA F , to provide an integrated PD-TIA that meets the device specifications, including specific sensitivity and responsivity at the operating wavelength.

[0040] For example, the PD may be one of the following: a needle PD; an avalanche PD; a waveguide needle PD; a waveguide needle PD with traveling wave geometry; a unidirectional carrier (UTC) PD, a resonant enhanced cavity PD; a SAGCM APD, a superlattice APD, and other suitable types of photodiodes.

[0041] Where appropriate, the PD may include mirrors (light reflectors) configured to create a dual pass through the absorbing layer, such as a multilayer quarter-wave stack of alternating high and low refractive index lattice-matched materials. For example, device parameters include the mirror thickness t of the multilayer quarter-wave stack. m and the thickness of the absorbing layer t i, where t is selected i and t m To obtain the required quantum efficiency, such as ≥85% or ≥90%

[0042] For improved performance, C PIN and C TIA The value of provides at least one of: a) C PIN with C TIA Match; b) C PIN Approximately equivalent to C TIA ; and c) minimum combined capacitance (C PIN +C TIA ).

[0043] In an example embodiment, device parameters of a monolithically integrated PD-TIA are optimized to provide specific sensitivity and responsiveness that meet receiver performance specifications for high-speed data applications, such as a 10G PON optical network unit (ONU) receiver or a 10G PON optical line terminal (OLT) receiver.

[0044] Elements of the monolithically integrated PIN-TIA and PIN-PD of the example embodiment may be combined with elements of other embodiments, as applicable. For example, the monolithically integrated PIN-TIA and PD-TIA of other embodiments may include any feasible combination of the individual features disclosed herein.

[0045] Another aspect of the present invention provides a method for fabricating a device structure including the monolithically integrated PIN-TIA and PD-TIA disclosed herein for an optical receiver.

[0046] The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of certain embodiments of the present invention, which is given by way of example only. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] FIG1 (Prior Art) shows a schematic functional block diagram of an optical receiver including a hybrid photodiode detector PD and a TIA;

[0048] Figure 2 Two views showing examples of commercially available InGaAs needle-shaped PDs;

[0049] Figure 3 An example graph showing device capacitance versus device area for needle-shaped PDs of different device areas is shown;

[0050] Figure 4 A schematic cross-section through the layers of an example InGaAs needle-shaped PD is shown to illustrate the window diameter Φ and the layer thickness t i Design parameters;

[0051] Figure 5A A schematic topological view (top view) of a monolithically integrated PIN-TIA of an exemplary embodiment is shown;

[0052] Figure 5B shows a schematic cross-sectional view of an epitaxial layer structure used to fabricate a monolithically integrated PIN and TIA of an exemplary embodiment;

[0053] Figure 6A A simplified equivalent circuit diagram showing the PIN of a monolithic integrated PIN-TIA is shown. Figure 6B A table listing some parameters;

[0054] Figure 7A Shows the sensitivity of the PIN device to the capacitance C PIN and TIA capacitor C TIA A schematic diagram of the dependence of

[0055] Figure 7B Shown is the PIN device capacitance C PIN and responsivity (A / W) versus i-layer thickness t i Schematic diagram of the correlation;

[0056] Figure 8 Some equations showing the relationships between device parameters are listed;

[0057] Figure 9 The quantum efficiency is shown to be dependent on the thickness of the layer t i A schematic diagram of the dependence of

[0058] Figure 10 Figure 2 shows calculated data based on a simplified model for a hybrid PD-TIA (discrete) and an integrated PIN-TIA (integrated) with three different apertures, for -3dB bandwidth f_-3dB (GHz) with i layer thickness t i (μm) (labeled as t_InGaAs(um) in the figure);

[0059] Figure 11 shows the effect of noise on the TIA feedback resistor R F A schematic diagram of the dependence of

[0060] Figure 12 The combined device capacitance and TIA (C PIN +C TIA ) Schematic diagram of the dependence of capacitance;

[0061] Figure 13 A simplified equivalent circuit schematic of a PIN and a TIA is shown to illustrate key parameters of a monolithically integrated PIN-TIA design of an example embodiment;

[0062] Figure 14 Example device specification table for a monolithically integrated PIN-TIA of an example embodiment;

[0063] Figure 15 A schematic diagram showing a circuit design of a monolithically integrated PIN-TIA according to an exemplary embodiment is shown;

[0064] Figure 16 A simplified equivalent circuit diagram of a monolithically integrated PIN-TIA of an exemplary embodiment is shown, showing device parameters of the PIN and first transistor Q1 of the TIA;

[0065] Figure 17 A simplified cross-sectional schematic diagram of an integrated PIN-TIA of a first embodiment is shown to illustrate the direct interconnection of the PIN and the TIA;

[0066] Figure 18 shows a simplified cross-sectional schematic diagram of an integrated PIN-TIA of a second embodiment, including a multilayer reflector (mirror);

[0067] Figure 19 A simulated data plot is shown to illustrate the inclusion of Figure 18 The effect of the reflector schematically illustrated in FIG;

[0068] Figure 20 Moore's Law graph showing transistor gate length (nm) over the past 50 years; and

[0069] Figure 21 A graph of the absorption coefficient of, for example, a semiconductor material versus wavelength is shown. DETAILED DESCRIPTION

[0070] FIG1 shows a schematic functional block diagram of an optical receiver, which includes a hybrid assembly 10 of a package substrate 12, a photodiode chip 20 including a photodiode (PD) 22, and a photodiode having a feedback resistor R F The photodiode chip 20 is interconnected with the TIA chip 30 via a wire bonding interconnect 38 to feed the photocurrent IPD to the TIA 322, thereby generating an output voltage V out The photodiode (PD) can be an APD, a pin-shaped photodiode (PIN), or another type of photodiode, depending on the required performance specifications. Typically, for GPON and 10GPON, to provide the required sensitivity, for example, better than -28.5dBm, the photodiode is an APD. As mentioned in the Background section, it is desirable to replace hybrid APD-TIAs with lower-cost, monolithically integrated PIN-TIAs with comparable performance and sensitivity.

[0071] Conventional wirebond interconnects in hybrid PIN-TIA optical receivers add significant parasitic effects that limit the performance of the PIN-TIA. Specifically, the bond pads add capacitance, and the bond wires add inductance. It should also be understood that the consistency of the wirebond interconnects of a hybrid component often depends on the type of package used, and in practice, some variability or inconsistency in the wirebond interconnects of individual optical receiver units can be expected. This variability or inconsistency in the wirebonds leads to corresponding variability or inconsistency in the parasitic capacitance and inductance of the hybrid PIN-TIA.

[0072] A monolithically integrated PIN-TIA according to embodiments of the present invention is disclosed that provides an alternative to conventional hybrid APD-TIAs for 10G-PON, with at least comparable performance and potentially providing performance improvements and / or cost reductions relative to other hybrid PD-TIAs.

[0073] Figure 2 An example top view (A) and side view (B) of a photodiode chip 20 comprising a 56 Gb / s InGaAs PIN22 (GCSDO480_16um_C3) is shown, which is suitable for high-speed optical receivers operating at 1577 nm. The device has an optical window 24 with a diameter of 16 μm and reportedly has a 36-40 GHz 3dB bandwidth when operated with an optimized TIA. In a traditional hybrid arrangement of a PIN and TIA, such as that shown in FIG1 , two bonding pads, an n-pad 26 and a p-pad 28 , such as a 75 μm 50Ω pad, are required to connect the PD to the TIA via wire bonding. Both pads of the PD add capacitance, which can account for a significant portion of the total capacitance of the device. Product data sheets indicate device capacitances ranging from 65 nF to 80 nF.

[0074] Taking an InGaAs PIN device with a publicly available datasheet for different regions as an example, and working backwards from the information on the datasheet, it is estimated that the parasitic capacitance of the pad accounts for about half of the total device capacitance. Figure 3 Capacitance C (pF) vs. device area (μm 2 ), the estimated value is obtained by extrapolating the typical capacitance and maximum capacitance data of devices based on different device areas to zero device area.

[0075] Figure 4 A schematic cross-sectional view of an InGaAs PIN device structure 100 is shown, showing a pin layer structure 110 including an n-layer 112, an i-layer 114, and a p-layer 116 formed on a semi-insulating (SI) indium phosphide (InP) substrate 102. The i-layer has a thickness t i The annular p-type contact 122 is formed on the p-layer and has a diameter of The optical aperture or window 124 of the device. The bonding pad includes a p-type contact pad 126 and an n-contact pad 128. The annular p-type contact 122 extends to the p-type contact pad 128. The n-layer 112 is formed on the n-contact layer 127, and the n-contact layer 127 is interconnected to the n-contact pad 126, for example, by a conductive path through the dielectric layer 104. The capacitance CPIN of the pin junction itself is necessary for the device to operate. For a given device aperture window diameter O, if the junction capacitance is zero, the flight time will be infinite and the bandwidth will be zero. A finite junction capacitance is required to balance RC and carrier flight time. However, the pad capacitance does not add any useful function and ideally, the pad capacitance is zero.

[0076] By design, the monolithic integration of the PIN and TIA eliminates pad capacitance and wire bond inductance. For example, an InGaAs PIN can be integrated with a TIA fabricated using an InP heterojunction bipolar transistor (HBT). This means that there is a direct on-chip interconnect, i.e., a photolithographically defined conductive trace, from the output of the PIN to the input of the TIA. Preferably, the conductive trace between the PIN and the TIA provides a short, low-resistance, low-inductance interconnect, eliminating the need for impedance matching. Thus, one of the 50Ω pads for the PIN is eliminated because there is a direct interconnect between the PIN and the TIA, rather than a wire bond connection. Because the conductive trace providing the direct interconnect between the PIN and the TIA is photolithographically defined, i.e., using one or more interconnect metallization layers, the PIN-TIA interconnect is more reproducibly and consistently defined for each PIN-TIA on the wafer, as well as from wafer to wafer and from batch to batch.

[0077] The schematic device topology (top view) of the monolithically integrated PIN-TIA of the exemplary embodiment 200 is shown in FIG. Figure 5A As shown, the monolithically integrated PIN-TIA chip 210 includes a PIN device structure 220 and a TIA circuit 230. There is a direct on-chip interconnect 240 between the p-type contact of the PIN 220 and the TIA circuit. Figure 5B 2 shows a schematic cross-sectional view of a monolithically integrated PIN-TIA chip 210 including a substrate 202 to illustrate the monolithic integration of an HBT epitaxial layer 204 and a cap epitaxial layer 206 for TIA to form a Figure 5B PIN shown in FIG. Although the other end of the PIN is coupled to a pad (i.e., a ground pad), the capacitance of the pad is effectively decoupled from the device operation. Because the output of the PIN is directly coupled to the first-stage amplifier of the TIA via a conductive trace providing direct on-chip interconnect, the PIN's pad capacitance is effectively ignored in the device operation. This has several beneficial consequences.

[0078] It is estimated that eliminating these parasitic capacitances will extend the RC-limited bandwidth by a factor of approximately 2. Monolithic integration of the PIN and TIA eliminates the pad connected to the PIN terminal of the TIA, which eliminates one of the two pads, halving the pad capacitance. Figure 6A In the equivalent circuit diagram shown, the PIN is modeled as a device current source IPD and a device capacitance C PIN , pad capacitance C PAD Wire bonding inductance L Bondwire The effect of the circuit is limited by LC. For 25GHz LC limit (f = 1 / 2Π(LC) 1 / 2 ), the limit is about 2nH (see Figure 6B ). The inductance of a typical gold wire bond with a length of 1 mm is approximately 0.8 nH at 10 GHz or 25 GHz (i.e., 0.8 nH / mm). Therefore, for all practical purposes, the LC limit is far beyond any significant circuit consideration for the application described, up to 25 GHz. At 50 GHz, the inductance needs to be managed, for example, by using multiple wire bonds, low inductance conductive interconnect traces, or other techniques designed to reduce inductance. By eliminating the wire bond connection between the PIN and the TIA, the pad inductance of the remaining pad is half the inductance of a hybrid arrangement with two pads. The monolithic integration of the PIN-TIA reduces the capacitance and inductance of the parasitic devices.

[0079] For example, more generally, assuming a single bond pad has a capacitance of about 15 fF, the inductance at 25 GHz peaks at 2.7 GHz, and assuming the bond wire is shorter than about 3 mm, the resonance will be in the bandwidth above 25 GHz and insignificant to 10 GHz.

[0080] The frequency response of the PD PIN is mainly limited by RC and transition time, which is the sum of the squares of the relevant response times. PIN Halve, which gives a higher bandwidth, or for the original bandwidth, increase the i-layer thickness t of the needle-shaped PD i An additional degree of freedom is available. Although a thicker i-layer increases the carrier flight time, which is usually undesirable, a lower device capacitance C PIN A trade-off is allowed because a thicker i-layer increases the responsivity, which is beneficial. For a given bandwidth, this trade-off allows a circular geometry (ie, normal incidence) PIN to have a higher responsivity than would otherwise be the case.

[0081] Figure 7A 、 Figure 7B and Figures 9 to 12 Some schematic diagrams showing the interdependence of device parameters. Figure 7AAs shown in the graph, the PIN-TIA sensitivity can be improved by reducing the capacitance of the PIN and the capacitance of the TIA. Figure 8 The equation shown, such as Figure 7B As shown in the graph, the capacitance of the PIN decreases with t i The thickness of the A / W decreases, and the responsivity in the A / W increases with the thickness ti. The quantum efficiency of the PIN also increases with the thickness of the (1-γt i ) increases exponentially, such as Figure 9 Schematically shown in .

[0082] To provide improved performance, first, the effective device capacitance (C PIN +C TIA ), i.e., by removing the bonding pads and providing direct interconnection between the PIN and TIA; second, the device thickness t1 is increased. Figure 10 As shown in the data shown in , the overall 3dB envelope of the PIN relative to the device thickness is improved. These combined effects provide improved bandwidth for a PIN of a given diameter.

[0083] The 3dB bandwidth (f_3dB) is given by the sum of the squares of the flight-time limited response and the RC response. Figure 10 The curves shown in are for a general needle-shaped PD structure, with certain assumptions about the bond pad capacitance (approximately 30 fF), the annular contact area (3 μm was used for the calculations), the literature values for hole and electron velocities (which are approximate, probably to within 20%), and using the approximation that all holes and electrons originate from the average absorption position within a circular (i.e., normal incidence) needle-shaped photodiode. The diameters quoted in the figure refer to the open optical aperture for coupling to the fiber, plus some additional surrounding area for the annular metal contact. For Figure 10 The data shown in , f_3dB has been calculated for some examples of monolithic integrated PIN-TIA (labeled “Integrated”) and hybrid PIN-TIA (labeled “Discrete”), for needle PDs with diameters of 20μm, 16μm, and 12μm, using publicly available data to infer the pad capacitance.

[0084] Simplified model for derivation of overflight restrictions

[0085] In a simplified model for the derivation of the fly-by limit, the average absorption position is calculated for each InGaAs thickness U, and both carriers are assumed to originate from that position.

[0086] Flyover time limited bandwidth f tr It is given by:

[0087] f tr *t i=0.443(1)

[0088] where t i is the flight time of the intrinsic depletion layer of InGaAs, and assuming the single flight time approximation of the rectangular pulse, the Fourier transform distribution of sinc(x) is obtained. Let the flight direction be z and the thickness of InGaAs be Z i , the velocity is assumed to be constant v i A simple rearrangement of equation (1) gives:

[0089]

[0090] Equation (2) also gives the flight time limit thickness for a given frequency. Lecture notes and textbooks usually assume the sum of the squares of the electron and hole flight times, but also do a lot of numerical work. In this work, the flight time is calculated assuming that all carriers originate from the average absorption position, and the two flight times are averaged to obtain a very good approximation that is algebraically understandable. In addition, the absorption curve is given by Beer's law as exp(-γz), where γ is the absorption coefficient. For light entering a PD with normal incidence geometry through the p-region, the average absorption position of the electron (through the p-contact) is given by:

[0091]

[0092] turn out:

[0093]

[0094] Therefore, the average absorption of holes is given by

[0095] z h，avg =z i -z e，avg (5)

[0096] These quantities are usually calculated numerically. These closed-form approximate expressions are useful for simplifying calculations.

[0097] Based on these assumptions, the simplified model provides a comparison of the f_-3dB bandwidth of some examples of monolithic integrated PIN-TIA and hybrid PIN-TIA. Although more complex modeling methods can be used, the basic physical principles will remain the same.

[0098] refer to Figure 10 The following observations were made:

[0099] For both integrated and discrete groups, reducing the diameter improves the frequency response at all t_InGaAs values.

[0100] For any given diameter, going from discrete (with pad capacitors) to integrated (without pad capacitors) improves frequency response at all t_InGaAs values.

[0101] Whether integrated or discrete, any given needle-shaped PD diameter has an optimal (i.e., peak) bandwidth;

[0102] This optimization (peak) is sharper for integrated circuits, since higher bandwidth is possible, limited only by the device size.

[0103] For sufficiently thick t_InGaAs (t i ), the value is decreasing for decreasing diameters; but for larger thicknesses the integrated approach still has a clear, smaller advantage in bandwidth.

[0104] Taking this data into account, for example, if greater bandwidth is desired, the device thickness can be reduced, restoring capacitance to achieve improved time-of-flight. Alternatively, if higher responsivity is desired, the device thickness can be increased, deteriorating the time-of-flight frequency response, but there is some leeway given the reduced capacitance. If the i-InGaAs layer is thinned for optimal bandwidth, responsivity is reduced. To achieve both increased bandwidth and increased responsivity (QE), mirrors or reflectors can be added to the PD to allow absorbed light to pass through twice, i.e., by increasing the effective thickness of the InGaAs i-layer, as described below.

[0105] Secondly, since the first-stage amplifier (TIA) can accommodate a higher transimpedance feedback resistor RF, the input-referred noise (IRN) and receiver sensitivity can be improved through the monolithic integration of the PIN and TIA. In other words, the TIA noise is inversely proportional to RF, such as Figure 11 Instead, the noise increases with the combined capacitance of the PIN and TIA (i.e., C PIN +C TIA ) and increase, such as Figure 12 As shown, for example, because the higher device capacitance limits the feedback resistor R F .

[0106] Figure 13 A simplified equivalent circuit schematic of the PIN and TIA is shown to illustrate the key parameters of the monolithic integrated PIN-TIA design, such as, Figure 14 Example unit specifications shown in the table.

[0107] Combining these two effects—reducing the PIN device capacitance and increasing the value of the transimpedance feedback resistor, RF—reduces TIA noise, thereby improving sensitivity. Consequently, it becomes possible to design a PIN-TIA with improved sensitivity, for example, better than -28dBm at 1577nm, meeting the requirements of 10G-PON optical receivers.

[0108] Figure 15 Schematic diagram of a circuit design for an example embodiment of a monolithically integrated PIN-TIA, wherein the TIA includes a three-stage amplifier having first, second, and third HBTs, Q1, Q2, and Q3, and a transimpedance feedback resistor R F .exist Figure 16 In the simplified equivalent circuit shown, PIN is shown as a circuit equivalent current source I with capacitance CPIN. AC Based on the current i received from PIN Π , the first transistor Q1 of the TIA is modeled as a capacitor C TIA , input resistance r Π , current source βi Π The figure also shows the base, emitter and collector resistors r b 、r e and r c , and the feedback resistor r F The second and third stages of the TIA are schematically represented by amplifier 1.

[0109] The best noise reduction effect of the first stage of the TIA occurs when both the PD capacitance and the capacitance of the first stage HBT, Q1, are minimized and comparable to each other. In principle, the capacitance of the HBT can be reduced by design, i.e., the mask set is adjusted to provide a smaller gate length HBT. However, in practice, the combined device capacitance C PIN +C TIA May be affected by C PIN There are limits to how much it can be reduced. Unless the PD capacitance can be reduced accordingly, the benefit of reducing the HBT capacitance is limited; and the cost and effort of design kit changes for smaller gate length HBTs may not be worth the effort. In a hybrid PD-TIA, since the bond pad parasitics dominate, reducing the device area of the PD to reduce C PIN The benefits of PIN-TIA are limited due to the increased difficulty of fiber alignment with PDs with smaller apertures. On the other hand, the PIN device capacitance C can be significantly reduced due to the monolithic integration of PIN-TIA. PIN By choosing a PIN with a smaller aperture, if the packaging logistics issues of aligning the fiber to the smaller aperture PIN are overcome, the size of the first-stage HBT can be reduced accordingly to reduce the capacitance of the first-stage HBT. This arrangement will lead to further improvements in noise and, therefore, receiver sensitivity.

[0110] Considering these design principles, in the monolithic integrated PIN-TIA of the exemplary embodiment, the PIN capacitor C PIN The TIA is designed so that the capacitor C TIAMatching with PIN capacitor, i.e. C TIA Assume that the fT of the InP HBT transistor is 100 GHz, the bandwidth BW = 7.5 GHz, and the TIA includes a three-stage transistor amplifier with a transimpedance feedback resistor R F For 1500Ω, use Figure 13 Calculated by the formula shown.

[0111] The design of an integrated PIN-TIA for improved sensitivity (i.e., lower values, such as less than -28dBm) and achieving a specified responsivity (e.g., ≥0.7A / W) requires recycling all possible photons, i.e., improving the quantum efficiency (QE) of the PIN. This is not practical for a discrete PIN wire-bonded to a TIA because the pad capacitance is the main factor limiting sensitivity even if the thickness ti is increased to infinity, i.e., to the point where the time-of-flight bandwidth dominates. On the other hand, for a monolithic integrated PIN and TIA, the sensitivity is mainly determined by the PIN capacitance C PIN , rather than the pad capacitance of the PIN, so there are several design options to improve the QE of the PIN, such as:

[0112] a) Increase the device thickness U until the flight time dominates because the pad capacitance does not dominate;

[0113] b) Reduce the device area A (e.g., aperture diameter) ), because pad capacitance is not the main factor;

[0114] c) For a given wavelength, a mirror is inserted, such as a quarter-wavelength reflector comprising alternating high / low refractive index materials stacked to create a thickness t through the i-InGaAs layer. i Dual channels, thus increasing QE while maintaining low flight time;

[0115] Figure 17 A schematic cross-sectional view of the various layers of an integrated PIN-TIA according to a first embodiment 300 is shown. The device structure includes a substrate 302, such as Si:InP, on which an epitaxial layer stack for the TIA circuit and the PIN device structure is formed. A first plurality of semiconductor layers of the epitaxial layer stack provides an HBT epitaxial layer structure 304 for the TIA circuit 330. A second plurality of layers of the epitaxial layer stack forms a PIN epitaxial layer structure 306 for the PIN 320, including an n-contact layer 327, an n-layer 312, an i-layer 314, a p-layer 316, and a PIN having a diameter of 1. 3. The p-type contact 322 of the PIN 320 is connected to the TIA circuit via a PIN-TIA interconnect 340, which extends through the dielectric filler 308. The TIA circuit 330 is formed on a first region of the substrate, which is isolated from a second region of the substrate on which the PIN 320 is formed by an isolation trench 350. For example, monolithically integrated InGaAs PINs and TIAs including InP HBTs can be fabricated using commercially available InP process technology.

[0116] For 10G PON, the PIN's i-layer comprises InGaAs to provide absorption at the OLT's transmission wavelength of 1577 nm. The PIN's n- and p-layers can be any suitable lattice-matched material compatible with InGaAs. To reduce unwanted absorption, the aperture is preferably made of a material that is substantially transparent at the transmission wavelength and may include an antireflection coating.

[0117] Fabrication involves providing an epitaxial layer structure, wherein an HBT epitaxial layer structure is provided on a substrate with an overlying PIN epitaxial layer structure. That is, a TIA circuit including InP HBTs is fabricated on a SI InP substrate for high-speed operation of the HBT. The InGaAs PIN is formed from the overlying epitaxial layer, so that the conductivity of the layers of the PIN epitaxial layer structure does not degrade the speed and performance of the underlying TIA circuit. Furthermore, because the HBT epitaxial layers forming the epitaxial layer stack of the HBT electronics are different from the PIN epitaxial layers forming the PIN epitaxial layer stack, each epitaxial layer can be optimized separately. If desired, a spacer comprising one or more intermediate layers can be provided between the HBT epitaxial layers and the PIN epitaxial layers, for example, to provide electrical isolation, act as an etch stop layer for ease of processing, etc. As shown schematically, regions of the TIA circuit can be isolated from regions of the PIN by dielectric-filled trenches. By integrating the HBT electronics for the TIA and PIN detector, as shown in the figure, the layers of the HBT epitaxial layer stack and the layers of the PIN epitaxial layer stack can be independently constructed and optimized to improve device performance. If necessary, the material of the epitaxial layer structure can be selected to be compatible with a single epitaxial growth, or alternatively, multiple epitaxial growths can be appropriately used. Different processes can be used to manufacture the HBT epitaxial layer and the PIN epitaxial layer. For example, in practice, MBE (molecular beam epitaxy) can be used to provide the HBT epitaxial layer, and MOCVD (metal organic chemical vapor deposition) can be used to provide the PIN epitaxial layer. A semi-insulating spacer can be provided between the HBT epitaxial layer and the PIN epitaxial layer. In other embodiments, an epitaxial layer structure compatible with a single epitaxial layer growth is preferably selected for HBTs and PINs.

[0118] A specific design problem for optical receivers for 1577 nm ONUs is that 1577 nm is close to the InGaAs band edge, in a region where the absorption coefficient is already low (see Figure 21 ). This wavelength has an absorption length of approximately 1.4 μm, compared to well under 1 μm at 1300 nm. This makes maximizing quantum efficiency more difficult. However, because 1577 nm is closer to the InGaAs band edge, high- / low-index lattice-matched dielectric stacks offer a greater possible contrast in this material system. This means it becomes practical to fabricate mirrors or reflectors that effectively pass through the i-InGaAs layer twice, effectively doubling the absorption length.

[0119] As an example, Figure 18 A schematic cross-sectional view of an integrated PIN-TIA device structure 400 of a second exemplary embodiment is shown, including a mirror 412 interposed between an n-contact layer 427 of a PIN and an i-InGaAs layer 414. For example, the mirror 412 comprises a multilayer stack of alternating high refractive index (e.g., n-doped semiconductor) / low refractive index quarter-wavelength lattice matching layers. The multilayer stack of n-doped materials serves as the n-layer of the PIN. The structures of the other layers of the PIN and TIA are as described in reference. Figure 17 As described. Figure 17 Components of device structure 400 that are similar to device structure 300 are labeled with the same reference numerals plus 100. Thus, an HBT epitaxial layer structure 404 for TIA circuit 430 and a PIN epitaxial layer structure 406 for PIN 420 are formed on substrate 402. The PIN epitaxial layer structure includes a multilayer reflector structure 412 serving as an n-layer, an i-layer 414, and a p-layer 416. An annular p-type contact 422 having an aperture window 424 is connected to the TIA circuit via a PIN-TIA interconnect 440, extending through dielectric filler 408. TIA circuit 430 is formed on a first region of the substrate, which is isolated from a second region of the substrate on which PIN 420 is formed by an isolation trench 450.

[0120] Figure 19 The figure shown shows some calculation results that simulate the effect of adding mirrors. The starting point is the estimated nearly 3dB QE loss from existing state-of-the-art 56G or 28G PINs with circular mesas and normal incidence (e.g., front-entry geometry). By increasing the thickness of the i-InGaAs layer (in Figure 19This becomes feasible because the parasitic capacitance of the PIN’s bond pad no longer degrades the device performance, and by adding a mirror with mirror thickness (μm) (shown along the other horizontal axis of the graph), simulation results show that the PIN can actually gain back somewhere between 1.5 and 2 dB (see the vertical axis of total QE loss (dB) for two passes).

[0121] Thus, each of these design options, used alone or in combination, can produce an optical receiver including a monolithically integrated PIN-TIA with improved performance, for example, meeting the performance specifications for 10G-PON 1577nm ONU optical receivers. This design approach makes it possible to replace the traditional hybrid APD and TIA with a monolithically integrated PIN-TIA with comparable sensitivity and responsivity. Implemented using commercially available InP process technology, the monolithically integrated PIN-TIA avoids the need for an APD and its high-voltage power supply and control circuitry, as well as the associated costs.

[0122] Because the exemplary embodiment of the monolithic PIN-TIA described herein has comparable sensitivity and responsivity to conventional / commercial hybrid APDs and TIAs for 10G PON applications, the monolithic PIN-TIA can be deployed in the optical receivers of 1577nm ONUs in existing fiber networks, where the OLT uses lasers that provide standard transmit power (e.g., 9dBm DML or 4dBm EML). Of course, using lasers with higher transmit power will relax the required sensitivity specifications, allowing further optimization of the monolithic PIN-TIA for next-generation PONs and other applications.

[0123] For some applications, it may be necessary to replace discrete APDs with vertical pin photodiodes, as described above. Using this design approach for monolithic integration of an APD and TIA using InP material technology, or for monolithic integration of a waveguide PIN and TIA based on InP material technology, is also considered feasible and may be beneficial for some high-speed data applications. That is, reducing the photodetector capacitance can allow optimization of other device parameters, thereby providing improved optical receiver performance for other wavelengths covered by other types of InGaAs photodetectors. Specifically, eliminating the pad capacitance of the PIN and TIA interconnect allows for a higher transimpedance feedback resistor, Rf, to achieve higher TIA transimpedance gain.

[0124] When designing a TIA, reducing capacitance allows for a higher transimpedance feedback resistor, Rf, to increase gain. TIA noise is inversely proportional to the feedback resistor, RF. Matching the TIA capacitance to the device capacitance of the PIN can be beneficial. Since many parameters can be adjusted to achieve the desired PIN-TIA performance, minimizing the PIN capacitance may not be necessary. Regarding the PIN ground pad, using multiple pads can be beneficial. For example, two pads doubles the capacitance and halves the inductance. For example, using multiple wire bonds for the ground pad reduces the bond wire inductance (e.g., approximately 1 nH / mm for a 25 μm bond wire). When designing the PIN, if the PIN responsivity (i.e., A / W) is high enough to enable a higher SNR in the PIN, the PIN presents a higher input signal to the TIA. This means that even if the TIA is noisier (e.g., from a lower Rf and higher capacitance), the integrated PIN-TIA can improve the SNR.

[0125] That is, for each of these examples, regardless of whether the photodetector is a vertical InGaAs PIN (top window), an InGaAs APD, an InGaAs waveguide PIN (side window), or another type of photodiode, eliminating the pad capacitance of the photodiode has a significant impact on improving device performance and enables other parameters of the photodetector and TIA to be modified or optimized, such as improving quantum efficiency and other parameters to meet the sensitivity, responsivity, and other specifications required for applications such as 10GPON and other high data rate applications requiring high-performance modulation schemes. In the above embodiments including a vertical PIN structure, the PIN can have an area containing the optical window with a diameter of, for example, 16μm to 20μm. Because reducing the area of the pin also reduces the capacitance, a smaller diameter pin can be used in conjunction with a lens to match the size of the fiber spot.

[0126] Monolithic integration of InGaAs PINs using InP HBTs provides a solution to a problem for TIAs that is not easily solved with silicon photonics including normal incidence, such as Germanium (Ge) PINs in front-incidence geometry. Ge has a lower absorption coefficient than InGaAs in the wavelength range of interest for 10G PON (see Figure 21 ), and 1577nm is very close to the bandgap of Ge, making it very difficult to achieve high bandwidth and high responsivity at the same time. In Ge-based systems, it is necessary to use waveguide needle photodiodes or APDs to achieve high responsivity and high bandwidth.

[0127] The monolithic integration approach described in this article is used to reduce the parasitic capacitance of the photodiode detector and then adjust other parameters of the PIN and TIA to improve quantum efficiency, such as meeting the sensitivity and responsivity specifications for high-data-rate applications. It can also be extended to other types of photodiode detectors, such as single-transport carrier (UTC) photodiode device structures and waveguide PIN geometries.

[0128] The monolithic integration of PIN-TIA eliminates hybrid integration parasitics such as pad capacitance and wire bond resistance / inductance. The direct interconnection of PIN-TIA provides lower capacitance by eliminating pad capacitance and provides a direct (short length) lower inductance / lower resistance interconnection. The reduced pad capacitance provides the associated freedom, resulting in improved bandwidth and reduced noise for a given PIN diameter.

[0129] The responsivity can be improved by increasing the thickness of the absorbing layer U. All other things being equal, an integrated pin-TIA will allow for a larger total bandwidth.

[0130] A semiconductor mirror can be inserted below the multiplication region to increase reflectivity. Figure 19 The benefits of increasing absorptivity, reflectivity, or both are shown. Figure 19 The calculations are based on public data published in the article by J. Brouckaert et al. (J. Lightwave Technology, Vol. 25, No. 4, April 2007). It is worth noting that at 1577 nm, the refractive index contrast of the semiconductor mirror can be significantly greater than at 1.3 μm or even 1.50 μm. This is because due to the proximity between the InGaAs bandgap wavelength of 1577 nm and approximately 1650 nm, a lower bandgap and therefore higher refractive index semiconductor can be used for a higher refractive index transparent semiconductor. The mirror can be used to supplement or replace the lost (i.e. reduced) QE at 1577 nm. If the CPIN is reduced, thinner t-InGaAs (referred to as t in other paragraphs) can be used to reduce the QE. i ) can achieve the highest bandwidth, but at the expense of single-pass responsivity. As described in this article, mirrors can recycle a large amount of non-absorbed light. In principle, mirrors can be made to be close to 100% reflective, although this comes at the expense of dealing with topographic issues of thick mirrors. However, this problem has been solved by standard VCSEL processing, which relies on the same principles. On the other hand, for applications in ONU receivers operating at 1577nm, the refractive index contrast possible in said application means that close to 100% reflectivity can be achieved with fewer layers and therefore with a smaller thickness (i.e. relative to the thickness typically required for VCSELs), which is a process design advantage.

[0131] Further design improvements

[0132] In a prototype embodiment of a monolithically integrated PIN-TIA, fabricated using an InGaAs PIN and a TIA circuit containing InP HBTs, a responsivity of 0.69 A / W was achieved at 1550 nm. Based on the design approach described herein, this responsivity can be improved by one or more of the following:

[0133] Increased absorber thickness: For 1557nm OLT applications, there is room to increase the thickness U without approaching the bandwidth limit. Based on empirical data combining literature data and modeling, increasing the absorber thickness by a factor of just over 1.5 should give a 1dB improvement.

[0134] Mirror provided below the absorber layer or RCE: If a mirror is provided, we expect that for OLT applications, QEs of >90% (possibly 95%) are possible. For 25 GHz operation, we expect that QEs of over 85% (possibly 90%) are possible.

[0135] Reducing absorption in other layers, such as the p+ cap layer: The p+ cap layer provides reduced sheet and contact resistance for the p-type contact, but signal may be lost due to light absorption. For example, thinning the layer or choosing a material that is transparent to 1.577 μm but close to the bandgap, such as a lattice-matched InGaAlAsP composition (possibly quaternary, such as InGaAlAs or InGaAsP), may be slightly worse for sheet and contact resistance, but provide improved light transmission. This same composition could potentially be used for the higher refractive index layer of the mirror.

[0136] Anti-reflection coating: Anti-reflection coating optimized for 1.577μm operating wavelength is available

[0137] Monolithically Integrated PD-TIA of Other Embodiments

[0138] In other embodiments, the design principles of the monolithically integrated PIN-TIA disclosed herein (including InGaAs PINs and TIA circuits fabricated with InP HBTs) can be extended to the monolithic integration of other types of photodiodes with TIAs. Other types of photodiode detectors include, for example, unidirectional carrier (UTC) PDs; waveguide PINs; resonant enhancement cavity PDs; and global notifications. To the best of the applicant's knowledge, monolithic integration of these types of PDs with TIAs is generally not considered. However, to the extent that these device structures can be fabricated to be compatible with HBT technology, such as InP HBTs, or HBTs fabricated with other compatible semiconductor material systems, other options for monolithically integrated PD-TIAs with improved performance include the following types of PDs:

[0139] UTC (Uni-Train Carrier) PDTo further increase bandwidth, a UTC PD design could be used. The advantages of UTC are well known. This design is likely to be compatible with HBT technology.

[0140] Waveguide PIN Waveguide PINs can achieve responsivity as close to 100% as possible. For ultra-high speeds and near-100% responsivity, this may require the presence of a traveling wave electrical signal. Traveling waveguide PINs and modulators are well known in the literature.

[0141] Resonant Cavity Enhanced Photodiode (or Resonant Cavity Enhanced (RCE) PD) . This is an interesting choice because the basic idea is to use mirrors to obtain multiple, rather than just two, passes through the absorption region to obtain maximum absorption with minimum absorption layer thickness. This device structure also provides high selectivity of QE to wavelength, i.e. absorption of one wavelength is favored. This arrangement will work well for OLTs with a well-defined specific wavelength (e.g. 1577nm) or other applications where the wavelength is well defined. The flight time is quite fast because the absorption layer is thin and the performance is limited by the capacitance. Eliminating the pad capacitance by monolithic integration with the TIA provides an attractive way to achieve a minimum or at least significantly reduced absorption thickness limit for a given bandwidth to increase or maximize the advantages of resonant cavity enhancement.

[0142] APD Achieving bandwidths of 10 GHz and above is difficult with currently available APDs. Monolithic integration of the APD and TIA reduces the device capacitance (CAPD) of the APD, allowing for a better chance of achieving the required bandwidth through similar arguments as above. Si APDs are known to be far superior to InP-based APDs in terms of excess noise, as electrons are primarily injected into the multiplication region.

[0143] Despite significant improvements to InP-based APDs, the carrier ratio at high gain means that the gain-bandwidth (GBW) product is limited; this further means that additional improvements are needed to make InP APDs usable for ultra-high-speed applications. For monolithically integrated InP APD-TIAs, the goal is to try to reduce the carrier flight time. For a SAGCM (separate absorption, classification, charging and multiplication) APD, the flight time is multiplied by two, once for the carriers to reach the multiplication region and once for the multiplied carriers to return to the opposing contact region. In such a design, the PD capacitance increases, which is generally undesirable, but this increase in capacitance is compensated by a reduction in the capacitance of the monolithically integrated APD-TIA. The responsivity will be reduced due to the smaller absorption region, but the reduced absorption can be compensated by a semiconductor mirror stack, for example as described in reference

[15] . Figure 19 described.

[0144] Comparison with Silicon Photonics

[0145] Silicon photonics (SiPh) is well known for the integration of PDs with electronic circuits; for example, the integration of circuits with PDs, which can be needle-shaped PDs or APDs, waveguides, or circular (i.e., normal incidence) geometries. Many coherent communication applications require sufficiently fast PDs (typically needle-shaped photodiodes), for example to establish relative phase for QPSK and high-order QAM high-performance modulation schemes. Used in applications such as phase comparators. The circuits are very simple to implement in silicon technology. SiPh tends to use CMOS circuits with BJTs, for example for pads / macros, but not necessarily HBTs, which have significant advantages over BJTs for fts, etc. To the best of the applicant's knowledge, few SiPh applications use monolithically integrated PDs with TIAs, for example, this may be because efficient CMOS circuits require smaller geometries (i.e., characterized by shorter transistor gate lengths) than are economically efficient.

[0146] Figure 20 The chart in the figure illustrates this from a Moore's Law perspective (data from available data points plotted on Wikipedia a few years ago). Any technology below the photonic characteristic limit is suitable for silicon photonics. The gate length improvements of the past half century will soon reach the atomic limit. Silicon photonics has been possible since the early 2000s, but at that time, it was expensive. What makes SiPh economical now is the decline in the Moore's Law curve, which has caused silicon integrated circuits (ICs) to phase out technologies that are perfectly suitable for SiPh (such as 130nm gate length technology), forcing existing foundries to seek business in gate length technologies no longer used by silicon ICs. The technology required to manufacture the best TIAs is expensive, or manufacturing TIAs at leading-edge speeds using obsolete technologies is impossible or too costly due to the total die area required by the obsolete technology. For example, SiPh photonic ICs with acceptable performance can be manufactured using lower-cost Si process technologies, such as 0.13-0.25μm, on medium-diameter wafers (e.g., 8-inch), rather than using more expensive incumbent technologies, such as 5-14nm. Therefore, TIAs are not usually manufactured using SiPh technology.

[0147] Optical Line Terminal (OLT) for PON applications

[0148] In particular, for optical line terminals (OLTs) used in PON applications, there is another reason related to the PD itself that makes SiPh difficult to implement. 1577nm is close to (or may even exceed) the Ge bandgap energy. Ge's absorption at that wavelength is unfavorable relative to InGaAs. If we convert the absorption length (representing 1-1 / e, or 63% QE) to a flight time requirement, even if the device's capacitance is zero, Figure 21This argument is clearly illustrated in the graphs in Figure 1. The blue horizontal lines depict the hole (blue) and electron transit time limits (green) at 10 GHz and 100 GHz for OLT 1577 nm applications—there is sufficient absorption above these lines, and none below them. The vertical lines represent the target wavelength of interest for the 1577 nm OLT transmission wavelength and, therefore, the ONU receive wavelength for this particular application. Since the Ge curve falls below the horizontal line at 1577 nm, achieving good absorption in Ge is difficult for PDs with normal incidence geometry, while for InGaAs, this is readily achievable at 10 GHz and above, though not at 100 GHz. Furthermore, for a given InGaAs thickness, the QE for electron transport (see UTC argument below) is larger than that for hole transport (which dominates for normal incidence acicular structures, where the absorber layer is not very thin relative to the absorption length). Achieving good absorption in Ge is difficult for PDs with circular, or normal incidence, geometry, while it is readily achievable for InGaAs. Thus, while 1577 nm somewhat emphasizes the QE vs. bandwidth tradeoff for InGaAs, this same wavelength makes it very difficult to achieve acceptable QE for circular, normal-incidence, geometry-based Ge-based PDs. If the absorption coefficient is high enough, one would have to resort to waveguide geometries with Ge to (1) achieve this without scattering, etc., and (2) sufficiently match the traveling wave of the electrical signal to the very long waveguides required for high-speed waveguides.

[0149] Therefore, the realization of a monolithically integrated PIN-TIA with an Anode PD in SiPh presents design and manufacturing challenges and presents a "high resistance path" for practical applications. In contrast, the monolithic integration of InGaAs PINs and TIAs fabricated with InP HBTs, as described herein, provides a "reduced resistance" path for practical applications, such as for OLTs and ONUs operating at 1.270μm or 1.577μm. In the InGaAlAsP penternary system, other absorber materials lattice-matched to InP can be used, but of all these materials, InGaAs, which is lattice-matched to InP, has the lowest bandgap energy, a direct bandgap, and the highest absorption coefficient near 1.3μm or 1.5μm.

[0150] Industrial Applicability

[0151] At the time of filing US62 / 950,479, optical receivers for OLTs and ONUs used in 10G PON and high-speed data center interconnects used optical receivers that included hybrid integrated APDs and TIAs because APDs offer higher sensitivity at these operating wavelengths than currently available needle-type PDs. For example, for ONU receivers operating at a wavelength of 1577 nm, existing needle-type PDs lack sufficient sensitivity to replace APDs for this application. This is partly due to the limited transmitted laser power. In the future, with the availability of higher-power lasers and sufficiently sensitive needle-type PDs and TIAs, it may be possible to replace avalanche photodiodes and TIAs with needle-type photodiodes and TIAs. However, for 10G PON systems to operate at these wavelengths with available laser powers, according to current industry standards, another solution is required.

[0152] In the method described herein, a monolithically integrated PIN-TIA is disclosed that has comparable sensitivity to a hybrid APD-TIA. This paper presents a design methodology for optimizing the parameters of a monolithically integrated PIN-TIA to meet the required specifications for applications such as ONU and OLT optical receivers for 10G PON, operating in the wavelength range of about 1.5μm to about 1.3μm. The monolithic integration of the PIN and TIA and the direct on-chip interconnection of the PIN and TIA eliminate parasitic effects including pad capacitance and wire inductance, allowing for design improvements to improve performance. Specifically, by reducing the device capacitance CPIN of the PIN and designing the TIA accordingly to reduce the capacitance C TIA , reducing the combined device capacitance C PIN +C TIA , thereby improving sensitivity. Preferably, the device capacitance is reduced sufficiently so that other effects dominate, that is, the reduced device capacitance allows relevant degrees of freedom to select or optimize other device parameters to improve performance. For example, increasing the thickness of the i layer, ti, or including a reflector to create a dual channel for absorbed light, thereby effectively doubling the absorption length to twice ti, increases QE and responsivity (A / W). In combination with selecting or optimizing other device parameters, such as device area or diameter, a monolithically integrated PIN-TIA can be achieved, for example using an InGaAs PIN and a TIA circuit including InP HBTs, which provides sensitivity comparable to that of hybrid APD-TIAs currently used for the application.

[0153] In other embodiments, other types of PDs are monolithically integrated with the TIA using similar design principles to reduce PD capacitance and optimize other parameters, including the thickness of the i layer t i , or 2*t iThe effective absorber thickness (if including the mirror); the aperture or device area; the capacitance of the TIA and the feedback resistance of the TIA; and the improved performance of optical receivers for 10G PON and other high-speed data applications (such as optical interconnects for data centers and 5G applications).

[0154] While the embodiments of the present invention have been described and illustrated in detail, it should be clearly understood that the description is for illustration and example only and not for limitation, with the scope of the invention being limited only by the appended claims.

Claims

1. An optical receiver comprising a monolithically integrated photodiode (PD) and a transimpedance amplifier (TIA), wherein: An epitaxial layer stack is formed on a semi-insulating (SI) indium phosphide (InP) substrate, the epitaxial layer stack comprising a first plurality of semiconductor layers formed on the semi-insulating indium phosphide substrate, and a second plurality of semiconductor layers located on top of the first plurality of semiconductor layers; The transimpedance amplifier includes an indium phosphide heterojunction bipolar transistor (HBT) formed by the first plurality of semiconductor layers; The photodiode includes a PIN diode formed by the second plurality of semiconductor layers of the epitaxial layer stack, including an n-layer, an i-layer, and a p-layer; and The PIN diode is a vertical PIN diode with a top window, or a waveguide PIN diode with a side window; The p-type contact of the PIN diode is directly interconnected to the input of the transimpedance amplifier through a conductive trace to provide the device capacitance C of the PIN diode. PIN and the transimpedance amplifier's capacitance C TIA ;and Select Include C PIN 、C TIA , the thickness of the i layer t i , the area of the PIN diode and the transimpedance feedback resistor R of the transimpedance amplifier F The device parameters are set to values to provide an integrated PIN-TIA that meets the performance specifications, including the specified sensitivity and the specified responsivity at the operating wavelength. The optical receiver of claim 1 , wherein the i-layer comprises InGaAs.

3. The optical receiver of claim 1, wherein the i-layer is selected from other absorbing materials in the InGaAs and InGaAlAsP material systems that are lattice matched to InP.

4. The optical receiver according to any one of claims 1 to 3, wherein The PIN diode is a vertical PIN diode with a top window and includes a mirror below the i-layer to create a dual channel through the i-layer.

5. The optical receiver of claim 4, wherein the mirror comprises a multilayer quarter-wavelength stack of alternating high-index and low-index lattice-matched materials.

6. The optical receiver of claim 5, wherein the device parameters include the mirror thickness t of the multilayer quarter-wavelength stack. m , and wherein the thickness of the i layer is selected to be t i and the mirror thickness t m to obtain the desired quantum efficiency.

7. The optical receiver according to any one of claims 1 to 3, wherein C PIN and C TIA The value of provides at least one of the following: a)C PIN with C TIA Match; b)C PIN Approximately equal to C TIA ;and c)C PIN +C TIA The sum of is the smallest.

8. The optical receiver according to any one of claims 1 to 3, wherein C PIN ≤50fF.

9. The optical receiver according to any one of claims 1 to 3, wherein C PIN ≤30fF.

10. The optical receiver according to any one of claims 1 to 3, wherein C PIN ≤15fF.

11. The optical receiver of claim 1, wherein the specified sensitivity and the specified responsivity meet performance specifications of a receiver of an optical network unit (ONU) of 10 GPON.

12. The optical receiver of claim 11, wherein the device parameters are optimized for an operating wavelength of 1577 nm.

13. The optical receiver according to any one of claims 1 to 3, wherein the specified sensitivity and the specified responsivity meet performance specifications of a receiver of an optical line terminal (OLT) of a 10G PON.

14. The optical receiver of claim 13, wherein the device parameters are optimized for an operating wavelength of 1270 nm.

15. The optical receiver according to any one of claims 1 to 3, wherein the specified sensitivity is equal to or better than -28 dBm.

16. The optical receiver according to any one of claims 1 to 3, wherein the specified sensitivity is equal to or better than -30 dBm.

17. The optical receiver according to any one of claims 1 to 3, wherein the specified responsivity is ≥ 0.6 A / W.

18. The optical receiver according to any one of claims 1 to 3, wherein the specified responsivity is ≥ 0.8 A / W.

19. The optical receiver according to any one of claims 1 to 3, wherein the specified responsivity is ≥ 1.0 A / W.

20. The optical receiver according to any one of claims 1 to 3, having a quantum efficiency of ≥ 85% or more preferably ≥ 90%.

21. The optical receiver according to any one of claims 1 to 3, wherein the heterojunction bipolar transistor is characterized by f T ≥100GHz, the transimpedance amplifier has a bandwidth (BW) of ≥7.5GHz, C PIN ≤50fF, C TIA ≤50fF, Rf≥1500Ω.

22. The optical receiver according to claim 21, wherein C PIN ≤30fF, C TIA ≤30fF.

23. The optical receiver according to claim 21, wherein C PIN ≤15fF, C TIA ≤15fF.

24. The optical receiver according to any one of claims 1 to 3, wherein: The p-layer comprises a single layer or a multi-layer structure; and / or The i-layer (absorption layer) comprises a single-layer or multi-layer structure; and / or The n-layer includes a single-layer or multi-layer structure.

25. The optical receiver according to any one of claims 1 to 3, wherein the PIN diode is a vertical PIN diode having a top surface window, and comprises at least one of the following: a) the optical window of the PIN diode includes an anti-reflection coating optimized for the operating wavelength; b) the p+ cap layer of the PIN diode is selected to be substantially transparent at the operating wavelength; and c) The p+ cap layer is selected to have a thickness and optical properties that reduce or minimize optical losses, rather than reducing or minimizing the sheet resistance and contact resistance of the p-type contact.

26. An optical receiver for an optical line terminal (OLT) or an optical network unit (ONU) of a 10G passive optical network (PON), comprising: Monolithically integrated photodiode (PD) and transimpedance amplifier (TIA), where: An epitaxial layer stack is formed on a semi-insulating (SI) indium phosphide (InP) substrate, the epitaxial layer stack comprising a first plurality of semiconductor layers formed on the semi-insulating indium phosphide substrate, and a second plurality of semiconductor layers located on top of the first plurality of semiconductor layers; The transimpedance amplifier includes an indium phosphide heterojunction bipolar transistor (HBT) formed by the first plurality of semiconductor layers of the epitaxial layer stack; The photodiode comprises a PIN diode formed by the second plurality of semiconductor layers of the epitaxial layer stack, wherein the epitaxial layer stack comprises an n-layer, an i-layer, and a p-layer; the PIN diode is a vertical PIN diode having a top surface window, or a waveguide PIN diode having a side surface window; The p-type contact of the PIN diode is directly interconnected to the input of the transimpedance amplifier via a conductive trace; and The i-layer comprises an absorbing material selected for the operating wavelength of the optical line terminal or the optical network unit.

27. The optical receiver according to claim 26, used in an optical network unit, wherein the i-layer comprises a single layer or a multi-layer structure, the multi-layer structure comprising a material absorbing at 1577 nm.

28. The optical receiver according to claim 26, used for an optical line terminal, wherein the i-layer comprises a single layer or a multi-layer structure, the multi-layer structure comprising a material absorbing at 1270 nm.

29. The optical receiver of any one of claims 26 to 28, wherein the i-layer is selected from other absorbing materials of the InGaAs and InGaAlAsP material systems, which are lattice matched to InP.

30. The optical receiver of claim 26, wherein The PIN diode is a vertical PIN diode with a top window and includes a mirror below the i-layer to create a dual channel through the i-layer.

31. An optical receiver comprising a monolithically integrated photodiode (PD) and a transimpedance amplifier (TIA), wherein: An epitaxial layer stack is formed on a semi-insulating (SI) indium phosphide (InP) substrate, the epitaxial layer stack comprising a first plurality of semiconductor layers formed on the semi-insulating indium phosphide substrate, and a second plurality of semiconductor layers located on top of the first plurality of semiconductor layers; The transimpedance amplifier includes a heterojunction bipolar transistor (HBT) formed by the first plurality of semiconductor layers of the epitaxial layer stack; The photodiode is formed by the second plurality of semiconductor layers of the epitaxial layer stack; and the photodiode is a vertical photodiode having a top surface window, or a waveguide photodiode having a side surface window; The p-type contact of the photodiode is directly interconnected to the input of the transimpedance amplifier through a conductive trace to provide the capacitance C of the photodiode. PD and the transimpedance amplifier's capacitance C TIA ; in: Selecting device parameters includes: the C TIA and the C PD ; The thickness of the absorption layer of the photodiode t i The area of the photodiode; and the transimpedance feedback resistor R of the transimpedance amplifier F , to provide an integrated PD-TIA that meets the device specifications, including specified sensitivity and specified responsivity at the operating wavelength.

32. The optical receiver of claim 31, wherein the photodiode is one of the following: a PIN diode, an avalanche photodiode, a single carrier photodiode, and a resonant enhanced cavity photodiode.

33. The optical receiver of claim 32, wherein the PIN diode is a waveguide PIN diode; and / or The avalanche photodiode is one of the following: a SAGCM avalanche photodiode and a superlattice avalanche photodiode.

34. The optical receiver of claim 32, further comprising a mirror configured to produce a double pass through the absorbing layer.

35. The optical receiver of claim 31 , wherein the photodiode is a resonant cavity enhanced photodiode.

36. The optical receiver of claim 34, wherein the mirror comprises a multilayer quarter-wave stack of alternating high-index and low-index lattice-matched materials.

37. The optical receiver of claim 36, wherein the device parameters include the mirror thickness t of the multilayer quarter-wavelength stack. m and the thickness of the absorbing layer t i , where t is selected i and t m to obtain the desired quantum efficiency.

38. An optical receiver according to any one of claims 31 to 37, wherein C PD and C TIA The value of provides at least one of the following: a)C PD with C TIA Match; b)C PD Approximately equal to C TIA ;and c)C PD +C TIA The sum of is the smallest.

39. An optical receiver according to any one of claims 31 to 37, wherein C PD ≤50fF.

40. An optical receiver according to any one of claims 31 to 37, wherein C PD ≤30fF.

41. An optical receiver according to any one of claims 31 to 37, wherein C PD ≤15fF.

42. The optical receiver of claim 31, wherein the specified sensitivity and the specified responsivity meet performance specifications of a receiver of an optical network unit (ONU) of 10 GPON.

43. The optical receiver of claim 42, wherein the device parameters are optimized for an operating wavelength of 1577 nm.

44. The optical receiver of claim 31, wherein the specified sensitivity and responsivity meet performance specifications of a receiver of an optical line terminal (OLT) of a 10G PON.

45. The optical receiver of claim 44, wherein the device parameters are optimized for an operating wavelength of 1270 nm.

46. An optical receiver according to any one of claims 31 to 37, wherein the specified sensitivity is equal to or better than -28 dBm.

47. The optical receiver of any one of claims 31 to 37, wherein the specified sensitivity is equal to or better than -30 dBm.

48. The optical receiver according to any one of claims 31 to 37, wherein the quantum efficiency thereof is ≥ 85%.

49. The optical receiver according to any one of claims 31 to 37, wherein the quantum efficiency thereof is ≥ 90%.

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