Prediction Method of Chip Failure Parameters
By combining the test data segmentation processing and linear fitting model, the problem of low accuracy in chip failure parameter prediction is solved, and more accurate chip failure parameter prediction is achieved.
Patent Information
- Application Number
- CN202110107069.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2021-01-26
- Publication Date
- 2025-08-19
- Estimated Expiration
- 2041-01-26
AI Technical Summary
In the prior art, the prediction method of chip failure parameters has the problem of low accuracy, especially when chip failure is affected by multiple failure mechanisms, the existing methods fail to effectively reflect the real situation.
By processing the test data in segments, a linear fitting model of multiple model data segments is obtained, and a chip prediction failure model is obtained based on the model proportion of each model data segment. Combined with the linear fitting model and model proportion of each model data segment, a more comprehensive chip prediction failure model is obtained.
It improves the accuracy of chip prediction failure parameters, can more comprehensively reflect the distribution characteristics of test data, and improves the accuracy of prediction.
Smart Images
Figure CN114791553B_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor manufacturing, and in particular to a method for predicting chip failure parameters. Background Art
[0002] In semiconductor manufacturing, radiation exposure is used to accelerate the failure of the chip under test, allowing for quick chip failure assessment. Accelerated failure is a temporary, recoverable failure. Exposure to radioactive particles causes the transistors within the chip to fail. Typically, six or four transistors constitute a single bit, and the failure rate is relative to the number of failed bits.
[0003] Chip failure testing is based on industry standards (such as those of the JEDEC Joint Electron Device Engineering Council). Accelerated testing of a limited number of representative samples is used to predict performance under actual operating conditions. After obtaining the TTF (Time to Failure) data, a linear fit is used to predict the corresponding chip failure rate or time to failure based on a specific statistical model and formula transformation.
[0004] However, there are still many problems with the existing chip failure parameter prediction methods. Summary of the Invention
[0005] The technical problem solved by the present invention is to provide a method for predicting chip failure parameters, which can effectively improve the accuracy of the obtained chip prediction failure parameters.
[0006] In order to solve the above technical problems, the technical solution of the present invention provides a method for predicting chip failure parameters, comprising: providing a plurality of test chips; performing failure tests on the plurality of test chips to obtain N test data, each of which includes: a failure time and a chip failure rate corresponding to the failure time; segmenting the N test data to obtain n model data segments, each of which includes M i The test data, and the M i ≤N; obtain the linear fitting model of each segment of the model data; obtain the model proportion r of each segment of the model data relative to the test data i , the model accounts for r i =M i / N; obtaining a chip failure prediction model according to the linear fitting model of each model data segment and the model proportion of each model data segment.
[0007] Optionally, the chip failure parameter prediction method according to claim 1 is characterized in that the method of obtaining the linear fitting model of each segment of the model data segment includes: obtaining the characteristic value t of several failure times in each segment of the model data segment i 63.2, the characteristic value is the 63.2th percentile among several failure times; obtain the slope value m corresponding to each segment of the model data. i According to the characteristic value t i 63.2 and slope value m i , obtain the linear fitting model based on failure time and chip failure rate for each model data segment, namely:
[0008]
[0009] Optionally, the chip failure parameter prediction method according to claim 2 is characterized in that the method of obtaining the linear fitting model of each segment of the model data further comprises: obtaining the characteristic value t of several failure times in each segment of the model data i 50, the characteristic value is the 50th percentile of several failure times; obtain the slope value corresponding to each segment of the model data i According to the characteristic value t i 50 and slope value slope i , obtain the linear fitting model based on failure time and chip failure rate for each model data segment, namely:
[0010]
[0011] Among them, normsdist returns the standard normal cumulative distribution function.
[0012] Optionally, the chip failure parameter prediction method according to claim 2 is characterized in that, according to the linear fitting model of each segment of the model data and the model proportion of each segment of the model data, the method for obtaining the chip failure prediction model comprises: i Multiply by the corresponding linear fitting model to obtain the initial chip prediction failure model; superimpose the initial chip prediction failure models corresponding to each segment of the model data to obtain the chip prediction failure model, that is:
[0013]
[0014] Optionally, according to the linear fitting model of each model data segment and the model proportion of each model data segment, the method for obtaining the chip failure prediction model further includes: converting the model proportion r of each model data segment into iMultiply by the corresponding linear fitting model to obtain the initial chip prediction failure model; superimpose the initial chip prediction failure models corresponding to each segment of the model data to obtain the chip prediction failure model, that is:
[0015]
[0016] Optionally, after obtaining the chip prediction failure model, the method further includes: obtaining the chip prediction failure rate F according to the chip prediction failure model. c (t e ).
[0017] Optionally, the chip prediction failure rate F is obtained according to the chip prediction failure model. c (t e ) method includes: providing the expected failure time t e According to the expected failure time t e Substitute and the chip prediction failure model F(t) to obtain the chip prediction failure rate F c (t e ).
[0018] Optionally, after obtaining the chip prediction failure model, the method further includes: obtaining the chip prediction failure time t according to the chip prediction failure model. c .
[0019] Optionally, the chip predicted failure time t is obtained according to the chip predicted failure model c The method includes: providing the expected failure rate F e According to the expected failure rate F e =F(t c ) is substituted into the chip to obtain the predicted failure time t c .
[0020] Optionally, when obtaining the chip predicted failure rate F c (t e ), further comprising: predicting the failure rate F of the chip according to the c (t e ) to obtain the predicted number of chip failures in the millions.
[0021] Optionally, the method for obtaining the chip predicted failure rate ppm in the order of millions includes: c (t e ) multiplied by 1E6, that is, the number of chip failures predicted in the million order of magnitude ppm = F c (t e )*1E6.
[0022] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:
[0023] In the prediction method provided by the technical solution of the present invention, N test data are segmented to obtain n model data segments, each of which includes M i The test data, and the M i ≤N; obtaining a linear fitting model for each model data segment; obtaining the model ratio of each model data segment relative to the test data; and obtaining a chip failure prediction model based on the linear fitting model of each model data segment and the model ratio of each model data segment. By taking into account the linear fitting model of each model data segment and obtaining a weight according to the corresponding model ratio, the ultimately obtained chip failure prediction model more comprehensively reflects the distribution characteristics of the test data, thereby effectively improving the accuracy of chip failure prediction parameters subsequently obtained through the chip failure prediction model.
[0024] Furthermore, after obtaining the chip prediction failure model, the method further includes: obtaining the chip prediction failure time t according to the chip prediction failure model. c , and obtaining the chip prediction failure rate F according to the chip prediction failure model c (t e ). Obtain corresponding parameters according to different needs to meet the application in multiple scenarios.
[0025] Further, when obtaining the chip predicted failure rate F c (t e ), further comprising: predicting the failure rate F of the chip according to the c (t e ) to obtain the predicted number of chip failures in the millions, in order to meet the needs of applications in multiple scenarios. BRIEF DESCRIPTION OF THE DRAWINGS
[0026] Figure 1 This is a diagram of the test data distribution under a single failure mechanism;
[0027] Figure 2 It is a schematic diagram of the test data distribution under various failure mechanisms;
[0028] Figures 3 to 5 This is a schematic diagram of the processing of test data distribution under various failure mechanisms.
[0029] Figure 6 1 is a flow chart of a method for predicting chip failure parameters according to an embodiment of the present invention;
[0030] Figures 7 to 11It is a structural diagram of each step in a method for predicting chip failure parameters according to an embodiment of the present invention. DETAILED DESCRIPTION
[0031] As described in the background art, there are still many problems with the chip failure parameter prediction method in the prior art, which will be described in detail below with reference to the accompanying drawings.
[0032] Please refer to Figure 1 If a chip's failure is affected by only a single failure mechanism, the test data itself exhibits good linearity—that is, it exhibits a single-modal distribution—and the resulting linear fit is also very good. The test data includes the test time t and the chip failure rate F(t) corresponding to the test time t. Therefore, the chip failure rate predicted by the linear fit is also relatively accurate.
[0033] Please refer to Figure 2 When the failure of a chip is affected by multiple failure mechanisms, the test data itself will exhibit a bi-modal or multi-modal distribution.
[0034] The existing methods for processing bi-modal or multi-modal distribution data include: 1. Directly fitting different failure mechanisms without distinguishing them (e.g. Figure 3 2. Fit most of the data groups, and do not fit other data (such as Figure 4 3. Extract the first segment of data separately for fitting and treat it as the worst case (such as Figure 5 shown).
[0035] The aforementioned approaches either suffer from fitting distortion, leading to inaccurate predictions of chip failure parameters, or fail to consider the combined factors of multiple failures in real-world situations. Consequently, none of these approaches can truly reflect actual conditions, and the accuracy of the predicted chip failure parameters is low.
[0036] To address the aforementioned technical issues, an embodiment of the present invention provides a method for predicting chip failure parameters. This method obtains a chip failure prediction model based on the linear fitting model for each model data segment and the model proportion for each model data segment. By taking into account the linear fitting model for each model data segment and deriving weights based on the corresponding model proportions, the resulting chip failure prediction model more comprehensively reflects the distribution characteristics of the test data, thereby effectively improving the accuracy of subsequent chip failure prediction parameters obtained using the chip failure prediction model.
[0037] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.
[0038] Figure 6 FIG. 4 is a flow chart of a method for predicting chip failure parameters according to an embodiment of the present invention.
[0039] Please refer to Figure 6 , the chip failure parameter prediction method includes:
[0040] Step S11, providing a plurality of test chips;
[0041] Step S12, performing failure tests on a plurality of the test chips to obtain N test data, each of the test data including: a failure time and a chip failure rate corresponding to the failure time;
[0042] Step S13, segmenting the N test data to obtain n model data segments, each of which includes M i The test data, and the M i ≤N;
[0043] Step S14, obtaining a linear fitting model for each segment of the model data;
[0044] Step S15: Obtain the model proportion r of each segment of the model data relative to the test data i , the model accounts for r i =M i / N;
[0045] Step S16: Obtain a chip failure prediction model based on the linear fitting model of each model data segment and the model proportion of each model data segment.
[0046] The following is a detailed description with reference to the accompanying drawings.
[0047] Figures 7 to 11 It is a structural diagram of each step in the chip failure parameter prediction method according to an embodiment of the present invention.
[0048] Please refer to Figure 7 , providing several test chips 100.
[0049] In this embodiment, the test chips 100 are selected as a certain number of sample test chips. Subsequently, failure tests are performed on the test chips 100 to obtain a number of test data, and then the failure parameters of other chips in the same batch are predicted based on the test data.
[0050] Please refer to Figure 8, performing failure tests on a number of the test chips 100 to obtain N test data, each of the test data including: a failure time and a chip failure rate corresponding to the failure time.
[0051] In this embodiment, the method for performing failure testing on several of the test chips 100 includes: providing a test device (not shown); placing several of the test chips 100 in the failure testing device for failure testing; detecting the electrical parameters of each of the test chips 100; and obtaining the test data based on the electrical parameters.
[0052] In this embodiment, the method for obtaining the test data based on the electrical parameters includes: providing a reference threshold; comparing the electrical parameters with the reference threshold; when the electrical parameters are greater than the reference threshold, determining that the corresponding test chip 100 has failed, and obtaining the failure time corresponding to the failure of the test chip 100; obtaining the number of all failed test chips 100 at the failure time; and obtaining the chip failure rate corresponding to the failure time based on the proportion of the number of all failed test chips 100 relative to a number of test chips 100.
[0053] Please refer to Figure 9 , segment the N test data to obtain n model data segments 101, each of which includes M i The test data, and the M i ≤N.
[0054] In this embodiment, the method for performing segmentation processing on the N test data includes: providing a segmentation processing model; and performing segmentation processing on the N test data according to the segmentation processing model.
[0055] In this embodiment, the segmented processing model is based on grouping the test data with slope trends within a certain threshold range into the same model data segment 101 .
[0056] In this embodiment, the test data are divided into three model data segments 101, that is, n=3.
[0057] Please refer to Figure 10 , obtaining a linear fitting model for each of the model data segments 101.
[0058] In this embodiment, the method for obtaining the linear fitting model of each segment of the model data 101 includes: obtaining the characteristic values t of several failure times in each segment of the model data 101 i 63.2, the characteristic value is the 63.2th percentile among several failure times; obtain the slope value m corresponding to each segment of the model data 101 iAccording to the characteristic value t i 63.2 and slope value m i , obtain the linear fitting model based on failure time and chip failure rate for each model data segment 101, namely:
[0059]
[0060] In this embodiment, the linear fitting model is obtained based on the Weibull (Weibull distribution) statistical model.
[0061] In this embodiment, since the model data segments 101 are three, there are also three corresponding linear fitting models, namely F1(t), F2(t) and F3(t).
[0062] It should be noted that, after the test data are divided into three model data segments 101, the linear fitting model of each model data segment 101 is obtained separately. Therefore, the number of test data in each model data segment 101 can no longer be fitted as N, but needs to be fitted as the number of test data in each model data segment 101 M. i The linear fitting model is fitted, and the chip failure rate of each segment of the linear fitting model also needs to be fitted starting from 0.
[0063] In other embodiments, the linear fitting model can also be obtained based on a Lognormal (lognormal distribution) statistical model. The method for obtaining the linear fitting model of each segment of the model data further includes: obtaining characteristic values t of several failure times in each segment of the model data i 50, the characteristic value is the 50th percentile of several failure times; obtain the slope value corresponding to each segment of the model data i According to the characteristic value t i 50 and slope value slope i , obtain the linear fitting model based on failure time and chip failure rate for each model data segment, namely:
[0064]
[0065] Among them, normsdist returns the standard normal cumulative distribution function.
[0066] After obtaining the linear fitting model of each segment of the model data 101, the model proportion r of each segment of the model data 101 relative to the test data is obtained. i , the model accounts for r i =M i / N.
[0067] In this embodiment, since the model data segments 101 are three segments, the model proportions of the model data segments are r1, r2, and r3, respectively.
[0068] In this embodiment, the model proportion r of each segment of the model data relative to the test data is obtained. i The purpose is to take into account the linear fitting models under each model data segment and obtain weights according to the corresponding model proportions, so that the chip prediction failure model finally obtained can more comprehensively reflect the distribution characteristics of some of the test data, thereby effectively improving the accuracy of the chip prediction failure parameters subsequently obtained through the chip prediction failure model.
[0069] Please refer to Figure 11 , obtaining a chip failure prediction model according to the linear fitting model of each model data segment 101 and the model proportion of each model data segment.
[0070] In this embodiment, for N test chip samples, when the failure time t is determined, the total number S of failed test chips is:
[0071]
[0072] Therefore, the overall failure rate F(t) = S / N, that is:
[0073]
[0074] Therefore, in this embodiment, according to the linear fitting model of each segment of the model data and the model proportion of each segment of the model data, the method for obtaining the chip failure prediction model includes: i Multiply by the corresponding linear fitting model to obtain the initial chip prediction failure model; superimpose the initial chip prediction failure models corresponding to each segment of the model data to obtain the chip prediction failure model, that is:
[0075]
[0076] In this embodiment, by taking into account the linear fitting models under each model data segment and obtaining weights according to the corresponding model proportions, the chip prediction failure model finally obtained can more comprehensively reflect the distribution characteristics of some of the test data, thereby effectively improving the accuracy of the chip prediction failure parameters subsequently obtained through the chip prediction failure model.
[0077] In other embodiments, according to the linear fitting model of each model data segment and the model proportion of each model data segment, the method for obtaining the chip failure prediction model may further include: calculating the model proportion r of each model data segment. i Multiply by the corresponding linear fitting model to obtain the initial chip prediction failure model; superimpose the initial chip prediction failure models corresponding to each segment of the model data to obtain the chip prediction failure model, that is:
[0078]
[0079] After obtaining the chip prediction failure model, the method further includes: obtaining the chip prediction failure rate F according to the chip prediction failure model; c (t e ).
[0080] In this embodiment, the chip prediction failure rate F is obtained according to the chip prediction failure model. c (t e ) method includes: providing the expected failure time t e According to the expected failure time t e Substitute and the chip prediction failure model F(t) to obtain the chip prediction failure rate F c (t e ).
[0081] After obtaining the chip prediction failure model, the method further includes: obtaining the chip prediction failure time t according to the chip prediction failure model; c .
[0082] In this embodiment, the chip predicted failure time t is obtained according to the chip predicted failure model. c The method includes: providing the expected failure rate F e According to the expected failure rate F e =F(t c ) is substituted into the chip to obtain the predicted failure time t c .
[0083] In this embodiment, the chip predicted failure time t is obtained according to the chip predicted failure model. c , and obtaining the chip prediction failure rate F according to the chip prediction failure model c (t e ). Obtain corresponding parameters according to different needs to meet the application in multiple scenarios.
[0084] When obtaining the chip predicted failure rate F c (t e ), further comprising: predicting the failure rate F of the chip according to the c (te ) to obtain the predicted number of chip failures in the millions.
[0085] In this embodiment, the method for obtaining the chip predicted failure rate ppm in the order of millions includes: c (t e ) multiplied by 1E6, that is, the number of chip failures predicted in the million order of magnitude ppm = F c (t e )*1E6.
[0086] In this embodiment, according to the chip prediction failure rate F c (t e ) to obtain the predicted number of chip failures in the millions, in order to meet the needs of applications in multiple scenarios.
[0087] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.
Claims
1. A method for predicting chip failure parameters, characterized in that: include: Provide several test chips; Performing failure tests on a plurality of the test chips to obtain N test data, each of the test data including: a failure time and a chip failure rate corresponding to the failure time; The N test data are segmented to obtain n model data segments, each of which includes The test data, and the ≤N; Obtaining a linear fitting model for each segment of the model data; Get the model ratio of each segment of the model data relative to the test data , the model accounts for = / N; A chip failure prediction model is obtained according to the linear fitting model of each model data segment and the model proportion of each model data segment.
2. The chip failure parameter prediction method according to claim 1, wherein: The method for obtaining the linear fitting model of each segment of the model data includes: obtaining the characteristic values of several failure times in each segment of the model data , the characteristic value is the 63.2th percentile among several failure times; obtain the slope value m corresponding to each segment of the model data i According to the characteristic value and slope value m i , obtain the linear fitting model based on failure time and chip failure rate for each model data segment, namely: 。 3. The chip failure parameter prediction method according to claim 1, wherein: The method for obtaining the linear fitting model of each segment of the model data further includes: obtaining characteristic values of several failure times in each segment of the model data , the characteristic value is the 50th percentile of several failure times; obtain the slope value corresponding to each segment of the model data According to the characteristic value and slope values , obtain the linear fitting model based on failure time and chip failure rate for each model data segment, namely: ； Where normsdist returns the standard normal cumulative distribution function.
4. The chip failure parameter prediction method according to claim 2, wherein: According to the linear fitting model of each segment of the model data and the model proportion of each segment of the model data, the method for obtaining the chip failure prediction model includes: Multiply by the corresponding linear fitting model to obtain the initial chip prediction failure model; superimpose the initial chip prediction failure models corresponding to each segment of the model data to obtain the chip prediction failure model, that is: 。 5. The chip failure parameter prediction method according to claim 3, wherein: According to the linear fitting model of each segment of the model data and the model proportion of each segment of the model data, the method for obtaining the chip failure prediction model further includes: Multiply by the corresponding linear fitting model to obtain the initial chip prediction failure model; superimpose the initial chip prediction failure models corresponding to each segment of the model data to obtain the chip prediction failure model, that is: 。 6. The chip failure parameter prediction method according to claim 4 or 5, characterized in that: After obtaining the chip prediction failure model, the method further includes: obtaining the chip prediction failure rate according to the chip prediction failure model. .
7. The chip failure parameter prediction method according to claim 6, wherein: Obtaining chip predicted failure rate according to the chip predicted failure model Methods include: providing expected failure time ; Based on the expected failure time Substitute and the chip prediction failure model F(t) to obtain the chip prediction failure rate .
8. The chip failure parameter prediction method according to claim 4 or 5, characterized in that: After obtaining the chip prediction failure model, the method further includes: obtaining the chip prediction failure time according to the chip prediction failure model .
9. The chip failure parameter prediction method according to claim 8, wherein: Obtain chip predicted failure time according to the chip predicted failure model Methods include: providing expected failure rates ; Based on the expected failure rate Substitute to obtain the predicted failure time of the chip .
10. The chip failure parameter prediction method according to claim 6, wherein: Obtaining the chip predicted failure rate Afterwards, the method further includes: predicting the failure rate of the chip , obtain the predicted number of chip failures in the millions, ppm.
11. The chip failure parameter prediction method according to claim 10, wherein: The method for obtaining the chip predicted failure number ppm in the order of millions includes: Multiply by 1E6, that is, the number of chip failures predicted in the million order of magnitude ppm = *1E6.
Citation Information
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