Receiver, system, and method of operating the receiver

Abstract

The present application discloses a receiver, a system, and an operating method of the receiver. The receiver includes: a first matching circuit configured to receive antenna input power through a branch point based on a radio signal received by an antenna, and input a portion of the received antenna input power as a first input power to the first circuit, wherein the antenna input power is input from the antenna, and the impedance of the first matching circuit decreases as the antenna input power increases; and a second matching circuit configured to receive antenna input power through a branch point and input another portion of the received antenna input power as a second input power to the second circuit, wherein the impedance of the second matching circuit increases as the antenna input power increases.

Description

Technical Field

[0001] The present invention relates to a receiver, a system and a method of operating a receiver. Background Art

[0002] Radio communication devices that include a radio frequency identification (RFID) system and a cellular system with high transmission power are known. If the RFID system and the cellular system use the same frequency band, the radio section of the RFID system, which receives transmission signals from the cellular system, is driven by the transmission signal, causing an increase in spurious emissions. Therefore, a resonant circuit is provided in the power supply circuit of the radio section, which shifts the resonant frequency to a frequency outside the frequency band used when receiving transmission signals from the cellular system (see, for example, Patent Document 1). Furthermore, radio power receivers that include interleaved rectifiers or matching devices are known (see, for example, Patent Documents 2 and 3).

[0003] In RFID tags and other applications, radio signals received by the antenna are sometimes converted into multiple types of power to operate various types of internal circuits. However, methods for optimizing the power efficiency of each of these multiple types of power relative to antenna input power have not yet been proposed. For example, if there are differences in the power efficiency of the multiple types of power, the communication distance over which power can be received to operate the corresponding internal circuits is shortened on the side with lower power efficiency.

[0004] In one aspect, the present disclosure aims to optimize the power efficiency of each of multiple types of power in a receiver that converts a radio signal received through an antenna into the multiple types of power.

[0005] [Related technical literature]

[0006] [Patent Document]

[0007] [Patent Document 1] Japanese Patent Application Laid-Open No. 2015-39235

[0008] [Patent Document 2] International Patent Application No. 2019-530395, Japan National Publication

[0009] [Patent Document 3] Japanese Patent Application Laid-Open No. 2019-47205 Summary of the Invention

[0010] According to one aspect of the embodiment, a receiver includes: a first matching circuit, which is configured to receive antenna input power through a branch point according to a radio signal received by an antenna, and input a portion of the received antenna input power as a first input power to the first circuit, the antenna input power is input from the antenna, and the impedance of the first matching circuit decreases as the antenna input power increases; and a second matching circuit, which is configured to receive antenna input power through a branch point and input another portion of the received antenna input power as a second input power to the second circuit, and the impedance of the second matching circuit increases as the antenna input power increases.

[0011] In one aspect, according to the present disclosure, it is possible to optimize power efficiency of each of a plurality of types of power in a receiver that converts a radio signal received through an antenna into the plurality of types of power. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 is a block diagram illustrating an example of a system including a receiver according to an embodiment;

[0013] Figure 2 It shows Figure 1 A diagram showing an example of the impedance characteristics and power characteristics of a receiver in FIG.

[0014] Figure 3 is a block diagram illustrating an example of a system including a receiver according to another embodiment;

[0015] Figure 4 It shows Figure 3 FIG. 1 is a diagram showing an example of the power characteristics of RP2 and RP3 and a Smith chart;

[0016] Figure 5 It shows Figure 3 Graphs showing examples of power characteristics and power efficiency of P2L and P3L and Smith charts of Z2L and Z3L;

[0017] Figure 6 It shows Figure 3 FIGURE 1 is a diagram showing an example of a Smith chart of Z2, Z3, Z23, and Z1;

[0018] Figure 7 is a block diagram illustrating an example of a system including another receiver;

[0019] Figure 8 It shows Figure 7 Figure 2 shows the power characteristics and power efficiency of P2L and P3L and the Smith chart of Z2L and Z3L;

[0020] Figure 9 It shows Figure 7 FIGURE 1 is a diagram showing an example of a Smith chart of Z2, Z3, Z23, and Z1;

[0021] Figure 10 is a block diagram illustrating another example of a system including another receiver;

[0022] Figure 11 It shows Figure 10 FIG. 1 is a diagram showing an example of the power characteristics of RP2 and RP3 and a Smith chart;

[0023] Figure 12 It shows Figure 10 Graphs of the power characteristics and power efficiency of P2L and P3L and Smith charts of Z2L and Z3L; and

[0024] Figure 13 It shows Figure 10 Graph of an example of a Smith chart for Z2, Z3, Z23, and Z1 in FIG. DETAILED DESCRIPTION

[0025] Hereinafter, embodiments will be described with reference to the accompanying drawings.

[0026] Figure 1 An example of a system including a receiver according to an embodiment is shown. Figure 1 The system 100 shown in FIG. 1 includes an antenna 1, a receiver 2, and a circuit portion 3. The circuit portion 3 includes a first circuit 3a and a second circuit 3b and is mounted on, for example, a large-scale integrated circuit (LSI). The antenna 1 and the receiver 2 are connected by wires, and the receiver 2 is connected to each of the first circuit 3a and the second circuit 3b by wires. For example, the receiver 2 and the circuit portion 3 are mounted on a wiring board housed in a housing of the system 100. The antenna 1 may be incorporated into or mounted on the wiring board. By incorporating the antenna 1 into the wiring board, the size of the system 100 may be reduced.

[0027] For example, the system 100 is a radio frequency identification (RFID) tag, but the system 100 is not limited thereto. The circuit portion 3 including the first circuit 3a and the second circuit 3b is mounted on an LSI chip for RFID.

[0028] Antenna 1 receives a high-frequency radio signal RF transmitted from a reader / writer of an RFID tag and outputs an antenna input power PIN according to the received radio signal RF to receiver 2. Receiver 2 includes a first matching circuit 2a and a second matching circuit 2b connected in parallel, which are connected to antenna 1 via a branch point BN.

[0029] First matching circuit 2a includes a delay element and performs impedance matching. First matching circuit 2a inputs a portion of antenna input power PIN, input through branch point BN, as first input power PIN1 (first high-frequency input signal IN1) to first circuit 3a. First circuit 3a operates in response to receiving first input power PIN1. First matching circuit 2a includes a π-type circuit, a T-type circuit, or a distributed element circuit and is designed to decrease impedance as antenna input power PIN increases.

[0030] Second matching circuit 2b includes a delay element and performs impedance matching. Second matching circuit 2b inputs another portion of the antenna input power PIN, which is input through branch point BN, as second input power PIN2 (second high-frequency input signal IN2) to second circuit 3b. Second circuit 3b operates in response to receiving second input power PIN2. Second matching circuit 2b includes a π-type circuit, a T-type circuit, or a distributed element circuit and is designed to increase impedance as antenna input power PIN increases.

[0031] The delay amount of the delay element of the first matching circuit 2a is different from the delay amount of the delay element of the second matching circuit 2b. This allows the phases of the first input signal IN1 and the second input signal IN2 to be offset from each other. For example, the delay amount of the delay element of the first matching circuit 2a is set to 0°, and the delay amount of the delay element of the second matching circuit 2b is set to +90° or +45°. In other words, the phase of the second input signal IN2 is delayed by, for example, 90° or 45° relative to the phase of the first input signal IN1. Here, the delay amount is represented by the phase of the radio signal RF received by the antenna 1. For example, the delay amount of the delay elements of the first matching circuit 2a and the second matching circuit 2b is less than one period of the radio signal RF.

[0032] The delay amount of the delay element of the first matching circuit 2a can be set to 0°, and the delay amount of the delay element of the second matching circuit 2b can be set to -90° or -45°. Alternatively, the delay amount of the delay element of the first matching circuit 2a can be set to -45°, and the delay amount of the delay element of the second matching circuit 2b can be set to +45°. Furthermore, the delay amount of the delay element of the first matching circuit 2a can be set to +45°, and the delay amount of the delay element of the second matching circuit 2b can be set to -45°.

[0033] The delay amounts of the delay elements of the first matching circuit 2a and the second matching circuit 2b are set to values for a predetermined communication characteristic obtained in consideration of the impedance of the antenna 1 and the frequency characteristics of the impedances on the first circuit 3a side and the second circuit 3b side. In this case, the delay amounts of the delay elements of the first matching circuit 2a and the second matching circuit 2b can be set in consideration of the simplification of the first matching circuit 2a and the second matching circuit 2b.

[0034] Figure 2 Examples of the impedance and power characteristics of the receiver 2 are shown. That is, Figure 1 Examples of the operation method of the receiver 2 are shown. As shown in the impedance characteristic on the left side of Figure 2 the impedance of the first matching circuit 2a seen from the branch point BN toward the LSI is approximately inversely proportional to the antenna input power PIN. The impedance of the second matching circuit 2b seen from the branch point BN toward the LSI is approximately proportional to the antenna input power PIN. That is, the impedance of the first matching circuit 2a decreases as the antenna input power PIN increases, while the impedance of the second matching circuit 2b increases as the antenna input power PIN increases.

[0035] When the antenna input power PIN is small, the impedance of the first matching circuit 2a is high and the impedance of the second matching circuit 2b is low, so that most of the antenna input power PIN is supplied to the second circuit 3b as the second input power PIN2 (PIN1 < PIN2). When the antenna input power PIN is large, the impedance of the first matching circuit 2a is low and the impedance of the second matching circuit 2b is high, so that most of the antenna input power PIN is supplied to the first circuit 3a as the first input power PIN1 (PIN1 > PIN2). Therefore, as shown on the Figure 2 right side, when the antenna input power PIN exceeds the power value PINmin2, the second input power PIN2 exceeds the minimum power PIN2min at which the second circuit 3b can operate, and the second circuit 3b can start operating. At this time, since the impedance of the first matching circuit 2a is high and the first input power PIN1 is lower than the second input power PIN2, the first input power PIN1 does not reach the minimum power PIN1min at which the first circuit 3a can operate. Therefore, the first circuit 3a does not operate. Therefore, most of the antenna input power PIN can be used for the operation of the second circuit 3b to improve the power efficiency.

[0036] ​​When the antenna input power PIN exceeds the power value PINmin1, the first input power PIN1 exceeds the minimum power PIN1min at which the first circuit 3a can operate, and the first circuit 3a can begin operation. At this point, the impedance of the second matching circuit 2b is high, and the increase in the second input power PIN2 has reached its peak. Therefore, the supply of excess second input power PIN2 to the second circuit 3b is prevented. Therefore, the required minimum second input power PIN2 can be supplied to the second circuit 3b, while the remaining power can be used to operate the first circuit 3a, thereby improving power efficiency.

[0037] As described above, in this embodiment, the first input power PIN1 and the second input power PIN2 inputted according to the antenna input power PIN can approach an ideal power distribution characteristic. By making the delay amounts (phases) of the delay elements of the first matching circuit 2a and the second matching circuit 2b different from each other, the impedance change characteristics of the first matching circuit 2a and the second matching circuit 2b with respect to the antenna input power PIN can be reversed.

[0038] That is, the impedance of the first matching circuit 2a can decrease as the antenna input power PIN increases, while the impedance of the second matching circuit 2b can increase as the antenna input power PIN increases. Figure 2 As described above, the first input power PIN1 supplied to the first circuit 3a and the second input power PIN2 supplied to the second circuit 3b can be appropriately set according to the antenna input power PIN. Therefore, the first input power PIN1 and the second input power PIN2 can be appropriately allocated according to the size of the antenna input power PIN in the receiver 2, which converts the radio signal RF received through the antenna 1 into the multiple types of power, thereby optimizing the power efficiency of each of the multiple types of power.

[0039] Figure 3 An example of a system including a receiver in another embodiment is shown. Figure 1 For elements that are substantially the same as those in the examples, detailed description will be omitted. Figure 3 The system 102 shown in FIG. 1 includes an antenna 10, a receiver 20, an LSI 30, and an electronic paper 40. The electronic paper 40 is an example of an electronic device.

[0040] The receiver 20 includes a balun 21 and matching circuits 22, 23, and 24. The LSI 30 includes a first circuit 31 and a second circuit 32. The system 102 is, for example, an RFID battery-free electronic paper tag, but is not limited thereto. The LSI 30 is an LSI chip for RFID.

[0041] The receiver 20 receives the radio signal RF as an unbalanced signal from the antenna 10. The balun 21 is provided between the antenna 10 and the matching circuit 22, and converts the unbalanced signal received from the antenna 10 into a balanced signal and outputs the balanced signal to the matching circuit 22.

[0042] Matching circuit 22 is provided between balun 21 and branch points BN+ and BN- to perform impedance matching between balun 21 and branch points BN+ and BN-. For example, matching circuit 22 is a π-type circuit including elements 22a, 22b, 22c, and 22d. At least one of elements 22a, 22b, 22c, and 22d includes a delay element.

[0043] Matching circuit 23 is provided between branch points BN+ and BN- and first circuit 31 of LSI 30 to perform impedance matching between branch points BN+ and BN- and first circuit 31. For example, matching circuit 23 includes elements 23a, 23b, 23c, and 23d as a π-type circuit. At least one of elements 23a, 23b, 23c, and 23d includes a delay element. Matching circuit 23 outputs a portion of the antenna input power received through matching circuit 22 to first circuit 31 as the first input power. Here, the X symbol shown in element 23d indicates that element 23d is not implemented in this embodiment. In the embodiment described later, Figure 7 and Figure 10 , elements marked with an X are not implemented.

[0044] Matching circuit 24 is provided between branch points BN+ and BN- and second circuit 32 of LSI 30 to perform impedance matching between branch points BN+ and BN- and second circuit 32. For example, matching circuit 24 is a π-type circuit including elements 24a, 24b, 24c, and 24d. At least one of elements 24a, 24b, 24c, and 24d includes a delay element. Matching circuit 24 outputs another portion of the antenna input power received by matching circuit 22 to second circuit 32 as second input power. Figure 3 The symbol P (PB, P1, P23, P2, P3, P2L, and P3L) shown in FIG represents power. Figure 3 The symbols Z (ZB, Z1, Z23, Z2, Z3, Z2L, and Z3L) shown in the figure represent the impedance viewed in the direction of the arrow. Figures 4 to 6 Reference will be made to Figure 5 and Figure 6 Describes the powers P2L and P3L and the impedances Z1, Z23, Z2, Z3, Z2L, and Z3L.

[0045] here, Figure 3The elements in matching circuits 22, 23, and 24 shown in FIG are examples, and elements may be added or deleted. Matching circuits 22, 23, and 24 may include T-type circuits (including delay elements) or distributed element circuits (including delay elements) instead of π-type circuits. Matching circuit 22 is an example of a third matching circuit. Matching circuit 23 is an example of a first matching circuit. Matching circuit 24 is an example of a second matching circuit.

[0046] The first circuit 31 includes a power supply voltage generating circuit PS1, which generates a first power supply voltage for operating the electronic paper 40 based on the first input power (P2L) received from the matching circuit 23. The first circuit 31 is represented as an equivalent circuit including an input capacitor CP2 and an input resistor RP2. The second circuit 32 includes the power supply voltage generating circuit PS2, a communication circuit RF-COM, a logic circuit LG, and a FRAM (registered trademark). The second circuit 32 is represented as an equivalent circuit including an input capacitor CP3 and an input resistor RP3.

[0047] FRAM is an example of electrically rewritable nonvolatile memory. Power supply voltage generation circuit PS2 generates a second power supply voltage for operating communication circuit RF-COM, logic circuit LG, and FRAM based on the second input power (P3L) received from matching circuit 24. If the second power supply voltages used in communication circuit RF-COM, logic circuit LG, and FRAM differ in type, power supply voltage generation circuit PS2 can generate multiple types of second power supply voltages.

[0048] The communication circuit RF-COM performs a reception process of receiving a radio signal RF through the antenna 10 and a transmission process of transmitting the radio signal RF from the antenna 10. The communication circuit RF-COM transmits information included in the radio signal RF received by the antenna 10 and is an example of an extractor that extracts display information to be displayed on the electronic paper 40.

[0049] The logic circuit LG writes display information received from the communication circuit RF-COM into the FRAM. The logic circuit LG generates control signals to operate the electronic paper 40, reads display information to be displayed on the electronic paper 40 from the FRAM, and outputs the control signals and display information to the electronic paper 40. Furthermore, the logic circuit LG outputs transmission information to be transmitted from the antenna 10 to the communication circuit RF-COM. The logic circuit LG is an example of a control circuit.

[0050] The electronic paper 40 operates in response to receiving the first power voltage from the power voltage generating circuit PS1 , and performs an operation of rewriting the display of the electronic paper 40 according to a control signal received from the logic circuit LG.

[0051] The minimum value of the second power supply voltage at which the communication circuit RF-COM, the logic circuit LG, and the FRAM can operate is lower than the minimum value of the first power supply voltage at which the electronic paper 40 can operate. Therefore, even if the distance between the RFID tag and the reader / writer is large, the antenna input power is low, and the first power supply voltage required for rewriting the electronic paper 40 cannot be generated, by operating the second circuit 32, the electronic product code (EPC) of the RFID tag can be read from the reader / writer, and an item to which the RFID tag is attached can be identified from a long distance.

[0052] Here, the system 102 may include another electronic device instead of the electronic paper 40. In this case, the LSI 30 outputs a first power supply voltage for operating the electronic device from the first circuit 31 and outputs a control signal for controlling the operation of the electronic device from the second circuit 32.

[0053] Figures 4 to 6 Shown Figure 3 An example of electrical characteristics of the receiver 20 and the LSI 30 is given below. Hereinafter, for example, the frequency of the radio signal RF is 920 MHz, the minimum power at which the rewriting operation of rewriting the display of the electronic paper 40 can be performed is +20 dBm, and the minimum power at which the second circuit 32 (communication circuit RF-COM, logic circuit LG, and FRAM) can operate is -20 dBm.

[0054] For example, the input capacitor CP2 of the first circuit 31 of the LSI 30 is set to 3 pF, and the input capacitor CP3 of the second circuit 32 of the LSI 30 is set to 1 pF. Since the input resistor RP2 of the first circuit 31 and the input resistor RP3 of the second circuit 32 depend on power, Figure 4 The corresponding power characteristics are shown in .

[0055] The circuit constants of matching circuit 22 are 7.5 nH for element 22a, 1.4 nH for elements 22b and 22c, and 3.3 pF for element 22d. This achieves matching between 50 Ω on the antenna 10 and balun 21 side and 100 Ω on the branch points BN+ and BN- side, and a delay of 13.4°.

[0056] The circuit constants of the matching circuit 23 are 10 nH for element 23 a, 0 Ω for elements 23 b and 23 c, and no element 23 d is implemented. This achieves matching between 100 Ω on the branch points BN+ and BN- side and 100 Ω / / 3 pF (CP2) on the first circuit 31 side, and a delay of 0°.

[0057] The circuit constants of the matching circuit 24 are 100 nH for element 24a, 0.6 pF for elements 24b and 24c, and 23 nH for element 24d. This achieves matching between 100 Ω on the branch points BN+ and BN- side and 3.5 kΩ / / 1 pF (CP3) on the second circuit 32 side, as well as a -90° delay.

[0058] Figure 4 Shown Figure 3 1. Example of power characteristics and Smith chart of input resistors RP2 and RP3. Input resistors RP2 and RP3 are different from each other in power dependence and Smith charts due to their different applications.

[0059] Figure 5 It shows Figure 3 FIG is a diagram showing an example of the power characteristics and power efficiency of P2L and P3L and the Smith chart of Z2L and Z3L. That is, Figure 5 An example of the operating method of receiver 20 is shown. As shown in the Smith chart of Z2L, impedance Z2L has a downward sloping characteristic due to input capacitor CP2. As shown in the Smith chart of Z3L, impedance Z3L, which differs from impedance Z2L in application, also has different characteristics from impedance Z2L.

[0060] In the power characteristics of power P2L, which is the operating power of the electronic paper 40, the rewriting operation of the electronic paper 40 can be performed at power PM ≥ +20 dBm (i.e., power P2L ≥ +20 dBm), and the rewriting operation of the electronic paper 40 can be performed at approximately the theoretical limit value. Here, power PM is the maximum available power of the antenna 10 (the maximum power that can be supplied under optimal matching conditions).

[0061] In the power characteristic of power P3L as the operating power of the second circuit 32, the logic circuit LG and the like of the second circuit 32 are enabled with power PM≥-20dBm (ie, power P3L≥-20dBm) and can operate approximately at the theoretical limit value.

[0062] This allows the power efficiency of power P2L to be 0% around power P3L = -20 dBm, where the logic circuit LG and the like of the second circuit 32 begin to operate, as shown in the power efficiencies of P2L and P3L. Therefore, almost all of the antenna input power can be used to operate the logic circuit LG and the like of the second circuit 32.

[0063] Furthermore, this allows the power efficiency of the power P3L to be 5% or less around the power P2L = +20 dBm at which the electronic paper 40 begins to operate. Therefore, most of the antenna input power can be used to operate the electronic paper 40, and unnecessary power P3L can be prevented from being supplied to the logic circuit LG of the second circuit 32, etc. Therefore, the power efficiency can be optimized for each of the multiple power states (+20 dBm for rewriting the electronic paper 40 and -20 dBm for the second circuit 32).

[0064] Here, by partially integrating Figure 3 The matching circuits 22, 23, and 24 can reduce the number of components of the matching circuit and reduce the circuit size of the receiver 20. Therefore, the reliability of the system 102 can be improved by reducing the number of components, and the cost of the system 102 can be reduced.

[0065] For example, it is possible not to implement element 22d of matching circuit 22, element 23a of matching circuit 23, and element 24a of matching circuit 24. This is because the combined parallel admittance of element 22d (3.3 pF, +19.08 mS), element 23a (100 nH, -j1.73 mS), and element 24a (10 nH, -j17.30 mS) is +j0.05 mS (approximately 0), and the characteristics are hardly changed.

[0066] Figure 6 Shown Figure 3 1, Z2, Z3, Z23, and Z1. As shown in the Smith chart for Z2, impedance Z2 is adjusted to match 100Ω at +20dBm and to have a larger impedance as the power decreases. The reason for matching to 100Ω rather than 50Ω is to simplify the circuit of matching circuit 23.

[0067] As shown in the Smith chart of Z3, the impedance Z3 is adjusted by impedance matching to match 100Ω at -20 dBm due to the delay of -90° and has a larger impedance as the power increases.

[0068] As shown in the Smith chart of Z23, the impedance Z23 is adjusted to match 100Ω at +20dBm and -20dBm. As shown in the Smith chart of Z1, the impedance Z1 is adjusted to match 50Ω at +20dBm and -20dBm, which is the impedance on the antenna 10 side.

[0069] As described above, this embodiment achieves substantially the same effects as the previous embodiment. For example, it is possible to achieve ideal power distribution characteristics for the powers P2L and P3L corresponding to the antenna input power. By allowing the delay amounts (phases) of the delay elements of matching circuits 23 and 24 to differ from each other, the characteristics of impedances Z2L and Z3L with respect to changes in antenna input power can be set to be opposite to each other. That is, impedance Z2L can decrease as antenna input power increases, while impedance Z3L can increase as antenna input power increases.

[0070] Therefore, if Figure 5 As described above, the power P2L supplied to the first circuit 31 and the power P3L supplied to the second circuit 32 can be appropriately set according to the antenna input power. Therefore, in the receiver 20 that converts the radio signal RF received through the antenna 10 into multiple types of power, the powers P2L and P3L can be appropriately distributed according to the amplitude of the antenna input power, thereby optimizing power efficiency for each of the multiple types of power.

[0071] Compared to conventional methods, the maximum available power PM for obtaining the minimum power (+20 dBm) of the power P2L that operates the matching circuit 23 can be reduced. Therefore, for example, if the system 102 (RFID tag) is attached to a shelf or an item, the distance between the reader / writer that identifies the item by reading the EPC and the system 102 can be made longer (for example, three to ten times longer than conventional methods).

[0072] Therefore, the number of systems 102 that transmit information to the reader / writer can be increased. Here, the system 102 may include another electronic device instead of the electronic paper 40.

[0073] Figure 7 An example of a system including another receiver is shown. Figure 3 The same elements are denoted by the same reference numerals and detailed description is omitted. Figure 7 The system 104 shown in FIG. 1 includes an antenna 10, a receiver 20A, an LSI 30, and an electronic paper 40. The receiver 20A has Figure 3 The configuration of the receiver 20 is substantially the same as that of the receiver 20, except that the matching circuit 24A is included instead of Figure 3 1. The matching circuit 24 of the receiver 20 in FIG. 1. In the matching circuit 24A, the elements 24a and 24d are not implemented and the elements 24b and 24c are set to 16 pF.

[0074] Figure 8 and Figure 9 Shown Figure 7: An example of electrical characteristics of the receiver 20A in FIG. As in the above embodiment, the frequency of the radio signal RF is 920 MHz, the minimum power at which the rewriting operation of the electronic paper 40 can be performed is +20 dBm, and the minimum power at which the second circuit 32 (communication circuit RF-COM, logic circuit LG, and FRAM) can operate is -20 dBm.

[0075] like Figure 3 As shown, Figure 7 The input capacitor CP2 of the first circuit 31 is set to 3 pF, and the input capacitor CP3 of the second circuit 32 is set to 1 pF. The input resistors RP2 and RP3 have power dependence, and Figure 3 The input resistors RP2 and RP3 are the same. Therefore, the power characteristics of the input resistors RP2 and RP3 are the same as the Smith chart. Figure 4 The same as in .

[0076] The circuit constants of the matching circuit 22 are substantially the same as those of the above embodiment, and are 7.5 nH for element 22a, 1.4 nH for elements 22b and 22c, and 3.3 pF for element 22d. This achieves matching between 50 Ω on the antenna 10 and balun 21 side and 97-j17 Ω on the branch points BN+ and BN- side, as well as a delay of 13.4°.

[0077] As in the above-described embodiment, the circuit constant of matching circuit 23 is 10 nH for element 23a, 0 Ω for elements 23b and 23c, and no element 23d is implemented. This achieves matching between 100 Ω on the branch points BN+ and BN- side and 100 Ω / / 3 pF (CP2) on the first circuit 31 side, as well as a 0° delay. The circuit constant of matching circuit 24 is 1 pF for elements 24b and 24c, and no elements 24a and 24d are implemented. This reduces the amount of coupling on the second circuit 32 side.

[0078] Figure 8 Shown Figure 7 The power characteristics and power efficiency of P2L and P3L and the Smith chart examples of Z2L and Z3L are shown in Figure 2. Figure 6 The power characteristics of power P2L are the same as Figure 5 Therefore, the rewriting operation of the electronic paper 40 can be performed at a power PM≥+20dBm (ie, power P2L≥+20dBm) and can work under the theoretical limit value.

[0079] In summary, the operation of the logic circuit LG and the like of the second circuit 32 is enabled when PM ≥ 0 dBm (ie, P3L ≥ -20 dBm). Therefore, the maximum available power PM is reduced by nearly 20 dB relative to the theoretical limit. Figure 7 In the system 104, in order to make the logic circuit LG of the second circuit 32 work, it is necessary to compare Figure 3 Therefore, the distance between the reader / writer for identifying an item by reading the EPC and the system 104 becomes shorter (for example, one-third to one-tenth) than that of the above-described embodiment.

[0080] Figure 9 Shown Figure 7 Examples of Smith charts for Z2, Z3, Z23, and Z1. The Smith chart for Z2 is Figure 6 As shown in the Smith chart of Z3, the impedance Z3 is adjusted to be high regardless of the power to reduce the coupling amount.

[0081] As shown in the Smith chart of Z23, the impedance Z23 is adjusted to approximately 100Ω at +20 dBm. As shown in the Smith chart of Z1, the impedance Z1 is adjusted to match 50Ω at +20 dBm, that is, the impedance on the antenna 10 side.

[0082] Figure 10 Another example of a system including another receiver is shown. Figure 3 The same elements are denoted by the same reference numerals and detailed description is omitted. Figure 10 The system 106 shown in FIG. 1 includes an antenna 10, a receiver 20B, an LSI 30B, and an electronic paper 40. The receiver 20B has Figure 3 The configuration of the receiver 20 is substantially the same as that of the receiver 20, except that it includes matching circuits 22B and 24B instead of Figure 3 Matching circuits 22 and 24 in FIG.

[0083] LSI 30B has Figure 3 The configuration of the LSI 30 in FIG. 1 is substantially the same configuration except that the second circuit 32B is included instead of Figure 3 The second circuit 32B has the same Figure 3 The configuration of the second circuit 32 in FIG is substantially the same as that in FIG, except that the input capacitor CP3 is connected to the Figure 3 The input capacitor CP3 in is different.

[0084] Figures 11 to 13 Shown Figure 10An example of electrical characteristics of the receiver 20B is shown below. For example, the frequency of the radio signal RF is 920 MHz, the minimum power at which the rewriting operation of rewriting the display of the electronic paper 40 can be performed is +20 dBm, and the minimum power at which the second circuit 32 (communication circuit RF-COM, logic circuit LG, and FRAM) can operate is -20 dBm.

[0085] For example, the input capacitor CP2 of the first circuit 31 of the LSI 30B is set to 3 pF, and the input capacitor CP3 of the second circuit 32B of the LSI 30B is set to 3 pF. The power supply voltage generating circuit PS1 and the power supply voltage generating circuit PS2 have the same characteristics. The input resistor RP2 of the first circuit 31 and the input resistor RP3 of the second circuit 32 are dependent on power and are the same as each other. The power characteristics of the input resistors RP2 and RP3 are as follows: Figure 11 shown.

[0086] The circuit constant of matching circuit 22B is 0Ω for elements 24b and 24c, and elements 22a and 22d are not implemented. This achieves matching between 50Ω on the antenna 10 and balun 21 side and 50Ω on the branch points BN+ and BN- side, and a delay of 0°.

[0087] The circuit constant of the matching circuit 23 is Figure 3 The circuit constants of the matching circuit 23 in FIG. 2 are substantially the same, being 10 nH for element 23 a and 0 Ω for elements 23 b and 23 c, with element 23 d not being implemented. This achieves matching between 100 Ω on the branch points BN+ and BN- side and 100 Ω / / 3 pF (CP2) on the first circuit 31 side, as well as a 0° delay.

[0088] The matching circuit 23 and the matching circuit 24B have the same characteristics except for delay, only convert 100Ω to 100Ω, and basically have no matching function except for canceling the admittance of the input capacitor CP2 and the input capacitor CP3.

[0089] Figure 11 Shown Figure 10 : An example of the power characteristics and Smith chart of the input resistors RP2 and RP3 in FIG. The power characteristics of the input resistors RP2 and RP3 are identical to each other, and the Smith charts of the input resistors RP2 and RP3 are identical to each other.

[0090] Figure 12 Shown Figure 10: An example of the power characteristics and power efficiency of P2L and P3L in the figure and the Smith chart of Z2L and Z3L. In the power characteristic of power P2L, which is the operating power of the electronic paper 40, the rewrite operation of the electronic paper 40 can be performed at power PM ≥ +30dBm (i.e., power P2L ≥ +20dBm). In the power characteristic of power P3L, which is the operating power of the second circuit 32B, the logic circuit LG of the second circuit 32B, etc. can be performed at power PM ≥ -15dBm (i.e., power P3L ≥ -20dBm). As shown in the power efficiency of P2L and P3L, the optimal power efficiency is limited to a specific power condition (in this example, approximately 0dBm). Here, as shown in the Smith chart of Z2L and Z3L, the impedance Z2L and the impedance Z3L have the same characteristics.

[0091] Figure 13 Shown Figure 10 Figure 1 shows an example of a Smith chart for Z2, Z3, Z23, and Z1. As shown in the Smith chart for Z2, when the power P2L is -3dBm (0dBm when P2L and P3L are combined), the impedance Z2 is adjusted to match 100Ω, and as the power decreases, the impedance increases.

[0092] As shown in the Smith chart for Z3, when power P3L is -3 dBm (0 dBm when P2L and P3L are combined), impedance Z3 is adjusted to match 100 Ω, and as power increases, the impedance increases. The Smith charts for Z23 and Z1 are identical, and impedance Z23 and Z1 are adjusted to match 50 Ω at +0 dBm (two 100 Ω in parallel).

[0093] The above detailed description makes the features and advantages of the embodiments clear. The appended claims are intended to encompass the features and advantages of these embodiments without departing from the spirit and scope of the invention. Moreover, any improvements and modifications can be readily made by one of ordinary skill in the art. Therefore, it is not intended that the scope of the embodiments of the invention be limited to the above-described embodiments, but rather that appropriate modifications and equivalents can be incorporated into the embodiments as disclosed.

Claims

1. A receiver, comprising: a first matching circuit configured to receive antenna input power through a branch point according to a radio signal received by the antenna, and input a portion of the received antenna input power as a first input power to the first circuit, the antenna input power being input from the antenna; as well as a second matching circuit configured to receive the antenna input power through the branch point and input another portion of the received antenna input power as a second input power to a second circuit; At least one of the first matching circuit or the second matching circuit includes a delay element, which delays the phase of the first input signal or the phase of the second input signal, so that the impedance of the first matching circuit decreases as the antenna input power increases, while the impedance of the second matching circuit increases as the antenna input power increases, and the first input power supplied to the first circuit and the second input power supplied to the second circuit are controlled by the impedance of the first matching circuit and the impedance of the second matching circuit.

2. The receiver according to claim 1, in, When the antenna input power is less than a predetermined value, the first input power is less than the second input power, and When the antenna input power is greater than the predetermined value, the first input power is greater than the second input power.

3. The receiver according to claim 1, wherein The phase of the first input signal and the phase of the second input signal are different from each other, the first input signal is input to the first circuit as the first input power by the first matching circuit, and the second input signal is input to the second circuit as the second input power by the second matching circuit.

4. The receiver according to claim 3, wherein The delay element delays the phase of the second input signal relative to the phase of the first input signal.

5. The receiver according to claim 4, wherein The phase delay caused by the delay element is smaller than one period of the radio signal received by the antenna. 6 . The receiver according to claim 1 , further comprising a third matching circuit for matching the impedance between the antenna and the branch point, wherein the third matching circuit is provided between the antenna and the branch point.

7. A system comprising: a receiver comprising a first matching circuit and a second matching circuit, wherein the first matching circuit and the second matching circuit receive antenna input power through a branch point according to a radio signal received by an antenna, the antenna input power being input from the antenna; First Circuit; as well as Second circuit, The first matching circuit inputs a portion of the received antenna input power as the first input power to the first circuit, The second matching circuit inputs another part of the received antenna input power as the second input power to the second circuit, At least one of the first matching circuit or the second matching circuit includes a delay element, and the delay element delays the phase of the first input signal or the phase of the second input signal, so that the impedance of the first matching circuit decreases as the antenna input power increases, while the impedance of the second matching circuit increases as the antenna input power increases, and the first input power supplied to the first circuit and the second input power supplied to the second circuit are controlled by the impedance of the first matching circuit and the impedance of the second matching circuit. wherein the first input power enables the first circuit to operate, and The second input power enables the second circuit to operate.

8. The system of claim 7, further comprising an electronic device connected to the first circuit and the second circuit, in, The first circuit includes a first power supply voltage generating circuit for generating a first power supply voltage for operating the electronic device based on the first input power, and The second circuit includes: a second power supply voltage generating circuit for generating a second power supply voltage based on the second input power; and a control circuit for generating a control signal for operating the electronic device, and operating the control circuit through the second power supply voltage.

9. The system according to claim 8, in, The electronic device is electronic paper, Wherein, the second circuit further includes: a nonvolatile memory that stores display information to be displayed on the electronic paper, the nonvolatile memory being electrically rewritable, and an extractor that extracts display information included in a radio signal received by the antenna, and The control circuit has a function of writing the display information extracted by the extractor into the nonvolatile memory and a function of reading the display information from the nonvolatile memory and outputting the display information to the electronic paper.

10. The system according to any one of claims 7 to 9, further comprising a board on which the first matching circuit, the second matching circuit, the first circuit, and the second circuit are mounted, the antenna being incorporated into the board.

11. A method for operating a receiver, the receiver comprising a first matching circuit and a second matching circuit, wherein the first matching circuit and the second matching circuit receive antenna input power through a branch point based on a radio signal received by an antenna, the antenna input power being input from the antenna, the first matching circuit inputting a portion of the received antenna input power as first input power to the first circuit, and the second matching circuit inputting another portion of the received antenna input power as second input power to the second circuit, and at least one of the first matching circuit or the second matching circuit comprising a delay element, the method comprising: The phase of the first input signal or the phase of the second input signal is delayed by the delay element, so that as the antenna input power increases, the impedance of the first matching circuit decreases, and as the antenna input power increases, the impedance of the second matching circuit increases, and the first input power supplied to the first circuit and the second input power supplied to the second circuit are controlled by the impedance of the first matching circuit and the impedance of the second matching circuit.

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