A method of manufacturing a semiconductor device

Abstract

A method for fabricating a semiconductor device is disclosed. A substrate is provided, which includes a MRAM region and a logic region. A magnetic tunneling junction (MTJ) is formed on the MRAM region. An upper electrode is formed on the MTJ. A flowable chemical vapor deposition (FCVD) process is performed to form a first intermetal dielectric layer around the upper electrode and the MTJ.

Description

TECHNICAL FIELD

[0001] The present application relates to a method for fabricating a semiconductor device, and more particularly to a method for fabricating a magnetoresistive random access memory (MRAM) device. BACKGROUND

[0002] It is known that the magnetoresistance (MR) effect is an effect in which the resistance of a material changes with an applied magnetic field. The physical quantity is defined as the difference in resistance with and without a magnetic field divided by the original resistance, and is used to represent the rate of change in resistance. At present, the magnetoresistance effect has been successfully applied in the production of hard disks, and has important commercial application value. In addition, using the characteristic that the giant magnetoresistance material has different resistance values in different magnetization states, a magnetic random access memory (MRAM) can also be made, which has the advantage of being able to continue to retain stored data without power.

[0003] The magnetoresistance effect described above is also applied in the field of magnetic field sensors, for example, an electronic compass component in a mobile phone equipped with a global positioning system (GPS), which is used to provide information such as the user's moving direction. At present, there are various magnetic field sensing technologies on the market, such as anisotropic magnetoresistance (AMR) sensing elements, giant magnetoresistance (GMR) sensing elements, magnetic tunneling junction (MTJ) sensing elements, etc. However, the disadvantages of the above-mentioned prior art usually include: occupying a large chip area, expensive manufacturing process, high power consumption, insufficient sensitivity, and being easily affected by temperature changes, etc., and it is necessary to further improve. SUMMARY

[0004] One embodiment of the present application discloses a method for fabricating a semiconductor device. First, a substrate is provided, which includes an MRAM region and a logic region, then a magnetic tunneling junction (MTJ) is formed on the MRAM region, an upper electrode is formed on the MTJ, and a flowable chemical vapor deposition (FCVD) process is performed to form a first intermetallic dielectric layer around the upper electrode and the MTJ. BRIEF DESCRIPTION OF DRAWINGS

[0005] Figures 1 to 6A flow diagram of a method of fabricating an MRAM cell for an embodiment of the present invention.

[0006] Explanation of main element symbols

[0007] 12: substrate

[0008] 14: MRAM region

[0009] 16: logic region

[0010] 18: ILD

[0011] 20: metal interconnect structure

[0012] 22: metal interconnect structure

[0013] 24: IMD

[0014] 26: metal interconnect

[0015] 28: stop layer

[0016] 30: IMD

[0017] 32: metal interconnect

[0018] 34: barrier layer

[0019] 36: metal layer

[0020] 38: MTJ stack

[0021] 42: lower electrode

[0022] 44: pinned layer

[0023] 46: barrier layer

[0024] 48: free layer

[0025] 50: upper electrode

[0026] 52: MTJ

[0027] 56: capping layer

[0028] 58: spacer

[0029] 60: spacer

[0030] 62: IMD

[0031] 70: metal interconnect

[0032] 72: stop layer

[0033] 74: IMD

[0034] 76: metal interconnect

[0035] 78: Stop Layer Detailed Implementation

[0036] Please refer to Figures 1 to 6 , Figures 1 to 6 This is a schematic diagram illustrating a method for fabricating an MRAM cell according to an embodiment of the present invention. Figure 1 As shown, a substrate 12 is first provided, for example, a substrate 12 made of a semiconductor material, wherein the semiconductor material can be selected from the group consisting of silicon, germanium, silicon-germanium composite, silicon carbide, gallium arsenide, etc., and an MRAM region 14 and a logic region 16 are preferably defined on the substrate 12.

[0037] The substrate 12 may contain active (active) devices such as metal-oxide-semiconductor (MOS) transistors, passive (passive) devices, conductive layers, and dielectric layers such as interlayer dielectric (ILD) 16 covering it. More specifically, the substrate 12 may contain planar or non-planar (such as fin structure transistors) MOS transistor devices, wherein the MOS transistors may include gate structures (such as metal gates) and source / drain regions, spacers, epitaxial layers, contact hole etch stop layers, and other transistor elements. The interlayer dielectric layer 18 may be disposed on the substrate 12 and cover the MOS transistors, and the interlayer dielectric layer 18 may have multiple contact plugs electrically connecting the gate and / or source / drain regions of the MOS transistors. Since the fabrication processes of planar or non-planar transistors and interlayer dielectric layers are well known in the art, they will not be described in detail here.

[0038] Then, metal interconnect structures 20 and 22 are sequentially formed on the interlayer dielectric layer 18 to electrically connect the aforementioned contact plug. The metal interconnect structure 20 includes an intermetal dielectric layer 24 and a metal interconnect 26 embedded in the intermetal dielectric layer 24. The metal interconnect structure 22 includes a stop layer 28, an intermetal dielectric layer 30, and a metal interconnect 32 embedded in the stop layer 28 and the intermetal dielectric layer 30.

[0039] In this embodiment, each metal interconnect 26 in metal interconnect structure 20 preferably comprises a trench conductor, and each metal interconnect 32 in metal interconnect structure 22 disposed in MRAM region 14 comprises a via conductor. In addition, each metal interconnect 26, 32 in each metal interconnect structure 20, 22 can be embedded in intermetal dielectric layer 24, 30 and / or stop layer 28 and electrically connected to each other according to a single damascene process or a dual damascene process. For example, each metal interconnect 26, 32 can further comprise a barrier layer 34 and a metal layer 36, wherein barrier layer 34 can be selected from a group consisting of titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN), and metal layer 36 can be selected from a group consisting of tungsten (W), copper (Cu), aluminum (Al), titanium aluminum alloy (TiAl), cobalt tungsten phosphide (CoWP), and the like, but not limited thereto. Since the single damascene or dual damascene process is well known in the art, no further elaboration is provided herein. In addition, metal layer 36 in metal interconnect 26 preferably comprises copper, metal layer 36 in metal interconnect 32 preferably comprises tungsten, intermetal dielectric layer 24, 30 preferably comprises silicon oxide such as tetraethylorthosilicate (TEOS), and stop layer 28 comprises a nitrogen doped carbide (NDC) layer, silicon nitride, or silicon carbon nitride (SiCN), but not limited thereto.

[0040] Next, a lower electrode 42, an MTJ stack structure 38, an upper electrode 50, and a patterned mask (not shown) are formed on the metal interconnect structure 22. In this embodiment, the MTJ stack structure 38 can be formed by first sequentially forming a pinned layer 44, a barrier layer 46, and a free layer 48 on the lower electrode 42. In this embodiment, the lower electrode 42 and the upper electrode 50 preferably contain conductive materials, such as, but not limited to, tantalum (Ta), tantalum nitride (TaN), platinum (Pt), copper (Cu), gold (Au), and aluminum (Al). The pinned layer 44 may contain ferromagnetic materials such as, but not limited to, cobalt-iron-boron (CoFeB), cobalt-iron (CoFe), iron (Fe), and cobalt (Co). Furthermore, the fixing layer 44 can also be made of an antiferromagnetic (AFM) material, such as iron-manganese (FeMn), platinum-manganese (PtMn), iridium-manganese (IrMn), nickel oxide (NiO), etc., to fix or restrict the magnetic moment direction of adjacent layers. The barrier layer 46 can be made of an insulating material containing oxides, such as aluminum oxide (AlO). x The free layer 48 can be made of ferromagnetic materials, such as iron, cobalt, nickel, or their alloys such as cobalt-iron-boron (CoFeB), but is not limited to these. The magnetization direction of the free layer 48 can be "freely" changed by an external magnetic field.

[0041] Subsequently, as Figure 2 As shown, a patterned mask is used as the mask to perform one or more etching processes to remove a portion of the upper electrode 50, a portion of the MTJ stack structure 38, a portion of the lower electrode 42, and a portion of the intermetallic dielectric layer 30 to form multiple MTJs 52 in the MRAM region 14. It is worth noting that the etching process performed on the patterned upper electrode 50, MTJ stack structure 38, lower electrode 42, and intermetallic dielectric layer 30 in this embodiment may include reactive ion etching (RIE) and / or ion beam etching (IBE). Due to the characteristics of the ion beam etching process, the remaining upper surface of the intermetallic dielectric layer 30 is preferably slightly lower than the upper surface of the metal interconnect 32, and the upper surface of the intermetallic dielectric layer 30 preferably presents an arc or curved surface. It should also be noted that when removing part of the intermetallic dielectric layer 30 using the ion beam etching process in this embodiment, it is preferable to remove part of the metal interconnects 32 at the same time, so that the metal interconnects 32 form an inclined sidewall near the junction of MTJ 52.

[0042] A masking layer 56 is then formed on the MTJ 52 and covers the surface of the inter-metal dielectric layer 30 of the MRAM region 14 and the logic region 16. In this embodiment, the masking layer 56 preferably comprises silicon nitride, but other dielectric materials such as, but not limited to, silicon oxide, silicon oxynitride, or silicon carbide may be selected according to the fabrication process requirements.

[0043] Then as Figure 3 As shown, firstly, a portion of the masking layer 56 is removed using etch-back to form spacer walls 58 and 60 on the sidewalls of each MTJ 52. Then, a flowable chemical vapor deposition (FCVD) process is performed, using a temperature below 100 degrees Celsius to form an intermetallic dielectric layer 62 covering each MTJ 52 and the intermetallic dielectric layer 30 of the logic region 16. In this embodiment, the intermetallic dielectric layer 62 preferably comprises an ultra-low dielectric constant dielectric layer, such as a porous dielectric material, for example, but not limited to silicon carbide (SiOC) or silicon carbide hydrogen (SiOCH). It should be noted that after forming the intermetallic dielectric layer 62 using the aforementioned FCVD process, at this stage, the top surface of the intermetallic dielectric layer 62 of the logic region 16 is preferably slightly lower than the top surface of the intermetallic dielectric layer 62 of the MRAM region 14, wherein the height difference between the intermetallic dielectric layer 62 of the MRAM region 14 and the logic region 16 is preferably approximately 400 angstroms.

[0044] like Figure 4 As shown, a planarization process is then performed, for example, by using chemical mechanical polishing (CMP) to remove part of the intermetallic dielectric layer 62 between the MRAM region 14 and the logic region 16, so that the top of the intermetallic dielectric layer 62 between the MRAM region 14 and the logic region 16 is approximately flush.

[0045] Then as Figure 5As shown, a pattern transfer fabrication process is performed to remove portions of the intermetal dielectric layer 62, portions of the intermetal dielectric layer 30 and portions of the stop layer 28 in the logic region 16 to form contact holes (not shown) and expose the underlying metal interconnects 26 using, for example, a patterned mask (not shown). The contact holes are then filled with desired metal materials, such as barrier layer materials including titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), etc. and low resistance metal layers selected from tungsten (W), copper (Cu), aluminum (Al), titanium aluminum (TiAl), cobalt tungsten phosphide (CoWP), etc. or combinations thereof. A planarization fabrication process, such as a chemical mechanical polishing fabrication process, is then performed to remove portions of the metal materials to form contact plugs or metal interconnects 70 in the contact holes to electrically connect the metal interconnects 26.

[0046] Subsequently, as shown in Figure 6 a stop layer 72 is formed in the MRAM region 14 and the logic region 16 and over the intermetal dielectric layer 62 and the metal interconnects 70, an intermetal dielectric layer 74 is formed over the stop layer 72, and one or more photolithography and etching fabrication processes are performed to remove portions of the intermetal dielectric layer 74, portions of the stop layer 72 and portions of the intermetal dielectric layer 62 in the MRAM region 14 and the logic region 16 to form contact holes (not shown). The contact holes are then filled with conductive materials and in conjunction with a planarization fabrication process, such as CMP, to form metal interconnects 76 in the MRAM region 14 and the logic region 16 to electrically connect the underlying MTJ 52 and the metal interconnects 70, respectively, wherein the metal interconnects 76 in the MRAM region 14 preferably directly contact the underlying top electrode 50 and the metal interconnects 76 in the logic region 16 contact the underlying metal interconnects 70. Another stop layer 78 is then formed over the intermetal dielectric layer 70 and over the metal interconnects 76.

[0047] In this embodiment, the stop layer 72 and the stop layer 78 can comprise the same or different materials, both of which can be selected from the group consisting of a nitrogen doped carbide (NDC), silicon nitride, and silicon carbon nitride (SiCN). The metal interconnects 76 disposed in the ILD layer 74 can be embedded in the ILD layer 74 according to a single damascene process or a dual damascene process, as previously described for the metal interconnects formed in the ILD layer 74. For example, the metal interconnects 76 can further comprise a barrier layer selected from the group consisting of titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN), and a metal layer selected from the group consisting of tungsten (W), copper (Cu), aluminum (Al), titanium aluminum (TiAl), cobalt tungsten phosphide (CoWP), and the like, but not limited thereto. Since the single damascene or dual damascene process is well known in the art, further description is not provided herein. Thus, the fabrication of the semiconductor device according to this embodiment of the present application is completed.

[0048] In summary, compared to the conventional method of forming an ILD layer over the MTJ and logic regions using an atomic layer deposition (ALD) process or a plasma-enhanced chemical vapor deposition (PECVD) process, the preferred embodiment of the present application uses a flowable chemical vapor deposition (FCVD) process to form the ILD layer 62 over the MTJ 52 and the ILD layer 30 over the logic region 16. This results in a lower height difference between the ILD layer 62 of the MRAM region 14 and the ILD layer 62 of the logic region 16 at the initial deposition stage, which allows the subsequent chemical mechanical polishing (CMP) process to remove the ILD layer 62 of both regions more uniformly and ensures the overall planarity of the MRAM region 14 and the logic region 16.

[0049] The above description is only preferred embodiments of the application. Any equivalent changes and modifications made according to the claims of the present application should be covered by the scope of the present application.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, Include: A substrate is provided, which includes a magnetoresistive random access memory region and a logic region; A magnetic tunneling junction (MTJ) is formed in the region of the magnetoresistive random access memory. An upper electrode is formed on the magnetic tunnel junction; A flowable chemical vapor deposition (FCVD) process is used to form a first intermetallic dielectric layer surrounding the upper electrode and the magnetic tunnel junction. A second intermetallic dielectric layer is formed on the magnetoresistive random access memory region and the logic region; A first metal interconnect is formed within the second metal inter-dielectric layer of the magnetoresistive random access memory region. The magnetic tunnel junction is formed on the first metal interconnect. The first intermetallic dielectric layer is formed in the magnetoresistive random access memory region and the logic region; Remove the first intermetallic dielectric layer of the logic region; as well as A second metal interconnect is formed on this logic region.

2. The method of claim 1, wherein the top surface of the upper electrode is lower than the top surface of the second metal interconnect.

3. The method of claim 1, further comprising: A stop layer is formed on the first intermetallic dielectric layer; A third intermetallic dielectric layer is formed on the stop layer; and A third metal interconnect is formed in the magnetoresistive random access memory region to connect the upper electrode, and a fourth metal interconnect is formed in the logic region to connect the second metal interconnect.

4. The method of claim 1, wherein the top surface of the first intermetallic dielectric layer of the logic region is lower than the top surface of the first intermetallic dielectric layer of the magnetoresistive random access memory region.

5. The method of claim 4, wherein the height difference between the first intermetallic dielectric layer of the logic region and the first intermetallic dielectric layer of the magnetoresistive random access memory region is less than 400 angstroms.

6. The method of claim 1, further comprising planarizing the first intermetallic dielectric layer after performing the flowable chemical vapor deposition fabrication process.

7. The method of claim 6, wherein the planarization process comprises a chemical mechanical polishing process.

8. A method for manufacturing a semiconductor device, characterized in that, Include: A substrate is provided, which includes a magnetoresistive random access memory region and a logic region; A magnetic tunneling junction (MTJ) is formed in the region of the magnetoresistive random access memory. An upper electrode is formed on the magnetic tunnel junction; and A flowable chemical vapor deposition (FCVD) process is performed to form a first intermetallic dielectric layer surrounding the upper electrode and the magnetic tunnel junction, wherein the top surface of the first intermetallic dielectric layer in the logic region is lower than the top surface of the first intermetallic dielectric layer in the magnetoresistive random access memory region.

9. The method of claim 8, wherein the height difference between the first intermetallic dielectric layer of the logic region and the first intermetallic dielectric layer of the magnetoresistive random access memory region is less than 400 angstroms.

10. The method of claim 8, further comprising planarizing the first intermetallic dielectric layer after performing the flowable chemical vapor deposition fabrication process.

Images