Vertical Cavity Surface Emitting Laser and Its Fabrication Method

Abstract

The present invention provides a vertical cavity surface emitting laser and a method for manufacturing the same. In the vertical cavity surface emitting laser, a tunneling junction is used to effectively connect multiple active layers in series, so as to increase the power per unit area. By optimizing the tunneling junction, an N-type atomic layer is provided in the N-type doped layer and a P-type atomic layer is provided in the P-type doped layer, so that the doping concentration in the tunneling junction is higher and the crystal quality of the semiconductor material is not damaged, which is beneficial to reducing the tunneling difficulty, increasing the tunneling current of carriers, and simultaneously improving the problem of the relatively large absorption coefficient of the tunneling junction and reducing the internal loss.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and particularly relates to a vertical cavity surface emitting laser and a preparation method thereof. Background Art

[0002] Vertical cavity surface emitting lasers (VCSELs) have been applied in the field of data communication for more than twenty years, but many emerging application requirements are driving the mass production and performance improvement of VCSELs. These applications include, but are not limited to, face recognition, gesture recognition, proximity sensing, high-resolution video display, automotive lidar, infrared illumination, infrared heating, and atomic clocks.

[0003] Currently, single-junction VCSELs widely used in mobile phones can only achieve tests at distances of dozens of meters, which is difficult to meet long-distance tests and cannot meet the requirements of vehicle-mounted radars. To achieve long-distance tests, it is necessary to develop a vertical cavity surface laser with higher power within an effective area. For this reason, multi-junction VCSELs have been proposed. Specifically, the multi-junction VCSEL utilizes active layers in a tunneling junction stacked cavity to connect the active layers in series, so as to increase the gain and improve the output power of the VCSEL per unit area.

[0004] However, the performance of existing multi-junction VCSELs still needs to be improved, and an important factor affecting the device performance lies in the performance of the tunneling junction. Generally, the tunneling difficulty can be reduced by highly doping the semiconductor material in the tunneling junction. However, when highly doping the semiconductor material, the high-concentration impurities are likely to damage the crystal quality, resulting in an increase in the absorption coefficient of the tunneling junction and an increase in internal loss. Therefore, this also limits the doping concentration in the tunneling junction from being increased. Summary of the Invention

[0005] The purpose of the present invention is to provide a vertical cavity surface emitting laser to solve the problems of large tunneling difficulty and low tunneling current in the tunneling junction of the existing vertical cavity surface emitting laser.

[0006] To solve the above technical problems, the present invention provides a vertical cavity surface emitting laser, including: at least two active layers formed on a substrate, and a tunneling junction is arranged between adjacent active layers, and the tunneling junction includes an N-type doping layer and a P-type doping layer. Among them, the N-type doping layer includes an N-type semiconductor layer doped with N-type impurities and an N-type atomic layer, and the N-type atomic layer is composed of at least two N-type impurity atoms; the P-type doping layer includes a P-type semiconductor layer doped with P-type impurities and a P-type atomic layer, and the P-type atomic layer is composed of at least two P-type impurity atoms.

[0007] Optionally, the N-type doped layer includes at least two N-type semiconductor layers, and the N-type atomic layer is disposed between adjacent N-type semiconductor layers; the P-type doped layer includes at least two P-type semiconductor layers, and the P-type atomic layer is disposed between adjacent P-type semiconductor layers.

[0008] Optionally, the N-type atomic layer is composed of at least two atoms selected from tellurium, selenium, silicon, and sulfur; and / or, the P-type atomic layer is composed of at least two atoms selected from carbon, magnesium, zinc, and beryllium.

[0009] Optionally, the thickness of the N-type atomic layer is less than or equal to 2.5 nm; and / or, the thickness of the P-type atomic layer is less than or equal to 1.5 nm.

[0010] Optionally, the thickness of the N-type doped layer ranges from 10 nm to 60 nm; and / or, the thickness of the P-type doped layer ranges from 5 nm to 40 nm.

[0011] Optionally, the P-type doped layer has a first thickness, the N-type doped layer has a second thickness, and the ratio of the first thickness to the second thickness is 3N / 4, where N is an integer greater than or equal to 1.

[0012] Optionally, the N-type doped layer further includes an intrinsic semiconductor layer, and the intrinsic semiconductor layer is located at the bottom layer and / or the top layer of the N-type doped layer.

[0013] Optionally, the vertical cavity surface emitting laser further includes: a first Bragg reflector and a second Bragg reflector, and the first Bragg reflector and the second Bragg reflector are respectively located below and above the multi-layer active layer.

[0014] The present invention also provides a method for manufacturing a vertical cavity surface emitting laser, including: forming a multi-layer active layer on a substrate, and a tunneling junction is disposed between adjacent active layers, and the tunneling junction includes an N-type doped layer and a P-type doped layer. Wherein, the N-type doped layer includes an N-type semiconductor layer doped with N-type impurities and an N-type atomic layer, and the N-type atomic layer is composed of at least two N-type impurities; the P-type doped layer includes a P-type semiconductor layer doped with P-type impurities and a P-type atomic layer, and the P-type atomic layer is composed of at least two P-type impurities.

[0015] Optionally, the N-type atomic layer is composed of at least two atoms selected from tellurium, selenium, silicon, and sulfur; and / or, the P-type atomic layer is composed of at least two atoms selected from carbon, magnesium, zinc, and beryllium.

[0016] In the vertical cavity surface emitting laser provided by the present invention, a tunneling junction is used to effectively connect multiple active layers in series, increase the gain, and effectively improve the power per unit area. Moreover, for the tunneling junction, its N-type doped layer not only includes an N-type semiconductor layer, but also includes an N-type atomic layer. Similarly, its P-type doped layer not only includes a P-type semiconductor layer, but also includes a P-type atomic layer. Thus, the impurity dose in the N-type doped layer is the sum of the impurity dose in the N-type semiconductor layer and the impurity in the N-type atomic layer, and the impurity dose in the P-type doped layer is the sum of the impurity dose in the P-type semiconductor layer and the impurity in the P-type atomic layer. This greatly increases the impurity concentration in the N-type and P-type doped layers, enabling the N-type and P-type doped layers to reach a higher doping concentration, which is beneficial to reducing the tunneling difficulty and increasing the tunneling current of carriers.

[0017] Furthermore, both the N-type atomic layer and the P-type atomic layer are composed of at least two types of atoms, which is beneficial to achieving a micro-roughened structure of the N-type and P-type atomic layers, achieving the effect of stress release, and improving the crystal quality of the epitaxial layer. In addition, by setting the N-type atomic layer and the P-type atomic layer, the doping dose of the N-type semiconductor layer and the P-type semiconductor layer is effectively alleviated, thereby improving the problem that the crystal of the semiconductor material is damaged when achieving high-concentration doping, reducing the absorption coefficient of the tunneling junction, and alleviating the internal loss. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 It is a schematic structural diagram of a vertical cavity surface emitting laser in an embodiment of the present invention.

[0019] Among them, the reference numerals are as follows:

[0020] 100 - Substrate;

[0021] 210 - First Bragg reflector;

[0022] 220 - Second Bragg reflector;

[0023] 300 - Multi-stage active series structure;

[0024] 310 - Active layer;

[0025] 320 - Tunneling junction;

[0026] 320N - N-type doped layer;

[0027] 321N - N-type semiconductor layer;

[0028] 322N - N-type atomic layer;

[0029] 320P - P-type semiconductor layer;

[0030] 321P - P-type semiconductor layer;

[0031] 322P-P type atomic layer;

[0032] 400 - oxide confinement layer;

[0033] 500 - cap layer. Detailed implementation manners

[0034] The vertical cavity surface emitting laser and its manufacturing method proposed by the present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. According to the following description, the advantages and features of the present invention will be clearer. It should be noted that the accompanying drawings are all in very simplified forms and use non-precise scales, only for the purpose of facilitating and clearly assisting in explaining the purpose of the embodiments of the present invention. It should be recognized that relative terms such as "above", "below", "top", "bottom", "upper" and "lower" shown in the accompanying drawings can be used to describe the relationships between various elements with respect to each other. These relative terms are intended to cover different orientations of the elements in addition to the orientations depicted in the accompanying drawings. For example, if the device is inverted relative to the view in the accompanying drawings, an element described as "above" another element will now be below that element.

[0035] Figure 1 is a schematic structural diagram of a vertical cavity surface emitting laser in an embodiment of the present invention. As Figure 1 shown, the vertical cavity surface emitting laser (VCSEL) includes: a multi-stage active series structure 300 formed on a substrate 100, and the multi-stage active series structure 300 includes at least two active layers 310.

[0036] Among them, a tunneling junction 320 is provided between adjacent active layers 310 to realize the series connection between adjacent active layers 310 by using the tunneling junction 320. For example Figure 1 five mutually series-connected active layers 310 are taken as an example for illustration. In this embodiment, multiple active layers 310 are effectively connected in series, so that the power per unit area can be effectively increased and higher luminous efficiency can be achieved. Specifically, the tunneling junction 320 includes a P-type doped layer 320P and an N-type doped layer 320N. In this embodiment, the P-type doped layer 320P and the N-type doped layer 320N in each tunneling junction 320 are stacked along the layer growth direction (such as Figure 1 the direction from bottom to top shown).

[0037] In an alternative solution, the N-type doping layer 320N may include: an N-type semiconductor layer 321N doped with N-type impurities and an N-type atomic layer 322N. That is, the overall impurity doping concentration of the N-type doping layer 320P is: the N-type impurity dose in the N-type semiconductor layer 321N plus the N-type atomic layer 322N, greatly increasing the overall doping concentration within the N-type doping layer 320N and overcoming the problem that the semiconductor material itself cannot achieve high-concentration doping. Among them, the N-type impurity dose in the N-type semiconductor layer 321N may be greater than 5E17 atoms / cm 3 (In a specific example, the N-type impurity dose in the N-type semiconductor layer 321N may be further greater than 5E18 atoms / cm 3 ). In addition, by providing the N-type atomic layer 322N to relieve the doping concentration within the N-type semiconductor layer 321N, it is also possible to avoid problems such as deterioration of the crystal quality of the semiconductor material and impurity absorption when performing high-concentration doping on the semiconductor material.

[0038] In a specific example, the thickness of the N-type atomic layer 322N may be only the thickness of one or several atomic layers (for example, the thickness of the N-type atomic layer 322N is less than or equal to 2.5 nm), such that the N-type impurities in the N-type atomic layer 322N are restricted within a plane. In addition, the small thickness of the N-type atomic layer 322N (for example, less than or equal to 2.5 nm) is conducive to the N-type atomic layer 322N formed having a micro-rough structure (specifically, the N-type atomic layer 322N can grow three-dimensionally longitudinally to form a micro-rough structure), thereby improving the crystal quality of the N-type semiconductor layer 321N epitaxially grown on the N-type atomic layer 322N and achieving stress release of the epitaxial layer formed by the epitaxial process.

[0039] In this embodiment, the N-type atomic layer 322N is specifically composed of at least two N-type impurities. By using co-doping of different impurities to form the N-type atomic layer 322N, it is easier to achieve a micro-rough structure based on the different volumes of different impurity atoms, improve the stress release effect, and further improve the crystal quality of the N-type semiconductor layer 321N epitaxially grown on the N-type atomic layer 322N. Among them, the N-type impurities may include tellurium (Te), selenium (Se), silicon (Si), sulfur (S), etc. For example, the N-type atomic layer 322N may be a silicon-tellurium co-doped layer, etc.

[0040] Further, the semiconductor material in the N-type semiconductor layer 321N may specifically be a III-V compound, such as gallium arsenide (GaAs) material. Also, the N-type impurities in the N-type semiconductor layer 321N may include at least one of tellurium (Te), selenium (Se), silicon (Si), and sulfur (S). For example, the N-type semiconductor layer 321N is a silicon-doped gallium arsenide layer (Si-GaAs), or the N-type semiconductor layer 321N is a tellurium-doped gallium arsenide layer (Te-GaAs), or the N-type semiconductor layer 321N is a silicon-tellurium co-doped gallium arsenide layer (SiTe-GaAs). Among them, Te impurities can achieve a higher impurity doping concentration in the N-type semiconductor layer 320N compared to Si impurities. Therefore, in a specific example, the N-type semiconductor layer 320N may be a tellurium-doped gallium arsenide layer (Te-GaAs).

[0041] In a specific embodiment, the N-type doping layer 320N has multiple N-type semiconductor layers 321N, and the N-type atomic layer 322N is disposed between adjacent N-type semiconductor layers 321N. In this embodiment, the N-type atomic layer 322N is disposed between each adjacent N-type semiconductor layers 321N. For example Figure 1 As shown, the N-type doping layer 320N may be provided with 3 N-type semiconductor layers 321N, and the N-type atomic layer 322N is disposed between adjacent N-type semiconductor layers 321N.

[0042] Continue to refer to Figure 1 As shown, the N-type doping layer 320N further includes an intrinsic semiconductor layer 323, and the intrinsic semiconductor layer 323 is located at the bottom and / or the bottom of the N-type doping layer 320N. In this embodiment, the intrinsic semiconductor layer 323 is disposed at the bottom of the N-type doping layer 320N, so that the N-type doping layer 320N contacts the adjacent P-type doping layer 320P with the intrinsic semiconductor layer 323, thereby preventing the N-type impurities in the N-type doping layer 320N and the P-type impurities in the P-type doping layer 320P from diffusing into each other and affecting the doping concentration and electrical neutrality problems. It is also beneficial to reduce the absorption coefficient of the material, and at the same time, it can improve the resistance difference between materials and reduce the resistance. Among them, the semiconductor material of the intrinsic semiconductor layer 323 may also be a III-V compound, such as gallium arsenide (GaAs) material.

[0043] Further, the total thickness of the N-type doping layer 320N can be controlled between 10 nm and 60 nm. Among them, the thickness of the N-type semiconductor layer 321N is, for example, 3 nm - 15 nm, and each N-type semiconductor layer 321N can be set with the same thickness or with different thicknesses; the thickness of the intrinsic semiconductor layer 323 is, for example, 0.5 nm - 2 nm. And as described above, the thickness of the N-type atomic layer 322N can be less than or equal to 2.5 nm.

[0044] In another alternative solution, the P-type doping layer 320P may include: a P-type semiconductor layer 321P doped with P-type impurities and a P-type atomic layer 322P. That is, the overall impurity doping concentration of the P-type doping layer 320P is: the P-type impurity dose in the P-type semiconductor layer 321P plus the P-type atomic layer 322P, greatly increasing the overall doping concentration within the P-type doping layer 320P and overcoming the problem that the semiconductor material itself cannot achieve high-concentration doping. Among them, the P-type impurity dose in the P-type semiconductor layer 321P can be greater than 1E18 atoms / cm 3 (In a specific example, the P-type impurity dose in the P-type semiconductor layer 321P can be further greater than 1E19 atoms / cm 3 ). In addition, by setting the P-type atomic layer 322P to relieve the doping concentration in the P-type semiconductor layer 321P, it is also possible to avoid problems such as deterioration of the crystal quality of the semiconductor material and impurity absorption when performing high-concentration doping on the semiconductor material.

[0045] In a specific example, the thickness of the P-type atomic layer 322P is only the thickness of one or several atomic layers (for example, the thickness of the P-type atomic layer 322P is less than or equal to 1.5 nm), so that the P-type impurities in the P-type atomic layer 322P are restricted within a plane. In addition, the thickness of the P-type atomic layer 322P is small (for example, less than or equal to 1.5 nm), which is beneficial to making the formed P-type atomic layer 322P have a micro-rough structure (specifically, it can be realized that the P-type atomic layer 322P can grow three-dimensionally longitudinally to form a micro-rough structure), thereby improving the crystal quality of the P-type semiconductor layer 321P epitaxially grown on the P-type atomic layer 322P and facilitating stress release of the epitaxial layer formed by the epitaxial process.

[0046] In this embodiment, the P-type atomic layer 322P is specifically composed of at least two P-type impurities. By using different impurities for co-doping to form the P-type atomic layer 322P, it is easier to achieve a micro-rough structure based on the different volumes of different impurity atoms, improve the stress release effect, and further improve the crystal quality of the P-type semiconductor layer 321P epitaxially grown on the P-type atomic layer 322P. Among them, the P-type impurities may include carbon (C), magnesium (Mg), zinc (Zn), beryllium (Be), etc. For example, the P-type atomic layer 322P can be a magnesium-carbon co-doped layer.

[0047] Furthermore, the semiconductor material in the P-type semiconductor layer 321P can specifically be a III-V compound, such as gallium arsenide (GaAs). In this embodiment, the semiconductor material in the P-type semiconductor layer 321P can further include aluminum gallium arsenide (AlGaAs) to facilitate increasing the hole concentration in the P-type semiconductor layer 321P. Also, the P-type impurities in the P-type semiconductor layer 321P can include at least one of carbon (C), magnesium (Mg), zinc (Zn), and beryllium (Be). For example, the P-type semiconductor layer 321P is a magnesium-doped aluminum gallium arsenide layer (Mg-AlGaAs), or the P-type semiconductor layer 321P is a carbon-doped aluminum gallium arsenide layer (C-AlGaAs), or the P-type semiconductor layer 321P is a magnesium-carbon co-doped aluminum gallium arsenide layer (MgC-AlGaAs). In one example, the P-type semiconductor layer 320P can specifically be a carbon-doped aluminum gallium arsenide layer (C-AlGaAs).

[0048] In a specific embodiment, the P-type doped layer 320P has multiple P-type semiconductor layers 321P, and the P-type atomic layer 322P is disposed between adjacent P-type semiconductor layers 321P. In this embodiment, the P-type atomic layer 322P is disposed between each pair of adjacent P-type semiconductor layers 321P. For example Figure 1 as shown, the P-type doped layer 320P can be provided with 3 P-type semiconductor layers 321P, and the P-type atomic layer 322P is disposed between each pair of adjacent P-type semiconductor layers 321P.

[0049] Furthermore, the total thickness of the P-type doped layer 320P can be controlled between 5 nm and 40 nm. Among them, the thickness of the P-type semiconductor layer 321P is, for example, 3 nm - 10 nm, and each P-type semiconductor layer 321P can be set with the same thickness or can also be set with different thicknesses; and as described above, the thickness of the P-type atomic layer 322P can be less than or equal to 2 nm.

[0050] It should be noted that in a specific solution, the N-type doped layer 320N in the tunneling junction 320 includes an N-type semiconductor layer 321N and an N-type atomic layer 322N; meanwhile, the P-type doped layer 320P in the tunneling junction 320 includes a P-type semiconductor layer 321P and a P-type atomic layer 322P.

[0051] In addition, the thicknesses of the P-type doped layer 320P and the N-type doped layer 320N in the tunneling junction 320 can be set proportionally. For example, the P-type doped layer 320P has a first thickness, the N-type doped layer 320N has a second thickness, and the ratio of the first thickness to the second thickness is 3N / 4 (N is an integer greater than or equal to 1). In this way, it is beneficial to reduce the tunneling difficulty of carriers in the tunneling junction 320, increase the tunneling current, and effectively reduce the absorption coefficient of the highly doped semiconductor material.

[0052] Continue to refer to Figure 1 As shown, the vertical cavity surface emitting laser further includes: a first Bragg reflector 210 and a second Bragg reflector 220, and the first Bragg reflector 210 and the second Bragg reflector 220 are respectively disposed below and above the multi-stage active series structure 300. In this embodiment, the first Bragg reflector 210 located below the multi-stage active series structure 300 can be an N-type Bragg reflector (N-DBR), and the second Bragg reflector 220 located above the multi-stage active series structure 300 is a P-type Bragg reflector (P-DBR).

[0053] In addition, an oxide confinement layer 400 is further disposed between the top active layer 310 and the second Bragg reflector 220. And a cap layer 500 can be further formed above the second Bragg reflector 220, and the material of the cap layer 500 includes, for example, P-type gallium arsenide. In this embodiment, a buffer layer is provided in the substrate 100, and the first Bragg reflector 210 and the multi-stage active series structure 300 are sequentially formed on the buffer layer.

[0054] Based on the above-described reflective laser, its manufacturing method will be described below. Specifically, refer to Figure 1 As shown, the manufacturing method of the reflective laser includes: epitaxially growing multiple active layers 310 on a substrate 100, and a tunneling junction 320 is further formed between adjacent active layers 310.

[0055] Among them, before forming the multiple active layers 310, it further includes epitaxially growing a first Bragg reflector 210 on the substrate 100. In a specific example, the first Bragg reflector 210 can be an N-type Bragg reflector (N-DBR).

[0056] Next, a multi-stage active series structure 300 is epitaxially grown on the first Bragg reflection layer 210. Taking the multi-stage active series structure 300 having M active layers 310 as an example, its preparation method includes: First, a first active layer is formed on the first Bragg reflection layer 210, and a first tunneling junction is formed on the first active layer; Then, a second active layer is formed on the first tunneling junction, and a second tunneling junction is formed on the second active layer... a (M-1)th tunneling junction is formed, and then a Mth active layer is formed on the (M-1)th tunneling junction. Thus, multiple active layers connected in series by tunneling junctions are prepared.

[0057] Continue to refer to Figure 1 As shown, the tunneling junction 320 specifically includes a P-type doped layer 320P and an N-type doped layer 320N stacked in sequence along the growth direction.

[0058] In an optional solution, the preparation method of the P-type doped layer 320P includes: epitaxially growing at least two P-type semiconductor layers 321P doped with P-type impurities, and a P-type atomic layer 322P is also grown between adjacent P-type semiconductor layers. The P-type atomic layer 322P is specifically composed of at least two P-type impurities. Among them, in the epitaxial growth process of the P-type semiconductor layer 321P, its growth temperature is, for example, 400°C - 700°C, and the growth pressure is, for example, 5 mbar - 500 mbar. And in the epitaxial growth process of the P-type atomic layer 322P, its growth temperature is, for example, 400°C - 700°C, and the growth pressure is, for example, 5 mbar - 500 mbar.

[0059] In Figure 1 In the shown example, the preparation method of the P-type doped layer 320P includes: epitaxially growing a first P-type semiconductor layer, a first P-type atomic layer, a second P-type semiconductor layer, a second P-type atomic layer, and a third P-type semiconductor layer in sequence.

[0060] In an optional solution, the preparation method of the N-type doped layer 320N includes: epitaxially growing at least two N-type semiconductor layers 321N doped with N-type impurities, and an N-type atomic layer 322N is also grown between adjacent N-type semiconductor layers. The N-type atomic layer 322N is specifically composed of at least two N-type impurities. Among them, in the epitaxial growth process of the N-type semiconductor layer 321N, its growth temperature is, for example, 400°C - 700°C, and the growth pressure is, for example, 5 mbar - 500 mbar. And in the epitaxial growth process of the N-type atomic layer 322N, its growth temperature is, for example, 400°C - 700°C, and the growth pressure is, for example, 5 mbar - 500 mbar.

[0061] Further, in the preparation process of the N-type doping layer 320N, an intrinsic semiconductor layer 323 is epitaxially grown before growing the bottommost N-type semiconductor layer 321N; and, an intrinsic semiconductor layer 323 is also epitaxially grown after growing the topmost N-type semiconductor layer 321N. Among them, in the epitaxial growth process of the intrinsic semiconductor layer 323, its growth temperature is, for example, 400°C - 700°C, and the growth pressure is, for example, 50 mbar - 500 mbar.

[0062] In Figure 1 In the illustrated example, the preparation method of the N-type doping layer 320N includes: sequentially epitaxially growing an intrinsic semiconductor layer, a first N-type semiconductor layer, a first N-type atomic layer, a second N-type semiconductor layer, a second N-type atomic layer, a third N-type semiconductor layer, and an intrinsic semiconductor layer.

[0063] Further, after forming the multi-stage active series structure 300, an oxide confinement layer 400 is epitaxially grown on the top active layer 310. And, a second Bragg reflector 220 is epitaxially grown on the oxide confinement layer 400, and the second Bragg reflector 220 is specifically a P-type Bragg reflector (P-DBR). In Figure 1 In the illustrated example, a cap layer 500, such as a P-type GaAs layer, may further be formed above the second Bragg reflector 220.

[0064] In summary, in the vertical cavity surface emitting laser provided in this embodiment, since N-type atomic layers and P-type atomic layers are respectively provided in the N-type doping layer and the P-type doping layer in its tunneling junction, the impurity concentration in the N-type doping layer and the P-type doping layer can be effectively increased, while avoiding crystal damage to the semiconductor material, overcoming the problem that it is difficult to increase the doping concentration of the tunneling junction in the existing vertical cavity surface emitting laser, effectively improving the problem that the absorption coefficient of the tunneling junction is relatively large, alleviating the internal loss, and reducing the tunneling difficulty of the tunneling junction and increasing the tunneling current.

[0065] It should be noted that although the present invention has been disclosed above with preferred embodiments, the above embodiments are not intended to limit the present invention. For any person skilled in the art, without departing from the scope of the technical solution of the present invention, many possible changes and modifications can be made to the technical solution of the present invention by using the technical content disclosed above, or it can be modified into equivalent embodiments with equivalent changes. Therefore, any simple modification, equivalent change, and modification made to the above embodiments according to the technical essence of the present invention without departing from the content of the technical solution of the present invention still belong to the scope of protection of the technical solution of the present invention.

[0066] It should also be noted that the references to "an embodiment", "embodiments", "specific embodiments", "some embodiments", etc. in the specification only indicate that the described embodiments may include specific features, structures or characteristics. Moreover, such phrases do not necessarily refer to the same embodiments. In addition, when a specific feature, structure or characteristic is described in connection with an embodiment, whether explicitly described or not, implementing such a feature, structure or characteristic in connection with other embodiments is within the knowledge of those skilled in the relevant art. Also, unless specifically stated or indicated, the terms "first", "second", "third", etc. in the specification are only used to distinguish the various components, elements, steps, etc. in the specification, rather than to represent the logical relationship or sequential relationship, etc. between the various components, elements, steps.

[0067] Furthermore, it should also be recognized that the singular forms "a" and "an" used herein include plural referents unless the context clearly dictates otherwise. For example, the recitation of "a step" or "a device" means the recitation of one or more steps or devices and may include sub-steps as well as sub-devices. All conjunctions used should be understood in their broadest sense. Also, the word "or" should be understood to have the definition of a logical "or", rather than the definition of a logical "exclusive or", unless the context clearly dictates otherwise.

Claims

1. A vertical cavity surface emitting laser, characterized in that: include: At least two active layers are formed on a substrate, with a tunnel junction being provided between adjacent active layers, the tunnel junction comprising an N-type doped layer and a P-type doped layer; Among them, the N-type doped layer includes an N-type semiconductor layer doped with N-type impurities and an N-type atomic layer, and the N-type atomic layer is composed of at least two N-type impurity atoms; the P-type doped layer includes a P-type semiconductor layer doped with P-type impurities and a P-type atomic layer, and the P-type atomic layer is composed of at least two P-type impurity atoms.

2. The vertical cavity surface emitting laser according to claim 1, wherein The N-type doped layer includes at least two N-type semiconductor layers, and the N-type atomic layer is arranged between adjacent N-type semiconductor layers; the P-type doped layer includes at least two P-type semiconductor layers, and the P-type atomic layer is arranged between adjacent P-type semiconductor layers.

3. The vertical cavity surface emitting laser according to claim 1, wherein: The N-type atomic layer is composed of at least two atoms selected from the group consisting of tellurium, selenium, silicon, and sulfur; and / or the P-type atomic layer is composed of at least two atoms selected from the group consisting of carbon, magnesium, zinc, and beryllium.

4. The vertical cavity surface emitting laser according to claim 1, wherein: The thickness of the N-type atomic layer is less than or equal to 2.5 nm; and / or the thickness of the P-type atomic layer is less than or equal to 1.5 nm.

5. The vertical cavity surface emitting laser according to claim 1, wherein: The thickness of the N-type doping layer is between 10 nm and 60 nm; and / or the thickness of the P-type doping layer is between 5 nm and 40 nm.

6. The vertical cavity surface emitting laser according to claim 1, wherein: The P-type doped layer has a first thickness, the N-type doped layer has a second thickness, and a ratio of the first thickness to the second thickness is 3N / 4, where N is an integer greater than or equal to 1.

7. The vertical cavity surface emitting laser according to claim 1, wherein: The N-type doped layer further includes an intrinsic semiconductor layer, and the intrinsic semiconductor layer is located at the bottommost layer and / or the topmost layer of the N-type doped layer.

8. The vertical cavity surface emitting laser according to any one of claims 1 to 7, wherein: Also includes: a first Bragg reflection layer and a second Bragg reflection layer, wherein the first Bragg reflection layer and the second Bragg reflection layer are respectively located below and above the multi-layer active layer.

9. A method for preparing a vertical cavity surface emitting laser, characterized in that: include: A plurality of active layers are formed on a substrate, and tunnel junctions are provided between adjacent active layers, wherein the tunnel junctions include an N-type doped layer and a P-type doped layer; Among them, the N-type doped layer includes an N-type semiconductor layer doped with N-type impurities and an N-type atomic layer, and the N-type atomic layer is composed of at least two N-type impurities; the P-type doped layer includes a P-type semiconductor layer doped with P-type impurities and a P-type atomic layer, and the P-type atomic layer is composed of at least two P-type impurities.

10. The method for preparing a vertical cavity surface emitting laser according to claim 9, wherein: The N-type atomic layer is composed of at least two atoms selected from the group consisting of tellurium, selenium, silicon, and sulfur; and / or the P-type atomic layer is composed of at least two atoms selected from the group consisting of carbon, magnesium, zinc, and beryllium.

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