Power-on reset circuit, method, storage medium and electronic device

Abstract

The present application proposes a power-on reset circuit, method, storage medium and electronic device, the circuit comprising: a first control unit, used to output a first control voltage signal whose voltage value is a ratio of K1 to the power-on voltage signal when the power-on voltage signal is greater than or equal to a first voltage threshold; K1 is a positive number less than 1; a reset unit, used to output an inverted reset signal in a low-level state and a reset signal in a high-level state when the first control voltage signal is greater than a second voltage threshold; output an inverted reset signal in a high-level state and a reset signal in a low-level state when the first control voltage signal is less than or equal to the second voltage threshold; since the voltage value of the power-on voltage signal is greater than or equal to the working voltage threshold when the voltage value of the first control voltage signal is the second voltage threshold, the high-level reset signal is sent out after the power-on voltage signal is greater than or equal to the operable working voltage threshold by adjusting the value of K1.

Description

Technical Field

[0001] The present application relates to the technical field of electronic circuits, and in particular to a power-on reset circuit, method, storage medium and electronic device. Background Art

[0002] In the prior art, when a circuit system is powered on, a power-on reset circuit in the circuit system will send a reset signal to initialize a subsequent circuit. After the reset signal is sent, the subsequent circuit can start to work.

[0003] However, in the existing power-on reset circuit, when the circuit system is powered on slowly, a reset signal is issued when the power-on voltage reaches the on-voltage of the inverter (about 0.7V). At this time, the voltage of the subsequent circuit has not yet reached the voltage value at which it can enter operation, and it has not entered the operable state. The reset signal is invalid and has no reset effect. Summary of the invention

[0004] Based on the above-mentioned shortcomings of the prior art, the present application provides a power-on reset circuit, method, storage medium and electronic device.

[0005] The first aspect of the present application discloses a power-on reset circuit, comprising:

[0006] a first control unit, configured to receive a power-on voltage signal and an inverted reset signal, and under the control of the inverted reset signal, when the power-on voltage signal is greater than or equal to the first voltage threshold, output the first control voltage signal whose voltage value is K1 according to the power-on voltage signal and whose ratio to the power-on voltage signal is K1; wherein K1 is a positive number less than 1;

[0007] A reset unit connected to the first control unit is used to receive the first control voltage signal, and when the first control voltage signal is greater than a second voltage threshold, output an inverted reset signal in a low level state and a reset signal in a high level state according to the first control voltage signal; when the first control voltage signal is less than or equal to the second voltage threshold, output an inverted reset signal in a high level state and a reset signal in a low level state according to the first control voltage signal; wherein the inverted reset signal is an inverted signal of the reset signal; when the voltage value of the first control voltage signal is the second voltage threshold, the voltage value of the power-on voltage signal is greater than or equal to the operating voltage threshold.

[0008] Optionally, in the above power-on reset circuit, it also includes:

[0009] a second control unit, configured to receive the power-on voltage signal and the enable signal, invert the enable signal, output an inverted enable signal, and if the enable signal is in a normal state, output a second control voltage signal whose voltage value is K2 according to the power-on voltage signal and whose ratio to the power-on voltage signal is K2; wherein K2 is a positive number less than 1;

[0010] a third control unit connected to the second control unit, configured to receive the power-on voltage signal, the inverted enable signal, and the second control voltage signal; if the enable signal is in a normal state, when the second control voltage signal is greater than or equal to a third voltage threshold, the inverted enable signal and the second control voltage signal are used to control the output of a third control voltage signal having a voltage value of zero; when the second control voltage signal is less than the third voltage threshold, the inverted enable signal and the second control voltage signal are used to control the output of the third control voltage signal having a voltage value equal to the value of the power-on voltage signal; wherein, when the voltage value of the second control voltage signal is equal to the third voltage threshold, the voltage value of the power-on voltage signal is greater than or equal to the operating voltage threshold;

[0011] A fourth control unit connected to the third control unit and the first control unit respectively, is used to receive the power-on voltage signal, the third control voltage signal and the inverted enable signal. If the enable signal is in a normal state, when the third control voltage signal is greater than or equal to a fourth voltage threshold, the third control voltage signal and the inverted enable signal control the first control voltage signal whose output voltage value is zero; wherein, when the third control voltage signal is zero, the fourth control unit stops controlling the first control voltage signal, and the first control unit controls the output of the first control voltage signal.

[0012] Optionally, in the above power-on reset circuit, the second control unit is further configured to: if the enable signal is in an abnormal state, the second control voltage signal output by the second control unit is zero;

[0013] The fourth control unit is further used for:

[0014] If the enable signal is in an abnormal state, the third control voltage signal output by the third control unit is pulled down to zero, and the control of the output of the first control voltage signal is stopped, and the first control unit controls the output of the first control voltage signal.

[0015] Optionally, in the above power-on reset circuit, the first control unit includes:

[0016] A first switch tube having a first end receiving the power-on voltage signal, a control end of the first switch tube being grounded, and a second end of the first switch tube being connected to one end of a first resistor; wherein the first voltage threshold is a turn-on voltage threshold of the first switch tube;

[0017] The other end of the first resistor is connected to one end of the second resistor;

[0018] The other end of the second resistor is connected to the second end of the second switch tube; the common end of the first resistor and the second resistor outputs the first control voltage signal; wherein, R1 is the resistance value of the first resistor; R2 is the resistance value of the second resistor;

[0019] A first terminal of the second switch tube is grounded, and a control terminal of the second switch tube receives the inverted reset signal.

[0020] Optionally, in the above power-on reset circuit, the reset unit includes:

[0021] A Schmitt trigger whose input terminal receives the first control voltage signal, and whose output terminal outputs the inverted reset signal; wherein the second voltage threshold is a threshold voltage of the Schmitt trigger;

[0022] A first inverter having an input terminal connected to the output terminal of the Schmitt trigger, the output terminal of the first inverter outputs a reset signal, and the input terminal of the first inverter receives the inverted reset signal.

[0023] Optionally, in the above power-on reset circuit, the second control unit includes:

[0024] A second inverter whose input terminal receives the enable signal, wherein the output terminal of the second inverter is connected to the control terminal of the third switch tube; wherein the output terminal of the second inverter outputs the inverted enable signal;

[0025] The first end of the third switch tube receives the power-on voltage signal, and the second end of the third switch tube is connected to one end of the third resistor;

[0026] The other end of the third resistor is connected to one end of the fourth resistor; wherein the common end between the third resistor and the fourth resistor outputs the second control voltage signal;

[0027] The other end of the fourth resistor is grounded.

[0028] Optionally, in the above power-on reset circuit, the third control unit includes:

[0029] a fourth switch tube whose control end receives the inverted enable signal, a first end of the fourth switch tube receives the power-on voltage signal, and a second end of the fourth switch tube is connected to one end of a fifth resistor;

[0030] The other end of the fifth resistor is connected to the second end of the fifth switch tube;

[0031] The control end of the fifth switch tube receives the second control voltage signal, and the first end of the fifth switch tube is grounded; wherein the common end between the fifth switch tube and the fifth resistor outputs the third control voltage signal; and the third voltage threshold is the turn-on voltage threshold of the fifth switch tube.

[0032] Optionally, in the above power-on reset circuit, the fourth control unit includes:

[0033] A sixth switch tube whose control end receives the inverted enable signal, a first end of the sixth switch tube is grounded, and a second end of the sixth switch tube receives the third control voltage signal;

[0034] A seventh switch tube receives the third control voltage signal at the control end, the first end of the seventh switch tube is grounded, and the second end of the seventh switch tube outputs the first control voltage signal; wherein the fourth voltage threshold is the turn-on voltage threshold of the seventh switch tube.

[0035] Optionally, in the above power-on reset circuit, the first switch tube is a PMOS tube; and the second switch tube is an NMOS tube.

[0036] Optionally, in the above power-on reset circuit, the first control unit further includes: a first capacitor having one end connected to a common end of the first resistor and the second resistor, and a second end of the first capacitor is grounded.

[0037] The second aspect of the present application discloses a power-on reset method, comprising:

[0038] receiving a power-on voltage signal and an inverted reset signal;

[0039] Under the control of the inverted reset signal, when the power-on voltage signal is greater than or equal to the first voltage threshold, the first control voltage signal having a voltage value and a ratio of the power-on voltage signal of K1 is obtained according to the power-on voltage signal; wherein K1 is a positive number less than 1;

[0040] When the first control voltage signal is greater than the second voltage threshold, an inverted reset signal in a low level state and a reset signal in a high level state are output according to the first control voltage signal; when the first control voltage signal is less than or equal to the second voltage threshold, an inverted reset signal in a high level state and a reset signal in a low level state are output according to the first control voltage signal; wherein the inverted reset signal is an inverted signal of the reset signal; when the voltage value of the first control voltage signal is the second voltage threshold, the voltage value of the power-on voltage signal is greater than or equal to the operating voltage threshold.

[0041] Optionally, in the above power-on reset method, it also includes:

[0042] Receive an enable signal;

[0043] Inverting the enable signal to obtain an inverted enable signal;

[0044] If the enable signal is in a normal state, a second control voltage signal having a voltage value and a ratio of K2 to the power-on voltage signal is obtained according to the power-on voltage signal;

[0045] When the second control voltage signal is greater than or equal to a third voltage threshold, a third control voltage signal having a voltage value of zero is obtained by controlling the inverted enable signal and the second control voltage signal;

[0046] When the second control voltage signal is less than the third voltage threshold, the third control voltage signal having a voltage value equal to the power-on voltage signal is obtained by controlling the inverted enable signal and the second control voltage signal; wherein, when the voltage value of the second control voltage signal is equal to the third voltage threshold, the voltage value of the power-on voltage signal is greater than or equal to the operating voltage threshold;

[0047] When the third control voltage signal is greater than or equal to a fourth voltage threshold, the first control voltage signal having a voltage value of zero is obtained by controlling the third control voltage signal and the inverted enable signal; wherein, when the third control voltage signal is zero, the third control voltage signal stops controlling the first control voltage signal.

[0048] Optionally, in the above power-on reset method, it also includes:

[0049] If the enable signal is in an abnormal state, the second control voltage signal with a voltage value of zero and the third control voltage signal with a voltage value of zero are obtained.

[0050] A third aspect of the present application discloses a computer storage medium for storing a program, wherein when the program is executed, it is used to implement the power-on reset method as described in any one of the second aspects above.

[0051] A fourth aspect of the present application discloses an electronic device, including a memory and a processor;

[0052] Wherein, the memory is used to store programs;

[0053] The processor is used to execute the program, and when the program is executed, it is specifically used to implement the power-on reset method as described in any one of the second aspects above.

[0054] A fifth aspect of the present application discloses an electronic device, comprising a power-on reset circuit as described in any one of the first aspects above.

[0055] It can be seen from the above technical solution that in the power-on reset circuit proposed in the embodiment of the present application, the first control unit can, under the control of the inverted reset signal, output a first control voltage signal whose ratio of the voltage value to the power-on voltage signal is K1 when the power-on voltage signal is greater than or equal to the first voltage threshold. Wherein, K1 is a positive number less than 1. Since the voltage value of the power-on voltage signal is gradually rising during the power-on process, the first control voltage signal is also gradually rising, and the reset unit in the embodiment of the present application outputs an inverted reset signal in a low-level state and a reset signal in a high-level state when the first control voltage signal is greater than the second voltage threshold, and outputs an inverted reset signal in a high-level state and a reset signal in a low-level state when the first control voltage signal is less than or equal to the second voltage threshold. Since the reset unit changes the reset signal from a low level state to a high level state when the first control voltage signal is greater than the second voltage threshold, that is, the power-on reset circuit generates a reset signal only when the first control voltage signal is greater than the second voltage threshold, and the condition that the first control voltage signal is greater than the second voltage threshold can be changed by adjusting the setting K1, so that when the voltage value of the first control voltage signal is the second voltage threshold, the voltage value of the power-on voltage signal is greater than or equal to the working voltage threshold, and then the voltage value of the first control voltage signal is greater than the second voltage threshold, that is, the voltage value of the power-on voltage signal is greater than or equal to the working voltage threshold, the reset signal changes to a high level state. Compared with the prior art, the power-on reset circuit proposed in the embodiment of the present application can send a high-level reset signal after the power-on voltage signal is greater than the operable working voltage threshold by setting the value of K1, and the reset signal will not fail, and the reliability is higher. BRIEF DESCRIPTION OF THE DRAWINGS

[0056] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying creative work.

[0057] Figure 1 A circuit diagram of an existing power-on reset circuit;

[0058] Figure 2 A circuit diagram of a power-on reset circuit proposed in an embodiment of the present application;

[0059] Figure 3 for Figure 2 Schematic diagram of signal changes in the circuit shown;

[0060] Figure 4 A circuit diagram of another power-on reset circuit proposed in an embodiment of the present application;

[0061] Figure 5 for Figure 4 A schematic diagram of signal changes in the circuit shown when the enable signal is in a normal state;

[0062] Figure 6 for Figure 4 A schematic diagram of signal changes in the circuit shown when the enable signal is in an abnormal state. DETAILED DESCRIPTION

[0063] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0064] See also Figure 1, in the existing power-on reset circuit, the first end of the first resistor R1 is connected to the power supply voltage VDD through a first P-channel metal-oxide-semiconductor (PMOS) transistor MP1. The second end of R1 is connected to the first end of the second resistor R2, the gate of the first N-channel metal-oxide-semiconductor (NMOS) transistor MN1. The second end of R2 is connected to the common ground terminal VSS, the source of MN1, the source of the second NMOS transistor MN2, and the source and drain of the first N-type MOS capacitor MC1. The first end of the third resistor R3 is connected to VDD, and the second end of R3 is connected to the drain of MN1 and the input terminal of the first inverter I1. The first end of the fourth resistor R4 is connected to VDD, and the second end of R4 is connected to the input terminal of the second inverter I2, the drain of MN2, and the gate of MC1. The output terminal of the first inverter I1 is connected to the gate of the third NMOS transistor MN3. The source of MN3 is connected to VSS and the source and drain of the second N-type MOS capacitor MC2. The drain of MN3 is connected to the gate of the P-type MOS capacitor MD1, the output terminal of the fourth inverter I4, and the input terminal of the fifth inverter I5. The source and drain of MD1 are connected to VDD. The input terminal of I4 is connected to the output terminal of the fifth inverter I5, the first input terminal of the NAND gate circuit N1, the gate of MC2, and the drain of MN4. The source of MN4 is connected to VSS, and the gate of MN4 is connected to the output terminal of the NOR gate circuit O1. The output terminal of I2 is connected to the first input terminal of O1 through D, and the output terminal of I3 is connected to the second input terminal of O1. The first input terminal of the first capacitor C1 is connected to the management voltage VDD / N, the second input terminal of C1 is connected to the reference voltage Vref, and the output terminal of C1 is connected to the second input terminal of the NAND gate circuit N1. The first input terminal of N1 is connected to the second end of the voltage latch circuit, and the output terminal of N1 is connected to the gate of MN2. The output terminal of the second inverter I2 is connected to the input terminal of the third inverter I3, and the output terminal of the third inverter I3 outputs the reset signal RSTB.

[0065] Based on Figure 1 the circuit shown, when VDD / N < Vref, a low level can be output at the RSTB terminal. When VDD / N > Vref, the RSTB terminal can continuously output a high level, and the circuit system works normally.

[0066] However, when VDD is powered on slowly, the drain voltage of MN1 and the voltage of node3 will rise with VDD. When the VDD voltage is greater than the on-voltage of I1, node2 is low, MN3 is off, the RST signal is low, node5 is low, and MN4 is off. At this time, the node levels of node0 and node4 are unknown, the output of N1 may be low, and MN2 is off. The node3 level will gradually rise with VDD, and after node3 passes through I2 and I3, the output RSTB is always high. Since the on-voltage of the second inverter I2 is very low, and node3 rises with VDD, when VDD is greater than the on-voltage of I2, RSTB is already in a high state. At this time, VDD has not risen to a voltage value that can enter operation, and has not entered an operable state. The reset signal is invalid and has no reset effect.

[0067] See also Figure 2 Based on the above problems in the prior art, an embodiment of the present application discloses a power-on reset circuit, including: a first control unit 201 and a reset unit 202.

[0068] The first control unit 201 is used to receive a power-on voltage signal and an inverted reset signal, and under the control of the inverted reset signal, when the power-on voltage signal is greater than or equal to a first voltage threshold, output a first control voltage signal whose voltage value is K1 and the ratio of the power-on voltage signal to the power-on voltage signal, wherein K1 is a positive number less than 1.

[0069] Specifically, the first control unit 201 receives a power-on voltage signal and an inverted reset signal, and when the power-on voltage signal is greater than or equal to the first voltage threshold, the first control voltage signal having a ratio of K1 between the power-on voltage signal and the inverted reset signal can be output according to the power-on voltage signal and the inverted reset signal under the control of the inverted reset signal. Optionally, the inverted reset signal can control the output voltage value of the first control voltage signal having a ratio of K1 between the power-on voltage signal and the power-on voltage signal through a level state. For example, under the control of the high level state of the inverted reset signal, the first control voltage signal having a ratio of K1 between the power-on voltage signal and the inverted reset signal can be output according to the power-on voltage signal and the inverted reset signal.

[0070] Optionally, K1 can be set by a first resistor and a second resistor in the first control unit. The resistance values ​​of the first resistor and the second resistor determine the value of K1.

[0071] When the power-on voltage signal is greater than or equal to the first voltage threshold, under the control of the inverted reset signal, according to the power-on voltage signal and the power-on voltage signal, the first control voltage signal whose ratio of the output voltage value to the power-on voltage signal is K1. The value of K1 is a positive number less than 1. Optionally, the first control voltage signal can be a voltage signal obtained by dividing the power-on voltage signal through the first resistor and the second resistor. When the power-on voltage signal is less than the first voltage threshold, the voltage value of the first control voltage signal output by the first control unit 201 is zero.

[0072] Optionally, continue to Figure 2 The first control unit 201 includes: a first switch tube Q1, a first resistor R1, a second resistor R2, and a second switch tube Q2.

[0073] The first end of the first switch tube Q1 receives the power-on voltage signal, the control end of the first switch tube Q1 is grounded GND, and the second end of the first switch tube is connected to one end of the first resistor R1. The first voltage threshold is the turn-on voltage threshold of the first switch tube Q1. The other end of the first resistor R1 is connected to one end of the second resistor R2. The other end of the second resistor R2 is connected to the second end of the second switch tube Q2, and the common end of the first resistor R1 and the second resistor R2 outputs the first control voltage signal Net1, wherein, R1 is the resistance value of the first resistor R1, and R2 is the resistance value of the second resistor R2. A first terminal of the second switch tube Q2 is grounded, and a control terminal of the second switch tube Q2 receives an inverted reset signal PORN.

[0074] When the power-on voltage signal VDD is less than the first voltage threshold (ie, less than the turn-on voltage threshold of the first switch tube Q1 ), the first switch tube Q1 cannot be turned on and is in the off state, so the voltage value output by the first control voltage signal Net1 is zero.

[0075] When the power-on voltage signal VDD is greater than or equal to the first voltage threshold (i.e., greater than or equal to the turn-on voltage threshold of the first switch tube Q1), the first switch tube Q2 is turned on, and at this time, the second switch tube Q2 is also in the turn-on state under the control of the high level state of the inverted reset signal Q2. Therefore, the output first control voltage signal Net1 is the signal obtained by dividing the power-on voltage signal by the second resistor R2. Specifically, the voltage value of the first control voltage signal Net1 at this time is

[0076] For details, see Figure 3That is, the power-on voltage signal VDD gradually rises from zero during the power-on process. During the rising process, when the power-on voltage signal VDD is less than the first voltage threshold, the first control voltage signal Net1 is always zero until the power-on voltage signal rises to the first voltage threshold. Since the inverted reset signal PORN is also in a high level state at this time, the first control unit outputs the first control voltage signal Net1 whose ratio to the power-on voltage signal is K1. The first control voltage signal Net1 rises with the rise of the power-on voltage signal VDD.

[0077] Optionally, in a specific embodiment of the present application, the first switch tube Q1 is a PMOS tube, and the second switch tube Q2 is an NMOS tube.

[0078] Optionally, continue to Figure 2 The first control unit also includes: a first capacitor C1 having one end connected to a common end of the first resistor and the second resistor, and a second end of the first capacitor C1 is grounded.

[0079] The reset unit 202 connected to the first control unit 201 is used to receive the first control voltage signal, and when the first control voltage signal is greater than the second voltage threshold, the inverted reset signal in the low level state and the reset signal in the high level state are output according to the first control voltage signal. When the first control voltage signal is less than or equal to the second voltage threshold, the inverted reset signal in the high level state and the reset signal in the low level state are output according to the first control voltage signal. The inverted reset signal is the inverted signal of the reset signal. When the voltage value of the first control voltage signal is greater than or equal to the second voltage threshold, the voltage value of the power-on voltage signal is greater than the operating voltage threshold of the subsequent circuit.

[0080] Specifically, the reset unit 202 receives the first control voltage signal output by the first control unit 201. That is, when the power-on voltage signal of the first control unit 201 is greater than or equal to the first voltage threshold, the first control voltage signal whose ratio to the power-on voltage signal is K1 is output to the reset unit 202. As the voltage value of the power-on voltage signal gradually increases, the voltage value of the first control voltage signal received by the reset unit 202 also gradually increases. When the first control voltage signal is less than or equal to the second voltage threshold, the reset unit 202 outputs an inverted reset signal in a high level state and a reset signal in a low level state according to the first control voltage signal. In other words, during the period when the first control voltage signal is less than or equal to the second voltage threshold, the reset signal is always in a low level state, which is equivalent to not outputting the reset signal. When the first control voltage signal is greater than the second voltage threshold, the reset unit 202 outputs an inverted reset signal in a low level state and a reset signal in a high level state according to the first control voltage signal.

[0081] Since the voltage value of the first control voltage signal rises with the rise of the power-on voltage signal, when it rises to the second voltage threshold, the reset signal level state flips from a low level state to a high level state, and a reset signal is issued. When the voltage value of the first control voltage signal is the second voltage threshold, the voltage value of the power-on voltage signal is greater than or equal to the working voltage threshold. That is, when the power-on voltage signal has risen to exceed the working voltage threshold, the reset unit 202 sends a reset signal. The working voltage threshold is the voltage threshold when the circuit system can enter the working state, that is, the minimum voltage value at which the subsequent circuit can work. If you want to make the voltage value of the first voltage signal the second voltage threshold, the voltage value of the power-on voltage signal is the working voltage threshold, which can be achieved by setting K1. Specifically, since the voltage value of the first control voltage signal Net1 received by the reset unit is K1 times the power-on voltage signal VDD. Therefore, when K1×VDD≥V2, VDD must be greater than or equal to the operating voltage threshold. Therefore, by setting the value of K1 and / or the second voltage threshold V2, when K1×VDD≥V2, VDD must be greater than the minimum voltage threshold at which the subsequent circuit can operate.

[0082] For details, see Figure 3 , when the first control voltage signal Net1 inputted by the first control unit to the reset unit rises with the voltage value of the power-on voltage signal, when reaching the second voltage threshold, it can be seen that the reset signal POR is flipped from a low level state to a high level state. The inverted reset signal PORN is inversely proportional to POR, and at this time, it is flipped from a high level state to a low level state.

[0083] Optionally, continue to Figure 2 In a specific embodiment of the present application, the reset unit 202 includes: a Schmitt trigger (Schmitt trigger, SMT), and a first inverter INV1.

[0084] The input end of the Schmitt trigger SMT receives the first control voltage signal Net1, and the output end of the Schmitt trigger SMT outputs the inverted reset signal PORN. The second voltage threshold is the threshold voltage of the Schmitt trigger. The input end of the first inverter I1 is connected to the output end of the Schmitt trigger SMT, the output end of the first inverter INV1 outputs the reset signal, and the input end of the first inverter INV1 receives the inverted reset signal PORN.

[0085] Specifically, the power supply terminal of the Schmitt trigger SMT receives the power-on voltage signal VDD, and the ground terminal is grounded GND. The power supply terminal of the first inverter receives the power-on voltage signal VDD, and the ground terminal is grounded GND. The power supply terminal of the Schmitt trigger SMT receives the power-on voltage signal, and after the power-on voltage signal is greater than the NMOS tube conduction voltage threshold in the Schmitt trigger SMT, the Schmitt trigger SMT can enter a normal working state. After the power-on voltage signal is greater than the NMOS tube conduction voltage threshold in the Schmitt trigger SMT, the Schmitt trigger SMT receives the first control voltage signal output by the first control unit 201. When the first control voltage signal is greater than the second voltage threshold, that is, greater than the rising threshold voltage of the Schmitt trigger, the output inverted reset signal is a low level, and when the first control voltage signal is less than or equal to the second voltage threshold, the output inverted reset signal is a low level. The input end of the first inverter INV1 receives the inverted reset signal PORN, so when the first control voltage signal is greater than the second voltage threshold, the output reset signal POR is a high level, and when the first control voltage signal is less than or equal to the second voltage threshold, the output reset signal POR is a low level. The rising threshold voltage of the Schmitt trigger can be set and adjusted.

[0086] Optionally, when the first control voltage signal is less than or equal to the second voltage threshold, the output inverted reset signal PORN is in a high level state, and the second switch tube is turned on, so that the voltage value of the first control voltage signal Net is K1 times the power-on voltage signal VDD, wherein When the first control signal is greater than the second voltage threshold, the output inverted reset signal PORN is in a low level state, so that the second switch tube is turned off. At this time, the voltage value of the first control voltage signal Net1 is equal to the voltage value of the power-on voltage signal.

[0087] For details, see Figure 3 When the first control voltage signal Net1 is greater than the second voltage threshold, the voltage of the first control voltage signal Net1 will be equal to the voltage value of the power-on voltage signal VDD, and will always be greater than the second voltage threshold, so that PORN will always be in a low level state, and the reset signal POR will also always be in a high level state, indicating that the circuit system is in an operable state.

[0088] In the existing power-on reset circuit, when the circuit system is powered on slowly, a reset signal is issued when the power-on voltage only reaches the on-voltage of the inverter (about 0.7V). At this time, the voltage of the circuit system has not yet reached the working voltage value and has not entered the working state. The reset signal is invalid and has no reset effect.

[0089] In the embodiment of the present application, the way of adjusting K1 can be achieved by changing the resistance values ​​of the first resistor and the second resistor in the first control unit, or by setting the second voltage threshold, so that when the voltage value of the first control voltage signal is the second voltage threshold, the voltage value of the power-on voltage signal is greater than or equal to the working voltage threshold, and then the voltage value of the first control voltage signal is greater than the second voltage threshold, that is, when the voltage value of the power-on voltage signal is greater than or equal to the working voltage threshold, the reset signal becomes a high level state. Compared with the prior art, the power-on reset circuit proposed in the embodiment of the present application can send a high level reset signal after the power-on voltage signal reaches the working voltage threshold by setting the value of K1 and / or the second voltage threshold, and the reset signal will not fail, and the reliability is higher.

[0090] Optionally, see Figure 4 In a specific embodiment of the present application, the power-on reset circuit further includes: a second control unit 403 , a third control unit 404 , and a fourth control unit 405 .

[0091] The second control unit 403 is used to receive the power-on voltage signal and the enable signal, invert the enable signal, output the inverted enable signal, and if the enable signal is in a normal state, output a second control voltage signal whose voltage value is K2 and the ratio of the power-on voltage signal to the power-on voltage signal, wherein K2 is a positive number less than 1.

[0092] For details, see Figure 5 When the circuit is powered on, the enable signal EN and the power-on voltage signal VDD in the normal state are both in a state of gradually rising from zero. After the enable signal EN rises to a high level state, since the inverted signal of the enable signal EN is an inverted enable signal, the inverted enable signal at this time is in a low level state. Under the control of the low level state of the inverted enable signal, the second control unit 403 outputs a second control voltage signal whose ratio of the voltage value to the power-on voltage signal is K2 according to the power-on voltage signal VDD and the enable signal EN. K2 is a positive number less than 1, and K2 can be set by the third resistor and the fourth resistor in the second control unit 403. Optionally, the power-on voltage signal can be a voltage-dividing signal of the power-on voltage signal. The third resistor and the fourth resistor are voltage-dividing resistors.

[0093] Optionally, in a specific embodiment of the present application, the second control unit is further configured to: if the enable signal is in an abnormal state, the second control voltage signal output by the second control unit is zero. When the enable signal is in a normal state, it will gradually rise from zero, but when the enable signal is in an abnormal state, Figure 6, the initial state of the enable signal EN is an indeterminate state, which may be zero or a medium-low level state. At this time, the inverted enable signal is at a high level, and cannot control the second control voltage signal whose ratio of the output voltage value to the power-on voltage signal is K2, that is, the second control voltage signal output by the second control unit is zero.

[0094] Optionally, continue to Figure 4 In a specific embodiment of the present application, the second control unit 403 includes: a second inverter INV2, a third switch tube Q3, a third resistor R3 and a fourth resistor R4.

[0095] The input end of the second inverter INV2 receives the enable signal EN, and the output end of the second inverter INV2 is connected to the control end of the third switch tube Q3. Among them, the output end of the second inverter INV2 outputs the inverted enable signal ENN. The power supply end of the second inverter INV2 is connected to the power-on voltage signal VDD, and the ground end is grounded GND. The first end of the third switch tube Q3 receives the power-on voltage signal VDD, and the second end of the third switch tube Q3 is connected to one end of the third resistor R3. The other end of the third resistor R3 is connected to one end of the fourth resistor R4. Among them, the common end between the third resistor R3 and the fourth resistor R4 outputs the second control voltage signal Net2. The other end of the fourth resistor R4 is grounded.

[0096] When the enable signal EN is in a normal state, the voltage values ​​of the enable signal EN and the power-on voltage signal VDD begin to gradually rise. When EN rises to a high level state, the inverted reset signal ENN output by the second inverter INV2 is in a low level state, so that the third switch tube Q3 is turned on under low level control, and the branch where the third resistor R3 and the fourth resistor R4 are located is turned on. The voltage value of the second control signal Net2 at this time is

[0097] When the enable signal EN is in an abnormal state, the inverted enable signal ENN is in a high level state, the third switch tube Q3 is not conducting, the branch where the third resistor R3 and the fourth resistor R4 are located is not conducting, and the voltage value of the second control signal Net2 is zero.

[0098] Optionally, the third switch tube Q3 is a PMOS tube.

[0099] The third control unit 404 connected to the second control unit 403 is used to receive the power-on voltage signal, the inverted enable signal, and the second control voltage signal. If the enable signal is in a normal state, when the second control voltage signal is greater than or equal to the third voltage threshold, the inverted enable signal and the second control voltage signal control the output voltage value of the third control voltage signal to be zero. When the second control voltage signal is less than the third voltage threshold, the inverted enable signal and the second control voltage signal control the output voltage value of the third control voltage signal to be equal to the value of the power-on voltage signal. When the voltage value of the second control voltage signal is equal to the third voltage threshold, the voltage value of the power-on voltage signal is greater than the operating voltage threshold at which the subsequent circuit can work.

[0100] Specifically, when the enable signal is in a normal state, the second control voltage signal whose voltage value output by the second control unit 403 and whose ratio to the power-on voltage signal is K2 is received by the second control unit 404. When the second control voltage signal is greater than or equal to the third voltage threshold, under the control of the low level state of the inverted enable signal and the second control voltage signal, the third control voltage signal whose voltage value is zero is output. When the second control voltage signal is less than the third voltage threshold, under the control of the low level state of the inverted enable signal and the second control voltage signal, the third control voltage signal whose voltage value is equal to the value of the power-on voltage signal is output.

[0101] For details, see Figure 5 , when the enable signal EN is in a normal state, as the enable signal EN and the power-on voltage signal VDD gradually increase, the second control voltage signal whose voltage value is K2 to the power-on voltage signal VDD also gradually increases. When the second control voltage signal is less than the third voltage threshold, under the control of the low level state of the inverted enable signal and the second control voltage signal, the third control voltage signal Net3 whose voltage value is equal to the value of the power-on voltage signal is output, that is, when the second control voltage signal is less than the third voltage threshold, the third control voltage signal Net3 gradually increases according to the value of the power-on voltage signal, but when the second control voltage rises to the third voltage threshold, the voltage value of the power-on voltage signal VDD is greater than or equal to the operating voltage threshold. At this time, under the control of the low level state of the inverted enable signal and the second control voltage signal, the third control voltage signal Net3 whose voltage value is zero is output. When VDD continues to rise to a high level state, the third control voltage signal Net3 is always output as zero.

[0102] Among them, since when the voltage value of the second control voltage signal rises to the third voltage threshold, the voltage value of the power-on voltage signal is now greater than or equal to the working voltage threshold, the value of K2 can be set so that when K2×VDD≥V3, VDD is a value greater than or equal to the working voltage threshold, where V3 is the third voltage threshold.

[0103] Optionally, in a specific embodiment of the present application, the third control unit 404 is further configured to:

[0104] If the enable signal is in an abnormal state, the third control voltage signal output by the third control unit is zero. Figure 6 , the initial state of the enable signal is uncertain, which is zero or a medium-low level, so the inverted enable signal is a high level. When the inverted enable signal is a high level, the third control unit 404 is controlled by the low level state of the inverted enable signal, and the output third control voltage signal is also zero.

[0105] Optionally, in a specific embodiment of the present application, the third control unit 404 includes: a fourth switch tube Q4, a fifth resistor R5, and a fifth switch tube Q5.

[0106] The control end receives the fourth switch tube Q4 of the inverted enable signal ENN, the first end of the fourth switch tube Q4 receives the power-on voltage signal VDD, and the second end of the fourth switch tube Q4 is connected to one end of the fifth resistor R5. The other end of the fifth resistor R5 is connected to the second end of the fifth switch tube Q5. The control end of the fifth switch tube Q5 receives the second control voltage signal Net2, and the first end of the fifth switch tube Q5 is grounded GND. Among them, the common end between the fifth switch tube Q5 and the fifth resistor R5 outputs the third control voltage signal Net3. The third voltage threshold is the turn-on voltage threshold of the fifth switch tube Q5.

[0107] When the enable signal EN is in a normal state, the voltage of the enable signal EN rises, the inverted enable signal ENN is in a low level state, the fourth switch tube Q4 is turned on, and the fifth switch tube Q5 is turned on when the second control signal Net2 rises to a value greater than or equal to the third voltage threshold. At this time, the fifth switch tube Q5 is turned on and grounded, so the voltage value of the third control signal Net3 is zero. When the second control signal Net2 is less than the third voltage threshold, the fifth switch tube Q5 is not turned on. At this time, the third control voltage signal is connected to the power-on voltage signal VDD through the turned-on fourth switch tube, so the output voltage value is equal to the power-on voltage signal VDD.

[0108] When the enable signal EN is in an abnormal state, the inverted enable signal is in a high level state, the fourth switch tube Q5 is turned off and not conducting, and the voltage value of the third control voltage signal output by the third control unit 404 is zero.

[0109] Optionally, the fourth switch tube Q4 is a PMOS tube, and the fifth switch tube Q5 is an NMOS tube.

[0110] The fourth control unit 405, which is respectively connected to the third control unit 404 and the first control unit 401, is used to receive the power-on voltage signal, the third control voltage signal and the inverted enable signal. If the enable signal is in a normal state, when the third control voltage signal is greater than or equal to the fourth voltage threshold, the third control voltage signal and the inverted enable signal are used to control the output voltage value of the first control voltage signal to be zero. When the third control voltage signal is zero, the fourth control unit stops controlling the first control voltage signal, and the first control unit controls the output of the first control voltage signal.

[0111] See also Figure 5 , when the enable signal EN is in a normal state, the third control unit 404 outputs a third control voltage signal Net3 whose voltage value is equal to the value of the power-on voltage signal VDD when the second control voltage signal is less than the third voltage threshold. As the power-on voltage signal VDD increases, the third control voltage signal Net3 received by the fourth control unit 405 also increases with VDD, but when the third control voltage signal Net3 is greater than or equal to the fourth voltage threshold, the third control voltage signal and the inverted enable signal control the output voltage value of the first control voltage signal Net1 to be zero. As VDD continues to rise, when the second control voltage signal gradually rises to a value greater than or equal to the third voltage threshold, the third control voltage signal Net3 is zero. When the third control voltage signal Net3 is zero, the fourth control unit 405 does not control the first control voltage signal Net1, and the first control unit 401 controls the output of the first control voltage signal Net1. Therefore, when the enable signal EN is in a normal state, during the VDD power-on process, the third control voltage signal Net3 gradually rises from zero and then drops to zero.

[0112] Optionally, the fourth control unit 405 is further configured to:

[0113] If the enable signal is in an abnormal state, the third control voltage signal output by the third control unit is pulled down to zero, the control of the output of the first control voltage signal is stopped, and the output of the first control voltage signal is controlled by the first control unit.

[0114] When the enable signal is in an abnormal state, since the initial level state of the enable signal is in an unstable state, the inverted enable signal is in a high level state during the power-on process. Under the control of the high level state of the inverted enable signal, the fourth control unit 405 pulls the third control voltage signal down to zero. When the third control voltage signal is zero, the fourth control unit 405 does not control the first control voltage signal. At this time, the first control unit 401 and the reset unit 402 work normally, that is, when the power-on voltage signal is greater than or equal to the first voltage threshold, the first control unit outputs a first control voltage signal whose ratio to the power-on voltage signal is K1, and when the first control voltage signal is greater than the second voltage threshold, the reset unit 402 outputs a low-level inverted reset signal and a high-level reset signal according to the first control voltage signal, so that the entire circuit system is initialized and enters a state of preparation for work.

[0115] See also Figure 6 When the enable signal EN is in an abnormal state, it can be seen that the third control voltage signal received by the fourth control unit is always zero, so the first control voltage signal Net1 cannot be controlled. At this time, the first control voltage signal Net1 is output controlled by the first control unit and the reset unit, and the changes of the first control voltage signal Net1, the reset signal POR and the power-on reset signal PORN when EN is in an abnormal state are similar to Figure 3 The changes of EN in the normal state shown are basically the same. The difference is that when the enable signal EN is in the normal state, the PORN signal is triggered to change from a low level to a high level only when the second control voltage signal received by the third control unit 404 is greater than or equal to the third voltage threshold, and when the enable state EN is in the abnormal state, the first control voltage signal is controlled only by the first control unit and the reset unit. Therefore, from the above description of the execution process and principle of the first control unit and the reset unit, it can be seen that the POR signal is triggered to change from a low level to a high level when the first control unit is greater than the second voltage threshold.

[0116] Optionally, continue to Figure 4 In a specific embodiment of the present application, the fourth control unit 405 includes: a sixth switch tube Q6 and a seventh switch tube Q7.

[0117] A sixth switch tube Q6 receives the inverted enable signal ENN at its control end, a first end of the sixth switch tube Q6 is grounded, and a second end of the sixth switch tube Q6 receives the third control voltage signal Net3.

[0118] The control terminal receives the seventh switch tube Q7 of the third control voltage signal Net3, the first terminal of the seventh switch tube Q7 is grounded GND, and the second terminal of the seventh switch tube Q7 outputs the first control voltage signal Net1. The fourth voltage threshold is the conduction voltage threshold of the seventh switch tube Q7.

[0119] When the enable signal EN is in a normal state, ENN is in a low level state, at which time the sixth switch tube Q6 is not turned on, and the control end of the seventh switch tube Q7 receives the third control voltage signal Net3. When the third control voltage signal Net3 is greater than or equal to the fourth voltage threshold (i.e., the conduction threshold of the seventh switch tube Q7), the seventh switch tube is turned on. Since the second end of the seventh switch tube Q7 outputs the first control voltage signal Net1, the first control voltage signal Net1 is pulled down to ground, and the output voltage is zero. When the third voltage control signal Net3 is zero, the seventh switch tube Q7 is not turned on, and therefore does not control the output of the first control voltage signal Net1.

[0120] When the enable signal EN is in an abnormal state, ENN is in a high level state, the sixth switch tube Q7 is turned on, the control end of the seventh switch tube Q7 is grounded through the sixth switch tube, the output of the third control voltage signal Net3 is zero, and the seventh switch tube Q7 does not control the output of the first control voltage signal Net1.

[0121] Optionally, the sixth switch tube Q6 and the seventh switch tube Q7 are NMOS tubes.

[0122] Optionally, in Figure 4 The power-on reset circuit shown in the figure is in a normal state when the enable signal EN changes from a high level to a low level state. Figure 4 The third switch tube Q3 and the fourth switch tube Q4 shown are in the off state, the branch where the third resistor R3 is located and the branch where the fifth resistor R5 is located are not conducting, the first switch tube Q1 in the first control unit 401 is conducting, the voltage value of the first control voltage signal is still consistent with the power-on voltage signal, the output reset signal is still in a high level state, and only the first control unit 401 and the reset unit 402 are running in the entire power-on reset circuit, entering a low power consumption state.

[0123] For details, see Figure 5 , when the enable signal is in a normal state, after the enable signal EN changes from a high level to a low level, the first control voltage signal Net1 is still in a high level state, and the third control voltage signal Net3 is in a low level, the reset signal POR remains in a high level state, and the inverted reset signal PORN remains in a low level state. Figure 6 When the enable signal is in an abnormal state, after the enable signal EN changes from a high level to a low level, the first control voltage signal Net1 is still in a high level state, and the third control voltage signal Net3 is in a low level, the reset signal POR remains in a high level state, and the inverted reset signal PORN is always in a low level state.

[0124] See also Figure 4, when the power-on reset signal also includes the second control unit 403, the third control unit 404, and the fourth control unit 405, when the enable signal EN is in a normal state, in the initial stage of power-on, the third switch tube Q3 and the fourth switch tube Q4 are both in a conducting state, and as the power-on voltage signal VDD increases, when the second control voltage signal Vet2 is still less than the third voltage threshold, the voltage value of the third control voltage signal is equal to the power-on voltage signal, and as the power-on voltage signal VDD increases, Q7 is turned on, the first control voltage signal is pulled down to zero, and the power-on reset signal POR is output as a low level, and in the first When the second control voltage signal Vet2 increases to be greater than or equal to the third voltage threshold, the power-on voltage signal VDD is greater than or equal to the working voltage threshold, the fifth switch tube Q5 is turned on, the third control voltage signal Net3 is pulled down to a low level state, and the first control voltage signal Q1 outputs the first control voltage signal Net1 with a ratio of K1 to the power-on voltage signal under the control of the first control unit 401, and when the first control voltage signal Net1 is greater than the second voltage threshold, the inverted reset signal of the low level state and the reset signal of the high level state are output according to the first control voltage signal. Therefore, when the power-on reset signal also includes the second control unit 403, the third control unit 404, and the fourth control unit 405, the condition for issuing the high level reset signal POR is when the second control voltage signal Net2 increases to be greater than or equal to the third voltage threshold.

[0125] When the enable signal EN is in an abnormal state, only the first control unit 401 and the reset unit 402 control the generation of the reset signal POR. The condition at this time is only when the first control voltage signal is greater than the second voltage threshold, that is, the power-on voltage signal VDD is greater than the operating voltage threshold of the subsequent circuit, and the low-level inverted reset signal and the high-level reset signal POR are output according to the first control voltage signal Net1. The condition for issuing the high-level reset signal POR is when the first control voltage signal Net1 increases to be greater than or equal to the second voltage threshold.

[0126] Therefore, when the power-on reset signal also includes the second control unit 403, the third control unit 404, and the fourth control unit 405, no matter whether the enable signal is abnormal, a high level reset signal can be issued when the power-on voltage signal VDD reaches the operating voltage threshold.

[0127] It should be noted that the first end of the switch tube in the power-on reset circuit mentioned above is the source, and the second end is the gate. The switch tube can be a device with a control switch function such as a MOS tube and a transistor.

[0128] In the power-on reset circuit proposed in the embodiment of the present application, the first control unit can output a first control voltage signal whose voltage value is K1 to the power-on voltage signal under the control of the inverted reset signal when the power-on voltage signal is greater than or equal to the first voltage threshold. Since the voltage value of the power-on voltage signal is gradually rising during the power-on process, the first control voltage signal is also gradually rising, and the reset unit in the embodiment of the present application outputs an inverted reset signal in a low-level state and a reset signal in a high-level state when the first control voltage signal is greater than the second voltage threshold, and outputs an inverted reset signal in a high-level state and a reset signal in a low-level state when the first control voltage signal is less than or equal to the second voltage threshold. Since the reset unit changes the reset signal from a low level state to a high level state when the first control voltage signal is greater than the second voltage threshold, that is, the power-on reset circuit generates a reset signal only when the first control voltage signal is greater than the second voltage threshold, and the condition that the first control voltage signal is greater than the second voltage threshold can be changed by adjusting the setting K1, so that when the voltage value of the first control voltage signal is the second voltage threshold, the voltage value of the power-on voltage signal is greater than or equal to the working voltage threshold, and then the voltage value of the first control voltage signal is greater than the second voltage threshold, that is, when the voltage value of the power-on voltage signal is greater than or equal to the working voltage threshold, the reset signal changes to a high level state. Compared with the prior art, the power-on reset circuit proposed in the embodiment of the present application can send a high-level reset signal after the power-on voltage signal reaches the working voltage threshold by setting the value of K1, and the reset signal will not fail, and the reliability is higher.

[0129] Based on the power-on reset circuit proposed in the above embodiment of the present application, the embodiment of the present application correspondingly discloses a power-on reset method, including:

[0130] A power-on voltage signal and an inverted reset signal are received. Under the control of the inverted reset signal, when the power-on voltage signal is greater than or equal to a first voltage threshold, a first control voltage signal having a voltage value and a ratio of K1 to the power-on voltage signal is obtained according to the power-on voltage signal. K1 is a positive number less than 1.

[0131] When the first control voltage signal is greater than the second voltage threshold, an inverted reset signal in a low level state and a reset signal in a high level state are output according to the first control voltage signal, and when the first control voltage signal is less than or equal to the second voltage threshold, an inverted reset signal in a high level state and a reset signal in a low level state are output according to the first control voltage signal. The inverted reset signal is an inverted signal of the reset signal, and when the voltage value of the first control voltage signal is the second voltage threshold, the voltage value of the power-on voltage signal is greater than or equal to the working voltage threshold.

[0132] Optionally, in a specific embodiment of the present application, the power-on reset method further includes:

[0133] An enable signal is received, the enable signal is inverted to obtain an inverted enable signal, and if the enable signal is in a normal state, a second control voltage signal having a voltage value and a ratio of K2 to the power-on voltage signal is obtained according to the power-on voltage signal. When the second control voltage signal is greater than or equal to a third voltage threshold, a third control voltage signal having a voltage value of zero is obtained by controlling the inverted enable signal and the second control voltage signal.

[0134] When the second control voltage signal is less than the third voltage threshold, the inverted enable signal and the second control voltage signal are controlled to obtain a third control voltage signal whose voltage value is equal to the value of the power-on voltage signal. Wherein, when the voltage value of the second control voltage signal is equal to the third voltage threshold, the voltage value of the power-on voltage signal is greater than or equal to the operating voltage threshold. When the third control voltage signal is greater than or equal to the fourth voltage threshold, the third control voltage signal and the inverted enable signal are controlled to obtain a first control voltage signal whose voltage value is zero. Wherein, when the third control voltage signal is zero, the third control voltage signal stops controlling the first control voltage signal.

[0135] Optionally, in a specific embodiment of the present application, the power-on reset method further includes:

[0136] If the enable signal is in an abnormal state, a second control voltage signal with a voltage value of zero and a third control voltage signal with a voltage value of zero are obtained.

[0137] It should be noted that the power-on reset method shown in the above embodiments can be implemented by a software program in a computer, or can be implemented by hardware such as a circuit or a single-chip microcomputer. There are many ways to implement the power-on reset method shown in the above embodiments, including but not limited to the contents proposed in the embodiments of the present application.

[0138] The specific execution process of the power-on reset method disclosed in the above embodiment of the present application is the same as the execution process of each unit in the power-on reset circuit disclosed in the above embodiment of the present application. Please refer to the corresponding part of the power-on reset circuit disclosed in the above embodiment of the present application, and no further details will be given here.

[0139] In the power-on reset method proposed in the embodiment of the present application, under the control of the inverted reset signal, when the power-on voltage signal is greater than or equal to the first voltage threshold, a first control voltage signal whose voltage value is K1 and whose ratio to the power-on voltage signal is obtained. Wherein, K1 is a positive number less than 1. Since the voltage value of the power-on voltage signal is gradually rising during the power-on process, the first control voltage signal is also gradually rising. In the embodiment of the present application, when the first control voltage signal is greater than the second voltage threshold, an inverted reset signal in a low-level state and a reset signal in a high-level state are output, and when the first control voltage signal is less than or equal to the second voltage threshold, an inverted reset signal in a high-level state and a reset signal in a low-level state are output. When the first control voltage signal is greater than the second voltage threshold, the reset signal will change from a low level state to a high level state, that is, the reset signal is generated only when the first control voltage signal is greater than the second voltage threshold, and the condition that the first control voltage signal is greater than the second voltage threshold can be changed by adjusting the setting K1, so that when the voltage value of the first control voltage signal is the second voltage threshold, the voltage value of the power-on voltage signal is greater than or equal to the working voltage threshold, and then the voltage value of the first control voltage signal is greater than the second voltage threshold, that is, when the voltage value of the power-on voltage signal is greater than or equal to the working voltage threshold, the reset signal will become a high level state. Compared with the prior art, the power-on reset method proposed in the embodiment of the present application can send a high-level reset signal after the power-on voltage signal is greater than the working voltage threshold by setting the value of K1, and the reset signal will not fail, and the reliability is higher.

[0140] The embodiment of the present application discloses a computer storage medium for storing a program. When the program is executed, it is used to implement any one of the power-on reset methods proposed in the above embodiments.

[0141] The embodiment of the present application discloses an electronic device, including a memory and a processor, wherein the memory is used to store programs, and the processor is used to execute programs, and when the programs are executed, they are specifically used to implement any one of the power-on reset methods described in the above embodiments.

[0142] An embodiment of the present application discloses another electronic device, comprising a power-on reset circuit as described in any of the above embodiments.

[0143] The above description of the disclosed embodiments enables one skilled in the art to implement or use the present invention. Various modifications to these embodiments will be apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.

[0144] It should also be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

Claims

1. A power-on reset circuit, characterized in that: include: A first control unit, configured to receive a power-on voltage signal and an inverted reset signal, and under the control of the inverted reset signal, when the power-on voltage signal is greater than or equal to a first voltage threshold, output a first control voltage signal whose voltage value is K1 and whose ratio to the power-on voltage signal is K1 according to the power-on voltage signal; wherein K1 is a positive number less than 1; a reset unit connected to the first control unit, configured to receive the first control voltage signal, and output an inverted reset signal in a low level state and a reset signal in a high level state according to the first control voltage signal when the first control voltage signal is greater than a second voltage threshold; and output an inverted reset signal in a high level state and a reset signal in a low level state according to the first control voltage signal when the first control voltage signal is less than or equal to the second voltage threshold; wherein the inverted reset signal is an inverted signal of the reset signal; and when the voltage value of the first control voltage signal is the second voltage threshold, the voltage value of the power-on voltage signal is greater than or equal to the working voltage threshold; The first control unit comprises: A first switch tube having a first end receiving the power-on voltage signal, a control end of the first switch tube being grounded, and a second end of the first switch tube being connected to one end of a first resistor; wherein the first voltage threshold is a turn-on voltage threshold of the first switch tube; the other end of the first resistor is connected to one end of a second resistor; the other end of the second resistor is connected to a second end of the second switch tube; a common end of the first resistor and the second resistor outputs the first control voltage signal; a first end of the second switch tube is grounded, and a control end of the second switch tube receives the inverted reset signal.

2. The circuit according to claim 1, characterized in that Also includes: a second control unit, configured to receive the power-on voltage signal and the enable signal, invert the enable signal, output an inverted enable signal, and if the enable signal is in a normal state, output a second control voltage signal whose voltage value is K2 according to the power-on voltage signal and whose ratio to the power-on voltage signal is K2; wherein K2 is a positive number less than 1; a third control unit connected to the second control unit, configured to receive the power-on voltage signal, the inverted enable signal, and the second control voltage signal; if the enable signal is in a normal state, when the second control voltage signal is greater than or equal to a third voltage threshold, the inverted enable signal and the second control voltage signal are used to control the output of a third control voltage signal having a voltage value of zero; when the second control voltage signal is less than the third voltage threshold, the inverted enable signal and the second control voltage signal are used to control the output of the third control voltage signal having a voltage value equal to the value of the power-on voltage signal; wherein, when the voltage value of the second control voltage signal is equal to the third voltage threshold, the voltage value of the power-on voltage signal is greater than or equal to the operating voltage threshold; A fourth control unit connected to the third control unit and the first control unit respectively, is used to receive the power-on voltage signal, the third control voltage signal and the inverted enable signal. If the enable signal is in a normal state, when the third control voltage signal is greater than or equal to a fourth voltage threshold, the third control voltage signal and the inverted enable signal control the first control voltage signal whose output voltage value is zero; wherein, when the third control voltage signal is zero, the fourth control unit stops controlling the first control voltage signal, and the first control unit controls the output of the first control voltage signal.

3. The circuit according to claim 2, characterized in that The second control unit is further configured to: if the enable signal is in an abnormal state, the second control voltage signal output by the second control unit is zero; The fourth control unit is further used for: If the enable signal is in an abnormal state, the third control voltage signal output by the third control unit is pulled down to zero, and the control of the output of the first control voltage signal is stopped, and the first control unit controls the output of the first control voltage signal.

4. The circuit according to any one of claims 1 to 3, characterized in that: ; R1 is the resistance value of the first resistor; R2 is the resistance value of the second resistor.

5. The circuit according to any one of claims 1 to 3, characterized in that: The reset unit comprises: A Schmitt trigger whose input terminal receives the first control voltage signal, and whose output terminal outputs the inverted reset signal; wherein the second voltage threshold is a threshold voltage of the Schmitt trigger; A first inverter having an input terminal connected to the output terminal of the Schmitt trigger, the output terminal of the first inverter outputs a reset signal, and the input terminal of the first inverter receives the inverted reset signal.

6. The circuit according to claim 2 or 3, characterized in that: The second control unit comprises: A second inverter whose input terminal receives the enable signal, wherein the output terminal of the second inverter is connected to the control terminal of the third switch tube; wherein the output terminal of the second inverter outputs the inverted enable signal; The first end of the third switch tube receives the power-on voltage signal, and the second end of the third switch tube is connected to one end of the third resistor; The other end of the third resistor is connected to one end of the fourth resistor; wherein the common end between the third resistor and the fourth resistor outputs the second control voltage signal; ; R3 is the resistance value of the third resistor; R4 is the resistance value of the fourth resistor; The other end of the fourth resistor is grounded.

7. The circuit according to claim 2 or 3, characterized in that: The third control unit comprises: a fourth switch tube whose control end receives the inverted enable signal, a first end of the fourth switch tube receives the power-on voltage signal, and a second end of the fourth switch tube is connected to one end of a fifth resistor; The other end of the fifth resistor is connected to the second end of the fifth switch tube; The control end of the fifth switch tube receives the second control voltage signal, and the first end of the fifth switch tube is grounded; wherein the common end between the fifth switch tube and the fifth resistor outputs the third control voltage signal; and the third voltage threshold is the turn-on voltage threshold of the fifth switch tube.

8. The circuit according to claim 2 or 3, characterized in that: The fourth control unit comprises: A sixth switch tube whose control end receives the inverted enable signal, a first end of the sixth switch tube is grounded, and a second end of the sixth switch tube receives the third control voltage signal; A seventh switch tube receives the third control voltage signal at the control end, the first end of the seventh switch tube is grounded, and the second end of the seventh switch tube outputs the first control voltage signal; wherein the fourth voltage threshold is the turn-on voltage threshold of the seventh switch tube.

9. The circuit according to claim 4, characterized in that The first switch tube is a PMOS tube; the second switch tube is an NMOS tube.

10. The circuit according to claim 4, characterized in that The first control unit further includes: a first capacitor having one end connected to a common end of the first resistor and the second resistor, and a second end of the first capacitor being grounded.

11. A power-on reset method, characterized in that: include: receiving a power-on voltage signal and an inverted reset signal; Under the control of the inverted reset signal, when the power-on voltage signal is greater than or equal to a first voltage threshold, a first control voltage signal having a voltage value and a ratio of K1 to the power-on voltage signal is obtained according to the power-on voltage signal; wherein K1 is a positive number less than 1; When the first control voltage signal is greater than the second voltage threshold, an inverted reset signal in a low level state and a reset signal in a high level state are output according to the first control voltage signal; when the first control voltage signal is less than or equal to the second voltage threshold, an inverted reset signal in a high level state and a reset signal in a low level state are output according to the first control voltage signal; wherein the inverted reset signal is an inverted signal of the reset signal; when the voltage value of the first control voltage signal is the second voltage threshold, the voltage value of the power-on voltage signal is greater than or equal to the working voltage threshold; Wherein, the power-on reset method is implemented by the power-on reset circuit described in claim 1.

12. The method according to claim 11, characterized in that Also includes: Receive an enable signal; Inverting the enable signal to obtain an inverted enable signal; If the enable signal is in a normal state, a second control voltage signal having a voltage value and a ratio of K2 to the power-on voltage signal is obtained according to the power-on voltage signal; When the second control voltage signal is greater than or equal to a third voltage threshold, a third control voltage signal having a voltage value of zero is obtained by controlling the inverted enable signal and the second control voltage signal; When the second control voltage signal is less than the third voltage threshold, the third control voltage signal having a voltage value equal to the power-on voltage signal is obtained by controlling the inverted enable signal and the second control voltage signal; wherein, when the voltage value of the second control voltage signal is equal to the third voltage threshold, the voltage value of the power-on voltage signal is greater than or equal to the operating voltage threshold; When the third control voltage signal is greater than or equal to a fourth voltage threshold, the first control voltage signal having a voltage value of zero is obtained by controlling the third control voltage signal and the inverted enable signal; wherein, when the third control voltage signal is zero, the third control voltage signal stops controlling the first control voltage signal.

13. The method according to claim 12, characterized in that Also includes: If the enable signal is in an abnormal state, the second control voltage signal with a voltage value of zero and the third control voltage signal with a voltage value of zero are obtained.

14. A computer storage medium, characterized in that: Used to store a program, which, when executed, is used to implement the power-on reset method as described in any one of claims 11 to 13.

15. An electronic device, characterized in that: including memory and processor; Wherein, the memory is used to store programs; The processor is used to execute the program, and when the program is executed, it is specifically used to implement the power-on reset method as described in any one of claims 11 to 13.

16. An electronic device, characterized in that: Comprising the power-on reset circuit as claimed in any one of claims 1 to 10.

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