Three-dimensional storage device and method of manufacturing the same

Abstract

In some aspects, a memory device includes a plurality of bottom phase change memory (PCM) cells, a plurality of top PCM cells over the plurality of bottom PCM cells, a plurality of bottom dummy cells at least partially surrounding the plurality of bottom PCM cells in a plan view, a plurality of top dummy cells over the plurality of bottom dummy cells, a first gap fill layer between adjacent bottom PCM cells, a second gap fill layer at least partially surrounding the plurality of bottom PCM cells in a plan view, a third gap fill layer between adjacent top PCM cells, and a fourth gap fill layer at least partially surrounding the plurality of top PCM cells in a plan view.

Description

BACKGROUND OF THE DISCLOSURE

[0001] The present disclosure relates to three-dimensional (3D) storage devices, layouts, and methods of manufacturing the same.

[0002] By improving process technology, circuit design, programming algorithms, and manufacturing processes, planar memory cells have been scaled down to smaller dimensions. However, as the feature size of memory cells approaches the lower limit, planar processes and manufacturing technologies become challenging and costly. As a result, the storage density of planar memory cells approaches the upper limit.

[0003] Three-dimensional (3D) storage architectures can address the density limitations in planar memory cells. A 3D storage architecture includes a memory array and a peripheral device for controlling signals to and from the memory array. For example, phase change memory (PCM) can utilize the difference in resistivity between the amorphous and crystalline phases of a phase change material based on electrothermal heating and quenching of the phase change material. PCM array cells can be vertically stacked in a 3D manner to form a 3D PCM device.

[0004] The layout configuration of the peripheral device in a storage device corresponds to the pattern and arrangement of a plurality of peripheral units or components therein. SUMMARY OF THE INVENTION

[0005] According to one aspect, a storage device includes a plurality of bottom phase change memory (PCM) cells, a plurality of top PCM cells on the plurality of bottom PCM cells, a plurality of bottom dummy cells at least partially surrounding the plurality of bottom PCM cells in a plan view, a plurality of top dummy cells on the plurality of bottom dummy cells, a first gap-fill layer between adjacent bottom PCM cells, a second gap-fill layer at least partially surrounding the plurality of bottom PCM cells in a plan view, a third gap-fill layer between adjacent top PCM cells, and a fourth gap-fill layer at least partially surrounding the plurality of top PCM cells in a plan view.

[0006] In some embodiments, the first gap-fill layer has better gap-filling ability than the second gap-fill layer, and the third gap-fill layer has better gap-filling ability than the fourth gap-fill layer.

[0007] In some embodiments, the first gap-fill layer has better thermal insulation ability than the second gap-fill layer, and the third gap-fill layer has better thermal insulation ability than the fourth gap-fill layer.

[0008] In some embodiments, the first gap-fill layer includes the same material as the third gap-fill layer, and the second gap-fill layer includes the same material as the fourth gap-fill layer.

[0009] In some embodiments, the first gap filling layer includes ceramics, glass, air, polymers, other relevant thermal insulation materials, or combinations thereof.

[0010] In some embodiments, the thermal conductivity of the first gap filling layer is not greater than 0.6 W / (m·K).

[0011] In some embodiments, the second gap filling layer includes silicon oxide, aluminum oxide, other relevant oxide materials, or combinations thereof.

[0012] In some embodiments, the storage device further includes a bottom bit line, a word line, a top bit line, a bottom bit line contact, a word line contact, and a top bit line contact. The bottom bit line is connected between the bottom bit line contact and the bottom PCM cell, the word line is connected between the word line contact and the bottom PCM cell and between the word line contact and the top PCM cell, and the top bit line is connected between the top bit line contact and the top PCM cell.

[0013] In some embodiments, the storage device further includes a peripheral stack below the plurality of bottom PCM cells. The peripheral stack includes a bottom bit line selector connected to the bottom bit line contact, a top bit line selector connected to the top bit line contact, and a word line driver connected to the word line contact.

[0014] According to another aspect, a method of manufacturing a storage device includes: forming a bottom bit line layer, forming a plurality of bottom PCM cells and a plurality of bottom dummy cells on the bottom bit line layer, filling a plurality of first trenches between adjacent bottom PCM cells and adjacent bottom dummy cells to form a first gap filling layer, removing the first gap filling layer outside the storage area, and patterning the bottom bit line layer in the dummy area to form a bottom bit line, forming a word line layer on the plurality of bottom PCM cells and bottom dummy cells, forming a plurality of top PCM cells and a plurality of top dummy cells on the word line layer, filling a plurality of second trenches between adjacent top PCM cells and adjacent top dummy cells to form a third gap filling layer, removing the third gap filling layer outside the storage area, and patterning the word line layer in the dummy area to form a word line, forming a top bit line layer on the plurality of top PCM cells and top dummy cells, and patterning the top bit line on the top dummy cells to form a top bit line.

[0015] In some embodiments, the method further includes: forming a word line contact after removing the first gap filling layer outside the storage area and patterning the bottom bit line layer in the dummy area.

[0016] In some embodiments, the word line contact is connected between the word line layer and the bottom PCM cell.

[0017] In some embodiments, the method further includes: after removing the first inter-gap fill layer outside the storage area and patterning the bottom bit line layer in the dummy area, performing a fill to form a second inter-gap fill layer covering the bottom PCM cells and the bottom dummy cells.

[0018] In some embodiments, the method further includes: before forming a word line layer over the plurality of bottom PCM cells and the bottom dummy cells, applying a first planarization process to the second inter-gap fill layer to expose a first top surface of the bottom PCM cells.

[0019] In some embodiments, the method further includes: after removing the third inter-gap fill layer outside the storage area and patterning the word line layer in the dummy area, forming top bit line contacts.

[0020] In some embodiments, the top bit line contacts are connected between the top bit line layer and the top PCM cells.

[0021] In some embodiments, the method further includes: after removing the third inter-gap fill layer outside the storage area and patterning the word line layer in the dummy area, performing a fill to form a fourth inter-gap fill layer covering the top PCM cells and the top dummy cells.

[0022] In some embodiments, the method further includes: before forming a top bit line layer over the plurality of top PCM cells and the top dummy cells, applying a second planarization process to the fourth inter-gap fill layer to expose a second top surface of the top PCM cells.

[0023] In some embodiments, the length of each of the bottom bit line layer, the word line layer, and the top bit line layer is less than the length of the memory block. In a plan view, the bottom dummy cells at least partially surround the bottom PCM cells in the memory block.

[0024] In some embodiments, patterning the bottom bit line layer in the dummy area to form the bottom bit lines further patterns the bottom bit line layer in the storage area in a first lateral direction such that the bottom bit lines in the storage area extend in a second lateral direction.

[0025] In some embodiments, patterning the word line layer in the dummy area to form the word lines further patterns the word line layer in the storage area in a second lateral direction such that the word lines in the storage area extend in a first lateral direction.

[0026] In some embodiments, patterning the top bit line layer in the dummy area to form the top bit lines further patterns the top bit line layer in the storage area in a first lateral direction such that the top bit lines in the storage area extend in a second lateral direction.

[0027] According to another aspect, a method of manufacturing a memory device includes: forming a bottom bit line layer, forming a plurality of bottom PCM cells and a plurality of bottom dummy cells on the bottom bit line layer, patterning the bottom bit line layer in a dummy region to form bottom bit lines, forming a word line layer on the plurality of bottom PCM cells and bottom dummy cells, forming a plurality of top PCM cells and a plurality of top dummy cells on the word line layer, patterning the word line layer in a dummy region to form word lines, forming a top bit line layer on the plurality of top PCM cells and top dummy cells, and patterning the top bit line layer on the top dummy cells to form top bit lines. The length of each of the bottom bit line layer, the word line layer, and the top bit line layer is less than the length of the memory block, and in a plan view, the bottom dummy cells at least partially surround the bottom PCM cells in the memory block.

[0028] In some embodiments, the method further includes forming word line contacts after patterning the bottom bit line layer in the dummy region.

[0029] In some embodiments, the word line contacts are connected between the word line layer and the bottom PCM cells.

[0030] In some embodiments, the method further includes forming top bit line contacts after patterning the word line layer in the dummy region.

[0031] In some embodiments, the top bit line contacts are connected between the top bit line layer and the top PCM cells.

[0032] In some embodiments, patterning the bottom bit line layer in the dummy region to form bottom bit lines also patterns the bottom bit line layer in the memory region in a first lateral direction such that the bottom bit lines in the memory region extend in a second lateral direction.

[0033] In some embodiments, patterning the word line layer in the dummy region to form word lines also patterns the word line layer in the memory region in a second lateral direction such that the word lines in the memory region extend in a first lateral direction.

[0034] In some embodiments, patterning the top bit line layer in the dummy region to form top bit lines also patterns the top bit line layer in the memory region in a first lateral direction such that the top bit lines in the memory region extend in a second lateral direction. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] The drawings incorporated herein and forming a part of the specification illustrate aspects of the present disclosure and, together with the description, further serve to explain the principles of the present disclosure and enable one of ordinary skill in the relevant art to make and use the present disclosure.

[0036] Figure 1Shows a perspective view of an exemplary 3D PCM device in accordance with some aspects of the present disclosure.

[0037] Figure 2A And Figure 2B Shows a side view of a cross-section of an exemplary 3D PCM device in accordance with some aspects of the present disclosure.

[0038] Figure 3 Shows a perspective view of an exemplary 3D storage device including an exemplary 3D PCM device having an interconnect layer in accordance with some aspects of the present disclosure.

[0039] Figure 4A And Figure 4B Shows a side view of a cross-section of an exemplary 3D storage device including an exemplary 3D PCM device, an interconnect layer, and a peripheral device in accordance with some aspects of the present disclosure.

[0040] Figure 5A And Figure 5B Shows a side view of a cross-section of an exemplary 3D storage device including a 3D PCM device and an interconnect layer in accordance with some aspects of the present disclosure.

[0041] Figure 6A-6L Shows a manufacturing process for forming an exemplary 3D storage device in accordance with some aspects of the present disclosure.

[0042] Figure 7 Shows a flowchart of a method for forming an exemplary 3D storage device in accordance with some aspects of the present disclosure.

[0043] The present disclosure will be described with reference to the accompanying drawings. Detailed Description

[0044] Although specific constructions and arrangements are discussed, it should be understood that this is done for illustrative purposes only. Those skilled in the relevant art will recognize that other constructions and arrangements may be used without departing from the spirit and scope of the present disclosure. Those skilled in the relevant art will also recognize that the present disclosure can also be used in a variety of other applications.

[0045] It should be noted that references in the specification to "one embodiment", "an embodiment", "example embodiment", "some embodiments", etc., indicate that the described embodiment may include a particular feature, structure, or characteristic, but not necessarily every embodiment includes that particular feature, structure, or characteristic. Moreover, these phrases do not necessarily refer to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, whether or not explicitly described, producing such feature, structure, or characteristic in connection with other embodiments will be within the knowledge of those skilled in the relevant art.

[0046] Generally, terms can be understood, at least in part, based on their use in context. For example, depending at least in part on the context, the term "one or more" as used herein can be used to describe any feature, structure, or property in a singular sense, or can be used to describe a combination of features, structures, or properties in a plural sense. Similarly, depending at least in part on the context, terms such as "a" or "the" can also be understood to convey a singular usage or to convey a plural usage. Additionally, again depending at least in part on the context, the term "based on" can be understood to not necessarily be intended to convey a set of exclusive factors, and can instead allow for the existence of additional factors that are not necessarily explicitly described.

[0047] It should be readily understood that the meanings of "above", "over", and "on" in this disclosure should be interpreted in the broadest sense such that "above" not only means directly "on" something, but also includes the meaning of being "on" something with intermediate features or layers therebetween, and "over" or "on" not only means the meaning of being "above" or "over" something, but can also include the meaning of being "above" or "over" something with no intermediate features or layers therebetween (i.e., directly on something).

[0048] In addition, for ease of description, spatial relative terms such as "below", "beneath", "lower", "above", "upper", etc. may be used herein to describe the relationship of one element or feature to another (or other) element or feature as shown in the figures. In addition to the orientation depicted in the figures, the spatial relative terms are also intended to encompass different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein may be interpreted correspondingly.

[0049] As used herein, the term "substrate" refers to a material on which subsequent material layers are added. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. Additionally, the substrate may include a variety of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material such as glass, plastic, or a sapphire wafer.

[0050] As used herein, the term "layer" refers to a portion of material that includes a region having a thickness. A layer can extend over an entire underlying or overlying structure, or can have an extent that is less than the extent of the underlying or overlying structure. Additionally, a layer can be a region of a homogeneous or heterogeneous continuous structure, the thickness of which is less than the thickness of the continuous structure. For example, a layer can be located between the top and bottom surfaces of a continuous structure, or between any pair of horizontal planes at the top and bottom surfaces of the continuous structure. A layer can extend horizontally, vertically, and / or along a tapered surface. A substrate can be a layer, can include one or more layers therein, and / or can have one or more layers thereon, above, and / or below it. A layer can include multiple layers. For example, an interconnect layer can include one or more conductors and contact layers (in which interconnect lines and / or via contacts are formed) and one or more dielectric layers.

[0051] As used herein, the term "3D" memory device or PCM device refers to a semiconductor device having memory cells that can be arranged on a substrate in a lateral orientation such that the number of memory cells can be scaled in a direction perpendicular to the substrate. As used herein, the term "vertical / vertically" refers to being nominally perpendicular to the lateral surface of the substrate.

[0052] Based on electrothermal heating and quenching of a phase change material (e.g., a chalcogenide alloy), a PCM can utilize the difference in resistivity between the amorphous and crystalline phases of the phase change material. The phase change material in a PCM cell can be located between two electrodes, and a current can be applied to repeatedly switch the material (or at least a portion of the material that blocks a current path) between the two phases to store data. PCM cells can be vertically stacked in a 3D manner to form a 3D PCM device. The 3D PCM device stores data based on a change in resistance of a bulk material property (e.g., being in a high resistance state or a low resistance state), in combination with an addressable stackable cross-point data access array.

[0053] As memory devices have evolved, more memory cell stacks have been arranged in memory devices. Specifically, multiple memory cells are stacked and arranged in a memory block. And multiple memory blocks are arranged in a single die. Conventionally, memory blocks are arranged in a die such that the memory cells therein are pre-determined in certain regions of the die as memory areas, while dummy cells are arranged on the dummy areas of the die that are between adjacent memory blocks. Depending on the circuit design, the dummy cells can have various uses. For example, the dummy cells are configured to operate as memory capacitors that are connected to a source line to provide a bias voltage, or to a source at ground level.

[0054] One of the manufacturing methods for forming memory cells and dummy cells in a memory block is to first form the memory block and then form the dummy cells around the memory block. However, due to the narrow block edges of the memory block, the gap between the dummy cells and the memory block may cause some etch loading effects. That is, the etch depth cannot be well controlled at the narrow block edges, resulting in uneven etch depth distribution and even some leakage paths between the dummy cells and the memory cells. In addition, chemical mechanical polishing (CMP) or other planarization processes may not be easily performed at the block edges. The low local pattern density at the block edges can lead to an uneven surface, such as metal depression or dielectric corrosion after the CMP process. These can also generate more defects on the memory cells at the block edges.

[0055] Another manufacturing method for forming the memory block and the dummy cells is to form both the memory cells and the dummy cells including bit lines and word lines connected between the memory cells and the dummy cells in a single process, and then cut all the bit lines and word lines connected between adjacent dummy cells and also cut the bit lines and word lines connected between the dummy cells and the memory cells. Thus, the area of the memory block is well defined after the cutting process. However, one of the problems is that the bit lines and word lines connected between the cells and extending across the entire die are too long. The long bit lines and word lines may have a high risk of peeling or bending problems during manufacturing, resulting in some short-circuit or contact failure problems between adjacent memory cells, thus reducing the overall performance and yield.

[0056] To solve one or more of the above problems, the present disclosure introduces a storage device and a method of manufacturing the same, in which photolithographic printing on the storage device is performed block by block. That is, to solve the problems of performing full photolithographic printing over the entire die (which results in a high risk of peeling and bending problems of bit lines and word lines), by performing photolithographic printing on the memory cells and dummy cells block by block, the bit lines and word lines are not as long, and thus the risk of peeling and bending problems is minimized. In particular, according to some embodiments of the present disclosure, the method includes: forming a first semiconductor stack, patterning the first semiconductor stack to form bottom memory cells in a memory region and bottom dummy cells in a dummy region, wherein the bottom memory cells and the bottom dummy cells are connected to sacrificial bottom bit lines, gap filling the bottom memory cells and the bottom dummy cells to form a first gap-fill layer, planarizing (e.g., CMP) the first gap-fill layer until the tops of the bottom memory cells and the bottom dummy cells, patterning to cut off the sacrificial bottom bit lines to form bottom bit lines, and also removing the first gap-fill layer outside the memory region, forming word line contacts in a contact region, gap filling the dummy region, the memory region, and the contact region to form a second gap-fill layer, planarizing the second gap-fill layer until the tops of the bottom memory cells and the bottom dummy cells, forming sacrificial bottom word lines connected between the word line contacts and the bottom memory cells on the bottom memory cells, and patterning to cut off the sacrificial bottom word lines to form bottom word lines, and also removing the second gap-fill layer in the dummy region. Thereafter, bottom memory cells having bottom bit lines and bottom word lines are formed.

[0057] In addition, the method further includes: forming a second semiconductor stack, patterning the second semiconductor stack to form top memory cells in a memory region and top dummy cells in a dummy region, wherein the top memory cells and the top dummy cells are both connected to a sacrificial top word line, gap filling the top memory cells and the top dummy cells to form a third gap-fill layer, planarizing (e.g., CMP) the third gap-fill layer until the tops of the top memory cells and the top dummy cells, patterning to cut off the sacrificial top word line to form top word lines, and also removing the third gap-fill layer outside the memory region, forming top bit line contacts in a contact region, gap filling the dummy region, the memory region, and the contact region to form a fourth gap-fill layer, planarizing the fourth gap-fill layer until the tops of the top memory cells and the top dummy cells, forming sacrificial top bit lines connected between the top bit line contacts and the top memory cells on the top memory cells, and patterning to cut off the sacrificial top bit lines to form top bit lines, and also removing the fourth gap-fill layer in the dummy region. Thereafter, top memory cells having top word lines and top bit lines are formed.

[0058] Note that, in some embodiments, the first gap-fill layer (and the third gap-fill layer) and the second gap-fill layer (and the fourth gap-fill layer) may include different materials such that, compared with the second gap-fill layer, the first gap-fill layer formed between the trenches of the memory cells may provide better gap-filling ability to fill the trenches in a narrower space. In addition, the first gap-fill layer formed between the trenches of the memory cells may provide better thermal insulation ability, thereby reducing thermal crosstalk that may undesirably switch adjacent unselected memory cells.

[0059] It should also be noted that, in some embodiments, the sacrificial bit lines and the sacrificial word lines are deposited only in block lengths, thus minimizing the risk of stripping and bending problems of the bit lines and the word lines.

[0060] Figure 1 A perspective view of an exemplary 3D PCM device 100 according to some embodiments of the present disclosure is shown. According to some embodiments, the 3D PCM device 100 has a transistorless cross-point architecture that positions memory cells at intersections of vertical conductors. The 3D PCM device 100 includes one or more bottom bit lines 133 in the same plane and one or more parallel top bit lines 131 in the same plane above the bottom bit lines 133. The 3D PCM device 100 further includes one or more parallel word lines (e.g., top word line 141, bottom word line 143, or a combination thereof) in the same plane that are vertically located between the bottom bit lines 133 and the top bit lines 131. As Figure 1 shown, each bottom bit line 133 and each top bit line 131 extend laterally in a bit line direction (e.g., the x direction) in a plan view (parallel to the wafer plane), and each word line 141 / 143 extends laterally in a word line direction (e.g., the y direction) in the plan view. In the plan view, each word line 141 / 143 intersects each bottom bit line 133 and each top bit line 131. In some embodiments, each word line 141 / 143 is perpendicular to each bottom bit line 133 and each top bit line 131.

[0061] Note that in Figure 1 the x-axis and the y-axis are included to show two orthogonal directions in the wafer plane. The x direction is the bit line direction, and the y direction is the word line direction. Note that the x direction and the y direction are interchangeable; that is, the x direction can be the word line direction, and the y direction can be the bit line direction. It should also be noted that in Figure 1includes a z-axis to further illustrate the spatial relationship of the components in the 3D PCM device 100. The substrate (not shown) of the 3D PCM device 100 includes two lateral surfaces that extend laterally in the x-y plane: a top surface on the front side of the wafer, and a bottom surface on the back side of the wafer opposite the front side. The z-axis is perpendicular to the x-axis and the y-axis. As used herein, when the substrate is in the lowest plane of a semiconductor device (e.g., the 3D PCM device 100) in the z-direction (the vertical direction perpendicular to the x-y plane), whether a component (e.g., a layer or a device) of the semiconductor device is "on", "above", or "below" another component (e.g., a layer or a device) in the z-direction is determined relative to the substrate of the semiconductor device. The same concepts for describing spatial relationships are applied throughout this disclosure.

[0062] As Figure 1As shown, the 3D PCM device 100 includes one or more top PCM cells 151 and one or more bottom PCM cells 153. Each top PCM cell 151 is disposed at the intersection of a top bit line 131 and a corresponding word line 141 / 143, and each bottom PCM cell 153 is disposed at the intersection of a bottom bit line 133 and a corresponding word line 141 / 143. In some embodiments, each of the top PCM cells 151 or the bottom PCM cells 153 has a vertical square pillar shape. In some embodiments, each of the top PCM cells 151 or the bottom PCM cells 153 includes at least a vertically stacked PCM element and a selector. In some embodiments, the selector is formed between the bottom bit line 133 and the PCM element. In some embodiments, each of the top PCM cells 151 or the bottom PCM cells 153 further includes a heater connected to the PCM element. Each of the top PCM cells 151 or the bottom PCM cells 153 stores a single data bit and can be written or read by changing the voltage applied to the corresponding selector, eliminating the need for a transistor. Each of the top PCM cells 151 or the bottom PCM cells 153 is individually accessed by current applied via top and bottom conductors (e.g., the corresponding word lines 141 / 143 and the top or bottom bit lines 131 or 133) in contact with each PCM cell. The top PCM cells 151 or the bottom PCM cells 153 in the 3D PCM device 100 are arranged in a memory array. In some embodiments, the PCM element may include a chalcogenide composition that includes at least one of germanium (Ge), antimony (Sb), tellurium (Te), indium (In), or gallium (Ga). In some embodiments, each of the bit lines 131, 133, and the word lines 141 / 143 includes a metal such as tungsten. In some embodiments, the PCM element may be a binary (two-element) compound such as GaSb, InSb, InSe, SbTe, or GeTe, a ternary (three-element) compound such as GeSbTe, GaSeTe, InSbTe, SnSbTe, or InSbGe, or a quaternary (four-element) compound such as AgInSbTe, (GeSn)SbTe, GeSb(SeTe), or TeGeSbS. In some embodiments, the selector may be an oval threshold switch (OTS) device made of at least one of oxygen (O), sulfur (S), selenium (Se), tellurium (Te), germanium (Ge), antimony (Sb), silicon (Si), or arsenic (As). The OTS device is formed of an OTS material that exhibits OTS characteristics.

[0063] In addition, as Figure 1As shown, the 3D PCM device 100 may further include one or more top bit line contacts 121 connected to the top bit line 131, one or more bottom bit line contacts 123 connected to the bottom bit line 133, and one or more word line contacts 125 connected to the word lines 141 / 143. The top bit line contacts 121, the bottom bit line contacts 123, and the word line contacts 125 may extend vertically in the z direction. In some embodiments, each of the top bit line contacts 121, the bottom bit line contacts 123, and the word line contacts 125 includes a metal, such as tungsten.

[0064] Figure 2A and Figure 2B FIG. shows a side view of a schematic cross-section of an exemplary 3D PCM device 100 in accordance with some aspects of the present disclosure. In Figure 2A , in a y-z plane cross-section, the 3D PCM device 100 includes one or more parallel top bit lines 131 formed on the top PCM cells 151, and one or more parallel bottom bit lines 133 formed below the bottom PCM cells 153. The word lines 141 / 143 extend laterally in the y direction between the top PCM cells 151 and the bottom PCM cells 153. In Figure 2B , in an x-z plane cross-section, the 3D PCM device 100 includes a top bit line 131 that extends laterally in the x direction and is connected to a top bit line contact 121 that extends vertically in the z direction. The 3D PCM device 100 further includes a bottom bit line 133 that extends laterally in the x direction and is connected to a bottom bit line contact 123 that extends vertically in the z direction. In some embodiments, the top bit line contacts 121 and the word line contacts 125 extend vertically in a region where no top or bottom PCM cells 151 or 153 are formed above or below.

[0065] Figure 3 FIG. shows a perspective view of an exemplary 3D PCM device 300 in accordance with some embodiments of the present disclosure. The 3D PCM device 300 includes one or more parallel bottom bit lines 333 (e.g., corresponding to Figure 1 the bottom bit line 133 in Figure 1 ), one or more parallel top bit lines 331 in the same plane above the bottom bit lines 333 (e.g., corresponding to Figure 1 the top bit line 131 in Figure 3As shown, each bottom bit line 333 and each top bit line 331 extend horizontally in a plan view (parallel to the wafer plane) along the bit line direction (e.g., the x direction), and each word line 341 / 343 extends horizontally in the plan view along the word line direction (e.g., the y direction). In the plan view, each word line 341 / 343 intersects each bottom bit line 333 and each top bit line 331. In some embodiments, each word line 341 / 343 is perpendicular to each bottom bit line 333 and each top bit line 331.

[0066] As Figure 3 shown, the 3D PCM device 300 includes one or more top PCM cells 351 (e.g., corresponding to Figure 1 the top PCM cell 151 in Figure 1 ) and one or more bottom PCM cells 353 (e.g., corresponding to Figure 1 the bottom PCM cell 153 in Figure 1 ). Each top PCM cell 351 is disposed at the intersection of a top bit line 331 and a corresponding word line 341 / 343, and each bottom PCM cell 353 is disposed at the intersection of a bottom bit line 333 and a corresponding word line 341 / 343. In some embodiments, each of the top PCM cells 351 or the bottom PCM cells 353 has a vertical square pillar shape. In some embodiments, each of the top PCM cells 351 or the bottom PCM cells 353 includes at least vertically stacked PCM elements (not shown) and a selector (not shown). Each of the top PCM cells 351 or the bottom PCM cells 353 stores a single data bit and can be written or read by changing the voltage applied to a corresponding selector (not shown), eliminating the need for a transistor. Each of the top PCM cells 351 or the bottom PCM cells 353 is individually accessed by current applied via top and bottom conductors (e.g., the corresponding word line 341 / 343 and the top or bottom bit line 331 or 333) in contact with each PCM cell. The top PCM cells 351 or the bottom PCM cells 353 in the 3D PCM device 300 are arranged in a memory array. The 3D PCM device 300 may also include one or more top bit line contacts 321 connected to the top bit line 331 (e.g., corresponding to Figure 1the word line contact 125). The top bit line contact 321, the bottom bit line contact 323, and the word line contact 325 can extend vertically in the z direction. In some embodiments, each of the top bit line contact 321, the bottom bit line contact 323, and the word line contact 325 includes a metal, such as tungsten.

[0067] The 3D PCM device 300 can include one or more top interconnect layers 365 (also referred to as top metal layers or M5 layers) that extend laterally above the memory cells of the memory array (e.g., the top PCM cells 351 or the bottom PCM cells 353). The 3D PCM device 300 can further include one or more first interconnect layers 364 (also referred to as M4 layers) that extend laterally below the PCM cells 351 / 353 of the memory array. The 3D PCM device 300 can further include one or more through-hole contacts 327 that extend vertically (e.g., in the z direction) and connect between the top interconnect layer 365 and the first interconnect layer 364.

[0068] Figure 4A and Figure 4B FIG. shows a side view of a schematic cross-section of an exemplary 3D PCM device 300 in accordance with some aspects of the present disclosure. In Figure 4A it, in a y-z plane cross-section, the 3D PCM device 300 includes one or more parallel top bit lines 331 formed on top of the top PCM cells 351 extending in the x direction, and one or more parallel bottom bit lines 333 formed below the bottom PCM cells 353 extending in the x direction. The top bit lines 331 are connected to the top bit line contacts 321, and the bottom bit lines 333 are connected to the bottom bit line contacts 323. The word lines 341 / 343 extend laterally in the y direction between the top PCM cells 351 and the bottom PCM cells 353. The word lines 341 / 343 are also connected to the word line contacts 325. The top interconnect layer 365 (also referred to as top metal layer or M5 layer) extends laterally (e.g., in the x direction or the y direction) above the PCM cells 351 / 353 of the memory array. In some embodiments, the top interconnect layer 365 extends in the y direction, which is perpendicular to the bit lines and parallel to the word lines. The first interconnect layer 364 extends laterally in the x direction or the y direction below the PCM cells 351 / 351 of the memory array. The through-hole contacts 327 extend vertically in the z direction and connect between the top interconnect layer 365 and the first interconnect layer 364. In some embodiments, the through-hole contacts 327 can further extend until, into, or through the substrate. Since Figure 4A and Figure 4B are for illustrative purposes only, an enlarged side view of a portion 500 of the exemplary 3D PCM device 300 will be discussed later to show a more detailed structure.

[0069] InFigure 4B In Figure 4B , in the x-z plane cross-section, the 3D PCM device 300 includes a top bit line 331 that extends laterally in the x direction and is connected to a top bit line contact 321 that extends vertically in the z direction. The 3D PCM device 300 further includes a bottom bit line 333 that extends laterally in the x direction and is connected to a bottom bit line contact 323 that extends vertically in the z direction. In some embodiments, the top bit line contact 321 and the word line contact 325 extend vertically in a region where no top PCM cell 351 or bottom PCM cell 353 is formed above or below.

[0070] As Figure 4A and Figure 4B shown, the 3D PCM device 300 may further include one or more peripheral blocks located below the memory array. The peripheral blocks may include one or more peripheral units that include a bottom bit line selector 303, a word line driver 305, or a top bit line selector 301. In some embodiments, the 3D PCM device 300 includes a substrate 307. One or more peripheral units include a bottom bit line selector 303, a word line driver 305, or a top bit line selector 301 formed on the substrate 307. The word line driver 305 may be connected to the word lines 341 / 343 via the word line contacts 325. A plurality of interconnect layers, such as a top interconnect layer 365, a first interconnect layer 364, a second interconnect layer 363 (also referred to as the M3 layer), a third interconnect layer 362 (also referred to as the M2 layer), a fourth interconnect layer 361 (also referred to as the M1 layer), may extend laterally (e.g., in the x direction or the y direction) and be connected via contacts between the word lines or the bit lines. The substrate 307 may include silicon (e.g., single-crystalline silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), or any other suitable material. In some embodiments, each of the word line driver (e.g., the word line driver 305), the bit line driver, or the bit line selector (e.g., the bottom bit line selector 303 and the top bit line selector 301) includes a p-channel metal oxide semiconductor (PMOS) transistor, an n-channel metal oxide semiconductor (NMOS) transistor, or a combination thereof. For ease of description, the peripheral units and the substrate may be referred to as a peripheral stack 309, and the memory cells formed on the peripheral stack 309 may be referred to as a memory stack.

[0071] Figure 5A and Figure 5B is Figure 4A and Figure 4B a magnified side view of a portion 500 of Figure 4A and Figure 4B that shows a cross-section of an exemplary 3D PCM device 300. Although Figure 5A and Figure 5B (and Figure 6A-6Lfocus only on the memory stack, but note that the peripheral stack 309 located below the memory stack is the same as or similar to the Figure 4A and Figure 4B peripheral stack 309 therein. As shown in Figure 5A , the 3DPCM device 300 includes a bottom PCM cell 353 and a top PCM cell 351 on the bottom PCM cell 353. The bottom PCM cell 353 is connected to one or more bottom bit line contacts 323 via one or more bottom bit lines 333. The top PCM cell 351 is connected to one or more top bit line contacts 321 via one or more top bit lines 331. The word lines 341 / 343 extend between the top PCM cell and the bottom PCM cell and in the y direction.

[0072] A first gap-fill layer 371 is formed and fills between adjacent bottom PCM cells 353. In some embodiments, the first gap-fill layer 371 fills in the memory region 381 (the region where the memory cells are located). A second gap-fill layer 373 is formed and fills outside the memory region 381 and may be formed within the contact region 385 (the region where the contacts (e.g., word line contacts 325 and / or top bit line contacts 321) are located). In a plan view, the second gap-fill layer 373 at least partially surrounds the first gap-fill layer 371 or the bottom PCM cells 353. Thus, in the plan view, the second gap-fill layer 373 at least partially surrounds the memory region 381. In some embodiments, the first gap-fill layer 371 may include ceramics, glass, air, polymers, other related thermal insulation materials, or combinations thereof (e.g., polymers surrounding air). In some embodiments, the thermal conductivity of the first gap-fill layer 371 does not exceed 0.6 W / (m·K). In some embodiments, the second gap-fill layer 373 may include silicon oxide, aluminum oxide, other related oxide materials, or combinations thereof. In some embodiments, the first gap-fill layer 371 has better gap-filling ability than the second gap-fill layer 373 because the first gap-fill layer 371 is configured to fill into the trenches between adjacent bottom PCM cells 353. In some embodiments, the first gap-fill layer 371 has better thermal insulation ability, thereby reducing thermal crosstalk that may undesirably switch adjacent unselected memory cells.

[0073] A third gap-fill layer 375 is formed and fills between adjacent top PCM cells 351. In some embodiments, the third gap-fill layer 375 fills in the storage region 381. A fourth gap-fill layer 377 is formed and fills outside the storage region 381 and may be formed within the contact region 385. In a plan view, the fourth gap-fill layer 377 at least partially surrounds the third gap-fill layer 375 or the top PCM cells 351. Thus, in a plan view, the fourth gap-fill layer 377 at least partially surrounds the storage region 381. In some embodiments, the third gap-fill layer 375 may include ceramics, glass, air, polymers, other related thermal insulation materials, or a combination thereof (e.g., a polymer surrounding air). In some embodiments, the thermal conductivity of the third gap-fill layer 375 does not exceed 0.6 W / (m·K). In some embodiments, the fourth gap-fill layer 377 may include silicon oxide, aluminum oxide, other related oxide materials, or a combination thereof. In some embodiments, the third gap-fill layer 375 has a better gap-filling ability than the fourth gap-fill layer 377 because the third gap-fill layer 375 is configured to fill into the trenches between adjacent top PCM cells 351. In some embodiments, the third gap-fill layer 375 has better thermal insulation ability, thereby reducing thermal crosstalk that may undesirably switch adjacent unselected memory cells. Note that the third gap-fill layer 375 may include the same or similar materials as the first gap-fill layer 371. Additionally, the fourth gap-fill layer 377 may include the same or similar materials as the second gap-fill layer 373.

[0074] Figure 5B A second side view of a cross-section of an exemplary 3D PCM device 300 is shown. As Figure 5B shown, the 3D PCM device 300 may further include dummy cells (e.g., top dummy cells 355 and bottom dummy cells 357) arranged to surround the memory cells (e.g., top PCM cells 351 and bottom PCM cells 353) in the memory block. These dummy cells 355 / 357 are located in one or more dummy regions 383. In a plan view, these dummy regions 383 may at least partially surround the storage region 381 in the memory block. As described above, these dummy cells are configured to operate as storage capacitors that are connected to a source line to provide a bias voltage, or to a source at a ground level. Note that although the shape and stack of the layers in the dummy cells are the same or similar to those of the memory cells, the dummy cells may not be connected to the bit lines or word lines in the same way as the memory cells. In some embodiments, the second gap-fill layer may not be formed and filled between adjacent dummy cells 355 / 357 in the dummy region 383, or may be only partially formed and filled between adjacent dummy cells 355 / 357.

[0075] Figure 6A-6LIllustrates a manufacturing process for forming an exemplary 3D memory device in accordance with some aspects of the present disclosure. Figure 7 Illustrates a flowchart of a method for forming an exemplary 3D memory device in accordance with some aspects of the present disclosure. The 3D memory device can be any suitable 3D memory device disclosed herein. It will be understood that the operations shown in method 700 may not be exhaustive, and other operations may be performed before, after, or between any of the shown operations. Additionally, some operations may be performed simultaneously, or in a different order than Figure 7 shown. Can be discussed together Figure 6A-6L and Figure 7 .

[0076] Referring Figure 7 , method 700 begins at operation 702, where a plurality of bottom memory cells and a plurality of bottom dummy cells are formed on a peripheral stack. Additionally, a plurality of first trenches between adjacent bottom memory cells are filled with a first gap-fill material to form a first gap-fill layer. For example, as Figure 6A shown, a plurality of bottom PCM cells 353 and a plurality of bottom dummy cells 357 are formed on a peripheral stack (e.g., Figure 4A and Figure 4B 309 in). In some embodiments, the bottom PCM cells 353 and the bottom dummy cells 357 can be formed by depositing a bottom bitline layer and depositing a first semiconductor stack on the bottom bitline layer. In some embodiments, the bottom bitline layer is deposited only for the length of a memory block. That is, the bottom bitline layer may not extend from one memory block to another. The length of the bottom bitline layer is less than the length of the memory block. Thus, the risk of peeling or bending problems is minimized. The first semiconductor stack can include a first bottom electrode layer, a first selector layer on the first bottom electrode layer, a first PCM element layer on the first selector layer, and a first top electrode layer on the first PCM element layer. By further etching or patterning the first semiconductor stack, the bottom PCM cells 353 and the bottom dummy cells 357 are formed. In some embodiments, performing the etching or patterning to form the bottom PCM cells 353 and the bottom dummy cells 357 includes a two-step etching process (also referred to as a double patterning process). That is, a first step of etching is applied to the first semiconductor stack to form a first trench 391 between adjacent bottom PCM cells 353, and a second step of etching is applied to cut the bottom bitline layer in the y direction to form a bottom bitline 333 extending in the x direction. When patterning the bottom bitline layer, the bottom bitline layer in the dummy region 383 is also patterned such that the dummy cells are isolated from each other.

[0077] Next, as Figure 6BAs shown, the first trench 391 between adjacent bottom PCM cells 353 is filled with a first gap-fill material 3711. In some embodiments, chemical mechanical polishing (CMP) or planarization may be applied to the first gap-fill material 3711 until the top surface of the bottom PCM cell 353 is exposed, such that the top surface of the bottom PCM cell 353 is exposed.

[0078] Method 700 proceeds to operation 704, as Figure 7 shown, where the first gap-fill layer outside the memory region is removed. Additionally, a word-line contact is formed thereafter. For example, as Figure 6C shown, by removing the first gap-fill material 3711 outside the memory region 381, the first gap-fill layer 371 is formed only on the memory region 381. In some embodiments, the first gap-fill material 3711 in the contact region 385 and the dummy region 383 is removed. The removal can be accomplished by wet etching, dry etching, or a combination thereof.

[0079] Next, as Figure 6D shown, a word-line contact 325 is formed that contacts, for example, a first interconnect layer (also referred to as the M4 layer 364 in Figure 4B ). The word-line contact 325 is configured to extend vertically (e.g., in the z direction) and connect between the word line and the peripheral cells below the memory stack.

[0080] Next, also as Figure 6D shown, then a second gap-fill layer 373 is filled and the second gap-fill layer 373 covers the first gap-fill layer 371, the bottom PCM cell 353, the bottom dummy cell 357, and the word-line contact 325.

[0081] Next, also as Figure 6D shown, another chemical mechanical polishing (CMP) or planarization may be applied to the second gap-fill material 373 until the top surface of the bottom PCM cell 353 is exposed, such that the top surface of the bottom PCM cell 353 is exposed.

[0082] Method 700 proceeds to operation 706, as Figure 7 shown, where a word line is formed that connects between the word-line contact and the plurality of bottom memory cells. For example, also as Figure 6E shown, a bottom word-line layer 3431 is formed and connected between the word-line contact 325, the bottom PCM cell 353, and the bottom dummy cell 357. In some embodiments, the bottom word-line layer 3431 is deposited only for the length of the memory block. That is, the bottom word-line layer 3431 may not extend from one memory block to another. The length of the bottom word-line layer 3431 is less than the length of the memory block. Thus, the risk of peeling or bending problems is minimized.

[0083] Next, asFigure 6F As shown, etching or patterning (e.g., double patterning) is applied to remove a portion of the second gap fill layer 373 in the dummy region 383 and cut off the bottom word line layer 3431 to form the bottom word line 343. That is, a first step of etching is applied to cut off the bottom word line layer 3431 in the x direction to form the bottom word line 343 extending in the y direction. Then, a second step of etching is applied to remove the portion of the second gap fill layer 373 in the dummy region 383. The bottom word line 343 can be connected between the word line contact 325 and the bottom PCM cell 353, as shown in another cross-sectional view. When patterning the bottom word line layer 3431, the bottom word line layer 3431 in the dummy region 383 is also patterned so that the dummy cells are isolated from each other.

[0084] Method 700 proceeds to operation 708, as Figure 7 shown, where a plurality of top storage cells are formed on a plurality of bottom storage cells. In addition, a plurality of second trenches filled between adjacent top storage cells are formed to form a third gap fill layer. For example, as Figure 6G shown, the top PCM cell 351 is formed on the bottom PCM cell 353, and the top dummy cell 355 is formed on the bottom dummy cell 357. Similar to or the same as forming the bottom PCM cell 353 and the bottom dummy cell 357, the top PCM cell 351 and the top dummy cell 355 can be formed by depositing a top word line layer and depositing a second semiconductor stack on the top word line layer. The second semiconductor stack may include a second bottom electrode layer, a second selector layer on the second bottom electrode layer, a second PCM element layer on the second selector layer, and a second top electrode layer on the second PCM element layer. By further etching or patterning the second semiconductor stack, the top PCM cell 351 and the top dummy cell 355 are formed.

[0085] Next, as Figure 6H shown, the second trench 393 between adjacent top PCM cells 351 is filled with a third gap fill material 3751. In some embodiments, chemical mechanical polishing (CMP) or planarization may be applied to the third gap fill material 3751 until the top surface of the top PCM cell 351 is exposed, such that the top surface of the top PCM cell 351 is exposed.

[0086] Method 700 proceeds to operation 710, as Figure 7 shown, where the third gap fill layer outside the storage region is removed and a top bit line contact is formed. For example, as Figure 6I shown, an etching or patterning process is applied to remove the third gap fill material 3751 in the dummy region 383 and the contact region 385 to form the third gap fill layer 375.

[0087] Next, asFigure 6J As shown, the top bit line contact 321 is formed to contact, for example, another first interconnect layer (also referred to as the M4 layer 364 in Figure 4B ).

[0088] Method 700 proceeds to operation 712, as Figure 7 shown, where a top bit line is formed that connects between the top bit line contact and the plurality of top memory cells. For example, as Figure 6K shown, before forming the top bit line, a fourth gap fill material (not shown) is filled and the fourth gap fill material covers the third gap fill layer 375, the top PCM cell 351, the top dummy cell 355, and the top bit line contact 321.

[0089] Next, another CMP or planarization can be applied to the fourth gap fill material until the top surface of the top PCM cell 351 is exposed. Thereafter, a fourth gap fill layer 377 is formed.

[0090] Next, also as Figure 6K shown, a top bit line layer 3311 is deposited that connects between the top bit line contact 321 and the top PCM cell 351. In some embodiments, the top bit line layer 3311 is only deposited for the length of the memory block. That is, the top bit line layer 3311 may not extend from one memory block to another. The length of the top bit line layer 3311 is less than the length of the memory block. Thus, the risk of peeling or bending problems is minimized.

[0091] Next, as Figure 6L shown, etching or patterning (e.g., double patterning) is applied to remove a portion of the fourth gap fill layer 377 in the dummy region 383 and cut the top bit line layer 3311 (e.g., in Figure 6K ) to form the top bit line 311. That is, a first step of etching is applied to cut the top bit line layer 3311 in the x direction to form a top bit line 331 that extends in the y direction. Then, a second step of etching is applied to remove a portion of the fourth gap fill layer 377 in the dummy region 383. When patterning the top bit line layer 3311 in the memory region 381, the top bit line layer 3311 in the dummy region 383 is also patterned such that the dummy cells are isolated from each other. It should also be noted that in another cross-sectional view, the top bit line 331 may connect between the top bit line contact 321 and the top PCM cell 351.

[0092] The foregoing description of the specific embodiments will thus fully disclose the general nature of the present disclosure, so that others can easily modify and / or adapt such specific embodiments for various applications by applying the knowledge within the scope of the art, without undue experimentation and without departing from the general concept of the present disclosure. Therefore, based on the teachings and guidance presented herein, such adaptations and modifications are intended to be within the meaning and scope of the equivalents of the disclosed embodiments. It should be understood that the phrases or terms herein are for the purpose of description and not for limitation, and thus the terms or phrases of this specification will be interpreted by those skilled in the art in accordance with the said teachings and guidance.

[0093] The embodiments of the present disclosure have been described above by means of functional building blocks, which illustrate the implementations of specified functions and their relationships. The boundaries of these functional building blocks have been arbitrarily defined herein for convenience of description. Alternative boundaries can be defined as long as the specified functions and their relationships are properly performed.

[0094] The Summary and Abstract sections may set forth one or more exemplary embodiments of the present disclosure as contemplated by the inventors, but not necessarily all exemplary embodiments, and thus are not intended to limit the present disclosure and the appended claims in any way.

[0095] The breadth and scope of the present disclosure should not be limited by any of the above exemplary embodiments, and should be defined only in accordance with the following claims and their equivalents.

Claims

1. A storage device, comprising: a plurality of bottom phase change memory (PCM) cells; a plurality of top PCM cells on the plurality of bottom PCM cells; a plurality of bottom dummy cells at least partially surrounding the plurality of bottom PCM cells in a plan view; a plurality of top dummy cells on the plurality of bottom dummy cells; a first gap filling layer between adjacent bottom PCM cells; a second gap filling layer at least partially surrounding the plurality of bottom PCM cells in the plan view; a third gap filling layer between adjacent top PCM cells; and a fourth gap filling layer at least partially surrounding the plurality of top PCM cells in the plan view, wherein the plurality of bottom dummy cells are located between adjacent memory blocks, and the fourth gap filling layer does not extend into the region of the plurality of top dummy cells.

2. The storage device according to claim 1, wherein, The first gap filling layer has a better gap filling ability than the second gap filling layer, and the third gap filling layer has a better gap filling ability than the fourth gap filling layer.

3. The storage device according to claim 1 or 2, wherein, The first gap filling layer has a better heat insulation ability than the second gap filling layer, and the third gap filling layer has a better heat insulation ability than the fourth gap filling layer.

4. The storage device according to claim 1 or 2, wherein The first gap filling layer includes the same material as the third gap filling layer, and the second gap filling layer includes the same material as the fourth gap filling layer.

5. The storage device according to claim 1 or 2, wherein, The thermal conductivity of the first gap filling layer is not greater than 0.6 W / (m·K).

6. The storage device according to claim 1 or 2, wherein The second gap filling layer includes silicon oxide, aluminum oxide, other related oxide materials, or a combination thereof.

7. The storage device according to claim 1 or 2, further comprising: a bottom bit line; a word line; a top bit line; a bottom bit line contact; a word line contact; and a top bit line contact, wherein the bottom bit line is connected between the bottom bit line contact and the bottom PCM cell, the word line is connected between the word line contact and the bottom PCM cell and between the word line contact and the top PCM, and the top bit line is connected between the top bit line contact and the top PCM cell.

8. The storage device according to claim 7, further comprising: a peripheral stack below the plurality of bottom PCM cells, wherein the peripheral stack includes: a bottom bit line selector connected to the bottom bit line contact; a top bit line selector connected to the top bit line contact; and a word line driver connected to the word line contact.

9. A method of manufacturing a storage device, comprising: forming a bottom bit line layer; forming a plurality of bottom PCM cells and a plurality of bottom dummy cells on the bottom bit line layer; filling a plurality of first trenches between adjacent bottom PCM cells and adjacent bottom dummy cells to form a first gap filling layer; removing the first gap filling layer outside the storage area and patterning the bottom bit line layer in the dummy area to form a bottom bit line; forming a word line layer on the plurality of bottom PCM cells and the bottom dummy cells; Form a plurality of top PCM cells and a plurality of top dummy cells on the word line layer; Fill a plurality of second trenches between adjacent top PCM cells and adjacent top dummy cells to form a third gap fill layer; Remove the third gap fill layer outside the storage area and pattern the word line layer in the dummy area to form word lines; Form a top bit line layer on the plurality of top PCM cells and the top dummy cells; And Pattern the top bit line layer on the top dummy cells to form top bit lines, wherein the plurality of bottom dummy cells are located between adjacent memory blocks, and the word line layer, the bottom bit line layer, and the top bit line layer only extend the size of one memory block.

10. The method according to claim 9, further comprising: After removing the first gap fill layer outside the storage area and patterning the bottom bit line layer in the dummy area, form word line contacts.

11. The method according to claim 10, wherein, The word line contacts are connected between the word line layer and the bottom PCM cells.

12. The method according to any one of claims 9-11, further comprising: After removing the first gap fill layer outside the storage area and patterning the bottom bit line layer in the dummy area, perform filling to form a second gap fill layer covering the bottom PCM cells and the bottom dummy cells.

13. The method according to claim 12, further comprising: Before forming the word line layer on the plurality of bottom PCM cells and the bottom dummy cells, apply a first planarization process to the second gap fill layer to expose a first top surface of the bottom PCM cells.

14. The method according to any one of claims 9-11, further comprising: After removing the third gap fill layer outside the storage area and patterning the word line layer in the dummy area, form top bit line contacts.

15. The method according to claim 14, wherein, The top bit line contacts are connected between the top bit line layer and the top PCM cells.

16. The method according to any one of claims 9-11, further comprising: After removing the third gap fill layer outside the storage area and patterning the word line layer in the dummy area, perform filling to form a fourth gap fill layer covering the top PCM cells and the top dummy cells.

17. The method according to claim 16, further comprising: Before forming the top bit line layer on the plurality of top PCM cells and the top dummy cells, apply a second planarization process to the fourth gap fill layer to expose a second top surface of the top PCM cells.

18. The method according to any one of claims 9-11, wherein The length of each of the bottom bit line layer, the word line layer, and the top bit line layer is less than the length of the memory block, and wherein, in a plan view, the bottom dummy cells at least partially surround the bottom PCM cells in the memory block.

19. The method according to any one of claims 9-11, wherein, Patterning the bottom bit line layer in the dummy region to form the bottom bit line and also patterning the bottom bit line layer in the storage region in a first lateral direction such that the bottom bit lines in the storage region extend in a second lateral direction.

20. The method according to any one of claims 9-11, wherein Patterning the word line layer in the dummy region to form the word line and also patterning the word line layer in the storage region in a second lateral direction such that the word lines in the storage region extend in a first lateral direction.

21. The method according to any one of claims 9-11, wherein, Patterning the top bit line layer in the dummy region to form the top bit line and also patterning the top bit line layer in the storage region in a first lateral direction such that the top bit lines in the storage region extend in a second lateral direction.

22. A method of manufacturing a storage device, comprising: Forming a bottom bit line layer; Forming a plurality of bottom PCM cells and a plurality of bottom dummy cells on the bottom bit line layer; Patterning the bottom bit line layer in the dummy region to form the bottom bit line and isolating the plurality of bottom dummy cells from the plurality of bottom PCM cells; Forming a word line layer on the plurality of bottom PCM cells and the bottom dummy cells; Forming a plurality of top PCM cells and a plurality of top dummy cells on the word line layer; Patterning the word line layer in the dummy region to form the word line; Forming a top bit line layer on the plurality of top PCM cells and the top dummy cells; And Patterning the top bit line layer on the top dummy cells to form the top bit line and isolating the plurality of top dummy cells from the plurality of top PCM cells, wherein each of the bottom bit line layer, the word line layer, and the top bit line layer has a length less than the length of a storage block, and wherein, in a plan view, the bottom dummy cells at least partially surround the bottom PCM cells in the storage block.

23. The method according to claim 22, further comprising: Forming word line contacts after patterning the bottom bit line layer in the dummy region.

24. The method according to claim 23, wherein, The word line contacts are connected between the word line layer and the bottom PCM cells.

25. The method according to any one of claims 22-24, further comprising: Forming top bit line contacts after patterning the word line layer in the dummy region.

26. The method according to claim 25, wherein, The top bit line contacts are connected between the top bit line layer and the top PCM cells.

27. The method according to any one of claims 22-24, wherein, Patterning the bottom bit line layer in the dummy region to form the bottom bit line and also patterning the bottom bit line layer in the storage region in a first lateral direction such that the bottom bit lines in the storage region extend in a second lateral direction.

28. The method according to any one of claims 22-24, wherein, Patterning the word line layer in the dummy region to form the word line and also patterning the word line layer in the storage region in a second lateral direction such that the word lines in the storage region extend in a first lateral direction.

29. The method according to any one of claims 22-24, wherein, Pattern the top bit line layer in the dummy region to form the top bit line and also pattern the top bit line layer in the storage region in a first lateral direction such that the top bit lines in the storage region extend in a second lateral direction.

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