Measurement circuit and method for timing parameters of superconducting logic devices

Abstract

The present invention provides a measurement circuit for timing parameters of a superconducting logic device, comprising a first input interface unit, an output interface unit, a splitter unit, at least two first buffer units, at least one second buffer unit, at least one third buffer unit and at least two fourth buffer units; the input end of the splitter unit is connected to the first input interface unit through at least two cascaded first buffer units, the first output end is connected to the data end of the logic device to be measured through at least one second buffer unit, and the second output end is connected to the clock end of the logic device to be measured through at least one third buffer unit; the output end of the logic device to be measured is connected to the output interface unit through at least two cascaded fourth buffer units; wherein the number of the second buffer units and the third buffer units is the same. The measurement circuit provided by the present invention solves the problem that there is no such measurement circuit in the prior art.

Description

Technical Field

[0001] The invention relates to the field of superconducting circuit design, and in particular to a measuring circuit and a measuring method for timing parameters of a superconducting logic device. Background Art

[0002] With the rapid development of social economy and military technology, the amount of data that needs to be processed has increased dramatically, and higher and higher requirements have been placed on the computing power of computers. Superconducting circuits based on Josephson junctions have gradually entered people's field of vision. Superconducting RSFQ (rapid single flux quantum) technology uses whether the superconducting circuit contains single flux quantum pulses in a specific time sequence to represent "1" and "0". The pulses are generally in the order of picoseconds (ps) in width, so superconducting RSFQ devices can operate at extremely high frequencies.

[0003] In order to use RSFQ devices to implement ultra-large-scale digital circuits, it is necessary to ensure that each level of RSFQ devices in the digital circuit can work correctly according to the design requirements under the control of the clock; if the timing relationship of the RSFQ device cannot meet the requirements, the entire digital circuit cannot work properly. In order to ensure that the RSFQ device works stably and reliably, it is necessary to ensure that the timing parameters used in the timing verification in the chip design are valid, and testing the timing parameters of the RSFQ device is the only way to verify whether the timing relationship is reliable and ensure the validity of the timing parameters.

[0004] In view of this, designing a measurement circuit and a measurement method for the timing parameters of superconducting logic devices has become a technical problem that technical personnel in this field urgently need to solve. Summary of the invention

[0005] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a measurement circuit and a measurement method for timing parameters of a superconducting logic device, so as to solve the problem that there is no such measurement circuit in the prior art.

[0006] To achieve the above-mentioned object and other related objects, the present invention provides a measurement circuit for timing parameters of a superconducting logic device, the measurement circuit comprising: a first input interface unit, an output interface unit, a splitter unit, at least two first buffer units, at least one second buffer unit, at least one third buffer unit and at least two fourth buffer units;

[0007] The input end of the splitter unit is connected to the first input interface unit through at least two cascaded first buffer units, the first output end is connected to the data end of the logic device under test through at least one second buffer unit, and the second output end is connected to the clock end of the logic device under test through at least one third buffer unit;

[0008] The output end of the logic device under test is connected to the output interface unit through at least two cascaded fourth buffer units;

[0009] Among them, the number of the second buffer units and the third buffer units is the same; when the number of the second buffer units is greater than or equal to 2, multiple second buffer units are cascaded between the first output end of the splitter unit and the data end of the logic device under test; when the number of the third buffer units is greater than or equal to 2, multiple third buffer units are cascaded between the second output end of the splitter unit and the clock end of the logic device under test.

[0010] Optionally, the measurement circuit further includes: a first delay unit and / or a second delay unit;

[0011] The first delay unit is connected between the second buffer unit and the data terminal of the logic device to be tested, and is used to delay at least one Josephson junction;

[0012] The second delay unit is connected between the third buffer unit and the clock terminal of the logic device to be tested, and is used for delaying at least one Josephson junction.

[0013] Optionally, the first delay unit and the second delay unit each include at least one delay buffer unit, and when the number of the delay buffer units is greater than or equal to 2, a plurality of the delay buffer units are cascaded.

[0014] Optionally, the measurement circuit further comprises: a second input interface unit, a first current collector unit and at least two fifth buffer units;

[0015] The first input end of the first concentrator unit is connected to the second input interface unit through at least two cascaded fifth buffer units, the second input end is connected to the second output end of the splitter unit, and the output end is connected to the input end of the third buffer unit.

[0016] Optionally, the measurement circuit further includes: a grounding unit, a second current collector unit and at least two sixth buffer units;

[0017] The first input end of the second current collector unit is connected to the ground unit through at least two cascaded sixth buffer units, the second input end is connected to the first output end of the splitter unit, and the output end is connected to the input end of the second buffer unit.

[0018] Optionally, the number of the first buffer unit, the fifth buffer unit and the sixth buffer unit is the same.

[0019] Optionally, the grounding unit is implemented by a buffer unit with input grounding.

[0020] The present invention also provides a method for measuring timing parameters of a superconducting logic device, the method comprising:

[0021] Provide a first measurement circuit as described above and (N+M) second measurement circuits as described above, wherein the clock pulses input to the clock terminal of the logic device to be measured in the N second measurement circuits have a delay of one Josephson junction in turn compared to the data pulses at the data terminal, and the data pulses input to the data terminal of the logic device to be measured in the M second measurement circuits have a delay of one Josephson junction in turn compared to the clock pulses at the clock terminal; wherein N and M are both natural numbers greater than or equal to 1;

[0022] The same input pulse is input to each measurement circuit, and the output pulse corresponding to each measurement circuit is obtained, so as to obtain the timing parameters of the logic device to be measured based on each output pulse; wherein the timing parameters include setup time and hold time.

[0023] Optionally, before and / or after the measurement, the measurement method further comprises: a step of clearing the clock pulses input to the clock terminal of the logic device to be measured in each measurement circuit.

[0024] Optionally, N and M are equal.

[0025] As described above, a measurement circuit and method for the timing parameters of a superconducting logic device of the present invention realizes the measurement of the timing relationship between the clock pulse and the data pulse of the superconducting logic device (the measurable step length is the delay of a Josephson junction), and can guide the timing verification of ultra-large-scale digital circuits before tape-out based on the measured data. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 Schematic diagram showing the comparison between the wide level pulse of CMOS circuit and the ultra-narrow pulse of superconducting RSFQ circuit.

[0027] Figure 2 Schematic diagram showing the timing relationship between clock pulses and data pulses for a superconducting RSFQ flip-flop.

[0028] Figure 3 Shown is a schematic diagram of the measurement circuit of the present invention.

[0029] Figure 4 It is a schematic diagram showing the input and output waveforms involved when testing each measurement circuit in the measurement method of the present invention.

[0030] Figure 5 When the Octopus test system is used to test each measurement circuit, Figure 4 Schematic diagram of the output waveform corresponding to Out1 in .

[0031] Figure 6 When the Octopus test system is used to test each measurement circuit, Figure 4 Schematic diagram of the output waveform corresponding to Out2 in .

[0032] Component number description

[0033] 100 Measurement circuit

[0034] 101 First input interface unit

[0035] 102 first buffer unit

[0036] 103 splitter unit

[0037] 104 Second buffer unit

[0038] 105 Third buffer unit

[0039] 106 Fourth buffer unit

[0040] 107 Output interface unit

[0041] 108 First delay unit

[0042] 109 Second delay unit

[0043] 110 Second input interface unit

[0044] 111 Fifth buffer unit

[0045] 112 First combiner unit

[0046] 113 Grounding Unit

[0047] 114 Sixth buffer unit

[0048] 115 Second combiner unit DETAILED DESCRIPTION

[0049] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0050] See also Figures 1 to 6It should be noted that the illustrations provided in this embodiment are only schematic illustrations of the basic concept of the present invention. Although the illustrations only show components related to the present invention and are not drawn according to the number, shape and size of components in actual implementation, the form, quantity and proportion of each component in actual implementation may be changed arbitrarily, and the component layout may also be more complicated.

[0051] like Figure 1 As shown, unlike the ns-level wide level pulses of CMOS circuits, the pulses of superconducting RSFQ circuits are ps-level ultra-narrow pulses, and the transmission of signals inside the circuit has no concept of rising edge and falling edge.

[0052] For superconducting logic devices, such as superconducting RSFQ triggers, timing parameters and operating range are the standards for measuring their electrical performance, and the timing parameters usually use setup time (setup) and hold time (hold) to constrain the timing relationship between clock pulses and data pulses.

[0053] The timing relationship between the clock pulse and data pulse of the superconducting RSFQ trigger is as follows: Figure 2 As shown, the starting point on the left side of the setup time (setup) represents the end point where the data pulse is stably captured by the current clock pulse T, and data pulses arriving earlier than this moment can be stably captured by the current clock pulse T; the end point on the right side of the hold time (hold) represents the starting point where the data pulse is stably captured by the next clock pulse 2T, and data pulses arriving later than this moment can be stably captured by the next clock pulse 2T.

[0054] The window formed by the setup time (setup) and the hold time (hold) is an invalid data input window, that is, the data pulse arriving in this window cannot be stably captured by the current clock pulse T or the next clock pulse 2T. For the current clock pulse T, the window between the starting point on the left side of the first setup time and the end point on the right side of the first hold time constitutes its invalid data input window; and for the next clock pulse 2T, the window between the end point on the right side of the first hold time and the starting point on the left side of the second setup time constitutes its valid data input window. In short, for any clock pulse, in order for the data pulse to be stably captured by it, the data pulse must fall within the valid data input window.

[0055] The measurement circuit and measurement method described in the present invention can measure the valid data input window and invalid data input window of the superconducting logic device, that is, measure the setup time and hold time, and realize the measurement of the timing parameters of the superconducting logic device, that is, the measurement of the timing relationship between the clock pulse and the data pulse of the superconducting logic device.

[0056] Embodiment 1

[0057] like Figure 3 As shown, this embodiment provides a measurement circuit for timing parameters of a superconducting logic device, and the measurement circuit 100 includes: a first input interface unit 101, at least two first buffer units 102, a splitter unit 103, at least one second buffer unit 104, at least one third buffer unit 105, at least two fourth buffer units 106 and an output interface unit 107; the input end of the splitter unit 103 is connected to the first input interface unit 101 through at least two cascaded first buffer units 102, the first output end is connected to the data end AI of the logic device DUT under test through at least one second buffer unit 104, and the second output end is connected to the clock end TI of the logic device DUT under test through at least one third buffer unit 105; the output end TO of the logic device DUT under test is connected to the output interface unit 107 through at least two cascaded fourth buffer units 106;

[0058] Among them, the number of the second buffer units 104 and the third buffer units 105 is the same, so that the data pulses and clock pulses input to the logic device under test DUT arrive at the same time; when the number of the second buffer units 104 is greater than or equal to 2, multiple second buffer units 104 are cascaded between the first output end of the splitter unit 103 and the data end AI of the logic device under test DUT; when the number of the third buffer units 105 is greater than or equal to 2, multiple third buffer units 105 are cascaded between the second output end of the splitter unit 103 and the clock end TI of the logic device under test DUT.

[0059] Specifically, the first input interface unit 101 is a CMOS-RSFQ interactive interface unit, and the output interface unit 107 is a RSFQ-CMOS interactive interface unit.

[0060] Specifically, the first buffer unit 102, the second buffer unit 104, the third buffer unit 105 and the fourth buffer unit 106 are all transmission lines with two Josephson junctions, and the use of the transmission line with two Josephson junctions can achieve stable signal transmission. The number of each buffer unit should be selected in consideration of transmission stability and circuit area, such as the number of the first buffer unit 102 is 2, the number of the second buffer unit 104 is 1, the number of the third buffer unit 105 is 1, and the number of the fourth buffer unit 106 is 2; of course, other number selections are also applicable to this embodiment.

[0061] In the measurement circuit of this example, Data1 is used as the input signal terminal, and the input pulse is input to the splitter unit 103 through the first input interface unit 101 and at least two of the first buffer units 102 and is split into two outputs, wherein one output of the splitter unit 103 is input to the data terminal AI of the logic device under test DUT through at least one of the second buffer units 104, and the other output is input to the clock terminal TI of the logic device under test DUT through at least one of the third buffer units 105. Since the number of the second buffer units 104 and the third buffer units 105 is the same, the two outputs simultaneously reach the data terminal AI and the clock terminal TI of the logic device under test DUT.

[0062] Furthermore, the measurement circuit 100 further includes: a second input interface unit 110, at least two fifth buffer units 111 and a first current sink unit 112; the first input end of the first current sink unit 112 is connected to the second input interface unit 110 through at least two cascaded fifth buffer units 111, the second input end is connected to the second output end of the splitter unit 103, and the output end is connected to the input end of the third buffer unit 105. It should be noted that when the number of the third buffer units 105 is greater than or equal to 2, the output end of the first current sink unit 112 is connected to the input end of the first third buffer unit 105.

[0063] Specifically, the second input interface unit 110 is a CMOS-RSFQ interactive interface unit. The fifth buffer unit 111 is a transmission line with two Josephson junctions, and the use of a transmission line with two Josephson junctions can achieve stable signal transmission.

[0064] In the measurement circuit described in this example, Data2 serves as a reset signal terminal, and Data2 and Data1 do not input signals at the same time; the reset pulse is input to the clock terminal TI of the logic device DUT under test through the second input interface unit 110, at least two of the fifth buffer units 111, the first concentrator unit 112 and the third buffer unit 105, and a clock pulse is provided separately for the clock terminal TI of the logic device DUT under test to reset the initial state of the logic device DUT under test, that is, to reset the initial state of the measurement circuit, to prevent residual pulses or other interference from the previous test in the circuit, thereby improving the test accuracy, and at the same time, realizing automatic reset, and continuous testing can be performed without manual reset.

[0065] Furthermore, the measurement circuit 100 further includes: a grounding unit 113, at least two sixth buffer units 114 and a second current sink unit 115; the first input end of the second current sink unit 115 is connected to the grounding unit 113 through at least two cascaded sixth buffer units 114, the second input end is connected to the first output end of the splitter unit 103, and the output end is connected to the input end of the second buffer unit 104. It should be noted that when the number of the second buffer units 104 is greater than or equal to 2, the output end of the second current sink unit 115 is connected to the input end of the first second buffer unit 104.

[0066] Specifically, the grounding unit 113 is implemented by a buffer unit with a grounded input so that it has no effective input; wherein the buffer unit with a grounded input is a transmission line with two Josephson junctions. The sixth buffer unit 114 is a transmission line with two Josephson junctions, and the use of a transmission line with two Josephson junctions can achieve stable signal transmission.

[0067] Specifically, the number of the first buffer unit 102 , the fifth buffer unit 111 and the sixth buffer unit 114 is the same, so as to form a completely symmetrical structure with the design of the clearing part.

[0068] In the measurement circuit of this example, the circuit connected to the data terminal AI and the clock terminal TI of the logic device under test DUT is designed as symmetrical as possible on the layout, thereby reducing the timing difference introduced by asymmetry. And by making the number of the first buffer unit 102, the fifth buffer unit 111 and the sixth buffer unit 114 the same, the circuit connected to the data terminal AI and the clock terminal TI of the logic device under test DUT is completely symmetrical on the layout, thereby preventing the timing difference introduced by asymmetry.

[0069] For the measurement circuit described in this embodiment, the concentrator unit and the splitter unit are the most stable circuit units in the current superconducting integrated circuits. By utilizing these most stable circuit units to measure the timing parameters of the logic device to be measured, the stability and reliability of the measurement circuit can be effectively improved. At the same time, the area and layout of the measurement circuit can be minimized, thereby facilitating the improvement of integration.

[0070] Embodiment 2

[0071] like Figure 3As shown, this embodiment provides a measurement circuit for timing parameters of a superconducting logic device. The difference from the first embodiment is that the measurement circuit 100 described in this embodiment also includes: a first delay unit 108 and / or a second delay unit 109; the first delay unit 108 is connected between the second buffer unit 104 and the data terminal AI of the logic device DUT to be tested, and is used to delay at least one Josephson junction; the second delay unit 109 is connected between the third buffer unit 105 and the clock terminal TI of the logic device DUT to be tested, and is used to delay at least one Josephson junction.

[0072] Specifically, the first delay unit 108 and the second delay unit 109 each include at least one delay buffer unit, and when the number of the delay buffer units is greater than or equal to 2, a plurality of the delay buffer units are cascaded. More specifically, the delay buffer unit is a transmission line having a Josephson junction to achieve a delay with a measurable step length of one Josephson junction. It should be noted that the number of the delay buffer units can be set according to the delay requirement, and this embodiment does not limit this.

[0073] In practical applications, if the clock pulse input to the logic device DUT to be tested is delayed by one Josephson junction compared to the data pulse, then the second delay unit 109 consisting of a delay buffer unit can be set only between the third buffer unit 105 and the clock terminal TI of the logic device DUT to be tested, and the first delay unit 108 is not set between the second buffer unit 104 and the data terminal AI of the logic device DUT to be tested; the first delay unit 108 and the second delay unit 109 can also be set at the same time, except that the number of delay buffer units in the second delay unit 109 is one more than the number of delay buffer units in the first delay unit 108.

[0074] If the data pulse input to the logic device DUT under test is delayed by one Josephson junction compared to the clock pulse, then the first delay unit 108 consisting of one delay buffer unit may be set only between the second buffer unit 104 and the data terminal AI of the logic device DUT under test, and the second delay unit 109 may not be set between the third buffer unit 105 and the clock terminal TI of the logic device DUT under test; the first delay unit 108 and the second delay unit 109 may also be set at the same time, except that the number of delay buffer units in the first delay unit 108 is one more than the number of delay buffer units in the second delay unit 109.

[0075] Based on the above configuration, by increasing the number of delay buffer units, the delay between the clock pulse and the data pulse can be made greater than one Josephson junction, which will not be listed one by one in this embodiment.

[0076] Embodiment 3

[0077] This embodiment provides a method for measuring timing parameters of a superconducting logic device, and the method comprises step a) and step b).

[0078] Step a) Provide a first measurement circuit as described in Example 1 and (N+M) second measurement circuits as described in Example 2, wherein the clock pulses input to the clock terminal of the logic device to be tested in the N second measurement circuits have a delay of one Josephson junction in turn compared to the data pulses at the data terminal, and the data pulses input to the data terminal of the logic device to be tested in the M second measurement circuits have a delay of one Josephson junction in turn compared to the clock pulses at the clock terminal; wherein N and M are both natural numbers greater than or equal to 1. It should be noted that in the N second measurement circuits, the data pulses input to the data terminal of the logic device to be tested are not delayed; and in the M second measurement circuits, the clock pulses input to the clock terminal of the logic device to be tested are not delayed.

[0079] Specifically, in the N second measurement circuits, the first delay unit 108 is not provided, only the second delay unit 109 is provided, and the second delay unit 109 in the N second measurement circuits has a delay buffer unit with an increasing number. In the M second measurement circuits, the second delay unit 109 is not provided, only the first delay unit 108 is provided, and the first delay unit 108 in the M second measurement circuits has a delay buffer unit with an increasing number. More specifically, N is equal to M. In practical applications, the values ​​of N and M should ensure that the invalid data input window is completely covered.

[0080] If N=M=3, the first measuring circuit is set to be circuit 1, the N second measuring circuits are circuit 2, circuit 3, and circuit 4 in order based on the delay time, and the M second measuring circuits are circuit 5, circuit 6, and circuit 7 in order based on the delay time; wherein the data pulse and clock pulse of the logic device to be measured in circuit 1 arrive synchronously, and no delay is made; the data pulses of the logic devices to be measured in circuits 2, 3, and 4 are not delayed, the clock pulse of the logic device to be measured in circuit 2 is delayed by one Josephson junction compared with the data pulse, and the clock pulse of the logic device to be measured in circuit 3 is delayed by one Josephson junction. The clock pulse of the logic device to be tested in circuit 4 is delayed by three Josephson junctions compared with the data pulse, and the clock pulse of the logic device to be tested in circuit 4 is delayed by three Josephson junctions compared with the data pulse; the clock pulses of the logic devices to be tested in circuits 5, 6 and 7 are not delayed, the data pulse of the logic device to be tested in circuit 5 is delayed by one Josephson junction compared with the clock pulse, the data pulse of the logic device to be tested in circuit 6 is delayed by two Josephson junctions compared with the clock pulse, and the data pulse of the logic device to be tested in circuit 7 is delayed by three Josephson junctions compared with the clock pulse.

[0081] Step b) inputting the same input pulse to each measurement circuit and obtaining the output pulse corresponding to each measurement circuit, so as to obtain the timing parameters of the logic device to be measured based on each output pulse; wherein the timing parameters include setup time and hold time.

[0082] like Figure 4 As shown in the figure, when testing each measurement circuit, some circuits can stably output Out1, and some circuits can stably output Out2; specifically, when the data pulse and clock pulse reaching the logic device to be tested meet the timing relationship within the same cycle, the output pulse is as follows: Figure 4 The waveform of Out1 in Figure 1. When the data pulse and clock pulse reaching the logic device under test do not meet the timing relationship within the same cycle, the output pulse cannot be locked by the clock pulse of the same cycle, and the output will be as follows when the next clock pulse arrives. Figure 4 The waveform of Out2 in .

[0083] Based on the test results, find the circuit with the least number of Josephson junctions between the data end and the clock end of the logic device under test and the stable output Out1, and the circuit with the least number of Josephson junctions between the data end and the clock end and the stable output Out2, so as to obtain the valid data input window and the invalid data input window, that is, the setup time and the hold time.

[0084] Specifically, when measuring the timing parameters of the logic device to be tested through various measurement circuits, each measurement circuit can measure the same logic device to be tested, or each measurement circuit can measure (N+M+1) logic devices to be tested produced in the same batch separately, which has almost no effect on the measurement results.

[0085] Specifically, a low-frequency low-temperature superconducting test system is used to test each measuring circuit; wherein the low-frequency low-temperature superconducting test system is an Octopus test system.

[0086] The Octopus test system is a commonly used low-frequency, low-temperature superconducting test system. Its input is rising edge triggered, that is, as long as there is a rising edge at the input, a superconducting signal can be captured, and the output is edge triggered, that is, each flip of the output represents a superconducting signal, and the rising edge and the falling edge are equally effective. Therefore, in the Octopus test system, Figure 4 The outputs Out1 and Out2 become edge-triggered waveforms; Out1 corresponds to Figure 5 The output waveform in the figure means that the data pulse and the clock pulse satisfy the timing relationship of the same cycle. When the input is valid, there is output synchronously at the output end. Out2 corresponds to Figure 6 The output waveform in the figure means that the data pulse and the clock pulse do not satisfy the timing relationship of the same cycle. When the input is valid, there is output at the output end with a clock offset.

[0087] Furthermore, the measuring method further comprises: step c) clearing the clock pulses input to the clock terminal of the logic device to be measured in each measuring circuit. It should be noted that step c) can be performed before step b), can also be performed after step b), and can also be performed both before step b) and after step b).

[0088] In summary, the measurement circuit and method of timing parameters of a superconducting logic device of the present invention realizes the measurement of the timing relationship between the clock pulse and the data pulse of the superconducting logic device (the measurable step length is the delay of a Josephson junction), and can guide the timing verification of ultra-large-scale digital circuits before tape-out based on the measured data. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has a high industrial utilization value.

[0089] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A circuit for measuring timing parameters of a superconducting logic device, characterized in that: The measuring circuit comprises: a first input interface unit, an output interface unit, a splitter unit, at least two first buffer units, at least one second buffer unit, at least one third buffer unit and at least two fourth buffer units; The input end of the splitter unit is connected to the first input interface unit through at least two cascaded first buffer units, the first output end is connected to the data end of the logic device under test through at least one second buffer unit, and the second output end is connected to the clock end of the logic device under test through at least one third buffer unit; The output end of the logic device under test is connected to the output interface unit through at least two cascaded fourth buffer units; Among them, the number of the second buffer units and the third buffer units is the same; when the number of the second buffer units is greater than or equal to 2, multiple second buffer units are cascaded between the first output end of the splitter unit and the data end of the logic device under test; when the number of the third buffer units is greater than or equal to 2, multiple third buffer units are cascaded between the second output end of the splitter unit and the clock end of the logic device under test.

2. The circuit for measuring timing parameters of a superconducting logic device according to claim 1, characterized in that: The measuring circuit further comprises: a first delay unit and / or a second delay unit; The first delay unit is connected between the second buffer unit and the data terminal of the logic device to be tested, and is used to delay at least one Josephson junction; The second delay unit is connected between the third buffer unit and the clock terminal of the logic device to be tested, and is used for delaying at least one Josephson junction.

3. The circuit for measuring timing parameters of a superconducting logic device according to claim 2, characterized in that: The first delay unit and the second delay unit each include at least one delay buffer unit. When the number of the delay buffer units is greater than or equal to 2, a plurality of the delay buffer units are cascaded.

4. The circuit for measuring timing parameters of a superconducting logic device according to any one of claims 1 to 3, characterized in that: The measuring circuit further comprises: a second input interface unit, a first current concentrator unit and at least two fifth buffer units; The first input end of the first concentrator unit is connected to the second input interface unit through at least two cascaded fifth buffer units, the second input end is connected to the second output end of the splitter unit, and the output end is connected to the input end of the third buffer unit.

5. The circuit for measuring timing parameters of a superconducting logic device according to claim 4, characterized in that: The measuring circuit further comprises: a grounding unit, a second current collector unit and at least two sixth buffer units; The first input end of the second current collector unit is connected to the ground unit through at least two cascaded sixth buffer units, the second input end is connected to the first output end of the splitter unit, and the output end is connected to the input end of the second buffer unit.

6. The circuit for measuring timing parameters of a superconducting logic device according to claim 5, characterized in that: The number of the first buffer unit, the fifth buffer unit and the sixth buffer unit is the same.

7. The circuit for measuring timing parameters of a superconducting logic device according to claim 5, characterized in that: The grounding unit is implemented by a buffer unit with a grounded input.

8. A method for measuring timing parameters of a superconducting logic device, characterized in that: The measuring method comprises: Provide a measurement circuit as claimed in any one of claims 1 and 4 to 7 and record it as a first measurement circuit, and provide (N+M) measurement circuits as claimed in any one of claims 2 to 7 and record them as second measurement circuits, the clock pulses input to the clock terminal of the logic device to be measured in the N second measurement circuits have a delay of one Josephson junction in sequence compared to the data pulses at the data terminal, and the data pulses input to the data terminal of the logic device to be measured in the M second measurement circuits have a delay of one Josephson junction in sequence compared to the clock pulses at the clock terminal; wherein N and M are both natural numbers greater than or equal to 1; The same input pulse is input to each measurement circuit, and the output pulse corresponding to each measurement circuit is obtained, so as to obtain the timing parameters of the logic device to be measured based on each output pulse; wherein the timing parameters include setup time and hold time.

9. The method for measuring timing parameters of a superconducting logic device according to claim 8, characterized in that: Before and / or after the measurement, the measurement method further comprises: a step of clearing the clock pulses input to the clock terminal of the logic device to be measured in each measurement circuit.

10. The method for measuring timing parameters of a superconducting logic device according to claim 8, characterized in that: N is equal to M.

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