In-memory arithmetic unit and in-memory arithmetic method

Abstract

The present disclosure provides an in-memory operator and an operation method thereof. The in-memory operator includes a memory cell array, an input buffer, and a sense amplifier. The memory cell array includes a memory cell block. The memory cell block corresponds to at least one word line, and the memory cell block is used to store multiple weight values. The multiple memory cells on the memory cell block store multiple bits corresponding to each weight value. The input buffer is coupled to multiple bit lines. The input buffer transmits multiple input signals to the bit lines respectively. The memory cell array multiplies the input signal with the weight value to generate multiple first operation results corresponding to multiple bit sequences respectively. The sense amplifier adds the first operation results according to the bit sequence corresponding to the first operation results to generate a second operation result.

Description

Technical Field

[0001] The present disclosure relates to an in-memory operator, and more particularly to an in-memory operator capable of storing unit weight values ​​and an in-memory operation method. Background Art

[0002] With the advancement of science and technology, artificial intelligence has become a mainstream technology. In order to enable the multiplication and addition operations of neural networks to be effectively executed, providing hardware circuits that are simple and can quickly perform multiplication and addition operations has become an important issue for circuit designers.

[0003] In response to this trend, the so-called in-memory AMU was proposed. These AMUs utilize memory to store weights and perform multiplication and addition operations on the received input signals. Due to the high density of storage cells within the memory, a large number of multiplication and addition operations can be performed with a relatively small circuit area.

[0004] Public content

[0005] The present disclosure provides an in-memory arithmetic unit and an arithmetic method thereof, which can complete a multiplication and addition operation by opening a portion of word lines.

[0006] The memory operator disclosed in the present invention includes a memory cell array, an input buffer, and a sense amplifier. The memory cell array includes a memory cell block. The memory cell block corresponds to at least one word line, and the memory cell block is used to store multiple weight values. The multiple memory cells on the memory cell block store multiple bits corresponding to each weight value. The input buffer is coupled to multiple bit lines. The input buffer transmits multiple input signals to the bit lines respectively. The memory cell array multiplies the input signal with the weight value to generate multiple first operation results corresponding to multiple bit sequences respectively. The sense amplifier adds the first operation results according to the bit sequence corresponding to the first operation results to generate a second operation result.

[0007] The in-memory operation method disclosed in the present invention includes: providing a memory cell block corresponding to at least one word line in a memory cell array, so that the memory cell block stores multiple weight values, wherein multiple memory cells on the memory cell block store multiple bits corresponding to each weight value; providing an input buffer to transmit multiple input signals to these bit lines respectively; multiplying the input signals and the weight values ​​in the memory cell array to generate multiple first operation results corresponding to multiple bit sequences respectively; and adding the first operation results according to the bit sequence corresponding to the first operation results to generate a second operation result.

[0008] Based on the above, the disclosed in-memory arithmetic unit includes a memory cell block to store multiple weight values. An input buffer transmits multiple input signals to corresponding bit lines to perform a multiplication operation on the input signals and the weight values. A sense amplifier senses the results of the multiplication operation and adds the results according to their corresponding bit order to obtain a multiplication-addition result. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 FIG. 1 is a schematic diagram of an in-memory arithmetic unit according to an embodiment of the present disclosure.

[0010] Figure 2 FIG. 1 is a schematic diagram of an in-memory arithmetic unit according to another embodiment of the present disclosure.

[0011] Figure 3 To correspond to this disclosure Figure 2 Schematic diagram of an implementation of an in-memory arithmetic unit according to an embodiment.

[0012] Figure 4 FIG. 1 is a schematic diagram of an in-memory arithmetic unit according to another embodiment of the present disclosure.

[0013] Figure 5 To correspond to this disclosure Figure 4 Schematic diagram of an implementation of an in-memory arithmetic unit according to an embodiment.

[0014] Figure 6 FIG. 1 is a schematic diagram of an in-memory arithmetic unit according to another embodiment of the present disclosure.

[0015] Figure 7 To correspond to this disclosure Figure 6 A schematic diagram of an implementation of an in-memory arithmetic unit according to an embodiment.

[0016] Figure 8 FIG. 1 is a schematic diagram of an in-memory arithmetic unit according to another embodiment of the present disclosure.

[0017] Figure 9 To correspond to this disclosure Figure 8 A schematic diagram of an implementation of an in-memory arithmetic unit according to an embodiment.

[0018] Figure 10 FIG. 1 is a schematic diagram of an in-memory arithmetic unit according to another embodiment of the present disclosure.

[0019] Figure 11 To correspond to this disclosure Figure 10 Schematic diagram of an implementation of an in-memory arithmetic unit according to an embodiment.

[0020] Figure 12 Flowchart of the in-memory operation method according to an embodiment of the present disclosure.

[0021] Description of Reference Numerals

[0022] 100, 200, 300, 400, 500, 600, 700, 800, 900, 1000, 1100: In-memory arithmetic unit

[0023] 110, 210, 310, 410, 510, 610, 710, 810, 910, 1010, 1110: memory cell arrays

[0024] 120, 220, 320, 420, 520, 620, 720, 820, 920, 1020, 1120: Sense amplifiers

[0025] 130, 230, 330, 530, 730, 930, 1130: Input buffer

[0026] 140, 240, 340, 440, 540, 640, 740, 840, 940, 1040, 1140: word line drivers

[0027] A: Input signal group

[0028] A1~An:input signal

[0029] CA1~CAm: storage unit block

[0030] W: weight value group

[0031] W1j~Wnj:weight values

[0032] A1(0)~An(2), A1(p-1)~An(p-1), W1j(0)~Wnj(3), Ai(1), Ai(2): bit

[0033] t1~tp-1: time point

[0034] SA1~SA6, CSA1~CSA6: Sensing circuit

[0035] 321, 322, 521, 721, 921, 1121: Multipliers

[0036] 323, 522, 722, 922, 1122: Adders

[0037] 324: Buffer

[0038] F1, F2: Field DETAILED DESCRIPTION

[0039] Please refer to Figure 1 , Figure 1This figure is a schematic diagram of an in-memory arithmetic unit according to one embodiment of the present disclosure. The in-memory arithmetic unit 100 includes a memory cell array 110, an input buffer 130, a sense amplifier 120, and a wordline driver 140. The memory cell array 110 includes a plurality of memory cell blocks CA1-CAm. Each of the memory cell blocks CA1-CAm corresponds to one or more wordlines. The wordline driver 140 is coupled to the wordlines to provide wordline signals to the corresponding wordlines.

[0040] In this embodiment, the memory cell block CAj stores a weight value set W, which includes a plurality of weight values ​​W1j-Wnj. Each weight value W1j-Wnj may have multiple bits and is stored in each memory cell in the memory cell block CAj. The memory cell array 110 of this embodiment may be a NAND flash memory cell array, wherein each memory cell is a single-level cell (SLC).

[0041] Input buffer 130 is coupled to a plurality of bit lines of memory cell array 110. Input buffer 130 stores input signal group A, which includes a plurality of input signals A1-An. When arithmetic unit 100 in the memory performs a computation, input buffer 130 transmits input signals A1-An to the bit lines of memory cell array 110. Multiple bits of input signals A1-An are multiplied by a plurality of weight values ​​W1j-Wnj in memory cell block CAj to generate a plurality of first computation results corresponding to the plurality of bit lines.

[0042] Please note that, taking the multiplication operation of p bits of the input signal A1 and q bits of the weight value W1j (p and q are both positive integers) as an example, the memory cell array 110 can generate p×q first operation results (each first operation result is one bit). And the above-mentioned first operation results have a bit order according to the level of their bits. For example, the first operation result generated by multiplying the most significant bit of the input signal A1 and the most significant bit of the weight value W1j can have the highest bit order; the first operation result generated by multiplying the least significant bit of the input signal A1 and the least significant bit of the weight value W1j can have the lowest bit order, and the rest can be inferred by analogy.

[0043] The sense amplifier 120 is coupled to the memory cell array 110. When the arithmetic unit 100 performs an operation in the memory, the sense amplifier 120 receives a first operation result generated by the memory cell array 110 and adds the first operation result to generate a second operation result according to the bit sequence corresponding to the first operation result.

[0044] In terms of operation details, when the arithmetic unit 100 in the memory performs a multiplication-addition operation, the word line driver 140 can activate one or more word lines corresponding to the memory cell block CAj. The input buffer 130 can provide multiple bits of the input signal (for example, the input signal A1) to the bit line. In this way, the multiple bits of the weight values ​​W1j~Wnj stored in the memory cell block CAj can be multiplied with the multiple bits of the input signal A1 to generate multiple first operation results. At the same time, the sense amplifier 120 can receive and sense the first operation result generated by the memory cell array 110. The sense amplifier 120 adds the first operation results according to the bit order corresponding to the first operation results to generate a second operation result.

[0045] Please refer to the following Figure 2 , Figure 2 This is a schematic diagram of an in-memory arithmetic unit according to another embodiment of the present disclosure. The in-memory arithmetic unit 200 includes a memory cell array 210, an input buffer 230, a sense amplifier 220, and a wordline driver 240. The memory cell array 210 includes a plurality of memory cell blocks CAj-CAm. Taking the memory cell block CAj as an example, the memory cell block CAj stores weight values ​​W1j-Wnj, where each weight value W1j-Wnj may have q bits, where q is a positive integer.

[0046] The input buffer 230 stores input signals A1 to An. Each of the input signals A1 to An has p bits, where p is a positive integer. During the operation process, the input buffer 230 can transmit multiple bits of the input signals A1 to An to multiple corresponding bit lines in a time-sharing manner. Specifically, the input buffer 230 can transmit the least significant bit A1(0) to An(0) of the input signals A1 to An to the corresponding bit line at time point t0; transmit the second bit A1(1) to An(1) of the input signals A1 to An to the corresponding bit line at time point t1; ...; transmit the most significant bit A1(p-1) to An(p-1) of the input signals A1 to An to the corresponding bit line at time point tp-1.

[0047] In this embodiment, since weight value W1j has q bits, the memory cells of q corresponding bit lines in memory cell block CAj are each used to store q bits of data corresponding to weight value W1j. Here, the number of corresponding bit lines corresponding to weight value W1j is equal to the number of bits of weight value W1j. Furthermore, the multiple bits A1(0)-A1(p-1) of input signal A1 can be transmitted to the aforementioned q corresponding bit lines in a time-sharing manner.

[0048] As can be seen from the above description, the memory cell array 210 can receive multiple bits A1(0)-A1(p-1), ..., An(0)-An(p-1) of the input signals A1-An in a time-sharing manner and perform multiplication operations on the input signals A1-An with the weight values ​​W1j-Wnj to generate multiple first operation results. The sense amplifier 220 can then perform an addition operation based on the bit order of the first operation results to generate a second operation result.

[0049] Please refer to the following Figure 3 , Figure 3 To correspond to this disclosure Figure 2 Schematic diagram of an implementation of an in-memory arithmetic unit of an embodiment. The in-memory arithmetic unit 300 includes a memory cell array 310, a sense amplifier 320, an input buffer 330, and a word line driver 340. Figure 3 In the example, the input signals A1 to An each have three bits A1(0) to An(2) and are stored in the input buffer 330. The first bit A1(0) to An(0) of the input signals A1 to An corresponds to the time point t0; the second bit A1(1) to An(1) of the input signals A1 to An corresponds to the time point t1; and the third bit A1(2) to An(2) of the input signals A1 to An corresponds to the time point t2. In addition, in the memory cell block CAj, each weight value of the weight values ​​W1j to Wnj has four bits W1j(0) to W1j(3), ..., Wnj(0) to Wnj(3). Therefore, in the memory cell array 310, each weight value of the weight values ​​W1j to Wnj corresponds to four corresponding bit lines. Moreover, each bit A1(0) to An(2) of the input signals A1 to An in the input buffer 330 can also be copied into four copies to be transmitted to the corresponding four corresponding bit lines respectively.

[0050] In this embodiment, the sense amplifier 320 includes a plurality of sense circuits SA1-SA4 and CSA1-CSA4, a plurality of first multipliers 321, a second multiplier 322, an adder 323, and a buffer 324. In this embodiment, the sense circuit SA1 is coupled to the bit lines corresponding to the fourth bits W1j(3)-Wnj(3) of the weight values ​​W1j-Wnj; the sense circuit SA2 is coupled to the bit lines corresponding to the third bits W1j(2)-Wnj(2) of the weight values ​​W1j-Wnj; the sense circuit SA3 is coupled to the bit lines corresponding to the second bits W1j(1)-Wnj(1) of the weight values ​​W1j-Wnj; and the sense circuit SA4 is coupled to the bit lines corresponding to the first bits W1j(0)-Wnj(0) of the weight values ​​W1j-Wnj. The sense circuits SA1-SA4 can be used to sense the current value or current discharge rate of the corresponding bit lines. Furthermore, sensing circuits CSA1-CSA4 are coupled to sensing circuits SA1-SA4, respectively. Taking sensing circuit CSA1 as an example, sensing circuit CSA1 is configured to accumulate the current values ​​or current discharge rates of corresponding bit lines sensed by multiple sensing circuits SA1 to sense the first computation result generated by memory cell block CAj. Sensing circuits CSA1-CSA4 may be analog current sensing circuits.

[0051] In this embodiment, multiple sensing circuits SA1 are coupled to corresponding bit lines of the same fourth bit sequence; multiple sensing circuits SA2 are coupled to corresponding bit lines of the same third bit sequence; multiple sensing circuits SA3 are coupled to corresponding bit lines of the same second bit sequence; and multiple sensing circuits SA4 are coupled to corresponding bit lines of the same first bit sequence.

[0052] The first multiplier 321 is coupled to the sensing circuits CSA1 to CSA4 respectively, and multiplies the output of the sensing circuit CSA1 by 2 to the power of 3; multiplies the output of the sensing circuit CSA2 by 2 to the power of 2; and multiplies the output of the sensing circuit CSA3 by 2 to the power of 1. The first multiplier 321 is used to generate a plurality of first signals. The second multiplier 322 is coupled to the first multiplier. The second multiplier 322 multiplies the above-mentioned first signal by 2 to the power of y to generate a plurality of second signals, where y is determined according to the time sequence of transmission of each bit A1(0) to An(2) of each input signal A1 to An, and y is an integer greater than or equal to 0. In detail, at time point t0, y=0; at time point t1, y=1; at time point t2, y=2. The second multiplier 322 is used to generate a plurality of second signals.

[0053] The adder 323 is coupled to the second multiplier 322 and is used to add the plurality of second signals to generate a second operation result. Here, the second operation result is also the multiplication and addition operation result of the operator 300 in the memory.

[0054] Incidentally, the buffer 324 may be coupled to the adder 323 and may serve as a medium for temporarily storing the second operation result.

[0055] Please refer to the following Figure 4 , Figure 4 This is a schematic diagram of an in-memory arithmetic unit according to another embodiment of the present disclosure. The in-memory arithmetic unit 400 includes a memory cell array 410, a sense amplifier 420, and a wordline driver 440. The memory cell array 410 includes a plurality of memory cell blocks CAj-CAm. Taking the memory cell block CAj as an example, the memory cell block CAj stores weight values ​​W1j-Wnj, where each weight value W1j-Wnj may have multiple bits.

[0056] In this embodiment, input signals A1-An are provided by an input buffer (not shown), and each of the input signals A1-An may have multiple bits. The input buffer enables the multiple bits of each input signal A1-An to be transmitted in parallel to multiple corresponding bit lines. Taking the example that each input signal A1-An has three bits, the input buffer of this embodiment enables the input signals A1(0), A1(1), and A1(2) to be simultaneously transmitted to multiple corresponding bit lines corresponding to the weight value W1j, and simultaneously enables the input signals An(0), An(1), and An(2) to be simultaneously transmitted to multiple corresponding bit lines corresponding to the weight value Wnj.

[0057] Compared to Figure 2 In this embodiment, instead of using a time-sharing method to transmit multiple bits of the input signal to corresponding bit lines, the multiple bits of the input signal are transmitted in parallel to multiple corresponding bit lines, effectively saving computation time. In this embodiment, the multiple bits of weight values ​​W1j-Wnj can be replicated into multiple replicated weight values, and the multiple replicated weight values ​​are written to the memory cell block CAj. In this embodiment, the weight values ​​W1j-Wnj can each be replicated into three replicated weight values.

[0058] Please refer to the following Figure 5 , Figure 5 To correspond to this disclosure Figure 4 Schematic diagram of an embodiment of an in-memory arithmetic unit. In-memory arithmetic unit 500 includes a memory cell array 510, a sense amplifier 520, an input buffer 530, and a word line driver 540. In this embodiment, input buffer 530 allows multiple bits A1(2)-A1(0), A2(2) of input signals A1 and A2 to be transmitted in parallel to multiple corresponding bit lines.

[0059] The memory cell block CAj in the memory cell array 510 is used to store a plurality of bits W1j(0)-W1j(3), ..., W2j(0)-W2j(3) of the weight values ​​W1j-W2j. In this embodiment, taking the input signal A1 as an example, the weight value W1j can be copied into three copies (corresponding to the input signal A1 having three bits) corresponding to the plurality of bits A1(2)-A1(0) of the input signal A1 and stored in the memory cell block CAj.

[0060] In this embodiment, all bits A1 ( 2 ) to A1 ( 0 ), A2 ( 2 ) of the input signals A1 to A2 can be input to the memory cell block CAj at once to perform a multiplication operation.

[0061] In addition, the sense amplifier 520 includes a plurality of sense circuits SA1-SA6, CSA1-CSA6, a multiplier 521, and an adder 522. The sense circuits SA1-SA6 are respectively coupled to corresponding bit lines of different bit orders and are used to sense the current values ​​or current discharge rates of the corresponding bit lines. The sense circuits CSA1-CSA6 are respectively coupled to the sense circuits SA1-SA6. Taking the sense circuit CSA1 as an example, the sense circuit CSA1 is used to accumulate the current values ​​or current discharge rates of the corresponding bit lines sensed by the plurality of sense circuits SA1 to sense the first operation result generated by the memory cell block CAj. The sense circuits CSA1-CSA6 can be analog current sensing circuits.

[0062] Multiplier 521 is coupled to the output terminals of sensing circuits CSA1 through CSA5, respectively. It multiplies the output of sensing circuit CSA1 by 2 to the power of 5; the output of sensing circuit CSA2 by 2 to the power of 4; the output of sensing circuit CSA3 by 2 to the power of 3; the output of sensing circuit CSA4 by 2 to the power of 2; and the output of sensing circuit CSA5 by 2 to the power of 1. Multiplier 521 is configured to generate a plurality of first signals.

[0063] The adder 522 is coupled to the first multiplier 521. The adder 522 adds the first signals generated by the first multiplier 521 to generate a second operation result.

[0064] Please refer to the following Figure 6 , Figure 6 FIG. 6 is a schematic diagram of an in-memory arithmetic unit according to another embodiment of the present disclosure. The in-memory arithmetic unit 600 includes a memory cell array 610, a sense amplifier 620, and a word line driver 640. The memory cell array 610 includes a plurality of memory cell blocks CAj-CAm. Figure 4The embodiments are different. In this embodiment, the weight values ​​W1j~Wnj stored in the storage unit block CAj are arranged according to the bit sequence of each bit of the weight values ​​W1j~Wnj. In detail, taking the weight value W1j as an example, the copied identical weight value W1j has multiple weight value W1j bits W1j(0)~W1j(3). Multiple weight value W1j bits W1j(0) are stored in multiple adjacent first corresponding bit lines; multiple weight value W1j bits W1j(1) are stored in multiple adjacent second corresponding bit lines; multiple weight value W1j bits W1j(2) are stored in multiple adjacent third corresponding bit lines; and multiple weight value W1j bits W1j(3) are stored in multiple adjacent fourth corresponding bit lines.

[0065] For implementation details, please refer to Figure 7 For the corresponding disclosure Figure 6 A schematic diagram of an implementation of an in-memory arithmetic unit of an embodiment. The in-memory arithmetic unit 700 includes a memory cell array 710, a sense amplifier 720, an input buffer 730, and a word line driver 740. The memory cell array 710 includes a memory cell block CAj. In the memory cell block CAj, the memory cells of adjacent corresponding bit lines are used to store multiple bits of weight value W1j of the same bit order. In this embodiment, the memory cells on the plurality of bit lines BL3 all store bit W1j(3) of weight value W1j; the memory cells on the plurality of bit lines BL2 all store bit W1j(2) of weight value W1j; the memory cells on the plurality of bit lines BL1 all store bit W1j(1) of weight value W1j; and the memory cells on the plurality of bit lines BL0 all store bit W1j(0) of weight value W1j.

[0066] The input buffer 730 provides input signals A1-A2 to the memory cell block CAj. In detail, taking the input signal A1 as an example, the input buffer 730 can store multiple copies of the input signal A1, and according to the bit order of each copy of the input signal A1, provide multiple bits A1(3)-A1(0) of the input signal A1 to the corresponding bit line BL3; provide multiple bits A1(3)-A1(0) of the input signal A1 to the corresponding bit line BL2; provide multiple bits A1(3)-A1(0) of the input signal A1 to the corresponding bit line BL1; and provide multiple bits A1(3)-A1(0) of the input signal A1 to the corresponding bit line BL0.

[0067] Sense amplifier 720 includes sensing circuits SA1-SA6, CSA1-CSA6, a multiplier 721, and an adder 722. Sensing circuits SA1-SA6 are used to sense the current value or current discharge rate of corresponding bit lines. In this embodiment, the output terminals of sensing circuits SA1-SA6 are respectively coupled to sensing circuits CSA1-CSA6. Sensing circuits CSA1-CSA6 are used to accumulate the current values ​​or current discharge rates of corresponding bit lines sensed by multiple sensing circuits SA1-SA6 to sense the first calculation result generated by memory cell block CAj. Sensing circuits CSA1-CSA6 may be analog current sensing circuits.

[0068] Multiplier 721 is coupled to the output terminals of sensing circuits CSA1-CSA5 and multiplies the output of sensing circuit CSA1 by 2 to the power of 5; the output of sensing circuit CSA2 by 2 to the power of 4; the output of sensing circuit CSA3 by 2 to the power of 3; the output of sensing circuit CSA4 by 2 to the power of 2; and the output of sensing circuit CSA5 by 2 to the power of 1. Multiplier 721 generates a plurality of first signals. Adder 722 is coupled to multiplier 721 and adds the plurality of first signals to generate a second operation result. Here, the second operation result is the multiplication-addition operation result of arithmetic unit 700 in the memory.

[0069] Please refer to Figure 8 , Figure 8 This is a schematic diagram of an in-memory operator according to another embodiment of the present disclosure. The in-memory operator 800 includes a memory cell array 810, a sense amplifier 820, and a word line driver 840. The memory cell array 810 includes memory cell blocks CAj to CAm. Taking the memory cell block CAj as an example, the memory cell block CAj and the input buffer (not shown) can set the corresponding arrangement relationship between the multiple bits Wij(0) to Wij(3) of the weight value and the multiple bits Ai(0) to Ai(2) of the input signal according to the bit sequence of the first operation result generated during the multiplication operation. In detail, the bit Ai(2) of the input signal is multiplied by the bit Wij(3) of the weight value to produce the most significant bit of the first operation result, and is therefore set in the field of 25 accordingly. The multiplication of bit Ai(1) of the input signal by bit Wij(3) of the weight value, and the multiplication of bit Ai(2) of the input signal by bit Wij(2) of the weight value, can both produce the second most significant bit of the first operation result, and are therefore set in the corresponding field 24. The multiplication of bit Ai(0) of the input signal by bit Wij(0) of the weight value can produce the least significant bit of the first operation result, and are therefore set in the corresponding field 20. The setting method of the remaining fields (24 to 21) can be deduced based on the above principle.

[0070] The following reference Figure 9 , Figure 9 To correspond to this disclosure Figure 8 Schematic diagram of an implementation of an in-memory operator of an embodiment. The in-memory operator 900 includes a memory cell array 910, a sense amplifier 920, an input buffer 930, and a word line driver 940. The memory cell array 910 has a memory cell block CAj, wherein in the first field F1, the memory cell block CAj stores the most significant bit Wij(3) of the weight value. Correspondingly, the input buffer 930 provides the most significant bit Ai(2) of the input signal in the first field F1. In the second field F2, the memory cell block CAj stores the most significant bit Wij(3) and the second highest bit Wij(2) of the weight value. Correspondingly, the input buffer 930 provides the bits Ai(1) and Ai(2) of the input signal in the second field F2. The bits Ai(1) and Ai(2) of the input signal correspond to the bits Wij(3) and Wij(2) of the weight value, respectively.

[0071] In the first field F1, the multiplication result of the input signal bit Ai(2) and the weight value bit Wij(3) can generate the most significant bit of the first operation result. In the second field F2, the multiplication result of the input signal bit Ai(1) and the weight value bit Wij(3) and the multiplication result of the input signal bit Ai(2) and the weight value bit Wij(2) can generate the second most significant bit of the first operation result. The same applies to the remaining fields.

[0072] Sense amplifier 920 includes sensing circuits SA1-SA3, CSA1-CSA6, a multiplier 921, and an adder 922. Sensing circuits SA1 are all located in the first field F1, sensing circuits SA2 are all located in the second field F2, and the same applies to the others. Sensing circuits SA1-SA3 are used to sense the current value or current discharge rate of the corresponding bit lines. Sensing circuits CSA1-CSA6 are used to accumulate the current values ​​or current discharge rates of the corresponding bit lines sensed by multiple sensing circuits SA1-SA3 to sense the first calculation result generated by memory cell block CAj. Multiplier 921 is coupled to the output terminals of sensing circuits CSA1-CSA5 and multiplies the output of sensing circuit CSA1 by 2 to the power of 5; the output of sensing circuit CSA2 by 2 to the power of 4; the output of sensing circuit CSA3 by 2 to the power of 3; the output of sensing circuit CSA4 by 2 to the power of 2; and the output of sensing circuit CSA5 by 2 to the power of 1. The multiplier 921 is used to generate a plurality of first signals. The adder 922 is coupled to the multiplier 921 and is used to add the plurality of first signals to generate a second operation result. Here, the second operation result is the multiplication and addition operation result of the operator 900 in the memory.

[0073] Please refer to Figure 10 , Figure 10 This is a schematic diagram of an in-memory arithmetic unit according to another embodiment of the present disclosure. The in-memory arithmetic unit 1000 includes a memory cell array 1010, a sense amplifier 1020, and a word line driver 1040. The memory cell array 1010 includes memory cell blocks CAj to CAm. Taking the memory cell block CAj as an example, the memory cell block CAj has multiple storage columns corresponding to multiple word lines. The word line driver 1040 can activate these word lines in sequence. The memory cell block CAj is used to store multiple bits of a weight value. The arrangement of the multiple bits of the weight value can be specifically described in the following embodiment.

[0074] An input buffer (not shown) is configured to provide multiple bits of input signals A1-An to corresponding bit lines of memory cell block CAj. Memory cell block CAj then performs a multiplication operation on multiple bits of the weight value and multiple bits of input signals A1-An based on the sequentially activated bit lines to generate a first operation result.

[0075] The sense amplifier 1020 is used to sense the first operation result and perform an addition operation on the first operation result according to a bit sequence to generate a second operation result.

[0076] Please refer to Figure 11 , Figure 11 To correspond to this disclosure Figure 10 Schematic diagram of an implementation of an in-memory arithmetic unit of an embodiment. The in-memory arithmetic unit 1100 includes a memory cell array 1110, a sense amplifier 1120, an input buffer 1130, and a word line driver 1140. The memory cell array 1110 includes a memory cell block CAj. The memory cell block CAj corresponds to word lines WL1 to WL6. The memory cell block CAj can be divided into a plurality of fields F1 to Fn, each field storing a plurality of bits W1j(0) to W1j(3), ..., Wnj(0) to Wnj(3) of weight values ​​W1j to Wnj. The plurality of fields F1 to Fn correspond to a plurality of bits A1(2) to A1(0), ..., An(2) to An(0) of received input signals A1 to An, respectively.

[0077] For example, in field F1, in the storage column corresponding to word line WL1, storage cell block CAj stores one bit W1j(0) of the weight value; in the storage column corresponding to word line WL2, storage cell block CAj stores two bits W1j(1) and W1j(0) of the weight value in sequence; in the storage column corresponding to word line WL3, storage cell block CAj stores two bits W1j(2), W1j(1), and W1j(0) of the weight value in sequence; in the storage column corresponding to word line WL4, storage cell block CAj stores two bits W1j(3), W1j(2), and W1j(1) of the weight value in sequence; in the storage column corresponding to word line WL5, storage cell block CAj stores two bits W1j(3) and W1j(2) of the weight value in sequence; in the storage column corresponding to word line WL6, storage cell block CAj stores two bits W1j(3) of the weight value. In the memory cell block CAj, memory cells that do not store weight values ​​store 0.

[0078] From the above description, it can be seen that in the same fields F1-Fn, the memory cell block CAj can store one or more weight value bits W1j(3)-W1j(0) on each word line WL1-WL6. The arrangement of the weight value bits W1j(3)-W1j(0) is related to the bit sequence of the operation result generated by multiplying the bits A1(2)-A1(0) of the corresponding input signal (taking input signal A1 as an example).

[0079] Sense amplifier 1120 includes sensing circuits SA1 and CSA1. Sensing circuit SA1 is configured to sense the current value or current discharge rate of a corresponding bit line. Sensing circuit CSA1 is configured to accumulate the current values ​​or current discharge rates of the corresponding bit lines sensed by multiple sensing circuits SA1 to sense a first operation result generated by memory cell block CAj.

[0080] Please note that since the word lines WL1 to WL6 are activated in a time-sharing manner and based on the special arrangement of the weight values ​​of this embodiment, at the same time point, the current values ​​or current discharge rates of the corresponding bit lines sensed by all sensing circuits SA1 correspond to the same bit sequence.

[0081] The multiplier 1121 can multiply the output of the sensing circuit CSA1 by a power of 2 y according to the activation sequence of the word lines WL1 - WL6 to obtain a plurality of first signals. In this embodiment, when the word lines WL1 - WL6 are activated in sequence, y can be equal to 0-5 in sequence.

[0082] The adder 1122 is coupled to the multiplier 1121 and is used to add the first signals to generate a second operation result. Here, the second operation result is the multiplication and addition operation result of the operator 1100 in the memory.

[0083] Please refer to Figure 12 , Figure 12 This is a flowchart of the in-memory operation method of an embodiment of the present disclosure. In step S1210, a memory cell block corresponding to at least one word line is provided in the memory cell array, so that the memory cell block stores multiple weight values, wherein the multiple memory cells on the memory cell block store multiple bits corresponding to each weight value. In step S1220, an input buffer is provided to transmit multiple input signals to these bit lines respectively. In step S1230, the input signal and the weight value are multiplied in the memory cell array to generate multiple first operation results corresponding to multiple bit sequences respectively. And, in step S1240, the first operation results are added together according to the bit sequence corresponding to the first operation results to generate a second operation result.

[0084] The implementation details of the above steps have been described in detail in the aforementioned embodiments and will not be repeated here.

[0085] In summary, the in-memory arithmetic unit of the present disclosure utilizes a time-sharing and / or spatial configuration correspondence between the multiple bits of the weight values ​​stored in the storage unit block and the multiple bits of the input signal, thereby achieving a pairwise multiplication operation between the multiple bits of the weight values ​​and the multiple bits of the input signal. In this way, the hardware structure of the in-memory arithmetic unit can be simplified. Furthermore, a single-level NAND flash memory in the form of a storage unit can be used to implement the in-memory arithmetic unit of the present disclosure.

Claims

1. An in-memory arithmetic unit, comprising: A memory cell array comprising: a memory cell block corresponding to at least one word line, the memory cell block being used to store a plurality of weight values, wherein a plurality of memory cells on the memory cell block store a plurality of bits corresponding to each of the weight values; and an input buffer coupled to the plurality of bit lines, transmitting a plurality of input signals to the plurality of bit lines respectively; wherein the plurality of input signals and the plurality of weight values ​​are multiplied in the memory cell array to generate a plurality of first operation results corresponding to a plurality of bit sequences respectively; and a sense amplifier, configured to add the first operation results to generate a second operation result according to the bit sequences corresponding to the first operation results; The input buffer transmits multiple bits of each input signal in parallel to multiple corresponding bit lines, and the number of the multiple corresponding bit lines is equal to the number of bits of each weight value multiplied by the number of bits of each input signal. 2 . The in-memory arithmetic unit according to claim 1 , wherein the input buffer transmits a plurality of bits of each input signal to a plurality of corresponding bit lines in a time-sharing manner. 3 . The in-memory operator according to claim 2 , wherein the number of the plurality of corresponding bit lines is equal to the number of bits of each weight value.

4. The memory arithmetic unit according to claim 2 , wherein the sense amplifier comprises: a plurality of sensing circuits, respectively coupled to the plurality of corresponding bit lines, for sensing current states of the plurality of corresponding bit lines to determine the plurality of first operation results; a plurality of first multipliers for multiplying the plurality of first operation results by 2 to the power of N to generate a plurality of first signals, wherein N is determined according to the plurality of bit sequences corresponding to the plurality of first operation results, and N is an integer greater than or equal to 0; a second multiplier coupled to the plurality of first multipliers, multiplying the plurality of first signals by 2 raised to the power of y to generate a plurality of second signals, wherein y is determined according to the bit transmission timing of each of the input signals, and y is an integer greater than or equal to 0; and An adder is coupled to the second multiplier to add the plurality of second signals to generate the second operation result.

5. The in-memory operator according to claim 1, wherein the multiple bits of the multiple weight values ​​are copied into multiple copied weight values, and the storage unit block is on the multiple corresponding bit lines and respectively stores the multiple bits of the multiple copied weight values.

6. The in-memory arithmetic unit according to claim 1 , wherein the sense amplifier comprises: a plurality of sensing circuits, respectively coupled to the plurality of corresponding bit lines, for sensing current states of the plurality of corresponding bit lines to determine the plurality of first operation results; a plurality of multipliers for multiplying the plurality of first operation results by 2 to the power of N to generate a plurality of first signals, wherein N is determined according to the plurality of bit sequences corresponding to the plurality of first operation results; as well as An adder is coupled to the plurality of multipliers to add the plurality of first signals to generate the second operation result. 7 . The in-memory arithmetic unit according to claim 1 , wherein the plurality of corresponding bit lines corresponding to the same bit sequence of the input signals are arranged adjacent to each other. 8 . The in-memory arithmetic unit according to claim 1 , wherein the plurality of corresponding bit lines are arranged in sequence according to a bit order of the plurality of bits of the corresponding input signals.

9. The in-memory operator according to claim 1, wherein the multiple bits of each input signal generate an input arrangement sequence according to the bit sequence of the corresponding multiple first operation results, and the input buffer transmits the multiple bits of each input signal to the multiple corresponding bit lines respectively according to the input arrangement sequence.

10. The in-memory operator according to claim 1, wherein the storage cell block comprises a plurality of storage columns, the at least one word line comprises a plurality of word lines corresponding to the plurality of storage columns respectively, and each of the storage columns stores at least one of the plurality of bits of the plurality of weight values ​​in a field corresponding to each of the input signals.

11. The in-memory arithmetic unit according to claim 10 , wherein the sense amplifier comprises: a plurality of sensing amplifier circuits, respectively coupled to the plurality of corresponding bit lines, for sensing current states of the plurality of corresponding bit lines to determine the plurality of first operation results; a multiplier for multiplying the plurality of first operation results by 2 to the power of N to generate a plurality of first signals, wherein N is determined according to the order of the enabled bit lines in the plurality of word lines, and N is an integer greater than or equal to 0; An adder is coupled to the multiplier to add the first signals to generate the second operation result. 12 . The in-memory arithmetic unit according to claim 1 , wherein the memory cell array is a NAND flash memory cell array.

13. An in-memory computing method, comprising: In a memory cell array, a memory cell block is provided corresponding to at least one word line, so that the memory cell block stores a plurality of weight values, wherein a plurality of memory cells on the memory cell block store a plurality of bits corresponding to each of the weight values; providing an input buffer to transmit a plurality of input signals to a plurality of bit lines respectively; Performing a multiplication operation on the plurality of input signals and the plurality of weight values ​​in the memory cell array to generate a plurality of first operation results respectively corresponding to a plurality of bit sequences; as well as Adding the plurality of first operation results to generate a second operation result according to the plurality of bit sequences corresponding to the plurality of first operation results; The step of providing the input buffer to transmit the multiple input signals to the multiple bit lines respectively through the multiple word lines includes: providing the input buffer so that the multiple bits of each input signal are transmitted in parallel to multiple corresponding bit lines, and the number of the multiple corresponding bit lines is equal to the number of bits of each weight value multiplied by the number of bits of each input signal.

14. The memory operation method according to claim 13 , wherein the step of providing the input buffer to transmit the plurality of input signals to the plurality of bit lines respectively through the plurality of word lines comprises: The input buffer is provided so that the multiple bits of each input signal are transmitted to the multiple corresponding bit lines in a time-sharing manner. 15 . The in-memory operation method according to claim 13 , wherein the plurality of corresponding bit lines corresponding to the same bit sequence of the input signals are arranged adjacent to each other. 16 . The memory operation method according to claim 13 , wherein the plurality of corresponding bit lines are arranged in sequence according to a bit order of the plurality of bits of the corresponding input signals.

17. The in-memory operation method according to claim 13, further comprising: generating an input permutation sequence according to the bit order of the plurality of first operation results generated corresponding to the plurality of bits of each of the input signals; as well as The input buffer is configured to transmit the plurality of bits of each input signal to the plurality of corresponding bit lines respectively according to the input arrangement sequence.

18. The memory operation method according to claim 13 , wherein the memory cell block comprises a plurality of memory columns, the at least one word line comprises a plurality of word lines corresponding to the plurality of memory columns, the memory operation method further comprising: Each of the memory banks is provided to store at least one of the bits of the weight values ​​in a field corresponding to each of the input signals.

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