Layout construction method

Abstract

The present invention discloses a layout construction method for simulating the use environment of a standard cell library unit, including: determining a substrate potential, connecting the substrate of the standard cell library unit to a set potential power supply through a substrate connection unit; simulating an active area environment, adding an active area with no electrical characteristics to the upper, lower, left, and right sides of the standard cell library unit; simulating an injection layer environment, wherein the injection layer width is greater than the injection layer of the standard cell library unit itself; simulating a gate environment, arranging an invalid gate in the upper, lower, left, and right directions of the effective gate of the standard cell library unit, and simulating the environment after the cell library is spliced ​​up and down, left, and right; simulating a first-layer metal environment, arranging vertically suspended first-layer metal wires on the left and right sides of the standard cell library unit to simulate a metal wire environment; simulating a second-layer metal environment, placing vertically suspended second-layer metal wires on the left and right sides of the standard cell library unit to simulate a metal wire environment. The present invention can improve the accuracy of the standard cell library unit in the characterization process.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuits, and in particular to a layout construction method. Background Art

[0002] In semiconductor integrated circuit manufacturing, each process requires a corresponding standard cell library. Before tape-out, standard cells from this library are used for automated logic synthesis and layout routing. The advantage of a design approach based on a standard cell library is that, at a specific process node, the library only needs to be designed and successfully verified once, and can then be reused in subsequent designs, significantly improving design efficiency and alleviating design costs.

[0003] refer to Figure 1 As shown, in the existing characterization process, standard cell library cells are connected to a set potential power supply via a substrate connection unit. Parasitic parameters and second-order effects of the layout are then extracted and combined with the circuit netlist to generate a post-simulation netlist. This post-simulation netlist is then simulated to obtain a series of data, including timing information and power consumption information, for the standard cell library cells. This characterization process fails to consider the second-order effects and parasitic resistance and capacitance that affect the standard cell in the actual operating environment. This ultimately leads to deviations in timing and power consumption information, resulting in inaccurate synthesis results and even functional failure. Summary of the Invention

[0004] The Summary of the Invention introduces a series of simplified concepts, which are simplifications of existing technologies in the field and are further described in detail in the Detailed Description of the Invention. The Summary of the Invention is not intended to define the key features and essential features of the claimed technical solution, nor is it intended to determine the scope of protection of the claimed technical solution.

[0005] The technical problem to be solved by the present invention is to provide a layout construction method which can improve the accuracy of standard cell library cells in the characterization process by constructing a simulated cell library usage environment through layout.

[0006] To solve the above technical problems, the present invention provides a layout construction method for simulating a cell library usage environment, comprising the following steps:

[0007] S1) Determine the substrate potential, and connect the standard cell library cell to the set potential power supply through the substrate connection unit;

[0008] S2) Simulating the active area environment, adding active areas without electrical characteristics above, below, left and right of the standard cell library cell;

[0009] S3) Simulates the injection layer environment, where the injection layer width is larger than the injection layer of the standard cell library cell itself;

[0010] S4) Simulating the gate environment, arranging inactive gates in the upper, lower, left, and right directions of the effective gates of the standard cell library cells, simulating the environment after the cell library is spliced ​​up and down and left and right;

[0011] S5) Simulating the first-layer metal environment, arranging vertically suspended first-layer metal lines on the left and right sides of the standard cell library unit to simulate the metal line environment;

[0012] S6) Simulate the second-layer metal environment by placing vertically suspended second-layer metal lines on the left and right sides of the standard cell library unit to simulate the metal line environment.

[0013] Optionally, the layout construction method is further improved, where the substrate connection unit is located on both sides of the standard cell library unit, and its P-well is connected to the N-well.

[0014] Optionally, the layout construction method can be further improved so that when step S2 is implemented, the distance between the active areas without electrical characteristics on the left and right sides of the standard cell library cell and the active area of ​​the standard cell library cell is the minimum design rule provided by the wafer manufacturer.

[0015] Optionally, the layout construction method can be further improved so that when step S2 is implemented, the distance between the active areas without electrical characteristics located on the upper and lower sides of the standard cell library unit and the active area of ​​the standard cell library unit is the distance between the active areas of the standard cell library units after actual splicing.

[0016] Optionally, the layout construction method can be further improved, and when step S3 is implemented, the width of the injection layer on the left and right sides of the standard cell library cell should be greater than 2 μm.

[0017] Optionally, the layout construction method can be further improved. When implementing step S3, the height of the injection layers on the upper and lower sides of the standard cell library unit should be equal to the height of the two standard cell library units after being spliced ​​together along the power line and the ground line.

[0018] Optionally, the layout construction method is further improved, and when step S4 is implemented, the distance from the inactive gate to the active gate is the distance after the standard cell library cells are spliced.

[0019] Optionally, the layout construction method can be further improved, and when step S5 is implemented,

[0020] The distance between the vertically suspended first-layer metal line and the standard cell library cell is half of the minimum design rule.

[0021] Optionally, the layout construction method may be further improved to further include:

[0022] If the power line and the ground line are not the first-layer metal connection lines, horizontally suspended first-layer metal lines are arranged above and below the standard cell library cells to simulate the metal line environment.

[0023] Optionally, the layout construction method is further improved, and when step S6 is implemented, the distance between the vertically suspended second-layer metal line and the standard cell library cell is half the minimum design rule spacing.

[0024] Optionally, the layout construction method can be further improved. When implementing step S6, if the power line and the ground line are not second-layer metal connections, horizontally suspended second-layer metal lines are placed above and below the standard cell library cells to simulate the metal line environment.

[0025] Optionally, the layout construction method may be further improved to include:

[0026] S7, if the standard cell library cell contains metals of other layers, the metal simulation environment of other layers can be performed according to step S6.

[0027] This invention simulates the cell library's usage environment through layout design to improve the accuracy of standard cell library cell characterization. Using the layout construction method of the present invention, the cell library can make the second-order effects and parasitic resistance and capacitance closer to reality when simulating the netlist after extraction, thereby improving the accuracy of the simulated netlist characterization after use. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The drawings herein are intended to illustrate the general characteristics of methods, structures, and / or materials used in certain exemplary embodiments of the present invention, supplementing the descriptions in the specification. However, the drawings herein are schematic diagrams not drawn to scale and may not accurately reflect the precise structure or performance characteristics of any given embodiment. The drawings herein should not be interpreted as defining or limiting the range of values ​​or properties encompassed by the exemplary embodiments of the present invention. The present invention is further described in detail below in conjunction with the drawings and specific embodiments:

[0029] Figure 1 It is a schematic diagram of the existing technical layout structure.

[0030] Figure 2 This is a schematic diagram of the structure of the present invention Figure 1 .

[0031] Figure 3 This is a schematic diagram of the structure of the present invention Figure 2 .

[0032] Figure 4 This is a schematic diagram of the structure of the present invention Figure 3 .

[0033] Figure 5 This is a schematic diagram of the structure of the present invention Figure 4 . DETAILED DESCRIPTION

[0034] The following describes the embodiments of the present invention through specific embodiments. Those skilled in the art can fully understand the other advantages and technical effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through different specific embodiments, and the details in this specification can also be applied based on different viewpoints, and various modifications or changes can be made without departing from the overall design concept of the invention. It should be noted that, in the absence of conflict, the following embodiments and the features in the embodiments can be combined with each other. The following exemplary embodiments of the present invention can be implemented in a variety of different forms and should not be interpreted as being limited to the specific embodiments described here. It should be understood that these embodiments are provided to make the disclosure of the present invention thorough and complete, and to fully convey the technical solutions of these exemplary embodiments to those skilled in the art. It should be understood that when an element is referred to as being "connected" or "coupled" to another element, the element can be directly connected or coupled to the other element, or there can be an intermediate element. The difference is that when an element is referred to as being "directly connected" or "directly coupled" to another element, there is no intermediate element.

[0035] First embodiment;

[0036] The present invention provides a layout construction method for simulating the use environment of a standard cell library cell, comprising the following steps:

[0037] S1) Determine the substrate potential, and connect the standard cell library cell to the set potential power supply through the substrate connection unit;

[0038] S2) Simulating the active area environment, adding active areas without electrical characteristics above, below, left and right of the standard cell library cell;

[0039] S3) Simulates the injection layer environment, where the injection layer width is larger than the injection layer of the standard cell library cell itself;

[0040] S4) Simulating the gate environment, arranging inactive gates in the upper, lower, left, and right directions of the effective gates of the standard cell library cells, simulating the environment after the cell library is spliced ​​up and down and left and right;

[0041] S5) Simulating the first-layer metal environment, arranging vertically suspended first-layer metal lines on the left and right sides of the standard cell library unit to simulate the metal line environment;

[0042] S6) Simulate the second-layer metal environment by placing vertically suspended second-layer metal lines on the left and right sides of the standard cell library unit to simulate the metal line environment.

[0043] In addition, it should be understood that, although the terms "first," "second," etc. may be used herein to describe different elements, parameters, components, regions, layers, and / or parts, these elements, parameters, components, regions, layers, and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, parameter, component, region, layer, or part from another element, parameter, component, region, layer, or part. Therefore, without departing from the teachings of exemplary embodiments of the present invention, the first element, parameter, component, region, layer, or part discussed below may also be referred to as a second element, parameter, component, region, layer, or part.

[0044] Second embodiment;

[0045] The present invention provides a layout construction method for simulating the use environment of a standard cell library cell, comprising the following steps:

[0046] S1) determining the substrate potential, connecting the standard cell library cell to the set potential power supply through the substrate connection unit, which is located on both sides of the standard cell library cell and connects its P well to the N well;

[0047] S2) Simulate the active area environment and add active areas with no electrical characteristics on the top, bottom, left, and right sides of the standard cell library cell. The distance between the active areas with no electrical characteristics on the left and right sides of the standard cell library cell and the active areas of the standard cell library cell is the minimum design rule provided by the wafer manufacturer.

[0048] S3) Simulate the injection layer environment. The injection layer width shown is larger than the injection layer of the standard cell library unit itself. The injection layer width on both sides of the standard cell library unit should be larger than 2 μm.

[0049] S4) simulating a gate environment, arranging inactive gates above, below, and left and right of the effective gates of the standard cell library cells, simulating an environment after the cell library is spliced ​​together. The distance from the inactive gate to the effective gate is the distance after the standard cell library cells are spliced ​​together.

[0050] S5) simulating a first-layer metal environment, arranging vertically suspended first-layer metal lines on the left and right sides of the standard cell library unit to simulate a metal line environment, wherein the distance between the vertically suspended first-layer metal lines and the standard cell library unit is half of the minimum design rule;

[0051] S6) simulating a second-layer metal environment, placing vertically suspended second-layer metal lines on the left and right sides of the standard cell library unit to simulate a metal line environment, wherein the distance between the vertically suspended second-layer metal lines and the standard cell library unit is half of the minimum design rule spacing.

[0052] Third embodiment;

[0053] The present invention provides a layout construction method for simulating the use environment of a standard cell library cell, comprising the following steps:

[0054] S1) determining the substrate potential, connecting the standard cell library cell to the set potential power supply through the substrate connection unit, which is located on both sides of the standard cell library cell and connects its P well to the N well;

[0055] S2) Simulate the active area environment and add active areas with no electrical characteristics on the top, bottom, left, and right sides of the standard cell library unit. The distance between the active areas with no electrical characteristics on the left and right sides of the standard cell library unit and the active area of ​​the standard cell library unit is the minimum design rule provided by the wafer manufacturer. The distance between the active areas with no electrical characteristics on the top and bottom sides of the standard cell library unit and the active area of ​​the standard cell library unit is the distance between the active areas of the standard cell library units after actual splicing.

[0056] S3) simulates the injection layer environment. The injection layer width is larger than the injection layer of the standard cell library unit itself. The injection layer heights on the upper and lower sides of the standard cell library unit should be equal to the height of the two standard cell library units after being spliced ​​up and down along the power line and ground line. Figure 3 Middle N2;

[0057] S4) simulating a gate environment, arranging inactive gates above, below, and left and right of the effective gates of the standard cell library cells, simulating an environment after the cell library is spliced ​​together. The distance from the inactive gate to the effective gate is the distance after the standard cell library cells are spliced ​​together.

[0058] S5) simulating a first-layer metal environment, arranging vertically suspended first-layer metal wires on the left and right sides of the standard cell library unit to simulate a metal wire environment, wherein the distance between the vertically suspended first-layer metal wires and the standard cell library unit is half of the minimum design rule; if the power line and the ground line are not first-layer metal lines, arranging horizontally suspended first-layer metal wires above and below the standard cell library unit to simulate a metal wire environment;

[0059] S6) Simulating a second-layer metal environment, placing vertically suspended second-layer metal wires on the left and right sides of the standard cell library unit to simulate a metal wire environment, wherein the distance between the vertically suspended second-layer metal wires and the standard cell library unit is half the minimum design rule spacing; if the power line and the ground line are not second-layer metal connections, then placing horizontally suspended second-layer metal wires above and below the standard cell library unit to simulate a metal wire environment.

[0060] Third embodiment;

[0061] The present invention provides a layout construction method for simulating the use environment of a standard cell library cell, comprising the following steps:

[0062] S1) determining the substrate potential, connecting the standard cell library cell to the set potential power supply through the substrate connection unit, which is located on both sides of the standard cell library cell and connects its P well to the N well;

[0063] S2) simulates the active area environment and adds active areas without electrical characteristics on the top, bottom, left and right sides of the standard cell library unit; the distance between the active areas without electrical characteristics on the left and right sides of the standard cell library unit and the active areas of the standard cell library unit is the minimum design rule provided by the wafer manufacturer, refer to Figure 3 In A1, the distance between the active areas without electrical characteristics located on the upper and lower sides of the standard cell library cell and the active area of ​​the standard cell library cell is the distance between the active areas of the standard cell library cells after actual splicing;

[0064] S3) simulates the injection layer environment. The injection layer width shown is larger than the injection layer of the standard cell library unit itself. The injection layer width on both sides of the standard cell library unit should be larger than 2um. Figure 3 Middle N1;

[0065] S4) simulating a gate environment, arranging inactive gates above, below, and left and right of the effective gates of the standard cell library cells, simulating an environment after the cell library is spliced ​​together. The distance from the inactive gate to the effective gate is the distance after the standard cell library cells are spliced ​​together.

[0066] S5) Simulate the first-layer metal environment. Arrange vertical suspended first-layer metal lines on the left and right sides of the standard cell library unit to simulate the metal line environment. The distance between the vertical suspended first-layer metal lines and the standard cell library unit is half the minimum design rule. Figure 4 In M1; if the power line VDD and the ground line VSS are not first-layer metal connections, then horizontally suspended first-layer metal lines are arranged above and below the standard cell library cells to simulate the metal line environment;

[0067] S6) M2 simulates the second-layer metal environment. Vertically suspended second-layer metal wires are placed on the left and right sides of the standard cell library unit to simulate the metal wire environment. Preferably, the distance between the vertically suspended second-layer metal wires and the standard cell library unit is half the minimum design rule spacing, refer to Figure 5 As shown; if the power line and ground line are not second-layer metal connections, then horizontally suspended second-layer metal lines are placed above and below the standard cell library cells to simulate the metal line environment;

[0068] S7, if the standard cell library cell contains metals of other layers, the metal simulation environment of other layers can be performed according to step S6.

[0069] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will also be understood that, unless expressly defined herein, terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, rather than being interpreted in an idealized or overly formal sense.

[0070] The present invention has been described in detail above by way of specific embodiments and examples, but these do not constitute limitations of the present invention. Without departing from the principles of the present invention, those skilled in the art may make many variations and improvements, which should also be considered within the scope of protection of the present invention.

Claims

1. A layout construction method for simulating the use environment of a standard cell library cell, characterized in that: The following steps are involved: S1) determining the substrate potential, and connecting the standard cell library cell to the set potential power supply through the substrate connection unit; S2) simulating an active area environment, and adding active areas without electrical characteristics above, below, left, and right of the standard cell library cell; S3) simulating an injection layer environment, wherein the injection layer width is larger than the injection layer of the standard cell library cell itself; S4) simulating a gate environment, arranging inactive gates in the upper, lower, left, and right directions of the effective gates of the standard cell library cells, and simulating an environment after the cell library is spliced ​​up and down and left and right; S5) simulating a first-layer metal environment, arranging vertically suspended first-layer metal wires on the left and right sides of the standard cell library unit to simulate a metal wire environment; the distance between the vertically suspended first-layer metal wires and the standard cell library unit is half of the minimum design rule; If the power line and ground line are not first-layer metal connections, horizontally suspended first-layer metal lines are arranged above and below the standard cell library cells to simulate the metal line environment; S6) simulating a second-layer metal environment by placing vertically suspended second-layer metal wires on the left and right sides of the standard cell library unit to simulate a metal wire environment; the distance between the vertically suspended second-layer metal wires and the standard cell library unit is half the minimum design rule spacing; If the power line and ground line are not second-layer metal connections, horizontally suspended second-layer metal lines are placed above and below the standard cell library cells to simulate the metal line environment.

2. The layout construction method according to claim 1, wherein: The substrate connection unit is located on both sides of the standard cell library unit and connects the P well and the N well.

3. The layout construction method according to claim 1, wherein: When implementing step S2), the distance between the active areas without electrical characteristics on the left and right sides of the standard cell library cell and the active area of ​​the standard cell library cell is the minimum design rule provided by the wafer manufacturer.

4. The layout construction method according to claim 1, wherein: When performing step S2), the distance between the active areas without electrical characteristics located on the upper and lower sides of the standard cell library unit and the active area of ​​the standard cell library unit is the distance between the active areas of the standard cell library units after actual splicing.

5. The layout construction method according to claim 1, wherein: When performing step S3, the width of the injection layer on the left and right sides of the standard cell library cell should be greater than 2 μm.

6. The layout construction method according to claim 1, wherein: When performing step S3, the height of the injection layers on the upper and lower sides of the standard cell library cell should be equal to the height of the two standard cell library cells after being spliced ​​up and down along the power line and the ground line.

7. The layout construction method according to claim 1, wherein: When step S4 is implemented, the distance between the inactive gate and the active gate is the distance after the standard cell library cells are spliced.

8. The layout construction method according to any one of claims 1 to 7, wherein: Also includes: S7 , if the standard cell library cell includes other metal layers, then the simulation environment of the other metal layers is executed according to step S6 .

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