A display panel and a display device

Abstract

The present invention discloses a display panel and a display device. The display panel includes: a gate circuit and pixel circuits of the first to Qth rows; the gate circuit includes at least one switch control unit, one switch control unit is correspondingly electrically connected to at least one row of pixel circuits, and the input end of the switch control unit is connected to a reset signal line; in a frame of a refreshed picture, when the pixel circuit of the first row enters the holding stage, the reset signal line is switched from a first reset signal to a different second reset signal; the switch control unit of the pixel circuit of the ith row turns off at an earlier moment in the writing stage than the start moment of the holding stage of the pixel circuit of the first row, and the switch control unit of the pixel circuit of the ith row turns on at an earlier moment in the holding stage than the switch control unit of the pixel circuit of the jth row in the holding stage. In the present invention, by arranging a switch control unit between the reset signal line and the reset module of the pixel circuit, the leakage time of the pixel circuit can be controlled, and the flicker difference can be improved.

Description

Technical Field

[0001] The present invention relates to the field of display technologies, and particularly to a display panel and a display device. Background Art

[0002] In a display panel, a pixel circuit provides a driving current required for display for a light-emitting element of the display panel and controls whether the light-emitting element enters a light-emitting stage, and is an indispensable element in most self-luminous display panels.

[0003] However, in an existing display panel, the control terminal of a driving transistor in the pixel circuit slowly leaks electricity after data writing, resulting in a large difference in the top flicker and the bottom flicker of the display panel when driving with a varying reset signal, which affects the display effect. Summary of the Invention

[0004] The present invention provides a display panel and a display device to solve the problem of a large difference in flicker between the top and the bottom of an existing display panel.

[0005] According to one aspect of the present invention, there is provided a display panel, including: a gate circuit and a first to Qth row pixel circuits arranged in sequence, where Q is a positive integer greater than or equal to 2;

[0006] The gate circuit includes at least one switch control unit, and one switch control unit is correspondingly electrically connected to at least one row of pixel circuits, and an input terminal of the switch control unit is connected to a reset signal line;

[0007] The pixel circuit includes a driving module, a reset module, a data writing module, and a compensation module. The reset module is connected between an output terminal of the switch control unit and a control terminal of the driving module. The data writing module is connected between a data signal line and a first terminal of the driving module. The compensation module is connected between the control terminal and a second terminal of the driving module;

[0008] In one frame of a refreshed picture, the working process of the pixel circuit includes a writing stage and a holding stage. The writing stage includes a data writing stage and a light-emitting stage. The holding stage does not include the data writing stage;

[0009] In the data writing stage, the reset module is turned off, and the driving module, the data writing module, and the compensation module are turned on, and a data signal of the data signal line is transmitted to the control terminal of the driving module; in the light-emitting stage, the switch control unit and the reset module are turned off, and the driving module is turned on; in the holding stage, the switch control unit first remains off and then is turned on;

[0010] The pixel circuit of the i-th row and the pixel circuit of the j-th row are electrically connected to two different switch control units, where both i and j are positive integers and i is less than j;

[0011] In a frame of refreshed picture, when the pixel circuit of the first row enters the holding stage, the reset signal line switches from the first reset signal to a different second reset signal; the switching control unit of the i-th row pixel circuit turns off at an earlier time than the start time of the holding stage of the first row pixel circuit, and the switching control unit of the i-th row pixel circuit turns on at an earlier time than the switching control unit of the j-th row pixel circuit in the holding stage.

[0012] According to another aspect of the present invention, a display device is provided, including the display panel as described above.

[0013] In the embodiment of the present invention, a switch control unit is arranged between the reset signal line and the reset module of the pixel circuit. By controlling the turn-off and turn-on of the switch control unit for each row, the difference in leakage time of the pixel circuits from the first row to the last row can be reduced, and further the difference in leakage time of the control ends of the driving modules of the pixel circuits at the top and bottom of the panel can be reduced, so that the pre-coupling potentials of the control ends of the driving modules of the pixel circuits in each row can be close, and further the flicker difference between the top and bottom can be reduced.

[0014] It should be understood that the content described in this part is not intended to identify the key or important features of the embodiments of the present invention, nor is it used to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. Description of the Drawings

[0015] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0016] Figure 1 is a schematic diagram of a display panel provided by an embodiment of the present invention;

[0017] Figure 2 is a schematic diagram of a pixel circuit provided by an embodiment of the present invention;

[0018] Figure 3 is a timing schematic diagram of a frame of refreshed picture provided by an embodiment of the present invention;

[0019] Figure 4 is a schematic diagram of an existing pixel circuit;

[0020] Figure 5 is Figure 4 the timing diagram of;

[0021] Figure 6 is a schematic diagram of another display panel provided by an embodiment of the present invention;

[0022] Figure 7 is a schematic diagram of yet another display panel provided by an embodiment of the present invention;

[0023] Figure 8 is a schematic diagram of yet another display panel provided by an embodiment of the present invention;

[0024] Figure 9 is a schematic diagram of yet another display panel provided by an embodiment of the present invention;

[0025] Figure 10 is the timing diagram of the pixel circuit of the i-th row provided by an embodiment of the present invention;

[0026] Figure 11 is the timing diagram of another frame refresh screen provided by an embodiment of the present invention;

[0027] Figure 12 is the timing diagram of yet another frame refresh screen provided by an embodiment of the present invention. Detailed implementation manners

[0028] In order to enable those skilled in the art to better understand the solution of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0029] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above drawings are used to distinguish similar objects, and do not necessarily have to be used to describe a specific order or sequence. It should be understood that such data can be interchanged under appropriate circumstances so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device that includes a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0030] Figure 1 is a schematic diagram of a display panel provided by an embodiment of the present invention,Figure 2 is a schematic diagram of a pixel circuit provided by an embodiment of the present invention, Figure 3 is a timing schematic diagram of a frame of refreshed picture provided by an embodiment of the present invention. As Figure 1 and Figure 2 shown, the display panel provided in this embodiment includes: a strobe circuit 100 and the first to Qth row pixel circuits 200 arranged in sequence, where Q is a positive integer greater than or equal to 2; the strobe circuit 100 includes at least one switch control unit 110, and one switch control unit 110 is correspondingly electrically connected to at least one row of pixel circuits 200, and the input end of the switch control unit 110 is connected to the reset signal line Vref; the pixel circuit 200 includes a driving module 210, a reset module 220, a data writing module 230, and a compensation module 240. The reset module 220 is connected between the output end of the switch control unit 110 and the control end N1 of the driving module 210. The data writing module 230 is connected between the data signal line Vdata and the first end N2 of the driving module 210. The compensation module 240 is connected between the control end N1 and the second end N3 of the driving module 210; in a frame of refreshed picture, the working process of the pixel circuit 200 includes a writing stage and a holding stage. The writing stage includes a data writing stage and a light emitting stage, and the holding stage does not include the data writing stage; in the data writing stage, the reset module 220 is turned off, and the driving module 210, the data writing module 230, and the compensation module 240 are turned on, and the data signal of the data signal line Vdata is transmitted to the control end N1 of the driving module 210; in the light emitting stage, the switch control unit 110 and the reset module 220 are turned off, and the driving module 210 is turned on; in the holding stage, the switch control unit 110 is first kept off and then turned on; the ith row pixel circuit and the jth row pixel circuit are electrically connected to different two switch control units 110a and 110b, where both i and j are positive integers and i is less than j; in a frame of refreshed picture, when the first row pixel circuit enters the holding stage, the reset signal line Vref switches from the first reset signal to a different second reset signal; the turn-off moment of the switch control unit 110a of the ith row pixel circuit in the writing stage is earlier than the start moment of the holding stage of the first row pixel circuit, and the turn-on moment of the switch control unit 110a of the ith row pixel circuit in the holding stage is earlier than the turn-on moment of the switch control unit 110b of the jth row pixel circuit in the holding stage.

[0031] It should be noted that, Figure 1 and Figure 2 only schematically show and mark the key structures in the above embodiments, and do not include all the structures that the circuit operates. Other circuit structures will be gradually shown in the following description of this embodiment. Figure 3 only schematically shows a timing relationship in the above embodiment, and is not limited to this timing relationship. According to Figure 3Deforming the middle timing relationship may fall within the protection scope of the present invention.

[0032] In this embodiment, the display area of the display panel includes the first to Qth row pixel circuits 200 arranged in sequence, where Q is a positive integer greater than or equal to 2. One row of pixel circuits 200 includes a plurality of pixel circuits 200 arranged in the row direction, and the first to Qth row pixel circuits 200 are arranged in sequence in the column direction. As Figure 1 shown, it is optional that the ith row pixel circuit and the jth row pixel circuit are arranged adjacent to each other, but in other embodiments, it is also optional that there is one or more rows of pixel circuits spaced between the ith row pixel circuit and the jth row pixel circuit. It should be noted that in a frame refresh screen of the display panel, when performing scanning refresh in a line-by-line scanning manner, the ith row pixel circuit is scanned and refreshed first, and then the jth row pixel circuit is scanned and refreshed later. Taking the data writing stage in the pixel circuit as an example, after the ith row pixel circuit finishes the data writing stage, the jth row pixel circuit then executes the data writing stage.

[0033] The non-display area of the display panel includes a gating circuit 100. The gating circuit 100 includes at least one switch control unit 110. One switch control unit 110 is correspondingly electrically connected to at least one row of pixel circuits 200, and the input end of the switch control unit 110 is electrically connected to the reset signal line Vref. As Figure 1 shown, it is optional that the gating circuit 100 includes a plurality of switch control units 110, where there is one switch control unit 110 electrically connected to one row of pixel circuits 200, and there is also one switch control unit 110 electrically connected to at least two rows of pixel circuits 200, but it is not limited thereto. For example, the switch control unit 110a is correspondingly electrically connected to the ith row pixel circuit, and the switch control unit 110b is correspondingly electrically connected to the adjacent jth row pixel circuit and the j + 1th row pixel circuit. However, in other embodiments, it is also optional that each switch control unit only corresponds to one row of pixel circuits; or, it is also optional that one switch control unit corresponds to multiple rows of pixel circuits; or, it is also optional that in the same gating circuit, different switch control units correspond to pixel circuits with the same or different numbers of rows; it is not limited thereto. When the switch control unit 110 is turned on, the reset signal provided by the reset signal line Vref will be transmitted to the pixel circuit 200. It is optional that the control end of the switch control unit 110 is electrically connected to the control signal line Vout. The control signal line Vout outputs an effective pulse to turn on the switch control unit 110, and the control signal line Vout outputs an invalid pulse to turn off the switch control unit 110.

[0034] The pixel circuit 200 is electrically connected to the light-emitting element 300. The pixel circuit 200 includes a driving module 210, a reset module 220, a data writing module 230, and a compensation module 240. The reset module 220 is connected between the output end of the switch control unit 110 and the control end N1 of the driving module 210. The data writing module 230 is connected between the data signal line Vdata and the first end N2 of the driving module 210. The compensation module 240 is connected between the control end N1 and the second end N3 of the driving module 210.

[0035] The control end N1 of the driving module 210 is electrically connected to the reset module 220. The first end of the driving module 210 is the node N2, and the second end of the driving module 210 is the node N3. The node N3 of the driving module 210 is coupled to the light-emitting element 300. The driving module 210 includes a driving transistor M1. After the driving transistor M1 is turned on, the driving module 210 provides a driving current for the light-emitting element 300. Optionally, the driving transistor M1 is an N-type transistor or a P-type transistor. As Figure 1 shown, if the driving transistor M1 is a PMOS, the source of the driving transistor M1 is electrically connected to the node N2, and the drain of the driving transistor M1 is electrically connected to the node N3. In other embodiments, if the driving transistor is an NMOS, the drain of the driving transistor is electrically connected to the node N2, and the source of the driving transistor is electrically connected to the node N3. It can be understood that the source and drain of the transistor are not constant, but change with the driving state of the transistor. Based on this, under the control of the node N1, the driving module 210 selectively provides a driving current for the light-emitting element 300.

[0036] The input end of the reset module 220 is electrically connected to the output end of the switch control unit 110. The output end of the reset module 220 is connected to the control end N1 of the driving module 210. The control end of the reset module 220 is connected to a scanning signal line S1. The scanning signal line S1 outputs a pulse signal. Specifically, the output of the valid pulse signal on the scanning signal line S1 turns on the reset module 220, and the output of the invalid pulse signal turns off the reset module 220. When the switch control unit 110 and the reset module 220 are both turned on, the input end of the reset module 220 can receive a reset signal from the reset signal line Vref and transmit it to the control end N1 of the driving module 210 to achieve the reset of the control end N1 of the driving module 210. It can be understood that the reset signals output by the reset signal line Vref at different working stages of the pixel circuit 200 may be different. The reset module 220 includes a reset transistor M2. Optionally, the reset transistor M2 is an N-type transistor, a P-type transistor, a double-gate transistor, or a combined transistor, where the combined transistor is composed of multiple transistors of the same type or different types and the multiple transistors are independently controlled by different scanning signal lines. As Figure 1As shown, the optional reset transistor M2 is a P-type transistor. Based on this, the reset module 220 selectively resets the control terminal N1 of the driving module 210.

[0037] The input terminal of the data writing module 230 is connected to the data signal line Vdata. The control terminal of the data writing module 230 is connected to a scan signal line S3. The output terminal of the data writing module 230 is electrically connected to the first terminal N2 of the driving module 210. The scan signal line S3 outputs a pulse signal. Specifically, the output of a valid pulse signal by the scan signal line S3 turns on the data writing module 230, and the output of an invalid pulse signal turns off the data writing module 230. When the data writing module 230 is turned on, the input terminal of the data writing module 230 can receive the data signal from the data signal line Vdata and transmit it to the first terminal N2 of the driving module 210, thereby realizing data writing to the driving module 210. It can be understood that the data signals output by the data signal line Vdata may be different in different working stages of the pixel circuit 200. The data writing module 230 includes a data writing transistor M3. Optionally, the data writing transistor M3 is an N-type transistor or a P-type transistor. As Figure 1 shown, the optional data writing transistor M3 is a P-type transistor. Based on this, under the control of the scan signal line S3, the data writing module 230 selectively provides a data signal to the first terminal N2 of the driving module 210.

[0038] The compensation module 240 is connected between the control terminal N1 and the second terminal N3 of the driving module 210 and is used to compensate for the threshold voltage of the driving module 210. The control terminal of the compensation module 240 is connected to a scan signal line S2. The scan signal line S2 outputs a pulse signal. Specifically, the output of a valid pulse signal by the scan signal line S2 turns on the compensation module 240, and the output of an invalid pulse signal turns off the compensation module 240. The compensation module 240 includes a compensation transistor M4. Optionally, the compensation transistor M4 is an N-type transistor, a P-type transistor, a double-gate transistor, or a combined transistor, where the combined transistor is composed of multiple transistors of the same type or different types and the multiple transistors are independently controlled by different scan signal lines. As Figure 1 shown, the optional compensation transistor M4 is a P-type transistor.

[0039] The pixel circuit 200 further includes a light-emitting module 250. The control terminal of the light-emitting module 250 is electrically connected to the light-emitting signal line EMIT. The light-emitting module 250 includes two light-emitting transistors. One of the light-emitting transistors is connected between the power supply voltage terminal PVDD and the first terminal N2 of the driving module 210, and the other light-emitting transistor is connected between the second terminal N3 of the driving module 210 and the light-emitting element 300. The light-emitting control signal output by the light-emitting signal line EMIT controls the turning on or off of the light-emitting module 250.

[0040] As Figure 3 shown, in a frame refresh screen, the working process of the pixel circuit 200 includes a writing stage and a holding stage. The writing stage includes a data writing stage and a light emitting stage. The holding stage includes a non-light emitting stage and a light emitting stage, and does not include the data writing stage. The working process of the pixel circuit in the first row will be described below as an example.

[0041] First, execute the writing stage:

[0042] In the data writing stage, the reset module 220 is turned off, and the driving module 210, the data writing module 230, and the compensation module 240 are turned on. Then, the data signal provided by the data signal line Vdata is transmitted to the control terminal N1 of the driving module 210 through the data writing module 230, the driving module 210, and the compensation module 240. In the data writing stage, the switch control unit 110 can be turned on or off; as Figure 3 shown, within the optional data writing stage, the switch control unit 110 remains on, but this is not limited thereto. At this time, the voltage of the control terminal N1 is approximately the sum of the data signal and the threshold voltage. It can be assumed that the voltage of the control terminal N1 is 1V. After the data is written, since the reset module 220 remains off, the control terminal N1 will gradually leak electricity, that is, the voltage of the control terminal N1 starts to leak and gradually increases from 1V.

[0043] In the light emitting stage, the switch control unit 110, the reset module 220, the data writing module 230, and the compensation module 240 are turned off, and the driving module 210 is turned on. Then, the driving module 210 provides a driving current to the light emitting element 300 to make the light emitting element 300 emit light. In the light emitting stage, the switch control unit 110 can first remain on and then be turned off; it can also be as Figure 3 shown, in the optional light emitting stage, the switch control unit 110 is turned off, but this is not limited thereto. The control terminal N1 continues to leak electricity.

[0044] Then, execute the holding stage:

[0045] In the non-light emitting stage, the light emitting module 250 is turned off, and the light emitting element 300 does not emit light. In the light emitting stage, the light emitting module 250 is turned on, the driving module 210 provides a driving current to the light emitting element 300, and the light emitting element 300 emits light.

[0046] It can be understood that the writing stage further includes a reset stage executed before the data writing stage. In the reset stage, the switch control module 110 and the reset module 220 are turned on, and the data writing module 230 and the compensation module 240 are turned off. Then, the first reset signal provided by the reset signal line Vref is transmitted to the control terminal N1 of the driving module 210.

[0047] It should be noted that the timing of a frame refresh screen is not limited to Figure 3As shown, for example, the writing phase may include multiple cycles in which a non-emitting phase and an emitting phase alternate, the holding phase may include multiple cycles in which a non-emitting phase and an emitting phase alternate, and the data writing phase is located in the non-emitting phase of the first cycle of the writing phase. Figure 3 Only one cycle of the writing phase and one cycle of the holding phase are shown.

[0048] A frame refresh screen includes a writing phase and a holding phase. The writing phase can also be understood as a writing frame, and the holding phase can also be understood as a holding frame. The writing frame includes a data writing phase, that is, the pixel circuit writes new display-related data; the holding frame does not include a data writing phase, that is, the pixel circuit is normally refreshed, but maintains the display-related data when it is the writing frame and does not write new display-related data. In order to improve the flicker phenomenon of the holding frame, in the writing phase, the reset signal line Vref provides a first reset signal, and in the holding phase, the reset signal line Vref provides a second reset signal different from the first reset signal. Then, when the switch control unit 110 is turned on, when the reset signal line Vref switches from the first reset signal to the second reset signal, the input end of the reset module 220 can receive the second reset signal, and the output end of the turned-off reset module 220 will be affected by the potential coupling of the second reset signal different from the first reset signal, thereby causing the potential of the control end N1 of the driving module 210 to change. Thus, when the reset signal switches from the first reset signal to the second reset signal, the flicker can be improved.

[0049] Figure 4 Is a schematic diagram of an existing pixel circuit, Figure 5 is Figure 4 The timing diagram of. As shown, in the pixel circuit 2, the reset signal line Vref is directly connected to the input end of the reset module 2B. In a frame refresh screen, when the pixel circuit in the first row enters the holding frame from the writing frame, the reset signal provided by the reset signal line Vref will switch from -3.5V to -5V. Then, the input ends of the reset modules 2B of each row of pixel circuits 2 in the display area all receive -5V simultaneously. Based on this, the output ends of the reset modules 2B of each row of pixel circuits 2 will be affected by the potential coupling of -5V simultaneously, thereby causing the potential of the control end N1 of the driving module 2A to change. Between the data writing phase and the switch to -5V, the control end N1 of the driving module 2A has been leaking electricity. Then, the duration from the data writing phase to the switch to -5V can be determined as the leakage duration of N1. Obviously, in a frame refresh screen, the pixel circuits 2 in the display area are scanned row by row. Then, from the first row of pixel circuits to the last row of pixel circuits, the leakage duration of N1 gradually decreases.

[0050] such as Figure 5As shown, exemplarily, when the reset signal line Vref switches to -5V, the leakage time of N1 in the pixel circuit of the first row is the longest, and its N1 potential leaks from 1V to 1.05V; the leakage time of N1 in the pixel circuit of the second row decreases, and its N1 potential leaks from 1V to 1.04V; and so on. The leakage time of N1 in the pixel circuit of the last row is the shortest, and the N1 potential may maintain 1V. When the reset signal switches from -3.5V to -5V, the control terminal N1 of the driving module 2A will be coupled by the -5V potential. Assuming that the potential coupling causes N1 to drop by 0.05V, then when the reset signal line Vref switches to -5V, N1 in the pixel circuit of the first row is coupled from 1.05V to 1V; N1 in the pixel circuit of the second row is coupled from 1.04V to 0.99V; and so on. The leakage time of N1 in the pixel circuit of the last row is the shortest, and the N1 potential is coupled from 1V to 0.95V. Obviously, the flicker performance at the top and bottom of the panel is inconsistent, that is, there is a difference in flicker between the top and bottom of the panel. The reason can be summarized as follows: from the pixel circuit of the first row to the pixel circuit of the last row, there is a large difference in leakage time and it gradually shortens, resulting in a large difference in the pre-coupling potential of the control terminals of each driving module and changing from large to small, which in turn affects the post-coupling potential.

[0051] Based on this, in this embodiment, a switch control unit 110 is provided between the reset module 220 and the reset signal line Vref. Before the reset signal line Vref switches from the first reset signal to the second reset signal, each switch control unit 110 is controlled to turn off, and after the reset signal line Vref switches from the first reset signal to the second reset signal, the turning-on moment of each switch control unit 110 in the holding stage is controlled. In this way, the time node at which the second reset signal couples the control terminal N1 of the driving module 210 can be adjusted, so as to achieve the effect of controlling the leakage time of different rows to be close by adjusting the turning-on moments of different switch control units 110. Then, the pre-coupling potentials of the control terminals N1 of each driving module 210 can be close, so that the post-coupling potentials are close. In this way, the flicker difference between the top and bottom of the panel is reduced, and the flicker between the top and bottom of the panel is made close to consistent.

[0052] Specifically, in the holding stage, the switch control unit 110 first remains off and then turns on. In a frame of refreshed image, when the pixel circuit in the first row switches from the writing stage to the holding stage, it is the time when the reset signal line Vref switches from the first reset signal to the second reset signal. When the switch control unit 110 is in the on state, the potential change of the reset signal can drive the control terminal N1 of the driving module 210 through the potential coupling at the input terminal of the reset module 220. Therefore, in the light-emitting stage of the writing stage, the switch control unit 110 is controlled to turn off, and in the holding stage, the switch control unit 110 first remains off and then turns on. Before the switch control unit 110 turns off, the reset signal line Vref provides the first reset signal to the input terminal of the reset module 220. After the switch control unit 110 turns on, the reset signal line Vref provides the second reset signal to the input terminal of the reset module 220. The potential change at the input terminal of the reset module 220 can couple the potential change of the control terminal N1 of the driving module 210. It can be seen that the starting moment of the switch control unit 110 in the holding stage in the pixel circuit 200 is the potential coupling node of the reset signal to the control terminal N1 of the driving module 210. Based on this, it can be known that from the end of the data writing stage to the starting moment of the switch control unit 110 in the holding stage, the control terminal N1 of the driving module 210 has been leaking electricity. Therefore, the time duration from the data writing stage to the starting moment of the switch control unit 110 in the holding stage can be determined as the leakage time duration of N1. Obviously, in a frame of refreshed image, the leakage time duration of N1 of each row of pixel circuits is related to the starting moment of its switch control unit 110 in the holding stage. Optionally, the driving transistor M1 is a PMOS, both the first reset signal and the second reset signal are less than 0V, and the first reset signal is greater than the second reset signal; optionally, the first reset signal is -3.5V and the second reset signal is -5V.

[0053] Among them, in a frame of refreshed image, the turn-off moment of the switch control unit 110a of the pixel circuit in the i-th row in the writing stage is earlier than the starting moment of the holding stage of the pixel circuit in the first row, and the turn-on moment of the switch control unit 110a of the pixel circuit in the i-th row in the holding stage is earlier than the turn-on moment of the switch control unit 110b of the pixel circuit in the j-th row in the holding stage.

[0054] In a frame of refreshed image, the switch control unit 110 of the pixel circuit in the first row turns off in the light-emitting stage, and after maintaining the off state for a period of time in the holding stage, it turns on. After the switch control unit 110 turns on, the signal at the input terminal of the reset module 220 switches from -3.5V to -5V, and then the control terminal N1 of the driving module 2A is coupled by the -5V potential. Specifically, the potential of its N1 leaks from 1V to 1.05V and then is coupled to 1V.

[0055] The turn-off moment of the switch control unit 110 of the pixel circuit in the second row should be earlier than the moment when the reset signal line Vref switches from the first reset signal to the second reset signal during the writing stage. The start moment of the data writing stage of the pixel circuit in the second row is later than that of the pixel circuit in the first row. Therefore, the starting moment of N1 leakage of the pixel circuit in the second row is later than that of the pixel circuit in the first row. Then, it can be set that the turn-on moment of the switch control unit 110 of the pixel circuit in the second row during the holding stage is later than that of the switch control unit 110 of the pixel circuit in the first row during the holding stage, which can extend the N1 leakage duration of the second pixel circuit and reduce the difference in N1 leakage duration between the pixel circuit in the second row and the pixel circuit in the first row. Thus, the pre-coupling potential of N1 of the pixel circuit in the second row and N1 of the pixel circuit in the first row can be close, and further reduce the flicker difference between the two rows of pixel circuits.

[0056] And so on, the turn-off moment of the switch control unit 110 of each row of pixel circuits during the writing stage is earlier than the start moment of the holding stage of the pixel circuit in the first row, ensuring that the switch control unit 110 is turned off before the reset signal line Vref switches to the second reset signal. The turn-on moment of the switch control unit 110 of the subsequent row of pixel circuits during the holding stage is later than that of the switch control unit 110 of the previous row of pixel circuits during the holding stage, which can reduce the difference in N1 leakage duration between adjacent two rows. For example, when the leakage durations of N1 in each row reach consistency, N1 of each row of pixel circuits 200 can be potential-coupled by the -5V reset signal when leaking to 1.05V.

[0057] In the embodiment of the present invention, a switch control unit is arranged between the reset signal line and the reset module of the pixel circuit. By controlling the turn-off and turn-on of the switch control unit of each row, the difference in leakage duration from the pixel circuit in the first row to the pixel circuit in the last row can be reduced, and further the difference in leakage duration of the control ends of the driving modules of the pixel circuits at the top and bottom of the panel can be reduced, so that the pre-coupling potentials of the control ends of the driving modules of each row of pixel circuits can be close, and further reduce the flicker difference between the top and the bottom.

[0058] Figure 6 It is a schematic diagram of another display panel provided by the embodiment of the present invention. As Figure 6 shown, the selectable gating circuit 100 includes the first to the Nth switch control units 110. The first to the Nth switch control units 110 are sequentially electrically connected to at least N adjacent rows of pixel circuits 200. The Nth switch control unit 110N is at least correspondingly electrically connected to the pixel circuit 200 in the Qth row, and N is greater than or equal to 2 and less than Q.

[0059] In this embodiment, the gating circuit 100 includes N switch control units 110, which are sequentially electrically connected to at least N adjacent rows of pixel circuits 200. One switch control unit 110 can be electrically connected to 1 adjacent row or multiple rows of pixel circuits 200. The Nth switch control unit 110N is at least correspondingly electrically connected to the Qth row of pixel circuits 200, where N is greater than or equal to 2 and less than Q. Then, starting from the Qth row of pixel circuits 200 upwards, at least N rows of pixel circuits 200 are electrically connected to the N switch control units 110, so as to adjust the leakage time of multiple rows of pixel circuits in at least the lower half of the panel. Since N is less than Q, the occupied space of the gating circuit 100 can be reduced, achieving a narrow border.

[0060] It can be understood that there is a large difference in the leakage time of the driving module control ends of the pixel circuits at the top and bottom of the panel. Then, by setting N switch control units 110 in at least the last N rows of pixel circuits 200, the leakage time of the driving module control ends of the last multiple rows of pixel circuits can be adjusted by turning on and off the switch control units 110. Furthermore, the difference in the leakage time N1 between the multiple rows at the bottom and the top of the panel can be reduced, and thus the flicker difference between the top and the bottom can be reduced.

[0061] As Figure 1 shown, the optional gating circuit 100 includes the 1st to the Nth switch control units 110, and the 1st to the Nth switch control units 110 are sequentially electrically connected to the 1st to the Qth rows of pixel circuits 200. The Nth switch control unit 110N is at least correspondingly electrically connected to the Qth row of pixel circuits 200, where N is greater than or equal to 2 and less than Q.

[0062] In this embodiment, the gating circuit 100 includes N switch control units 110, which are sequentially electrically connected to Q rows of pixel circuits 200. One switch control unit 110 can be electrically connected to 1 adjacent row or multiple rows of pixel circuits 200. The Nth switch control unit 110N is at least correspondingly electrically connected to the Qth row of pixel circuits 200, where N is greater than or equal to 2 and less than Q. Then, from the 1st row of pixel circuits 200 to the Qth row of pixel circuits 200, each row of pixel circuits 200 is electrically connected to the switch control unit 110, so as to adjust the leakage time of all rows of pixel circuits in the panel. The leakage times of the pixel circuits 200 connected to the same switch control unit 110 are the same. Since N is less than Q, the occupied space of the gating circuit 100 can be reduced, achieving a narrow border.

[0063] It can be understood that there is a large difference in the leakage time of the driving module control ends of the pixel circuits at the top and bottom of the panel. Then, by setting a switch control unit 110 in each row of pixel circuits 200, the leakage time of the driving module control end of the pixel circuit can be adjusted by turning on and off the switch control unit 110. Furthermore, the difference in the leakage time N1 between the top and the bottom of the panel can be reduced, so that the pre-coupling potentials of the driving module control ends of each row of pixel circuits can be close, and thus the flicker difference between the top and the bottom can be reduced.

[0064] Figure 7 This is a schematic diagram of another display panel provided by an embodiment of the present invention. As Figure 7 shown, the optional gating circuit 100 includes the first to Qth switch control units 110, and the first to Qth switch control units 110 are sequentially electrically connected to the first to Qth row pixel circuits 200. In this embodiment, the Q switch control units 110 are sequentially electrically connected to the Q row pixel circuits 200, and one switch control unit 110 can be electrically connected to 1 row pixel circuit 200. Then, from the first row pixel circuit 200 to the Qth row pixel circuit 200, each row pixel circuit 200 is electrically connected to the switch control unit 110, realizing independent adjustment of the leakage time of each row pixel circuit in the panel. Furthermore, the difference in the N1 leakage time of different row pixel circuits can be reduced, so that the pre-coupling potential of the driving module control end of each row pixel circuit can be close to or consistent, thereby reducing the flicker difference between the top and the bottom.

[0065] For the above embodiments, it is optional that the number of rows of pixel circuits corresponding to one switch control unit is equal. If N = Q, one switch control unit is electrically connected to 1 row pixel circuit, and the independent adjustment of the leakage time of each row pixel circuit in the panel is realized by independently controlling the switch control unit. If N is less than Q, one switch control unit is electrically connected to 1 row or multiple rows of pixel circuits, and the adjustment of the leakage time of each row pixel circuit in the panel is realized by independently controlling the switch control unit.

[0066] Figure 8 This is a schematic diagram of another display panel provided by an embodiment of the present invention. As Figure 2 and Figure 8 shown, the optional display panel further includes: a driving chip 400; the switch control unit 110 includes a gating switch K1; the control end of the gating switch K1 is electrically connected to the driving chip 400, the input end of the gating switch K1 is electrically connected to the reset signal line Vref, and the output end of the gating switch K1 is electrically connected to the input end of the reset module 220 of the pixel circuit 200; the driving chip 400 is used to control the opening and closing of the gating switch K1, and when it is opened, the reset signal line Vref provides a reset signal to the input end of the reset module 220.

[0067] In this embodiment, the driving chip 400 is located in the non-display area on the side of the display panel. In other embodiments, the driving chip can also be optionally located in the non-display area at the top or bottom of the display panel, without specific limitation. Moreover, the driving chip 400 can also be reused as a display chip, etc., without specific limitation on its position and structure. The driving chip 400 provides an independent control signal Vout to each switching control unit 110. For example, it provides Vout1 to the switching control unit 110 corresponding to the first row of pixel circuits, provides Vout2 to the switching control unit 110 corresponding to the second row of pixel circuits, and provides VoutN to the switching control unit 110 jointly corresponding to the (Q - 1)-th and Q-th row of pixel circuits. By independently controlling the turn-off and turn-on of the switching control unit 110, the driving chip 400 can adjust the leakage time N1 of different rows of pixel circuits, and specifically can control the leakage time N1 of different rows of pixel circuits to be close, thereby improving the flicker difference between the top and bottom of the display panel.

[0068] The switching control unit 110 includes a gating switch K1. Optionally, the gating switch K1 is an NMOS or a PMOS. Then, the gating switch K1 can be fabricated synchronously with the transistors in the pixel circuit 200 without adding a new film layer, reducing the process complexity and realizing the thinning of the display panel. The control signal Vout provided by the driving chip 400 is a pulse signal. When the control signal Vout is a valid pulse signal, the gating switch K1 is turned on, and when the control signal Vout is an invalid pulse signal, the gating switch K1 is turned off.

[0069] Optionally, the driving chip 400 also provides a reset signal to the reset signal line Vref. When the gating switch K1 is turned on, the driving chip 400 provides a reset signal to the input end of the reset module 220 through the reset signal line Vref.

[0070] Figure 9 It is a schematic diagram of another display panel provided by the embodiment of the present invention. As Figure 2 and Figure 9 shown, optionally, the display panel further includes: a multi-stage cascaded shift register 500; the switching control unit 110 includes a gating switch K1, and one shift register 500 corresponds to one switching control unit 110; the control end of the gating switch K1 is electrically connected to the output end Vout of the shift register 500, the input end of the gating switch K1 is electrically connected to the reset signal line Vref, and the output end of the gating switch K1 is electrically connected to the input end of the reset module 220 of the pixel circuit 200; the shift registers 500 of adjacent switching control units 110 are cascaded; the shift register 500 is used to control the turn-on and turn-off of the gating switch K1.

[0071] In this embodiment, a multi-stage cascaded shift register 500 is provided in the non-display area of the display panel. The multi-stage cascaded shift register 500 can shift and output a control signal. One-level shift register 500 is electrically connected to a switch control unit 110 correspondingly, and can provide an independent control signal Vout to the switch control unit 110 to control the switch control unit 110 to turn on or off. It can be understood that, for example, if the pixel circuits of the j-th and the (j + 1)-th rows are commonly electrically connected to the same switch control unit 110, the control signal Vout output by the shift register 500 to the corresponding switch control unit 110 can control the leakage time of the drive module control terminals of these two rows of pixel circuits to be consistent. By independently controlling the turn-off and turn-on of the switch control unit 110 through different shift registers 500, the N1 leakage time of different rows of pixel circuits can be adjusted, specifically, the N1 leakage time of different rows of pixel circuits can be controlled to be close, thereby improving the flicker difference between the top and bottom of the display panel.

[0072] The switch control unit 110 includes a strobe switch K1, and the optional strobe switch K1 can be an NMOS or a PMOS. The control signal Vout provided by the shift register 500 is a pulse signal. When the control signal Vout is a valid pulse signal, the strobe switch K1 can be turned on, and when the control signal Vout is an invalid pulse signal, the strobe switch K1 can be turned off.

[0073] It can be understood that the above description of the non-display area structure is only one embodiment of the present invention, and the structure of the display panel in the present invention includes but is not limited to the above examples.

[0074] The optional strobe switches are all N-type transistors; or, the strobe switches are all P-type transistors. The same type of strobe switch can reduce the process complexity.

[0075] Figure 10 is the timing diagram of the i-th row pixel circuit provided by the embodiment of the present invention. Combining Figure 2 and Figure 10 as shown, the writing stage further includes a reset stage executed before the data writing stage; after the end of the reset stage or after the end of the data writing stage, the switch control unit 110 switches to turn off. In the reset stage, the reset module 220 is turned on, and the reset signal should be transmitted to the control terminal N1 of the drive module 210 to implement the reset of the N1 node. Then, the switch control unit 110 should ensure to be turned on in the reset stage so that the reset signal can be transmitted to the control terminal N1 of the drive module 210 through the switch control unit 110 and the reset module 220.

[0076] After the end of the reset stage, the reset module 220 is turned off. After the hold stage is turned on, the switch control unit 110 is turned on again. Then, the switch control unit 110 can be switched to the off state after the end of the reset stage. As Figure 10As shown, the turn-off moment of the optional switch control unit 110 during the writing phase can be within the data writing phase; or, in other embodiments, the turn-off moment of the optional switch control unit during the writing phase can overlap with the end moment of the reset phase; or, in other embodiments, it can also be optional as Figure 3 As shown, the turn-off moment of the switch control unit during the writing phase is after the end moment of the data writing phase; or, in other embodiments, it can also be optional as Figure 3 As shown, the turn-off moment of the switch control unit during the writing phase overlaps with the start moment of the light-emitting phase of the writing phase; or, in other embodiments, it can also be optional that the turn-off moment of the switch control unit is within the light-emitting phase during the writing phase. The turn-off moment of the switch control unit 110 during the writing phase is not specifically restricted, as long as it satisfies that the switch control unit 110 is turned on during the reset phase, and the turn-off moment of the switch control unit of the i-th row pixel circuit during the writing phase is earlier than the start moment of the holding phase of the first row pixel circuit.

[0077] Refer to Figure 10 As shown, during some time periods starting from and after the start of the holding phase, the switch control unit remains turned off. For any row of pixel circuits, the switch control unit remains turned off when the holding phase starts, and during some time periods after the start of the holding phase, the switch control unit remains turned off, which can extend the leakage duration of the control terminal N1 of the driving module of the pixel circuit. In this way, by adjusting the turn-on moment of the switch control unit of each row of pixel circuits during the holding phase, the difference in the N1 leakage duration of different rows of pixel circuits can be reduced. The turn-on moment of the switch control unit during the holding phase is not specifically restricted, as long as it satisfies that the turn-on moment of the switch control unit of the i-th row pixel circuit during the holding phase is earlier than the turn-on moment of the switch control unit of the j-th row pixel circuit during the holding phase.

[0078] Refer to Figure 3 As shown, the writing phase further includes a reset phase executed before the data writing phase; in a frame of refreshed image, the end moment of the writing phase of the first row pixel circuit is later than the end moment of the reset phase of the Q-th row pixel circuit. In a frame of refreshed image, the end moment of the writing phase of the first row pixel circuit corresponds to the moment when the reset signal line Vref switches from the first reset signal to the second reset signal. During the reset phase, both the switch control unit and the reset module are turned on, so when the reset signal line Vref switches from the first reset signal to the second reset signal, the reset phase of all pixel circuits should be completed to avoid the second reset signal from performing potential coupling on N1 during the writing phase of the pixel circuit.

[0079] In a frame refresh screen, the pixel circuits of the first to Qth rows are scanned row by row. Therefore, the reset phases of the pixel circuits of the first to Qth rows are executed sequentially. When the reset phase of the Qth row pixel circuit ends, the reset phases of the pixel circuits of the first to Qth rows must have been executed sequentially and completed. By defining that the end time of the writing phase of the first row pixel circuit is later than the end time of the reset phase of the Qth row pixel circuit, it can be ensured that when the reset signal line Vref switches from the first reset signal to the second reset signal, the reset phases of the pixel circuits of the first to Qth rows have all been completed sequentially, avoiding the potential coupling of the second reset signal to N1 during the writing phase of the pixel circuit.

[0080] Figure 11 This is the timing diagram of another frame refresh screen provided by the embodiment of the present invention. Combining Figure 2 and Figure 11 As shown, in a frame refresh screen, the time interval between the end time of the data writing phase in the pixel circuit of the ith row and the end time of the data writing phase in the pixel circuit of the jth row is x1; the time interval between the start time of the switch control unit electrically connected to the pixel circuit of the ith row during the holding phase and the start time of the switch control unit electrically connected to the pixel circuit of the jth row during the holding phase is x2; x1 = x2.

[0081] In this embodiment, in a frame refresh screen, the pixel circuits of the first to Qth rows are scanned and refreshed row by row. The working processes of each row of pixel circuits are similar, all including a sequentially executed reset phase, data writing phase, light emitting phase, and holding phase. Based on this, by designing x1 = x2, the leakage time of N1 in the pixel circuit of the ith row can be made close to or equal to the leakage time of N1 in the pixel circuit of the jth row, thereby improving the problem of large flicker differences between the top and bottom of the display panel.

[0082] Figure 12 This is the timing diagram of another frame refresh screen provided by the embodiment of the present invention. Combining Figure 2 and Figure 12 As shown, in a frame refresh screen, the time interval between the end time of the data writing phase in the pixel circuit of the ith row and the start time of the switch control unit during the holding phase is y1; the time interval between the end time of the data writing phase in the pixel circuit of the jth row and the start time of the switch control unit during the holding phase is y2; y1 = y2.

[0083] In this embodiment, in a frame refresh screen, the pixel circuits of the first to Qth rows are scanned and refreshed row by row. The working processes of each row of pixel circuits are similar, all including a sequentially executed reset phase, data writing phase, light emitting phase, and holding phase. Based on this, by designing y1 = y2, the leakage time of N1 in the pixel circuit of the ith row can be made close to or equal to the leakage time of N1 in the pixel circuit of the jth row, thereby improving the problem of large flicker differences between the top and bottom of the display panel.

[0084] Combined Figure 2 and Figure 3 As shown, optionally in a frame refresh screen, when the pixel circuit in the first row enters the holding stage, the data signal line Vdata switches from the first data signal to a different second data signal. Optionally, both the first data signal and the second data signal are greater than 0V, and the first data signal is less than the second data signal. In this embodiment, Vdata provides a VGH signal greater than the first data signal in the holding stage, which can cause the second data signal VGH to perform potential coupling on the first end N2 of the driving module 210, realize data reset, and improve the flicker at the top and bottom of the display panel.

[0085] An embodiment of the present invention further provides a display device, which includes the display panel described in any of the above embodiments. Optionally, the display panel is an OLED panel, but is not limited thereto. A gating circuit is provided in the display device. The gating circuit includes a plurality of switch control units. The switch control units are electrically connected to one or more rows of pixel circuits. By controlling the opening or closing of the switch control units, the purpose of adjusting the leakage time of N1 of the pixel circuit is achieved. Furthermore, the leakage time of the N1 nodes of each row of pixel circuits can be adjusted to be approximately equal. Then, the N1 of each row of pixel circuits can leak to the same level before being coupled by the second reset signal. Then, the levels after N1 is coupled are relatively close, which can improve the problem of large differences in flicker between the top and bottom.

[0086] It should be understood that various forms of the processes shown above can be used, reordering, adding, or deleting steps. For example, the steps described in the present invention can be executed in parallel, sequentially, or in a different order, as long as the desired results of the technical solution of the present invention can be achieved. This is not limited herein.

[0087] The above specific embodiments do not constitute a limitation to the protection scope of the present invention. Those skilled in the art should understand that various modifications, combinations, sub - combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention shall be included within the protection scope of the present invention.

Claims

1. A display panel, characterized in that, Including: A gating circuit and the first to Qth row pixel circuits arranged in sequence, where Q is a positive integer greater than or equal to 2; The gating circuit includes at least one switch control unit, and one switch control unit is correspondingly electrically connected to at least one row of pixel circuits, and the input end of the switch control unit is connected to the reset signal line; The pixel circuit includes a driving module, a reset module, a data writing module, and a compensation module. The reset module is connected between the output end of the switch control unit and the control end of the driving module. The data writing module is connected between the data signal line and the first end of the driving module. The compensation module is connected between the control end and the second end of the driving module; In a frame of refreshed image, the working process of the pixel circuit includes a writing stage and a holding stage. The writing stage includes a data writing stage and a light emitting stage, and the holding stage does not include the data writing stage; In the data writing stage, the reset module is turned off, and the driving module, the data writing module, and the compensation module are turned on, and the data signal of the data signal line is transmitted to the control end of the driving module; in the light emitting stage, the switch control unit and the reset module are turned off, and the driving module is turned on; in the holding stage, the switch control unit is first kept off and then turned on; The ith row pixel circuit and the jth row pixel circuit are electrically connected to two different switch control units, where both i and j are positive integers and i is less than j; In a frame of refreshed image, when the first row pixel circuit enters the holding stage, the reset signal line switches from the first reset signal to a different second reset signal; the turn-off moment of the switch control unit of the ith row pixel circuit in the writing stage is earlier than the start moment of the holding stage of the first row pixel circuit, and the turn-on moment of the switch control unit of the ith row pixel circuit in the holding stage is earlier than the turn-on moment of the switch control unit of the jth row pixel circuit in the holding stage; both the first reset signal and the second reset signal are less than 0V, and the first reset signal is greater than the second reset signal.

2. The display panel according to claim 1, wherein The gating circuit includes the first to Nth switch control units, and the first to Nth switch control units are sequentially electrically connected to at least N adjacent rows of pixel circuits. The Nth switch control unit is at least correspondingly electrically connected to the Qth row pixel circuit, where N is greater than or equal to 2 and less than Q.

3. The display panel according to claim 1, wherein The gating circuit includes the first to Nth switch control units, and the first to Nth switch control units are sequentially electrically connected to the first to Qth row pixel circuits. The Nth switch control unit is at least correspondingly electrically connected to the Qth row pixel circuit, where N is greater than or equal to 2 and less than Q.

4. The display panel according to claim 1, characterized in that, The gating circuit includes the first to Qth switch control units, and the first to Qth switch control units are sequentially electrically connected to the first to Qth row pixel circuits.

5. The display panel according to any one of claims 2-4, wherein The number of rows of pixel circuits correspondingly electrically connected by one switch control unit is equal.

6. The display panel according to claim 1, wherein Further including: A driving chip; The switch control unit includes a gating switch; The control terminal of the strobe switch is electrically connected to the driving chip, the input terminal of the strobe switch is electrically connected to the reset signal line, and the output terminal of the strobe switch is electrically connected to the input terminal of the reset module of the pixel circuit; The driving chip is used to control the opening and closing of the strobe switch. When it is opened, the reset signal line provides a reset signal to the input terminal of the reset module.

7. The display panel according to claim 1, characterized in that, It further includes: A shift register with multiple levels of cascading; The switch control unit includes a strobe switch, and one level of the shift register corresponds to one switch control unit; The control terminal of the strobe switch is electrically connected to the output terminal of the shift register, the input terminal of the strobe switch is electrically connected to the reset signal line, and the output terminal of the strobe switch is electrically connected to the input terminal of the reset module of the pixel circuit; The shift registers of adjacent switch control units are cascaded; The shift register is used to control the opening and closing of the strobe switch.

8. The display panel according to claim 6 or 7, characterized in that All the strobe switches are N-type transistors; or all the strobe switches are P-type transistors.

9. The display panel according to claim 1, wherein The writing stage further includes a reset stage executed before the data writing stage; After the end of the reset stage or after the end of the data writing stage, the switch control unit switches to the off state.

10. The display panel according to claim 1, wherein During a partial time period starting from and after the start of the holding stage, the switch control unit remains off.

11. The display panel according to claim 1, wherein, The writing stage further includes a reset stage executed before the data writing stage; In a frame of refreshed image, the end time of the writing stage of the pixel circuit in the first row is later than the end time of the reset stage of the pixel circuit in the Qth row.

12. The display panel according to claim 1, wherein In a frame of refreshed image, the time interval between the end time of the data writing stage in the pixel circuit of the ith row and the end time of the data writing stage in the pixel circuit of the jth row is x1; The time interval between the opening time of the switch control unit electrically connected to the pixel circuit of the ith row during the holding stage and the opening time of the switch control unit electrically connected to the pixel circuit of the jth row during the holding stage is x2; x1 = x2.

13. The display panel according to claim 1, wherein In a frame of refreshed image, the time interval between the end time of the data writing stage in the pixel circuit of the ith row and the opening time of the switch control unit during the holding stage is y1; The time interval between the end time of the data writing stage in the pixel circuit of the jth row and the opening time of the switch control unit during the holding stage is y2; y1 = y2.

14. The display panel according to claim 1, wherein, In a frame of refreshed image, when the pixel circuit in the first row enters the holding stage, the data signal line switches from the first data signal to a different second data signal.

15. The display panel according to claim 14, wherein, Both the first data signal and the second data signal are greater than 0V, and the first data signal is less than the second data signal.

16. A display device, characterized in that, It includes a display panel according to any one of claims 1-15.

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