A storage and computing array folding layout method to reduce IR Drop
Through the collapse layout method of the computing array, the layout of the computing unit is optimized, which solves the problems of voltage drop and area waste in the traditional computing array, and improves the calculation accuracy and adaptability.
Patent Information
- Application Number
- CN202210167096.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2022-02-23
- Publication Date
- 2025-08-26
- Estimated Expiration
- 2042-02-23
AI Technical Summary
The voltage drop (IR drop) problem caused by elongated metal lines in traditional memory arrays affects the calculation accuracy. After the array scale is expanded, the number of memory devices connected to the metal lines increases, resulting in uneven current and affecting the calculation accuracy. At the same time, the array layout is difficult to form a standard shape, resulting in waste of area.
The collapse layout method of the memory array is used to cut the memory array into two smaller arrays in the word line direction, and the bit line and source line are connected through the cross line. After cross-merging, a mirror-symmetric layout is formed, and the interconnection method of the memory unit is optimized to reduce the length of the metal line and complex connections.
It effectively reduces the parasitic resistance on the metal wire, reduces voltage drop, improves calculation accuracy and array adaptability, reduces area waste, and ensures the gate consistency of the memory cell.
Smart Images
Figure CN114822627B_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a storage and computing array folding layout method for reducing IR Drop, and belongs to the technical field of integrated circuits. Background Art
[0002] Traditional computer architectures are mostly von Neumann, separating storage and computation. This architecture not only consumes significant energy during data transmission but also causes a mismatch between storage and computation speeds, impacting overall computing speed. In-memory computing integrates storage and computation, breaking the speed and power consumption barriers inherent in storage and computation. Currently, non-volatile devices are commonly used as computational memory units (CIMs). When operating, a computational memory array composed of these devices can change weights by varying the device threshold voltage. Multiplication and accumulation operations are performed by subtracting the output currents of two columns of non-volatile devices operating in the linear region of the array. The difference in the output currents of the two columns, after passing through the current subtraction circuit, represents the result of the computation.
[0003] The non-volatile memory computing unit is made up of memristors, FLASH and other types. The memory computing unit usually includes a data input terminal and a convolution result output terminal. The memory computing array composed of memory computing units usually has multiple ports such as word line WL, bit line BL, and source line SL. The word line WL end serves as the data input terminal of the memory computing unit, the bit line BL end serves as the data output terminal of the memory computing unit, and the source line SL end serves as the source terminal of the memory computing unit; wherein the word line WL end is connected to the wl of multiple memory computing units, the bit line BL end is connected to the bl of multiple memory computing units, and the source line SL is connected to the sl of multiple memory computing units, such as Figure 1 Shown are the storage and computing units that constitute the storage and computing array.
[0004] Since the data input and data output terminals are perpendicular to each other in the connection direction of the storage and computing power supply, the WL and BL terminals of the storage and computing array can serve as the data input and data output terminals of each other. The storage and computing array can be divided into two modes during operation: convolution calculation and weight erase. In the convolution calculation mode, the data input through the driving circuit of the word line WL terminal is used as an operand, and the clamping voltage is applied through the readout circuit of the bit line BL terminal so that the weight data pre-programmed in the single storage and computing device is used as another operand to complete the multiplication operation with the input data of the word line WL. The current formula for the multiplication operation of a single storage and computing device is as follows:
[0005]
[0006] Where I is the current value of the multiplication operation of a single storage device, V DS is the voltage difference between the drain and source of the storage device, V GS is the voltage difference between the gate and source of the storage device, V THis the threshold voltage of the memory device; the read current at the BL end is obtained by adding the current I of all the turned-on memory devices on a BL.
[0007] Furthermore, in the weight erase / write mode, all ports of the memory and computing array need to drive circuits to complete the weight erase / write function of the memory and computing devices. Therefore, a large number of peripheral circuits such as drive circuits and readout circuits are required outside the memory and computing array to realize the in-memory calculation.
[0008] The parasitic resistance on the thin metal wire causes a voltage drop (IRdrop) when the current passes through the metal wire. The voltage drop problem is an important factor affecting the calculation accuracy of the memory computing array. As the scale of the memory computing array expands, the number of memory computing devices connected to the single metal wire at the BL end also increases. The voltage drop problem on the single metal wire at the BL end of the memory computing array is also becoming more and more significant, which will cause the V of all memory computing devices on the single metal wire at the BL end of the memory computing array to drop. DS They cannot be exactly the same, so since the current I of each storage and computing device is different, the read current on the BL line will deviate, which will eventually affect the calculation accuracy of the storage and computing array.
[0009] Taking a 1000×1000 memory and computing array fabricated using SMIC's 55nm process as an example, the pitch between memory and computing devices is 3um, and the memory and computing devices are connected using 0.5um wide metal wires. The sheet resistance of the metal wires provided by the foundry is 0.05Ohm / Sqr, so the parasitic resistance of a BL in the array caused by the metal wire length is 300Ohm. If the read current at the BL end is 50uA, the voltage drop is 15mV, resulting in a V drop of 0.05ohm for the first memory and computing device on the BL line. DS and the V of the last storage device DS The difference is 15mV, which will cause the current I of the storage and computing devices connected to the BL line to be different, and thus cause an error in the read current on the BL line.
[0010] In addition, in the existing storage and computing chip design, as the amount of data increases layer by layer in the storage and computing chip, the scale of the storage and computing arrays at each layer also increases layer by layer. This will lead to the difficulty in forming a standard square chip in the chip layout design due to the large difference in the layout area of the storage and computing arrays, resulting in a large amount of area waste. Summary of the Invention
[0011] In order to solve the above-mentioned problems that currently exist, the present invention optimizes the layout of storage and computing units in large-scale storage and computing arrays, provides a storage and computing array folding layout method that reduces IR Drop, improves the layout shape of the storage and computing array, and effectively alleviates the voltage drop (IR drop) problem on slender metal wires.
[0012] The present invention provides a method for folding the layout of a storage and computing array, and the technical solution is as follows:
[0013] To achieve the above purpose: the present invention provides the following technical solutions: Figure 3 The conventional layout of the m×n scale memory array shown in the figure has the following characteristics: the memory array includes m rows of memory cells and n columns of memory cells. Usually, the data input end and the data output end are perpendicular to each other, so the word line end WL is specified. <1> To WL <m>The data input terminal of the m-row storage unit, the bit line terminal BL <1> To BL <n>The data output terminal of the n-column storage unit, the source line terminal SL <1> To SL <n>It is the source of n columns of storage and computing units.
[0014] The present invention provides a storage and computing array folding layout method for reducing IR Drop, which specifically includes the following steps:
[0015] Step 1: Figure 3 The m×n storage array shown in WL <m 2>It is cut along the WL direction to form two storage and computing arrays of m / 2×n scale;
[0016] Step 2: In the two m / 2×n memory arrays obtained in the above steps, the same bit line BL is connected to the same source line SL by cross-connection, such as Figure 4 As shown;
[0017] Step 3: Figure 4 The two m / 2×n scale memory and computing arrays connected across the lines are cross-merged: the same bit lines BL are merged and led out through a metal line, and the same source lines SL are merged and led out through a metal line;
[0018] Step 4: WL at the word line WL end <1> To WL <m 2>Lead out from the left side of the array, WL<m / 2+1> To WL <m>Lead out from the right side of the array.
[0019] According to a memory and computing array folding layout method for reducing IR Drop of the present invention, in the memory and computing array after cross-merging in step 3, the bit line BL end BL <1> To BL <n>There are two columns of storage and computing units connected to each metal line.
[0020] According to a storage and computing array folding layout method for reducing IR Drop of the present invention, optionally, the method further includes: Figure 5 In the cross-merged array shown, the bit line BL terminal BL <1> To BL <n>The two columns of storage and calculation units connected to the bit line BL where n is an even number are mirror-symmetrical with the metal line of the bit line BL as the center, and the gates of the two adjacent columns of storage and calculation units after the symmetry are interconnected and led out by a word line WL.
[0021] According to the present invention, a storage and computing array folding layout method for reducing IR Drop is provided. Since the same BL and SL in the two arrays connected across the wires in step 2 are far apart, this will cause signal delays between the BL end readout circuit and the drive circuit, resulting in reduced BL end current reading accuracy. Therefore, the two arrays are cross-merged, and the same bit lines BL are merged and led out of a single metal line, and the same source lines SL are merged and led out of a single metal line.
[0022] According to the present invention, a storage and computing array folding layout method for reducing IR Drop is formed after step 4. In the storage and computing array formed, the connection between the WL end and the gate of the storage and computing unit is complex. Frequent jumps of the gate of the storage and computing unit on the connection line of the WL end will cause the consistency of the gates of each storage and computing unit to decrease, increasing the weight error of the storage and computing unit. Therefore, some storage and computing units in the storage and computing array are mirror-symmetrically processed, and the gates of adjacent storage and computing units after the mirror-symmetrical processing can be interconnected, which can ensure the local consistency of the gates of the storage and computing units and reduce the weight error.
[0023] According to the present invention, a storage and computing array folding layout method for reducing IR Drop is compared Figure 3 In the traditional array layout, the scale of the storage and computing array changes from m×n to m / 2×2n. Without changing the array topology, the length and width of the array can be flexibly adjusted, effectively avoiding the situation where m is much larger than n in the middle layer of the storage and computing chip, and the situation where it is difficult to splice into a square layout with smaller-scale storage and computing arrays.
[0024] According to the present invention, a storage and computing array folding layout method for reducing IR Drop is compared Figure 3 In the traditional array layout, the number of memory and computing devices on a metal line at the BL end is reduced from m to m / 2, and the length of the BL metal line will be 1 / 2 of the traditional array layout. (where □ is the square resistance of the metal line in the process of the memory and computing array layout of the present invention) It can be seen that the parasitic resistance will be 1 / 2 of that of the traditional array layout. Furthermore, the IR drop on this BL will be 1 / 2 of that of the traditional array layout.
[0025] The beneficial effects of the present invention are:
[0026] The present invention optimizes the layout of interconnected memory and computing units in a memory and computing array, providing a memory and computing array folding layout method for reducing IRDrop. According to the present invention, the memory and computing array folding layout method for reducing IR Drop can reduce the column length of the memory and computing array by 50% while maintaining the original interconnection relationship between the memory and computing units in the memory and computing array. It also reduces the routing distance between the drain of the memory and computing device and the driving circuit and readout circuit at the BL end of the memory and computing array by 50%, thereby reducing the parasitic resistance of the long-distance metal routing by 50%. This can reduce the IR drop caused by the long metal wiring at the BL end by 50% in convolution computing mode.
[0027] Furthermore, according to a storage and computing array folding layout method for reducing IR Drop of the present invention, some storage and computing units in the storage and computing array are mirror-symmetrically processed, and the gates of adjacent storage and computing units after the mirror-symmetrical layout can be interconnected to ensure the local consistency of the gates of the storage and computing units.
[0028] In addition, the layout method of the present invention improves the overall shape of the storage and computing array layout, enhances the adaptability of storage and computing arrays of different sizes, and greatly reduces area waste during array layout. BRIEF DESCRIPTION OF THE DRAWINGS
[0029] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.
[0030] Figure 1 The storage and computing unit constituting the storage and computing array of the present invention;
[0031] Figure 2 It is a flow chart of a storage and computing array folding layout method for reducing IR Drop according to the present invention;
[0032] Figure 3 The traditional layout of the m×n storage and computing array;
[0033] Figure 4 A schematic diagram of a storage and computation array formed after steps one and two according to the stacking method of the present invention;
[0034] Figure 5 Schematic diagram of a storage and computation array formed after step three according to the stacking method of the present invention;
[0035] Figure 6 Schematic diagram of a storage and computing array formed after mirror symmetry according to the stacking method of the present invention;
[0036] Figure 7 A schematic diagram of a 1024×256 storage and computation array according to an embodiment of the present invention;
[0037] Figure 8 The diagram of the 1024×256 storage and computation array formed after steps one and two is shown below.
[0038] Figure 9 The following is a schematic diagram of two 512×256 storage and computing arrays formed after step 3;
[0039] Figure 10 This is a schematic diagram of the storage and computing array after cross-merging and further mirroring. DETAILED DESCRIPTION
[0040] To make the objectives, technical solutions and advantages of the present invention more clear, the embodiments of the present invention will be described in further detail below with reference to the accompanying drawings.
[0041] Example 1:
[0042] This embodiment provides a storage and computing array folding layout method to reduce IR Drop, combined with Figure 7 As shown, the memory computing array has the following features: the memory computing unit is a floating gate memory computing tube, the memory computing array includes 1024 rows of memory computing units and 256 columns of memory computing units, and the sub-line WL end WL <1> To WL <1024> Connected to the gate of 1024 rows of storage units, bit line BL terminal BL <1> To BL <256> Connected to the drain of 256 columns of storage and calculation units, the source line SL end SL <1> To SL <256> Connected to the sources of 256 columns of storage and computing units respectively.
[0043] The memory and computation array described in this example has a five-fold difference in row and column length in the actual layout. Adding driver and readout circuits to the BL, SL, and WL blocks results in an irregular overall shape, making it difficult to adapt to smaller arrays. Therefore, the following steps can be used to appropriately modify the memory and computation array shape without changing the original interconnection relationship between the memory and computation units.
[0044] Step 1: Figure 7 The 1024×256 scale storage array shown in WL <512> It is cut along the WL direction to form two 256×512 storage and computing arrays.
[0045] Step 2: In the two 512×256 memory arrays, the same BL and the same SL are as follows: Figure 8 The cross-line connection shown in the figure; in the two arrays connected by cross-line, the distance between the same BL and SL is very far, which will cause signal delay between the BL end readout circuit and the drive circuit, resulting in a decrease in the accuracy of BL end current reading;
[0046] Step 3: Figure 8 The two 512×256 memory and computation arrays shown are cross-merged. The same BL merge is led out by a metal line, and the same SL merge is led out by a metal line.
[0047] Step 4: WL <1> To WL <512> Lead out from the left side of the array, WL <513> To WL <1024> Lead out from the right side of the array, the array layout is as follows Figure 9 shown.
[0048] After the array layout is formed through the above steps, the width of the storage and computing array in the column direction is doubled, and the distance between the driving circuit and the readout circuit at the BL end and the drain of each storage and computing unit is reduced by 1 / 2, which can reduce the voltage drop on the BL metal line.
[0049] However, the disadvantage of this layout is that in the formed storage and computing array, the connection between the WL end and the gate of the storage and computing unit is complex. Frequent jumping of the gate of the storage and computing unit on the connection line of the WL end will cause the consistency of the gates of each storage and computing unit to decrease, increasing the weight w error of the storage and computing unit.
[0050] According to this embodiment, the above Figure 9 BL in the storage and computing array layout <1> To BL <256> The storage and computing units in the even columns are mirror-symmetrical with the BL metal line as the center, and the following is obtained: Figure 10 The array layout shown, in which the gates of adjacent storage and computing units can be interconnected, can improve the consistency of the gates of the storage and computing units in the storage and computing array and reduce weight errors.
[0051] In summary, the folding layout method for a storage and computing array that reduces IR Drop described in this embodiment can reduce the column length of the storage and computing array by 50% while ensuring the original interconnection relationship of the storage and computing units, and reduce the routing distance between the drain of the storage and computing device and the driving circuit and readout circuit at the BL end of the storage and computing array by 50%. The parasitic resistance of the long-distance metal routing is reduced by 50%, thereby reducing the IR drop caused by the long metal wire at the BL end in the convolution computing mode by 50%. In addition, the layout method of the present invention improves the overall shape of the storage and computing array layout, improves the adaptability of storage and computing arrays of different sizes, and significantly reduces the area waste during array layout.
[0052] Some steps in the embodiments of the present invention may be implemented using software, and the corresponding software program may be stored in a readable storage medium, such as a CD or a hard disk.
[0053] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.< / n> < / n> < / m> < / m> < / m> < / n> < / n> < / m>
Claims
1. A storage and computing array folding layout method for reducing IR Drop, characterized in that: The memory computing array includes m rows of memory computing units and n columns of memory computing units, each memory computing unit is composed of a non-volatile memory computing device; the word line terminal WL of the memory computing array <1> To WL <m>They are connected to the storage and calculation units of rows 1 to m respectively, which are the data input terminals of the storage and calculation array, and the bit line terminals BL of the storage and calculation array are connected to the storage and calculation units of rows 1 to m respectively, which are the data input terminals of the storage and calculation array. <1> To BL <n>The data output terminals of the storage and calculation array are connected to the storage and calculation units of columns 1 to n respectively. The source line terminals SL of the storage and calculation array are connected to the storage and calculation units of columns 1 to n respectively. <1> To SL <n>The data input terminals are connected to the source terminals of the storage and computing units in columns 1 to n, respectively, and the data input terminals and the data output terminals are perpendicular to each other in the connection direction. The method comprises the following steps:< / n> < / n> < / m> Step 1: Place the m×n memory array at the word line end WL <m 2> It is cut along the word line WL direction to form two m / 2×n memory and calculation arrays;< / m> Step 2: Cross-connect the same bit line BL and the same source line SL in the two m / 2×n memory arrays obtained in Step 1; Step 3: Cross-merge the two m / 2×n memory / calculation arrays connected across the wires: merge the same bit lines BL and lead them out through one metal line; merge the same source lines SL and lead them out through one metal line; Step 4: In the cross-merged memory array, the WL at the end of the word line WL <1> To WL <m 2>Leading out from one side of the array, the word line WL end WL<m / 2+1> To WL <m> Lead out from the other side of the array;< / m> < / m> In the memory array after cross-merging in step 3, the bit line BL terminal BL <1> To BL <n> There are two columns of storage and computing units connected to each metal wire;< / n> The method further comprises: The bit line BL terminal BL <1> To BL <n> In the figure, two columns of storage and calculation units connected to the bit line BL where n is an even number are mirror-symmetrical with the bit line BL as the center, and the gates of the two adjacent columns of storage and calculation units after the symmetrical layout are interconnected and led out by a word line WL.< / n> 2. The method for reducing IR Drop by folding a storage and computing array according to claim 1, characterized in that: In the mirror-symmetric storage and computing array, the gates of two adjacent columns of storage and computing units are connected by the same word line WL, which can ensure the local consistency of the gates of the storage and computing units and reduce weight errors.
3. A storage and computing array folding layout method for reducing IR Drop according to claim 1 or 2, characterized in that: In the memory-computing array after the folded layout, the number of memory-computing devices on a metal line at the BL end is reduced from m to m / 2, and the length of the metal line is reduced by 1 / 2, thereby reducing the voltage drop of the metal line at the BL end and improving the readout accuracy of the readout current at the BL end.
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