Reference voltage determination method, device, computer equipment and storage medium

Abstract

The embodiments of the present application provide a reference voltage determination method, device, computer equipment, and storage medium, relating to the field of memory technology. The reference voltage determination method is applied to a random access memory, performs data write training on the random access memory according to each initial reference voltage, obtains each data write delay window corresponding to each initial reference voltage; determines a starting reference voltage corresponding to the starting data write delay window, an ending reference voltage corresponding to the ending data write delay window, and an optimal reference voltage corresponding to the maximum data write delay window, which are greater than a preset data write delay window in multiple data write delay windows; and determines a target reference voltage corresponding to the random access memory based on the starting reference voltage, the ending reference voltage, and the optimal reference voltage. This method solves the technical problem of the poor reliability of the current DDR4 memory reference voltage in traditional technology, and achieves the technical effect of improving the reliability of the DDR4 memory reference voltage.

Description

Technical Field

[0001] The present application relates to the field of memory technology, and in particular, to a reference voltage determination method, apparatus, computer equipment, and storage medium. Background Art

[0002] The current training method for DDR4 (Double Data Rate 4, fourth-generation double-rate synchronous dynamic random access memory) reference voltage is based on the interface signals and steps specified in the Write DQ Training (data write training) in the DFI (DDR PHY Interface) 4.0 protocol, and is implemented using the DDR controller and PHY (physical layer).

[0003] In data reading and writing, the read data select signal (DQS signal) is generally used as a clock signal to collect the read and write data (DQ signal) to achieve the purpose of reading and writing. Data write training refers to scanning the delay of the data write delay chain built into the physical layer to obtain the delay window for normal reading and writing data, such as Figure 1 The area between the left boundary (minimum delay) and the right boundary (maximum delay) in the data write delay window is the data write delay window under the current reference voltage. The midpoint of the left and right boundaries is the optimal delay, and the reference voltage corresponding to the optimal delay is the optimal reference voltage. This optimal reference voltage is generally used as the actual reference voltage. However, the optimal reference voltage determined in this way is generally easy to shift to one side, such as close to the left or right boundary. In actual operation, if the actual reference voltage jitters, it is easy to jump out of the delay window, resulting in data write errors.

[0004] Therefore, the reliability of the current DDR4 memory reference voltage is poor. Summary of the Invention

[0005] Embodiments of the present application provide a reference voltage determination method, apparatus, computer device, and storage medium.

[0006] A first aspect of an embodiment of the present application provides a reference voltage determination method, which is applied to a random access memory, and includes:

[0007] Performing data writing training on the random access memory according to each initial reference voltage to obtain each data writing delay window corresponding to each initial reference voltage;

[0008] Determine a starting reference voltage corresponding to a starting data write delay window, a termination reference voltage corresponding to a termination data write delay window, and an optimal reference voltage corresponding to a maximum data write delay window, which are greater than a preset data write delay window among the multiple data write delay windows;

[0009] The target reference voltage corresponding to the random access memory is determined according to the starting reference voltage, the ending reference voltage and the optimal reference voltage.

[0010] In an optional embodiment of the present application, determining a starting reference voltage corresponding to a starting data write delay window, an ending reference voltage corresponding to an ending data write delay window, and an optimal reference voltage corresponding to a maximum data write delay window, which are greater than a preset data write delay window, among multiple data write delay windows, includes:

[0011] Determine an initial reference voltage corresponding to a first data write delay window greater than a preset data write delay window in the plurality of data write delay windows as a starting reference voltage;

[0012] Determine an initial reference voltage corresponding to a last data write delay window greater than a preset data write delay window in the plurality of data write delay windows as a termination reference voltage;

[0013] An initial reference voltage corresponding to a maximum data write delay window among the multiple data write delay windows is determined as an optimal reference voltage.

[0014] In an optional embodiment of the present application, determining an initial reference voltage corresponding to a maximum data write delay window among a plurality of data write delay windows as an optimal reference voltage includes:

[0015] Determine whether the current data write delay window corresponding to the current initial reference voltage is greater than the historical maximum data write delay window corresponding to the historical best reference voltage;

[0016] If the current data write delay window corresponding to the current initial reference voltage is greater than the historical maximum data write delay window, the optimal reference voltage is updated to the current initial reference voltage.

[0017] In an optional embodiment of the present application, determining whether a current data write delay window corresponding to a current initial reference voltage is greater than a historical maximum data write delay window corresponding to a historical optimal reference voltage includes:

[0018] Obtaining the jump information of the current data write delay window corresponding to the current initial reference voltage sent by the physical layer in the random access memory; wherein the jump information is used to indicate whether the size of the data write delay window has changed;

[0019] It is determined according to the jump information whether the current data write delay window is greater than the historical maximum data write delay window corresponding to the historical best reference voltage.

[0020] In an optional embodiment of the present application, before determining the starting reference voltage corresponding to the starting data write delay window, the ending reference voltage corresponding to the ending data write delay window, and the optimal reference voltage corresponding to the maximum data write delay window, which are greater than the preset data write delay window in the multiple data write delay windows, the method further includes:

[0021] Obtaining scan result information of the delay chain delay at the current initial reference voltage sent by the physical layer in the random access memory; wherein the scan result information is used to indicate the relative size of the current data write delay window and the preset data write delay window;

[0022] The relative size of the current data write delay window and the preset data write delay window is determined according to the scan result information.

[0023] In an optional embodiment of the present application, determining a target reference voltage corresponding to the random access memory according to the starting reference voltage, the ending reference voltage, and the optimal reference voltage includes:

[0024] Determine, according to the power stability parameters of the memory chips in the random access memory, a first weight coefficient corresponding to the starting reference voltage and the ending reference voltage and a second weight coefficient corresponding to the optimal reference voltage;

[0025] A target reference voltage corresponding to the random access memory is determined according to the starting reference voltage, the ending reference voltage, the first weight coefficient, the optimal reference voltage and the second weight coefficient.

[0026] In an optional embodiment of the present application, determining a target reference voltage corresponding to the random access memory according to the starting reference voltage, the ending reference voltage, the first weight coefficient, the optimal reference voltage, and the second weight coefficient includes:

[0027] Determine a median reference voltage according to the starting reference voltage and the ending reference voltage;

[0028] Determine a first weight coefficient corresponding to a median reference voltage and a second weight coefficient corresponding to an optimal reference voltage according to power supply stability parameters of memory chips in a random access memory;

[0029] A target reference voltage corresponding to the random access memory is determined according to the median reference voltage, the first weight coefficient, the optimal reference voltage and the second weight coefficient.

[0030] According to a second aspect of an embodiment of the present application, a reference voltage determination device is provided, which is applied to a random access memory. The reference voltage determination device includes:

[0031] A training module is used to perform data writing training on the random access memory according to each initial reference voltage to obtain each data writing delay window corresponding to each initial reference voltage;

[0032] A first determining module is configured to determine a starting reference voltage corresponding to a starting data write delay window, a termination reference voltage corresponding to a termination data write delay window, and an optimal reference voltage corresponding to a maximum data write delay window, among multiple data write delay windows that are greater than a preset data write delay window;

[0033] The second determining module is configured to determine a target reference voltage corresponding to the random access memory according to the starting reference voltage, the ending reference voltage and the optimal reference voltage.

[0034] According to a third aspect of an embodiment of the present application, a computer device is provided, comprising: a memory and a processor, wherein the memory stores a computer program, and the processor implements the steps of any of the above methods when executing the computer program.

[0035] A fourth aspect of the embodiments of the present application provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program implements the steps of any of the above methods when executed by a processor.

[0036] The above-mentioned reference voltage determination method first performs data writing training on the random access memory according to each initial reference voltage to obtain each data write delay window corresponding to each initial reference voltage, and then determines the starting reference voltage corresponding to the starting data write delay window, the ending reference voltage corresponding to the ending data write delay window, and the optimal reference voltage corresponding to the maximum data write delay window, which are greater than the preset data write delay window in multiple data write delay windows. Finally, the target reference voltage that can be used for actual use is comprehensively determined based on the starting reference voltage, the ending reference voltage and the optimal reference voltage. The data write delay window corresponding to the target reference voltage is larger, and the corresponding reference voltage upward jitter range and downward jitter threshold range are relatively large. In actual application, the actual reference voltage is not easy to jump out of the data write delay window, and the actual data reading and writing are more stable, which solves the technical problem of poor reliability of the current DDR4 memory reference voltage in traditional technology and achieves the technical effect of improving the reliability of the DDR4 memory reference voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0038] Figure 1 A schematic diagram of a reading delay window in a reference voltage determination method provided in one embodiment of the present application;

[0039] Figure 2The corresponding relationship between the initial reference voltage and the delay in the reference voltage training process provided by one embodiment of the present application Figure 1 ;

[0040] Figure 3 The corresponding relationship between the initial reference voltage and the delay in the reference voltage training process provided by one embodiment of the present application Figure 2 ;

[0041] Figure 4 The corresponding relationship between the initial reference voltage and the delay in the reference voltage training process provided by one embodiment of the present application Figure 3 ;

[0042] Figure 5 A flowchart of a method for determining a reference voltage according to an embodiment of the present application is provided;

[0043] Figure 6 The corresponding relationship between the initial reference voltage and the delay in the reference voltage training process provided by one embodiment of the present application Figure 4 ;

[0044] Figure 7 A flowchart of a method for determining a reference voltage according to an embodiment of the present application is provided;

[0045] Figure 8 A schematic flow chart of a reference voltage determination method provided in one embodiment of the present application;

[0046] Figure 9 A flowchart of a method for determining a reference voltage according to an embodiment of the present application is provided;

[0047] Figure 10 A flowchart of a method for determining a reference voltage according to an embodiment of the present application is provided;

[0048] Figure 11 A flowchart of a method for determining a reference voltage according to an embodiment of the present application is provided;

[0049] Figure 12 A flowchart of a method for determining a reference voltage according to an embodiment of the present application is provided;

[0050] Figure 13 A schematic diagram of the structure of a reference voltage determination device provided in one embodiment of the present application;

[0051] Figure 14 A schematic diagram of the computer device structure provided for one embodiment of the present application. DETAILED DESCRIPTION

[0052] In the process of implementing the present application, the inventors discovered that the reliability of the current DDR4 memory reference voltage is relatively poor.

[0053] In response to the above problems, an embodiment of the present application provides a method for determining a reference voltage. First, data write training is performed on the random access memory according to each initial reference voltage to obtain each data write delay window corresponding to each initial reference voltage. Then, a starting reference voltage corresponding to the starting data write delay window, an ending reference voltage corresponding to the ending data write delay window, and an optimal reference voltage corresponding to the maximum data write delay window are determined, which are greater than the preset data write delay window. Finally, a target reference voltage that can be used for actual use is comprehensively determined based on the starting reference voltage, the ending reference voltage and the optimal reference voltage. The data write delay window corresponding to the target reference voltage is larger, and the upward jitter range and the downward jitter threshold range of the corresponding reference voltage are relatively large. In actual applications, the actual reference voltage is not easy to jump out of the data write delay window, and the actual data reading and writing are more stable. This solves the technical problem of poor reliability of the current DDR4 memory reference voltage in traditional technology, and achieves the technical effect of improving the reliability of the DDR4 memory reference voltage.

[0054] The solutions in the embodiments of the present application can be implemented using various computer languages, for example, the object-oriented programming language Java and the interpreted scripting language JavaScript.

[0055] In order to make the technical solutions and advantages of the embodiments of the present application more clearly understood, the exemplary embodiments of the present application are further described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present application, and are not an exhaustive list of all the embodiments. It should be noted that the embodiments and features in the embodiments of the present application can be combined with each other unless they conflict.

[0056] The following briefly describes the application environment of the reference voltage determination method provided in the embodiment of the present application:

[0057] The reference voltage determination method provided in the embodiments of the present application is applied to a random access memory (RAM), which can be any of the DDR4 and DDR5 series, and is not specifically limited in the embodiments of the present application. The following description uses DDR4 memory as an example. DDR4 memory generally includes a physical layer, a controller, and memory chips.

[0058] Among them, the physical layer is used to determine the change of the delay window during the training process through the training results of the controller. Since there is no signal in the signals specified by the DFI protocol that can indicate the specific size of the delay window, the physical layer generally uses dfi_wdqlvl_result (the interface signal of the data write delay window change) to determine whether the data write delay window has changed relative to the previous data write delay window, and records it, and feeds the recorded results back to the controller. For example, when the delay window increases, the dfi_wdqlvl_result interface signal is pulled high (set to the character "1"); when the delay window decreases, the dfi_wdqlvl_result interface signal is pulled low (set to the character "0").

[0059] When the controller detects that the dfi_wdqllv_result interface signal is pulled high ("1"), it updates the target reference voltage to the reference voltage corresponding to the current data write delay window; otherwise, it does not update. Figure 2 In the example, if the data write delay window of vref4 is greater than the data write delay window of vref3, the target reference voltage is updated to vref4, and so on, until the training of each reference voltage is completed.

[0060] The controller is used to generate data read commands, data write commands, and perform data write training (Write DQ training) based on various reference voltages. Figure 2 The controller writes data into the training results based on each reference voltage (vref0, vref1, ..., vref8) in sequence. The horizontal axis is the delay and the vertical axis is the reference voltage. Figure 2 We can clearly see that the minimum delay and maximum delay of vref0 and vref8 are equal, and the corresponding delay window is 0. The difference between the minimum delay and maximum delay of vref4 is the largest, and the corresponding delay window is the largest. Therefore, we generally determine vref4 as the actual reference voltage. After exiting the training mode and entering the working mode, if the actual reference voltage fluctuates within the range of vref1 to vref7, the data can be written into the DDR4 memory normally.

[0061] However, the following situations may occur during actual use of the reference voltage:

[0062] See Figure 3 , Figure 3 The data write delay window corresponding to vref6 is the largest, and vref6 is determined as the target reference voltage. However, once the reference voltage in the actual circuit fluctuates upward by two units, exceeding vref8, the data write delay window is completely invalid, resulting in data write failure in the DDR4 memory. Similarly, see Figure 4, Figure 4 The data write delay window corresponding to vref2 is the largest, and vref2 is determined as the target reference voltage. However, once the reference voltage in the actual circuit jitters down by two units and jitters below vref0, the data write delay window will be completely invalid, resulting in the failure of DDR4 memory data writing.

[0063] The following uses the controller mentioned above as the execution subject, and applies the reference voltage determination method to the controller in the DDR4 memory as an example to illustrate how to train the reference voltage to obtain the target reference voltage. Figure 5 The reference voltage determination method provided in the embodiment of the present application includes the following steps 501 to 503:

[0064] Step 501: The controller performs data writing training on the random access memory according to each initial reference voltage to obtain each data writing delay window corresponding to each initial reference voltage.

[0065] For example, the initial reference voltages include vref0, vref1, ..., vref8. When the controller performs data write training on the DDR4 memory, the corresponding data write delay windows under each initial reference voltage are T0, T1, ..., T8 respectively. The specific data write training method can be: drive the memory particles to work with each initial reference voltage, first configure the delay chain to zero delay, write the pre-configured data to the pre-configured target address, and then read the data from the same address after the data is written. If the read data and the written data are exactly the same, it means that the current delay can write data normally. Then gradually increase the delay of the delay chain, repeat the above writing and reading until the delay chain scan is completed, so as to obtain the minimum delay and maximum delay that can normally write data under the current initial reference voltage. By calculating the difference between the minimum delay and the maximum delay, the corresponding data write delay window can be obtained. Of course, the method of determining the data write delay window includes but is not limited to this, and will not be exhaustive here.

[0066] Step 502: The controller determines a starting reference voltage corresponding to the starting data write delay window, an ending reference voltage corresponding to the ending data write delay window, and an optimal reference voltage corresponding to the maximum data write delay window, which is greater than the preset data write delay window in multiple data write delay windows.

[0067] See Figure 6 For example, the above initial reference voltages vref0, vref1, ..., vref8 correspond to different delay windows. If the preset data writing delay window is t1-t2, then Figure 6As can be seen in the figure, the data write delay windows of vref0, vref1, and vref8 are all smaller than the preset delay window, and the remaining ones are the data write delay windows corresponding to vref2, vref3, vref4, vref5, vref6, and vref7. In the first case, if training is performed in the order from vref0 to vref8, then the starting data write delay window in the six data write delay windows is the data write delay window corresponding to vref2, that is, the starting reference voltage is vref2; the ending data write delay window is the data write delay window corresponding to vref7, that is, the ending reference voltage is vref7; the maximum data write delay window is the data write delay window corresponding to vref2, that is, the optimal reference voltage is vref2. In the first case, if training is performed in the order from vref8 to vref0, then the starting data write delay window in the six data write delay windows is the data write delay window corresponding to vref7, that is, the starting reference voltage is vref7; the ending data write delay window is the data write delay window corresponding to vref2, that is, the ending reference voltage is vref2; and the maximum data write delay window is the data write delay window corresponding to vref2, that is, the optimal reference voltage is vref2. It should be explained that the preset data write delay window can be set according to actual conditions and is not specifically limited in this embodiment. When the preset data write delay window is 0, it is equivalent to not selecting each data write delay window, and the size comparison and reference voltage determination are directly based on all data write delay windows.

[0068] Step 503: The controller determines a target reference voltage corresponding to the random access memory according to the starting reference voltage, the ending reference voltage, and the optimal reference voltage.

[0069] The controller determines a practical target reference voltage based on the above-obtained starting reference voltage, ending reference voltage, and optimal reference voltage. The target reference voltage can be determined by taking the average value or configuring different weight coefficients, etc., which can take into account the three reference voltages. This embodiment does not specifically limit this.

[0070] The reference voltage determination method of the embodiment of the present application first performs data writing training on the random access memory according to each initial reference voltage to obtain each data writing delay window corresponding to each initial reference voltage, and then determines the starting reference voltage corresponding to the starting data writing delay window, the ending reference voltage corresponding to the ending data writing delay window, and the optimal reference voltage corresponding to the maximum data writing delay window, which are greater than the preset data writing delay window in multiple data writing delay windows. Finally, the target reference voltage that can be used for actual use is comprehensively determined based on the starting reference voltage, the ending reference voltage and the optimal reference voltage. The data writing delay window corresponding to the target reference voltage is larger, and the upward jitter range and the downward jitter threshold range of the corresponding reference voltage are relatively large. In actual applications, the actual reference voltage is not easy to jump out of the data writing delay window, and the actual data reading and writing are more stable. This solves the technical problem of poor reliability of the current DDR4 memory reference voltage in traditional technology, and achieves the technical effect of improving the reliability of the DDR4 memory reference voltage.

[0071] See Figure 7 In an optional embodiment of the present application, the above step 502, in which the controller determines a starting reference voltage corresponding to the starting data write delay window, an ending reference voltage corresponding to the ending data write delay window, and an optimal reference voltage corresponding to the maximum data write delay window, which are greater than the preset data write delay window, among the multiple data write delay windows, includes the following steps 701 to 703:

[0072] Step 701: The controller determines an initial reference voltage corresponding to the first data write delay window greater than a preset data write delay window among multiple data write delay windows as a starting reference voltage.

[0073] Step 702: The controller determines an initial reference voltage corresponding to the last data write delay window greater than a preset data write delay window among the multiple data write delay windows as a termination reference voltage.

[0074] Step 703: The controller determines an initial reference voltage corresponding to a maximum data write delay window among a plurality of data write delay windows as an optimal reference voltage.

[0075] The initial reference voltage refers to the reference voltage corresponding to the first data write delay window greater than the preset data write delay window during the training process, for example Figure 6 The termination reference voltage is the reference voltage corresponding to the first data write delay window greater than the preset data write delay window during the training process, for example Figure 6 vref7 in the training process; the optimal reference voltage is greater than the preset data write delay window during training, and greater than the reference voltage corresponding to all other data write delay windows, such as Figure 6 vref2 in.

[0076] The embodiment of the present disclosure determines the starting reference voltage based on the preset data write delay window, which can screen out a large amount of useless data in the early stage of training, improve the efficiency of subsequent data processing, and further improve the efficiency of determining the reference voltage of the present application.

[0077] In the embodiment of the present application, each initial reference voltage may be trained sequentially, and then the starting reference voltage, the ending reference voltage, and the optimal reference voltage may be determined based on the obtained training results. Alternatively, the optimal reference voltage may be determined in real time after each initial reference voltage training is completed. For example:

[0078] See Figure 8 In an optional embodiment of the present disclosure, the above step 703, in which the controller determines the initial reference voltage corresponding to the maximum data write delay window among the multiple data write delay windows as the optimal reference voltage, includes the following steps 801-802:

[0079] Step 801: The controller determines whether the current data write delay window corresponding to the current initial reference voltage is greater than the historical maximum data write delay window corresponding to the historical best reference voltage.

[0080] The historical best reference voltage refers to the reference voltage with the largest data write delay window among all currently trained initial reference voltages. Assuming that the data write delay windows corresponding to vref0 and vref1 are both larger than the preset data write delay window, when training vref2, the largest data write delay window corresponding to vref0 and vref1 is vref1. The controller then determines the relative size between the current data write delay window corresponding to vref2 and the historical maximum data write delay window corresponding to the historical best reference voltage vref1.

[0081] Step 802: If the current data write delay window corresponding to the current initial reference voltage is greater than the historical maximum data write delay window, the controller updates the optimal reference voltage to the current initial reference voltage.

[0082] For example, the above Figure 6 In the example, if the current data write delay window corresponding to vref2 is greater than the historical maximum data write delay window corresponding to the historical best reference voltage vref1, then the best reference voltage is updated to the current initial reference voltage vref2. Similarly, the best reference voltage is continuously updated during the training process. After the training is completed, if Figure 6, the starting reference voltage is vref2, the ending reference voltage is vref7, the optimal reference voltage is vref2, and vref2-vref7 constitutes the reference voltage window of the embodiment of the present application.

[0083] On the one hand, the embodiment of the present application determines the optimal reference voltage in real time during the training process based on each initial reference voltage, which can greatly improve the timeliness of the reference voltage determination, and thus improve the timeliness of the target reference voltage; at the same time, it can prevent the training interruption caused by program failure, data disorder, etc., and can also obtain a better optimal reference voltage for determining the target reference voltage based on the current training progress, as well as the starting reference voltage and the ending reference voltage, further improving the stability and reliability of the reference voltage determination provided by the embodiment of the present application; on the other hand, the embodiment of the present application determines the reference voltage in real time by setting the preset data write delay window, which can screen out a large amount of useless data in the early stage, improve the efficiency of subsequent data processing, and thus improve the efficiency of the reference voltage determination of the present application; on the third hand,

[0084] In a specific embodiment of the present application, the training process of the starting reference voltage, the ending reference voltage and the optimal reference voltage in the above steps is further described:

[0085] Table (1)

[0086]

[0087]

[0088] Please continue to see Figure 6 If the preset data write delay window is t1-t2, the training results for each reference voltage are as shown in Table (1). When training for the first time, regardless of whether the data write delay window corresponding to the first initial reference voltage Vref0 is larger than the preset data write delay window, the size, and whether it is larger than the preset reading delay, the initial reference voltage of the first training can be determined as the starting reference voltage, the ending reference voltage, and the optimal reference voltage. Then, based on the training process, the starting reference voltage, the ending reference voltage, and the optimal reference voltage are continuously updated in real time. For example, the first starting reference voltage that is larger than the preset data write delay window is Vref2; the ending reference voltage in each training is the current initial reference voltage currently being trained; in each training process, the data write delay window of the current reference voltage is compared with the data write delay window of the previous reference voltage. If it is larger, the optimal reference voltage is updated to the current reference voltage; otherwise, the original optimal reference voltage remains unchanged.

[0089] See Figure 9In an optional embodiment of the present application, the above step 801, in which the controller determines whether the current data write delay window corresponding to the current initial reference voltage is greater than the historical maximum data write delay window corresponding to the historical optimal reference voltage, includes the following steps 901-902:

[0090] Step 901: The controller obtains the transition information of the current data write delay window corresponding to the current initial reference voltage, which is sent by the physical layer in the random access memory.

[0091] The transition information indicates whether the size of the data write delay window has changed. Based on the application environment described above, the physical layer determines and records the current delay window size based on the dfi_wdqlvl_result (the interface signal indicating the data write delay window change) and sends the dfi_wdqlvl_result (the interface signal indicating the data write delay window change) as the transition information to the controller.

[0092] Step 902: The controller determines whether the current data write delay window is greater than the historical maximum data write delay window corresponding to the historical best reference voltage according to the jump information.

[0093] Based on the obtained jump information, the controller determines whether the current data write delay window is greater than the historical maximum data write delay window corresponding to the historical best reference voltage. If the dfi_wdqlvl_result (the interface signal for the change of the data write delay window) is "1", it means that the current data write delay window is greater than the historical maximum data write delay window corresponding to the historical best reference voltage, that is, the current data write delay window has increased; on the contrary, if the dfi_wdqlvl_result (the interface signal for the change of the data write delay window) is "0", it means that the current data write delay window is smaller than the historical maximum data write delay window corresponding to the historical maximum data write delay window, that is, the current data write delay window has decreased.

[0094] Data training

[0095] The embodiment of the present application is based on the jump information of the data write delay window corresponding to the current initial reference voltage sent by the physical layer to determine whether the current data write delay window is greater than the historical maximum data write delay window corresponding to the historical best reference voltage. There is no need to determine the specific delay value, which greatly saves computing resources and improves the efficiency of reference voltage determination. At the same time, there is no need to perform a large amount of calculations, and the performance requirements for the controller and the physical layer are also reduced accordingly. It can be fully implemented using an ordinary controller, which greatly reduces the hardware cost.

[0096] See Figure 10In an optional embodiment of the present application, in step 502, before the controller determines that the starting reference voltage corresponding to the starting data write delay window, the ending reference voltage corresponding to the ending data write delay window, and the optimal reference voltage corresponding to the maximum data write delay window are greater than the preset data write delay window, the method further includes steps 1001 and 1002:

[0097] Step 1001: The controller obtains scan result information of the delay chain delay at the current initial reference voltage sent by the physical layer in the random access memory.

[0098] The scan result information indicates the relative size of the current data write delay window to the preset data write delay window. This scan result information refers to the delay value determined by the scanner for the delay chain. For example, it can be a real-time scan reading, or it can be represented based on the identifier of the dfi_wdqlvl_resp (delay response signal), which is the write data training response, as the scan result information. This embodiment does not specifically limit this.

[0099] Step 1002: The controller determines the relative size of the current data write delay window and the preset data write delay window according to the scan result information.

[0100] Based on the two methods above, if real-time scanning and reading are performed, the relative size of the two can be directly determined from the reading results. If the identification character of the dfi_wdqlvl_resp (delay response signal) is used as the scanning result information, then if the identification character is 2'b10, it means that the current delay is increasing relative to the previous delay, and if the identification character is 2'b01, it means that the current delay is decreasing relative to the previous delay.

[0101] The embodiment of the present application determines the relative size of the current data write delay window and the preset data write delay window based on the scanning result information of the delay chain delay sent by the physical layer under the current initial reference voltage. The judgment method is simple and fast, and there is no need to determine the specific delay value, which greatly saves computing resources and improves the efficiency of reference voltage determination. At the same time, there is no need to perform a large amount of calculations, and the performance requirements for the controller and the physical layer are also reduced accordingly. It can be fully implemented using an ordinary controller, which greatly reduces hardware costs.

[0102] See Figure 11 In an optional embodiment of the present application, the above step 503, in which the controller determines the target reference voltage corresponding to the random access memory according to the starting reference voltage, the ending reference voltage, and the optimal reference voltage, includes the following steps 1101 and 1102:

[0103] Step 1101: The controller determines a first weight coefficient corresponding to a starting reference voltage and an ending reference voltage and a second weight coefficient corresponding to an optimal reference voltage according to power stability parameters of memory chips in a random access memory.

[0104] Among them, the power supply stability parameter refers to a parameter used to characterize the stability of the power supply of the memory particle, such as the quality coefficient and phase of the power supply. This embodiment does not make any specific restrictions and can be selected according to actual conditions. The first weight coefficient is used to characterize the proportion of the starting reference voltage and the ending reference voltage. Correspondingly, the second weight coefficient is used to characterize the proportion of the optimal reference voltage. In general, the power supply stability of the memory particle is positively correlated with the optimal reference voltage with the largest data write delay window, that is, the more stable the power supply and the smaller the fluctuation range, the larger the second weight coefficient of the corresponding optimal reference voltage; on the contrary, the more unstable the power supply and the larger the fluctuation range, the smaller the corresponding second weight coefficient. The controller can configure the first weight coefficient and the second weight coefficient according to the stability of the actual power supply of the memory particle. This embodiment does not impose any restrictions on their specific values.

[0105] Step 1102: The controller determines a target reference voltage corresponding to the random access memory according to the starting reference voltage, the ending reference voltage, the first weight coefficient, the optimal reference voltage, and the second weight coefficient.

[0106] The controller performs weighted summation of the starting reference voltage, the ending reference voltage and the optimal reference voltage based on the first weight coefficient and the second weight coefficient to obtain the corresponding target reference coefficient. It should be noted that the sum of the first weight coefficient and the second weight coefficient is not greater than 1 to avoid the calculated target reference voltage exceeding the range of its initial reference voltage, thereby ensuring the reliability of the reference voltage determination.

[0107] The embodiment of the present application determines the first weight coefficient corresponding to the starting reference voltage and the ending reference voltage and the second weight coefficient corresponding to the optimal reference voltage according to the power stability parameters of the memory particles in the random access memory, and then determines the target reference voltage corresponding to the random access memory according to the starting reference voltage, the ending reference voltage, the optimal reference voltage, the first weight coefficient and the second weight coefficient. The first weight coefficient and the second weight coefficient are determined according to the stability of the memory particles, so that the obtained target reference voltage is more suitable for actual work. The upward jitter range and the downward jitter threshold range of the target reference voltage are relatively large. In actual applications, the actual reference voltage is not easy to jump out of the data write delay window, and the actual data reading and writing are more stable.

[0108] See Figure 12In an optional embodiment of the present application, the above step 1102, in which the controller determines the target reference voltage corresponding to the random access memory according to the starting reference voltage, the first weight coefficient, the ending reference voltage, the optimal reference voltage, and the second weight coefficient, includes the following steps 1201-1203:

[0109] Step 1201: The controller determines a median reference voltage according to the start reference voltage and the end reference voltage.

[0110] The median reference voltage is the average value of the start reference voltage and the end reference voltage, that is, the midpoint value.

[0111] Step 1202: The controller determines a first weight coefficient corresponding to the median reference voltage and a second weight coefficient corresponding to the optimal reference voltage according to the power stability parameters of the memory chips in the random access memory.

[0112] Unlike the above embodiment, the first weight coefficient in this embodiment refers to the weight coefficient of the median of the initial reference voltage and the final reference voltage. It can be configured based on the stability of the memory chip power supply. This first weight coefficient is negatively correlated with the stability of the memory chip power supply. That is, the more stable the power supply and the smaller the fluctuation range, the larger the corresponding first weight coefficient; conversely, the more unstable the power supply and the larger the fluctuation range, the larger the corresponding first weight coefficient. The controller can configure the first and second weight coefficients based on the actual stability of the memory chip power supply. This embodiment does not impose any restrictions on their specific values.

[0113] Step 1203: The controller determines a target reference voltage corresponding to the random access memory according to the median reference voltage, the first weight coefficient, the optimal reference voltage, and the second weight coefficient.

[0114] The controller can calculate the target reference voltage based on the following formula (1):

[0115] vref_final=vref_best*vref_best_weight+[(vref_min+vref_max) / 2]*vref_win_weight(1)

[0116] In formula (1), vref_final represents the target reference voltage, vref_best represents the best reference voltage, vref_best_weight represents the second weight coefficient, vref_min represents the starting reference voltage, vref_max represents the ending reference voltage, (vref_min+vref_max) / 2 represents the median reference voltage, and vref_win_weight represents the first weight coefficient.

[0117] In the embodiment of the present application, a median reference voltage is first determined based on the starting reference voltage and the ending reference voltage, and then a target reference voltage corresponding to the random access memory is determined based on the median reference voltage, the first weight coefficient, the optimal reference voltage and the second weight coefficient. The target reference voltage is determined by comprehensively considering the proportion of the median reference voltage and the optimal reference voltage, so that the upward jitter range and the downward jitter threshold range of the target reference voltage are relatively large. In actual applications, the actual reference voltage is not easy to jump out of the data write delay window, and the actual data reading and writing are more stable.

[0118] It should be understood that, although the various steps in the flowchart are shown in sequence as indicated by the arrows, these steps are not necessarily performed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order restriction on the execution of these steps, and these steps may be performed in other orders. Moreover, at least a portion of the steps in the figure may include multiple sub-steps or multiple stages, and these sub-steps or stages are not necessarily performed at the same time, but may be performed at different times. The execution order of these sub-steps or stages is not necessarily to be performed in sequence, but may be performed in turn or alternately with other steps or at least a portion of the sub-steps or stages of other steps.

[0119] See Figure 13 An embodiment of the present application provides a reference voltage determination device 1300, which is applied to a random access memory. The reference voltage determination device 1300 includes a training module 1310, a first determination module 1320, and a second determination module 1330, wherein:

[0120] The training module 1310 is used to perform data writing training on the random access memory according to each initial reference voltage to obtain each data writing delay window corresponding to each initial reference voltage;

[0121] The first determining module 1320 is configured to determine a starting reference voltage corresponding to a starting data write delay window, a termination reference voltage corresponding to a termination data write delay window, and an optimal reference voltage corresponding to a maximum data write delay window, among multiple data write delay windows that are greater than a preset data write delay window;

[0122] The second determining module 1330 is configured to determine a target reference voltage corresponding to the random access memory according to the starting reference voltage, the ending reference voltage, and the optimal reference voltage.

[0123] In an optional embodiment of the present application, the first determination module 1320 is specifically used to determine the initial reference voltage corresponding to the first data write delay window in multiple data write delay windows that is greater than the preset data write delay window as the starting reference voltage; determine the initial reference voltage corresponding to the last data write delay window in multiple data write delay windows that is greater than the preset data write delay window as the ending reference voltage; and determine the initial reference voltage corresponding to the largest data write delay window in multiple data write delay windows as the optimal reference voltage.

[0124] In an optional embodiment of the present application, the first determination module 1320 is specifically used to determine whether the current data write delay window corresponding to the current initial reference voltage is greater than the historical maximum data write delay window corresponding to the historical best reference voltage; if the current data write delay window corresponding to the current initial reference voltage is greater than the historical maximum data write delay window, the best reference voltage is updated to the current initial reference voltage.

[0125] In an optional embodiment of the present application, the first determination module 1320 is specifically used to obtain the jump information of the current data write delay window corresponding to the current initial reference voltage sent by the physical layer in the random access memory; wherein the jump information is used to indicate whether the size of the data write delay window has changed; and determine whether the current data write delay window is greater than the historical maximum data write delay window corresponding to the historical best reference voltage based on the jump information.

[0126] In an optional embodiment of the present application, the first determination module 1320 is also used to obtain the scanning result information sent by the physical layer in the random access memory for the delay chain delay under the current initial reference voltage; wherein the scanning result information is used to indicate the relative size of the current data write delay window and the preset data write delay window; and determine the relative size of the current data write delay window and the preset data write delay window based on the scanning result information.

[0127] In an optional embodiment of the present application, the second determination module 1330 is specifically used to determine the first weight coefficient corresponding to the starting reference voltage and the ending reference and the second weight coefficient corresponding to the optimal reference voltage according to the power stability parameters of the memory particles in the random access memory; and determine the target reference voltage corresponding to the random access memory according to the starting reference voltage, the ending reference voltage, the first weight coefficient, the optimal reference voltage and the second weight coefficient.

[0128] In an optional embodiment of the present application, the second determination module 1330 is specifically used to determine a median reference voltage based on the starting reference voltage and the ending reference voltage; determine a first weight coefficient corresponding to the median reference voltage and a second weight coefficient corresponding to the optimal reference voltage based on the power stability parameters of the memory particles in the random access memory; and determine a target reference voltage corresponding to the random access memory based on the median reference voltage, the first weight coefficient, the optimal reference voltage and the second weight coefficient.

[0129] The specific limitations of the reference voltage determination device described above can be found in the limitations of the reference voltage determination method described above and will not be further elaborated here. Each module in the reference voltage determination device described above may be implemented in whole or in part through software, hardware, or a combination thereof. Each module may be embedded in or independent of a processor in a computer device in hardware form, or may be stored in a memory in a computer device in software form, so that the processor can call and execute the corresponding operations of each module.

[0130] In one embodiment, a computer device is provided. The internal structure diagram of the computer device can be as follows: Figure 14 As shown. The computer device includes a processor, a memory, a network interface and a database connected via a system bus. The processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program and a database. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The database of the computer device is used to store data. The network interface of the computer device is used to communicate with an external terminal via a network connection. When the computer program is executed by the processor, a reference voltage determination method as described above is implemented. It includes: a memory and a processor, the memory stores a computer program, and when the processor executes the computer program, any step in the reference voltage determination method as described above is implemented.

[0131] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, any step in the above reference voltage determination method can be implemented.

[0132] Those skilled in the art will appreciate that the embodiments of the present application can be provided as methods, systems, or computer program products. Therefore, the present application can adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the present application can adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to magnetic disk storage, CD-ROM, optical storage, etc.) that contain computer-usable program code.

[0133] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the steps in the process. Figure 1 a process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0134] These computer program instructions may also be stored in a computer readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 a process or multiple processes and / or boxes Figure 1 The function specified in one or more boxes.

[0135] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operational steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing the instructions executed on the computer or other programmable device for implementing the process. Figure 1 a process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0136] Although the preferred embodiments of the present application have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present application.

[0137] Obviously, those skilled in the art may make various changes and modifications to this application without departing from the spirit and scope of this application. Thus, if these modifications and variations of this application fall within the scope of the claims of this application and their equivalents, this application is intended to include these modifications and variations.

Claims

1. A method for determining a reference voltage, characterized in that: Applied to random access memory, the method includes: Performing data writing training on the random access memory according to each initial reference voltage to obtain each data writing delay window corresponding to each initial reference voltage; Determine a starting reference voltage corresponding to a starting data write delay window, a termination reference voltage corresponding to a termination data write delay window, and an optimal reference voltage corresponding to a maximum data write delay window, which is greater than a preset data write delay window among the plurality of data write delay windows; Determine a target reference voltage corresponding to the random access memory according to the starting reference voltage, the ending reference voltage and the optimal reference voltage; The determining of a starting reference voltage corresponding to the starting data write delay window, an ending reference voltage corresponding to the ending data write delay window, and an optimal reference voltage corresponding to the maximum data write delay window, which are greater than a preset data write delay window, in the plurality of data write delay windows, includes: determining an initial reference voltage corresponding to a first data write delay window greater than the preset data write delay window among the plurality of data write delay windows as the starting reference voltage; determining an initial reference voltage corresponding to a last data write delay window greater than the preset data write delay window in the plurality of data write delay windows as the termination reference voltage; An initial reference voltage corresponding to a maximum data write delay window among the plurality of data write delay windows is determined as an optimal reference voltage.

2. The reference voltage determination method according to claim 1, wherein: The step of determining an initial reference voltage corresponding to a maximum data write delay window among the plurality of data write delay windows as an optimal reference voltage comprises: Determine whether the current data write delay window corresponding to the current initial reference voltage is greater than the historical maximum data write delay window corresponding to the historical best reference voltage; If the current data write delay window corresponding to the current initial reference voltage is greater than the historical maximum data write delay window, the optimal reference voltage is updated to the current initial reference voltage.

3. The reference voltage determination method according to claim 2, wherein: The determining whether the current data write delay window corresponding to the current initial reference voltage is greater than the historical maximum data write delay window corresponding to the historical best reference voltage includes: Obtaining transition information of the current data write delay window corresponding to the current initial reference voltage, sent by the physical layer in the random access memory; wherein the transition information is used to indicate whether the size of the data write delay window changes; It is determined according to the jump information whether the current data write delay window is greater than the historical maximum data write delay window corresponding to the historical best reference voltage.

4. The reference voltage determination method according to claim 1, wherein: Before determining the starting reference voltage corresponding to the starting data write delay window, the ending reference voltage corresponding to the ending data write delay window, and the optimal reference voltage corresponding to the maximum data write delay window, which are greater than the preset data write delay window, among the multiple data write delay windows, the method further includes: Obtaining scan result information of the delay chain delay at the current initial reference voltage sent by the physical layer in the random access memory; wherein the scan result information is used to indicate the relative size of the current data write delay window and the preset data write delay window; The relative sizes of the current data write delay window and the preset data write delay window are determined according to the scan result information.

5. The reference voltage determination method according to claim 1, wherein: The step of determining a target reference voltage corresponding to the random access memory according to the starting reference voltage, the ending reference voltage, and the optimal reference voltage includes: Determine, according to the power stability parameters of the memory chips in the random access memory, a first weight coefficient corresponding to the starting reference voltage and the ending reference voltage and a second weight coefficient corresponding to the optimal reference voltage; The target reference voltage corresponding to the random access memory is determined according to the starting reference voltage, the ending reference voltage, the first weight coefficient, the optimal reference voltage and the second weight coefficient.

6. The reference voltage determination method according to claim 5, wherein: The determining the target reference voltage corresponding to the random access memory according to the starting reference voltage, the ending reference voltage, the first weight coefficient, the optimal reference voltage, and the second weight coefficient includes: Determine a median reference voltage according to the starting reference voltage and the ending reference voltage; Determine the first weight coefficient corresponding to the median reference voltage and the second weight coefficient corresponding to the optimal reference voltage respectively according to the power stability parameter of the memory chip in the random access memory; The target reference voltage corresponding to the random access memory is determined according to the median reference voltage, the first weight coefficient, the optimal reference voltage and the second weight coefficient.

7. A reference voltage determination device, characterized in that: Applied to random access memory, the reference voltage determining device includes: A training module, configured to perform data writing training on the random access memory according to each initial reference voltage, and obtain each data writing delay window corresponding to each initial reference voltage; A first determination module is configured to determine, among the multiple data write delay windows, a starting reference voltage corresponding to the starting data write delay window, a terminating reference voltage corresponding to the terminating data write delay window, and an optimal reference voltage corresponding to the maximum data write delay window; and is specifically configured to determine the initial reference voltage corresponding to the first data write delay window that is larger than the preset data write delay window among the multiple data write delay windows as the starting reference voltage; determining an initial reference voltage corresponding to a last data write delay window greater than the preset data write delay window in the plurality of data write delay windows as the termination reference voltage; determining an initial reference voltage corresponding to a maximum data write delay window among the plurality of data write delay windows as an optimal reference voltage; The second determining module is configured to determine a target reference voltage corresponding to the random access memory according to the starting reference voltage, the ending reference voltage, and the optimal reference voltage.

8. A computer device comprising: The method comprises a memory and a processor, wherein the memory stores a computer program, and is characterized in that the processor implements the steps of the method according to any one of claims 1 to 6 when executing the computer program.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 6 are implemented.

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