Semiconductor structure and method of forming a semiconductor structure

Abstract

A semiconductor structure and a method for forming the semiconductor structure, the method comprising: providing a substrate, the substrate comprising a first region and a second region adjacent to each other; implanting first ions into the first region and the second region by a first ion implantation process to form an initial drift region in the first region and the second region; forming a gate structure on a portion of the initial drift region, the gate structure extending from a surface of the second region to a surface of the first region; after forming the gate structure, implanting second ions into the second region by a second ion implantation process to form a body region in the second region and to form a drift region from the initial drift region of the first region, the body region having a depth greater than a depth of the drift region, and a portion of the body region being located at a bottom of the gate structure, the second ions having a conductivity type opposite to a conductivity type of the first ions; and implanting third ions into the body region by a third ion implantation process, the third ions having the same conductivity type as the second ions. The semiconductor structure formed by the method has improved performance.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor manufacturing, and in particular, to a semiconductor structure and a forming method of the semiconductor structure. BACKGROUND

[0002] Lateral Double-diffused metal oxide semiconductor (LDMOS) is a high-voltage power device, which has the characteristics of high working voltage, relatively simple process, and high switching frequency, and the processing technology based on bulk silicon material is relatively mature, so the LDMOS has a wide development prospect. The drain, source and gate of the LDMOS are located on the surface thereof, which is easy to integrate into the chip, so the LDMOS is particularly suitable as a high-voltage power device in high-voltage integrated circuits and power integrated circuits.

[0003] However, the performance of the existing LDMOS needs to be improved. SUMMARY

[0004] The present application solves the technical problem of providing a semiconductor structure and a forming method of the semiconductor structure to improve the performance of the LDMOS.

[0005] To solve the above technical problem, the technical scheme of the present application provides a forming method of a semiconductor structure, comprising: providing a substrate, the substrate comprising adjacent first and second regions; using a first ion implantation process to implant first ions in the first and second regions to form initial drift regions in the first and second regions; forming a gate structure on part of the initial drift regions, the gate structure extending from the surface of the second region to the surface of the first region; after forming the gate structure, using a second ion implantation process to implant second ions in the second region to form a body region in the second region, and the initial drift region of the first region forms a drift region, the depth of the body region is greater than the depth of the drift region, and part of the body region is located at the bottom of the gate structure, the conductivity type of the second ions is opposite to that of the first ions; using a third ion implantation process to implant third ions in the body region to form an enhancement region on the surface of the body region, the conductivity type of the third ions is the same as that of the second ions.

[0006] Optionally, the concentration of the third ions is greater than the concentration of the second ions.

[0007] Optionally, the implantation depth of the second ion implantation process is greater than the implantation depth of the third ion implantation process.

[0008] Optionally, before the second ion implantation process is used to implant the second ions into the second region, the method further comprises: forming a mask structure on part of the initial drift region and part of the gate structure, the mask structure exposing part of the gate structure and the second region surface.

[0009] Optionally, the method of using the second ion implantation process to implant the second ions into the second region comprises: using the mask structure as a mask, implanting the second ions into part of the gate structure and the second region to form the drift region and the body region.

[0010] Optionally, the method of using the third ion implantation process to implant the third ions into the body region comprises: using the mask structure as a mask, implanting the third ions into the body region and part of the gate structure on the body region.

[0011] Optionally, after the third ion implantation process is used to implant the third ions into the body region, the method further comprises: using a fourth ion implantation process to implant fourth ions into the body region to form an inversion region on the body region surface, the fourth ions having the same conductivity type as the first ions.

[0012] Optionally, the method of using the fourth ion implantation process to implant the fourth ions into the body region comprises: using the mask structure as a mask, implanting the fourth ions into the body region and part of the gate structure on the body region.

[0013] Optionally, the implantation depth of the fourth ion implantation process is less than the implantation depth of the third ion implantation process.

[0014] Optionally, the fourth ions comprise N-type ions or P-type ions; the N-type ions comprise phosphorus ions, arsenic ions or antimony ions; the P-type ions comprise boron ions, boron-fluorine ions or indium ions.

[0015] Optionally, the fourth ions further comprise fluorine ions or carbon ions.

[0016] Optionally, the method further comprises: forming a drain region in the drift region and a source region in the body region, the source region and the drain region having the same conductivity type as the first ions.

[0017] Optionally, before the drain region is formed in the drift region and the source region is formed in the body region, the method further comprises: forming a side wall on the gate structure sidewall; and the method of forming the drain region in the drift region and the source region in the body region comprises: using the side wall and the gate structure as a mask, implanting ions into the body region and the drift region to form the source region and the drain region.

[0018] Optionally, after the third ion implantation process is used to implant the third ions into the body region, the method further comprises: performing a first annealing process on the semiconductor structure; and the first annealing process comprises a thermal annealing process.

[0019] Optionally, after the second ion implantation process is used to implant the second ions into the second region, the method further comprises: performing a second annealing process on the semiconductor structure; and the second annealing process comprises a laser annealing process or a spike annealing process.

[0020] Optionally, the first ions comprise N-type ions or P-type ions; the N-type ions comprise phosphorus ions, arsenic ions or antimony ions; and the P-type ions comprise boron ions, boron-fluorine ions or indium ions.

[0021] Optionally, the second ions comprise N-type ions or P-type ions; the N-type ions comprise phosphorus ions, arsenic ions or antimony ions; and the P-type ions comprise boron ions, boron-fluorine ions or indium ions.

[0022] Optionally, the method for forming the gate structure comprises: forming a gate structure material layer on the substrate; forming a patterned layer on the gate structure material layer, the patterned layer exposing part of the surface of the gate structure material layer; and etching the gate structure material layer using the patterned layer as a mask until part of the surface of the first region and part of the surface of the second region are exposed, thereby forming the gate structure.

[0023] Optionally, before the gate structure is formed on part of the initial drift region, the method further comprises: forming an isolation structure in the first region, the depth of the isolation structure being less than the depth of the initial drift region; and the gate structure is adjacent to the isolation structure or is located on part of the isolation structure.

[0024] Optionally, the material of the isolation structure comprises silicon oxide.

[0025] Correspondingly, the present application also provides a semiconductor structure, which comprises: a substrate comprising an adjacent drift region and body region, the depth of the body region being greater than the depth of the drift region, the first ions being located in the drift region, and the second ions being located in the body region, the conductive type of the second ions being opposite to the conductive type of the first ions; a gate structure located on the substrate, the gate structure extending from the surface of the body region to the surface of the drift region, and part of the body region being located at the bottom of the gate structure; and an enhancement region located on the surface of the body region, the third ions being located in the enhancement region, the conductive type of the third ions being the same as the conductive type of the second ions.

[0026] Optionally, the concentration of the third ions is greater than the concentration of the second ions.

[0027] Optionally, the depth of the enhancement region is less than the depth of the body region.

[0028] Optionally, the method further comprises: forming a reverse type region on the surface of the body region, the reverse type region containing fourth ions, the fourth ions having the same conductivity type as the first ions.

[0029] Optionally, the depth of the reverse type region is less than the depth of the enhanced region.

[0030] Optionally, the fourth ions include N-type ions or P-type ions; the N-type ions include phosphorus ions, arsenic ions or antimony ions; the P-type ions include boron ions, boron-fluorine ions or indium ions.

[0031] Optionally, the fourth ions further include fluorine ions or carbon ions.

[0032] Optionally, the method further comprises: forming a side wall on both sides of the gate structure; forming a drain region in the drift region, the drain region being adjacent to the side wall; forming a source region in the body region, the source region being adjacent to the side wall; the ions of the source region and the drain region having the same conductivity type as the first ions.

[0033] Optionally, the first ions include N-type ions or P-type ions; the N-type ions include phosphorus ions, arsenic ions or antimony ions; the P-type ions include boron ions, boron-fluorine ions or indium ions; the second ions include N-type ions or P-type ions; the N-type ions include phosphorus ions, arsenic ions or antimony ions; the P-type ions include boron ions, boron-fluorine ions or indium ions.

[0034] Optionally, the method further comprises: forming an isolation structure in the drift region; the depth of the isolation structure being less than the depth of the drift region; the gate structure being adjacent to the isolation structure or being on part of the isolation structure.

[0035] Compared with the prior art, the technical scheme of the present application has the following beneficial effects:

[0036] The method for forming the semiconductor structure in the technical solution of the present application forms an initial drift region in the first region and the second region, forms a gate structure on part of the initial drift region, the gate structure extends from the surface of the second region to the surface of the first region, then performs a second ion implantation on the second region to form a body region in the second region and a drift region in the first region, and then performs a third ion implantation on the body region, the third ion has a conductive type opposite to that of the first ion. The method forms the gate structure first, then performs the second ion implantation and the third ion implantation on the second region. On the one hand, the third ion implantation can compensate the second ion implantation, so that the implantation energy and the dosage of the second ion implantation do not have to be too large, thereby reducing the case that the depth of the body region formed by the second ion implantation is too deep when the implantation energy and the dosage of the second ion implantation are too large, so as to make the ions in the body region and the drift region unbalanced. On the other hand, the third ion implantation can enhance the ion concentration on the surface of the body region, thereby maintaining the effective channel length of the semiconductor structure and reducing the lateral resistance of the semiconductor structure. In addition, the gate structure is formed first, so that the subsequent adjustment window of the ion concentration on the surface of the body region is large, the electrical properties of the drift region and the body region are more balanced and stable, and the semiconductor structure with good electrical properties is beneficial to be formed. In summary, the performance of the semiconductor structure is improved.

[0037] Further, after the second ion implantation on the part of the initial drift region exposed by the gate structure, the semiconductor structure is subjected to a second annealing treatment. The second annealing treatment can repair part of the defects generated by the second ion implantation and weaken the ion diffusion effect of the subsequent third ion implantation process.

[0038] Further, the method further comprises: performing a fourth ion implantation on the body region, the fourth ion implantation is performed by using fourth ions, and the fourth ions have the same conductive type as the first ions. The fourth ions can partially offset the third ions and the second ions in the body region, so that the electrical properties of the ions in the body region and the drift region are more balanced, and the electrical properties of the semiconductor structure are more stable. BRIEF DESCRIPTION OF DRAWINGS

[0039] Figures 1 to 3 FIG. 1 is a schematic diagram of the cross-sectional structure of the semiconductor structure in the forming process according to an embodiment of the present application;

[0040] Figures 4 to 9 FIG. 2 is a schematic diagram of the cross-sectional structure of the semiconductor structure in the forming process according to an embodiment of the present application. DETAILED DESCRIPTION

[0041] As described in the background, the performance of the existing lateral double diffusion metal oxide semiconductor needs to be improved. The present application will be described in connection with specific embodiments.

[0042] Figures 1 to 3 is a schematic diagram of the cross-sectional structure of the semiconductor structure in an embodiment.

[0043] Referring to Figure 1 , the method comprises: providing a substrate 100, the substrate 100 comprising adjacent first region I and second region II; forming an initial drift region 101 in the first region I and the second region II; forming an initial gate structure 102 on the initial drift region 101.

[0044] Referring to Figure 2 , a first mask layer 103 is formed on the initial gate structure 102, the first mask layer 103 exposing the initial gate structure 102 on the second region II; the second region II is subjected to a first ion implantation with the first mask layer 103 as a mask, a body region 105 is formed in the second region II, and the initial drift region 101 in the first region I forms a drift region 104, the ion conduction type in the body region 105 being opposite to the ion conduction type in the drift region 104.

[0045] Referring to Figure 3 , after the body region 105 is formed, part of the initial gate structure 102 is removed to form a gate structure 106, the gate structure 106 extending from the surface of the drift region 104 to the surface of the body region 105; a second mask layer 107 is formed on the drift region 104 and the gate structure 106; the body region 105 is subjected to a second ion implantation with the second mask layer 107 as a mask, the ion conduction type of the implantation ions of the second ion implantation being the same as that of the first ion implantation.

[0046] The ion in the drift region 104 is an N-type ion, the N-type ion comprising a phosphorus ion, the ion in the body region 105 is a P-type ion, the P-type ion comprising a boron ion. The ion concentration of the second ion implantation is greater than that of the first ion implantation, so as to increase the ion concentration on the surface of the body region 105, and the lateral resistance of the semiconductor structure can be reduced.

[0047] However, the molecular weight of the phosphorus ions in the drift region 104 is larger than that of the boron ions in the body region 105, so the phosphorus ions in the drift region 104 are prone to diffuse into the body region 105, so that the width of the drift region 104 becomes larger, so that the performance of the semiconductor structure changes. Moreover, after the second ion implantation, an annealing process is performed, which makes the high-concentration second ion implantation injection ions prone to diffuse, which can cause a short channel effect. And the gate structure 106 is formed after the first ion implantation, the injection ions of the first ion implantation process enter the substrate 100 to form the body region 105 through the initial gate structure 102, so that the depth range of the body region 105 is not good to adjust, and the ion concentration on the surface of the body region 105 is also not good to adjust. Therefore, when the semiconductor structure has a short channel effect or a reverse short channel effect, the performance of the semiconductor structure is difficult to adjust.

[0048] In order to solve the above problems, the technical scheme of the present application provides a semiconductor structure and a forming method thereof. The method comprises the following steps: forming an initial drift region in a first region and a second region, forming a gate structure on part of the initial drift region, the gate structure extending from the surface of the second region to the surface of the first region, then performing a second ion implantation on the second region to form a body region in the second region and a drift region in the first region, and then performing a third ion implantation on the body region, the third ion being of an opposite conductivity type to the first ion. The method forms the gate structure first, and then performs the second ion implantation and the third ion implantation on the second region. On the one hand, the third ion implantation is of the same conductivity type as the second ion implantation, so that the third ion implantation can compensate for the second ion implantation, so that even if the first ion in the second region is of a reverse type, the injection energy and dose of the second ion implantation do not have to be too large, so as to reduce the case that the depth of the body region formed by the second ion implantation is too deep when the injection energy and dose of the second ion implantation are too large, so as to make the ions in the body region and the drift region unbalanced. On the other hand, the third ion implantation can enhance the ion concentration on the surface of the body region, so as to maintain the effective channel length of the semiconductor structure and reduce the lateral resistance of the semiconductor structure. Moreover, the gate structure is formed first, so that the subsequent adjustment window of the ion concentration on the surface of the body region is larger, so that the electrical properties of the drift region and the body region are more balanced and stable, which is beneficial to forming a semiconductor structure with good electrical properties. In summary, the performance of the semiconductor structure is improved.

[0049] In order to make the above-mentioned purposes, features and advantages of the present application more obvious and easy to understand, the specific embodiments of the present application will be described in detail below with reference to the drawings.

[0050] Figures 4 to 9 is a schematic diagram of the cross-sectional structure of the semiconductor structure forming process in the embodiment of the present application.

[0051] Please refer to Figure 4 A substrate 200 is provided, which includes a first region I and a second region II adjacent to each other.

[0052] The material of the substrate 200 includes silicon (Si), germanium (Ge), or silicon-germanium (GeSi), silicon carbide (SiC), and can also include silicon-on-insulator (SOI), germanium-on-insulator (GOI), or other materials such as gallium arsenide and other group III-V compounds. In the present embodiment, the material of the substrate 200 is silicon.

[0053] In the present embodiment, the substrate 200 has a well region (not shown) therein.

[0054] The conductivity type of the well region includes N-type or P-type according to the type of the semiconductor device to be formed.

[0055] In the present embodiment, the semiconductor structure to be formed is an N-type LDMOS, and the conductivity type of the well region is N-type.

[0056] In the present embodiment, the well region is formed by doping N-type ions in the substrate 200 through an ion implantation process. In other embodiments, P-type ions are doped in the substrate through an ion implantation process.

[0057] The N-type ions are one or more of phosphorus ions, arsenic ions, and antimony ions; and the P-type ions are one or more of boron ions, indium ions, and gallium ions.

[0058] In the present embodiment, the substrate 200 is a planar substrate.

[0059] In other embodiments, the substrate includes a substrate and a fin portion located on a portion of the surface of the substrate.

[0060] Please continue to refer to Figure 4 A first ion implantation process is performed to implant first ions in the first region I and the second region II, thereby forming an initial drift region 201 in the first region I and the second region II.

[0061] The initial drift region 201 is used to form a drift region and a body region subsequently. Specifically, the initial drift region 201 is located in the well region.

[0062] The first ions include N-type ions or P-type ions. In the present embodiment, the semiconductor structure to be formed is an N-type LDMOS, and the first ions are N-type ions, which include one or more of phosphorus ions, arsenic ions, and antimony ions.

[0063] In the present embodiment, the first ions are phosphorus ions.

[0064] In other embodiments, the semiconductor structure to be formed is a P-type LDMOS, and the first ions can also be P-type ions, including one or more of boron ions, indium ions, and gallium ions.

[0065] Please refer to Figure 5 The isolation structure 300 is formed in the first region I.

[0066] The isolation structure 300 is used to block the diffusion of ions in the subsequently formed drain region to the channel, thereby increasing the breakdown voltage of the semiconductor structure and improving the breakdown resistance of the semiconductor structure.

[0067] In the present embodiment, the depth of the isolation structure 300 is less than the depth of the initial drift region 201, i.e., the depth of the isolation structure 300 is less than the depth of the subsequently formed drift region. Thus, the subsequently formed isolation structure 300 does not completely block the channel between the drain region and the channel, thereby not affecting the electrical performance of the semiconductor structure while improving the breakdown resistance of the device.

[0068] The formation method of the isolation structure 300 includes: forming an isolation groove (not shown) in the first region I; forming an isolation material layer (not shown) in the isolation groove and on the substrate; and planarizing the isolation material layer until the surface of the substrate is exposed, thereby forming the isolation structure 300.

[0069] The material of the isolation structure 300 includes a dielectric material, which includes one or more of a combination of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbon nitride, and silicon carbon oxynitride.

[0070] In the present embodiment, the material of the isolation structure 300 includes silicon oxide.

[0071] Please continue to refer to Figure 5 The gate structure 202 is formed on part of the initial drift region 201, and the gate structure 202 extends from the surface of the second region II to the surface of the first region I. The gate structure 202 is adjacent to the isolation structure 300, or the gate structure 202 is located on part of the isolation structure 300.

[0072] The formation method of the gate structure 202 includes: forming a gate structure material layer (not shown) on the substrate 200 and the isolation structure 300; forming a patterned layer (not shown) on the gate structure material layer, which exposes part of the surface of the gate structure material layer; etching the gate structure material layer with the patterned layer as a mask until part of the surface of the first region I, part or all of the surface of the isolation structure 300, and part of the surface of the second region II are exposed, thereby forming the gate structure 202.

[0073] The gate structure 202 comprises a gate dielectric layer (not shown) and a gate layer (not shown) on the gate dielectric layer.

[0074] In the embodiment, the gate structure 202 further comprises a protective layer (not shown) on the top surface of the gate layer, which is used to protect the top surface of the gate layer, reduce the influence of subsequent processes on the gate layer, and improve the performance of the formed semiconductor structure.

[0075] Please refer to Figure 6 After the gate structure 202 is formed, a mask structure 203 is formed on part of the initial drift region 201 and part of the gate structure 202, which exposes part of the gate structure 202 on the second region II and the surface of the second region II.

[0076] In the embodiment, the material of the mask structure 203 comprises photoresist.

[0077] Please refer to Figure 6 A second ion implantation process is performed in the second region II using the mask structure 203 as a mask to form a body region 204 in the second region II and a drift region 205 from the initial drift region 201 of the first region I, the depth of the body region 204 is greater than the depth of the drift region 205, part of the body region 204 is located at the bottom of the gate structure 202, and the conductivity type of the second ion is opposite to that of the first ion.

[0078] The drift region 205 is used to separate the subsequently formed drain region and the channel region, thereby extending the current channel of the semiconductor structure and improving the breakdown voltage. The body region 204 is used to separate the subsequently formed source region and the channel region.

[0079] The gate structure 202 is formed first, and then the second ion is implanted in the second region II using the mask structure 203 as a mask. Since the gate structure 202 exposes part of the surface of the second region II, the second ion implantation process using the mask structure 203 as a mask is not blocked by the gate structure 202, so the implantation depth of the second ion in the second region II can be deeper, the depth of the body region 204 can be greater than the depth of the drift region 205, and the phenomenon of diffusion of phosphorus ions in the drift region 205 into the body region 204 can be offset, so that the ions in the body region 204 and the drift region 205 maintain a balanced state.

[0080] The second ion comprises N-type ions or P-type ions; the N-type ions comprise phosphorus ions, arsenic ions or antimony ions; and the P-type ions comprise boron ions, boron-fluorine ions or indium ions.

[0081] In the embodiment, the second ions include P-type ions, and the P-type ions are boron ions.

[0082] After the second ion implantation process is performed to implant the second ions into the second region II, the method further includes performing a second annealing process on the semiconductor structure, and the second annealing process includes laser annealing or spike annealing.

[0083] The second annealing process can repair a part of defects caused by the second ion implantation process and weaken the ion diffusion effect of a subsequent third ion implantation process.

[0084] Please refer to Figure 7 A third ion implantation process is performed to implant third ions into the body region 204 using the mask structure 203 as a mask, and the third ions form an enhanced region 206 on the surface of the body region 204, and the conductivity type of the third ions is the same as that of the second ions.

[0085] In the embodiment, a part of the enhanced region 206 is also located at the bottom of the gate structure 202.

[0086] In the embodiment, the concentration of the third ions is greater than that of the second ions, and the implantation depth of the third ion implantation process is less than that of the second ion implantation process, that is, the depth of the enhanced region 206 is less than that of the body region 204.

[0087] On the one hand, the conductivity type of the third ions is the same as that of the second ions, and the third ion implantation can compensate for the second ion implantation, so that the implantation energy and dose of the second ion implantation do not have to be too large, thereby reducing the case that the depth of the body region 204 formed by the second ion implantation is too deep when the implantation energy and dose of the second ion implantation are too large, so that the ions of the body region 204 and the drift region 205 are not balanced.

[0088] On the other hand, the concentration of the third ions is greater than that of the second ions, and the implantation depth of the third ion implantation process is less than that of the second ion implantation process, so that the third ion implantation can enhance the ion concentration on the surface of the body region 204, thereby maintaining the effective channel length of the semiconductor structure and reducing the lateral resistance of the semiconductor structure.

[0089] In addition, the gate structure 202 is formed first, and the gate structure 202 exposes a part of the surface of the body region 204, so that the subsequent ion concentration adjustment window of the surface of the body region 204 is large, and it is easy to make the electrical properties of the drift region 205 and the body region 204 more balanced and stable, which is beneficial to form a semiconductor structure with good electrical properties.

[0090] The third ion comprises an N-type ion or a P-type ion; the N-type ion comprises a phosphorus ion, an arsenic ion or an antimony ion; the P-type ion comprises a boron ion, a boron-fluorine ion or an indium ion.

[0091] In the embodiment, the third ion comprises a P-type ion, and the P-type ion comprises a boron ion.

[0092] Please refer to Figure 8 After the third ion implantation process is used to implant the third ion into the body region 204, a fourth ion implantation process is further used to implant a fourth ion into the body region 204 with the mask structure 203 as a mask, so as to form a counter-type region 207 on the surface of the body region 204, and the fourth ion has the same conductivity type as the first ion.

[0093] In the embodiment, part of the counter-type region 207 is also located at the bottom of the gate structure 202.

[0094] The fourth ion comprises an N-type ion or a P-type ion; the N-type ion comprises a phosphorus ion, an arsenic ion or an antimony ion; the P-type ion comprises a boron ion, a boron-fluorine ion or an indium ion.

[0095] The fourth ion has the same conductivity type as the first ion, that is, the conductivity type of the fourth ion is different from the conductivity type of the second ion in the body region 204 and the conductivity type of the third ion in the enhancement region 206. The fourth ion can partially offset the third ion and the second ion in the body region 204, so that the ion electric properties in the body region 204 and the drift region 205 are relatively balanced, and the semiconductor structure has relatively stable electric properties.

[0096] In the embodiment, the implantation depth of the fourth ion implantation process is smaller than the implantation depth of the third ion implantation process, that is, the depth of the counter-type region 207 is smaller than the depth of the enhancement region 206, so that the fourth ion does not completely offset the third ion and the second ion in the body region 204, thereby playing a fine-tuning role, so that the ion electric properties in the body region 204 and the drift region 205 are relatively balanced.

[0097] In the embodiment, the fourth ion comprises an N-type ion.

[0098] In the embodiment, the fourth ion further comprises a fluorine ion or a carbon ion. The fluorine ion or the carbon ion can repair defects generated by ion implantation into the body region 204, so that the ion on the surface of the body region 204 is stable and is not prone to interface diffusion.

[0099] In other embodiments, the fourth ion can not comprise a fluorine ion or a carbon ion.

[0100] After the fourth ion implantation process is performed to implant the fourth ions into the body region 204, the semiconductor structure is subjected to a first annealing process, and the first annealing process comprises thermal annealing.

[0101] Since the semiconductor structure is annealed by the second annealing process first, the second annealing process can repair a part of defects caused by the second ion implantation, so that the ion diffusion effect of the third ions can be weakened when the semiconductor structure is subjected to the first annealing process, thereby reducing the occurrence of short channel effect or reverse short channel effect.

[0102] In other embodiments, the fourth ions can not be implanted into the body region. The second annealing process is performed after the third ion implantation.

[0103] After the gate structure 202 is formed, a mask structure 203 is formed, and the second ion implantation, the third ion implantation and the fourth ion implantation are all performed by using the mask structure 203, so that the mask structure can be saved, the process flow can be simplified, and the production cost can be saved.

[0104] After the fourth ion implantation process is performed to implant the fourth ions into the body region 204, the mask structure 203 is removed.

[0105] In the embodiment, the process of removing the mask structure 203 comprises a dry etching process.

[0106] Please refer to Figure 9 A side wall 208 is formed on the side wall of the gate structure 202.

[0107] The side wall 208 has the following functions: on the one hand, it is used to protect the side wall surface of the gate structure 202 from being affected by subsequent processes, so as to maintain the morphology and improve the stability of the electrical performance; on the other hand, it is used to position the positions of the source region and the drain region formed subsequently.

[0108] The method for forming the side wall 208 comprises: forming a side wall material layer (not shown in the figure) on the surface of the substrate 200 and the top surface and the side wall surface of the gate structure 202; and etching back the side wall material layer until the surface of the substrate 200 and the top surface of the gate layer are exposed, so as to form the side wall 208.

[0109] The material of the side wall 208 comprises a dielectric material, and the dielectric material comprises one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbon nitride and silicon carbon oxynitride. In the embodiment, the material of the side wall 208 comprises silicon nitride.

[0110] Please continue to refer to Figure 9A drain region 209 is formed in the drift region 205, and a source region 210 is formed in the body region 204, the ion conductive type of the source region 210 and the drain region 209 being the same as the conductive type of the first ion.

[0111] The method for forming the source region 210 and the drain region 209 in the body region 204 and the drift region 205 includes: performing ion implantation on the body region 204 and the drift region 205 by taking the side wall 208 and the gate structure 202 as a mask.

[0112] The ion of the source region 210 and the drain region 209 includes N-type ion or P-type ion; the N-type ion includes phosphorus ion, arsenic ion or antimony ion; the P-type ion includes boron ion, boron fluoride ion or indium ion.

[0113] In the embodiment, the ion of the source region 210 and the drain region 209 includes N-type ion.

[0114] Correspondingly, the embodiment of the present application further provides a semiconductor structure, please continue to refer to Figure 9 , comprising:

[0115] A substrate 200, the substrate 200 includes adjacent drift region 205 and body region 204, the depth of the body region 204 is greater than the depth of the drift region 205, the drift region 205 has a first ion, the body region 204 has a second ion, the conductive type of the second ion is opposite to the conductive type of the first ion;

[0116] A gate structure 202 on the substrate 200, the gate structure 202 extends from the surface of the body region 204 to the surface of the drift region 205, and part of the body region 204 is located at the bottom of the gate structure 202;

[0117] An enhanced region 206 on the surface of the body region 204, the enhanced region 206 has a third ion, the conductive type of the third ion is the same as the conductive type of the second ion.

[0118] In the embodiment, the concentration of the third ion is greater than the concentration of the second ion.

[0119] In the embodiment, the depth of the enhanced region 206 is less than the depth of the body region 204.

[0120] In the embodiment, further comprising: a reverse type region 207 on the surface of the body region 204, the reverse type region 207 has a fourth ion, the conductive type of the fourth ion is the same as the conductive type of the first ion.

[0121] In the embodiment, the depth of the reverse type region 207 is less than the depth of the enhanced region 206.

[0122] In the embodiment, the fourth ion comprises N-type ion or P-type ion; the N-type ion comprises phosphorus ion, arsenic ion or antimony ion; the P-type ion comprises boron ion, boron-fluorine ion or indium ion.

[0123] In the embodiment, the fourth ion further comprises fluorine ion or carbon ion.

[0124] In the embodiment, further comprising: a side wall 208 located on both sides of the gate structure 202; a drain region 209 located in the drift region 205, the drain region 209 being adjacent to the side wall 208; a source region 210 located in the body region 204, the source region 210 being adjacent to the side wall 208; the ion conductive type of the source region 210 and the drain region 209 being the same as the conductive type of the first ion.

[0125] In the embodiment, the first ion comprises N-type ion or P-type ion; the N-type ion comprises phosphorus ion, arsenic ion or antimony ion; the P-type ion comprises boron ion, boron-fluorine ion or indium ion; the second ion comprises N-type ion or P-type ion; the N-type ion comprises phosphorus ion, arsenic ion or antimony ion; the P-type ion comprises boron ion, boron-fluorine ion or indium ion.

[0126] In the embodiment, further comprising: an isolation structure 300 located in the drift region 205; the depth of the isolation structure 300 being less than the depth of the drift region 205; the gate structure 202 being adjacent to the isolation structure 300 or being located on part of the isolation structure 300.

[0127] Although the present application has been disclosed as above, the present application is not limited to the above. Any person skilled in the art, without departing from the spirit and scope of the present application, can make various changes and modifications, therefore the protection scope of the present application should be defined by the scope of the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, the substrate comprising an adjacent first region and a second region; A first ion is implanted into the first region and the second region using a first ion implantation process to form an initial drift region in the first region and the second region. A gate structure is formed on a portion of the initial drift region, the gate structure extending from the surface of the second region to the surface of the first region; After the gate structure is formed, a second ion implantation process is used to implant a second ion into the second region to form a body region in the second region, and to make the initial drift region of the first region form a drift region. The depth of the body region is greater than the depth of the drift region, and part of the body region is located at the bottom of the gate structure. The conductivity type of the second ion is opposite to that of the first ion. The depth of the body region located at the bottom of the gate structure is less than the depth of the body region located outside the bottom region of the gate structure. A third ion is implanted into the body region using a third ion implantation process to form an enhancement region on the surface of the body region. The conductivity type of the third ion is the same as that of the second ion. The depth of the enhancement region located at the bottom of the gate structure is less than the depth of the enhancement region located outside the bottom region of the gate structure. A fourth ion is implanted into the body region using a fourth ion implantation process to form an inversion region on the surface of the body region. The conductivity type of the fourth ion is the same as that of the first ion. The implantation depth of the fourth ion implantation process is less than that of the third ion implantation process. Part of the inversion region is also located at the bottom of the gate structure. The depth of the inversion region located at the bottom of the gate structure is less than the depth of the inversion region located outside the bottom region of the gate structure.

2. The method for forming a semiconductor structure as described in claim 1, characterized in that, The concentration of the third ion is greater than the concentration of the second ion.

3. The method for forming a semiconductor structure as described in claim 1, characterized in that, The implantation depth of the second ion implantation process is greater than the implantation depth of the third ion implantation process.

4. The method for forming a semiconductor structure as described in claim 1, characterized in that, After the gate structure is formed, and before the second ion is implanted in the second region using a second ion implantation process, the method further includes: forming a mask structure on a portion of the initial drift region and a portion of the gate structure, the mask structure exposing a portion of the gate structure and the surface of the second region located on the second region.

5. The method for forming a semiconductor structure as described in claim 4, characterized in that, The method of implanting a second ion into the second region using a second ion implantation process includes: using the mask structure as a mask, performing a second ion implantation on a portion of the gate structure and the second region to form a drift region and a body region.

6. The method for forming a semiconductor structure as described in claim 4, characterized in that, The method of implanting third ions into the body region using a third ion implantation process includes: using the mask structure as a mask to perform third ion implantation on the body region and a portion of the gate structure located on the body region.

7. The method for forming a semiconductor structure as described in claim 4, characterized in that, The method of implanting a fourth ion into the body region using a fourth ion implantation process includes: using the mask structure as a mask to perform fourth ion implantation on the body region and a portion of the gate structure located on the body region.

8. The method for forming a semiconductor structure as described in claim 1, characterized in that, The fourth ion includes N-type ions or P-type ions; the N-type ions include phosphorus ions, arsenic ions or antimony ions; the P-type ions include boron ions, boron-fluorine ions or indium ions.

9. The method for forming a semiconductor structure as described in claim 8, characterized in that, The fourth ion also includes fluoride ions or carbon ions.

10. The method for forming a semiconductor structure as described in claim 1, characterized in that, Also includes: A drain region is formed in the drift region, and a source region is formed in the body region. The ionic conductivity type of the source region and the drain region is the same as that of the first ion.

11. The method for forming a semiconductor structure as described in claim 10, characterized in that, Before forming a drain region in the drift region and a source region in the body region, the method further includes: forming a sidewall on the sidewall of the gate structure; the method of forming a drain region in the drift region and a source region in the body region includes: using the sidewall and the gate structure as a mask, performing ion implantation on the body region and the drift region to form the source region and the drain region.

12. The method for forming a semiconductor structure as described in claim 1, characterized in that, After implanting third ions into the body region using a third ion implantation process, the method further includes: performing a first annealing treatment on the semiconductor structure; the first annealing treatment includes thermal annealing.

13. The method for forming a semiconductor structure as described in claim 1, characterized in that, After implanting a second ion into the second region using a second ion implantation process, the method further includes: performing a second annealing process on the semiconductor structure; the second annealing process includes laser annealing or peak annealing.

14. The method for forming a semiconductor structure as described in claim 1, characterized in that, The first ion includes N-type ions or P-type ions; the N-type ions include phosphorus ions, arsenic ions or antimony ions; the P-type ions include boron ions, borofluorine ions or indium ions.

15. The method for forming a semiconductor structure as described in claim 1, characterized in that, The second ion includes N-type ions or P-type ions; the N-type ions include phosphorus ions, arsenic ions or antimony ions; the P-type ions include boron ions, borofluorine ions or indium ions.

16. The method for forming a semiconductor structure as described in claim 1, characterized in that, The method for forming the gate structure includes: forming a gate structure material layer on a substrate; forming a patterned layer on the gate structure material layer, wherein the patterned layer exposes a portion of the surface of the gate structure material layer; and etching the gate structure material layer using the patterned layer as a mask until a portion of the surface of a first region and a portion of the surface of a second region are exposed, thereby forming the gate structure.

17. The method for forming a semiconductor structure as described in claim 1, characterized in that, Before forming a gate structure on a portion of the initial drift region, the method further includes: forming an isolation structure in a first region, the depth of the isolation structure being less than the depth of the initial drift region; the gate structure being adjacent to or located on a portion of the isolation structure.

18. The method for forming a semiconductor structure as described in claim 17, characterized in that, The material of the isolation structure includes silicon dioxide.

19. A semiconductor structure, characterized in that, include: A substrate comprising adjacent drift regions and a body region, wherein the depth of the body region is greater than the depth of the drift regions, the drift regions contain a first ion, and the body regions contain a second ion, wherein the conductivity type of the second ion is opposite to that of the first ion; A gate structure located on a substrate, the gate structure extending from the surface of the body region to the surface of the drift region, and a portion of the body region being located at the bottom of the gate structure, wherein the depth of the body region at the bottom of the gate structure is less than the depth of the body region outside the bottom region of the gate structure; An enhancement region located on the surface of the body region, wherein the enhancement region contains a third ion, the third ion having the same conductivity type as the second ion, and the depth of the enhancement region located at the bottom of the gate structure is less than the depth of the enhancement region located outside the bottom region of the gate structure. An inversion region is located on the surface of the body region. The inversion region contains a fourth ion, the fourth ion having the same conductivity type as the first ion. The depth of the inversion region is less than the depth of the enhancement region. Part of the inversion region is also located at the bottom of the gate structure. The depth of the inversion region at the bottom of the gate structure is less than the depth of the inversion region outside the bottom region of the gate structure.

20. The semiconductor structure as claimed in claim 19, characterized in that, The concentration of the third ion is greater than the concentration of the second ion.

21. The semiconductor structure as claimed in claim 19, characterized in that, The depth of the enhancement region is less than the depth of the body region.

22. The semiconductor structure as described in claim 19, characterized in that, The fourth ion includes N-type ions or P-type ions; the N-type ions include phosphorus ions, arsenic ions or antimony ions; the P-type ions include boron ions, boron-fluorine ions or indium ions.

23. The semiconductor structure as described in claim 22, characterized in that, The fourth ion also includes fluoride ions or carbon ions.

24. The semiconductor structure as claimed in claim 19, characterized in that, Also includes: Sidewalls located on both sides of the gate structure; a drain region located in the drift region, the drain region being adjacent to the sidewalls; a source region located in the body region, the source region being adjacent to the sidewalls; the ionic conductivity type of the source region and the drain region is the same as the conductivity type of the first ion.

25. The semiconductor structure as claimed in claim 19, characterized in that, The first ion includes N-type ions or P-type ions; the N-type ions include phosphorus ions, arsenic ions or antimony ions; the P-type ions include boron ions, boron-fluorine ions or indium ions; the second ion includes N-type ions or P-type ions; the N-type ions include phosphorus ions, arsenic ions or antimony ions; the P-type ions include boron ions, boron-fluorine ions or indium ions.

26. The semiconductor structure as claimed in claim 19, characterized in that, Also includes: An isolation structure located within the drift zone; The depth of the isolation structure is less than the depth of the drift region; The gate structure is adjacent to or located on part of the isolation structure.

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