Method of forming a semiconductor structure

Abstract

A method for forming a semiconductor structure includes: providing a layer to be etched; forming a core layer on the layer to be etched, the core layer having a plurality of first openings exposing a portion of the surface of the layer to be etched; forming a sacrificial layer within the first openings, the sacrificial layer exposing the surface of the core layer and having a surface flush with the surface of the core layer, the sacrificial layer being made of a different material than the core layer and also different from the material of the surface of the layer to be etched; forming a pad material layer on the sacrificial layer and the core layer; and forming a patterned layer on the pad material layer, the patterned layer exposing a portion of the surface of the pad material layer. The semiconductor structure formed by this method exhibits improved performance.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a method for forming a semiconductor structure. Background Technology

[0002] Currently, in the back end of line (BEOL) process of semiconductor devices, after the semiconductor device layer is formed, a metal interconnect layer needs to be formed on top of the semiconductor device layer. Each metal interconnect layer includes metal interconnects and an inter-layer dielectric (ILD). This requires the fabrication of trenches and vias in the inter-layer dielectric layer, and then the deposition of metal in the trenches and vias. The deposited metal is the metal interconnect.

[0003] However, there are still some issues that need to be addressed in the manufacturing process of the grooves and connecting holes. Summary of the Invention

[0004] The technical problem solved by this invention is to provide a method for forming a semiconductor structure to improve the performance of the semiconductor structure.

[0005] To address the aforementioned technical problems, the present invention provides a method for forming a semiconductor structure, comprising: providing a layer to be etched; forming a core layer on the layer to be etched, the core layer having a plurality of first openings, the first openings exposing a portion of the surface of the layer to be etched; forming a sacrificial layer within the first openings, the sacrificial layer exposing the surface of the core layer, and the surface of the sacrificial layer being flush with the surface of the core layer, the material of the sacrificial layer being different from the material of the core layer, and the material of the sacrificial layer being different from the material of the surface of the layer to be etched; forming a pad material layer on the sacrificial layer and the core layer; and forming a patterned layer on the pad material layer, the patterned layer exposing a portion of the surface of the pad material layer.

[0006] Optionally, before forming the sacrificial layer within the first opening, the method further includes: forming a sidewall on the sidewall of the first opening; the material of the sidewall is different from the material of the core layer, the material of the sidewall is different from the material of the surface of the layer to be etched, and the material of the sidewall is different from the material of the sacrificial layer.

[0007] Optionally, the method further includes: etching the pad material layer using the patterned layer as a mask until a portion of the core layer surface or a portion of the sacrificial layer surface is exposed to form a mask structure, the mask structure including a pad layer and a patterned layer located on the pad layer; etching the exposed core layer surface or a portion of the sacrificial layer surface using the mask structure as a mask to form a second opening within the core layer or the sacrificial layer; forming a fill layer within the second opening; removing the sacrificial layer after forming the fill layer; and removing a portion of the core layer after removing the sacrificial layer.

[0008] Optionally, the process for removing the sacrificial layer includes a dry etching process or a wet etching process.

[0009] Optionally, the etching rate of the sacrificial layer is greater than the etching rate of the core layer; the etching rate of the sacrificial layer is greater than the etching rate of the sidewall; and the etching rate of the sacrificial layer is greater than the etching rate of the surface material of the layer to be etched.

[0010] Optionally, before forming the patterned layer on the pad material layer, the method further includes: forming an anti-reflective material layer on the pad material layer; etching the anti-reflective material layer while etching the pad material layer using the patterned layer as a mask; the mask structure further includes an anti-reflective layer located between the pad material layer and the patterned layer.

[0011] Optionally, the material of the filling layer is the same as the material of the sidewall.

[0012] Optionally, it also includes: after removing part of the core layer, etching the layer to be etched using the core layer, sidewalls, and filler layer as a mask.

[0013] Optionally, the layer to be etched includes a substrate, the substrate including: a base; a device layer on the base, the device layer including an isolation structure and a device structure within the isolation structure, the device structure including a transistor, diode, triode, capacitor, inductor or conductive structure; a conductive layer on the device layer, the conductive layer being electrically connected to the device structure; the conductive layer is etched using the core layer, sidewalls and filler layer as masks until the surface of the device layer is exposed.

[0014] Optionally, the layer to be etched further includes: a first stop layer on the substrate; a hard mask layer on the first stop layer; a second stop layer on the hard mask layer; and etching the second stop layer, the hard mask layer, the first stop layer, and the conductive layer using the core layer, sidewalls, and filler layer as masks until the surface of the device layer is exposed.

[0015] Optionally, the sidewall material includes oxides of titanium or oxides of tantalum.

[0016] Optionally, the method for forming the sacrificial layer includes: forming a sacrificial material layer inside the first opening and on the core layer; planarizing the sacrificial material layer until the surface of the core layer is exposed, thereby forming the sacrificial layer.

[0017] Optionally, the material of the sacrificial layer includes a dielectric material, which includes silicon nitride or silicon oxide.

[0018] Optionally, the core layer is made of silicon; the surface of the layer to be etched is made of a dielectric material, which may be silicon nitride or silicon oxide.

[0019] Optionally, the material of the liner layer includes organic materials, including amorphous carbon or amorphous silicon.

[0020] Optionally, the process for forming the liner material layer includes a spin coating process.

[0021] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0022] The formation method in the technical solution of the present invention involves first forming a sacrificial layer within a first opening, and then forming a pad material layer on the sacrificial layer and the core layer. Since the first opening contains a sacrificial layer, the sacrificial layer and the core layer form a flat surface. The surface of the pad material layer formed on the sacrificial layer and the core layer is also relatively flat. Therefore, the dimensional accuracy of the patterned layer formed on the pad material layer is high, which is beneficial for improving the performance of the semiconductor structure. Attached Figure Description

[0023] Figure 1 and Figure 2 This is a schematic diagram of the semiconductor structure formation process in one embodiment;

[0024] Figures 3 to 12 This is a schematic diagram of the semiconductor structure formation process in one embodiment. Detailed Implementation

[0025] As described in the background section, the manufacturing process for trenches and connecting holes still needs improvement. This will now be analyzed and explained in conjunction with specific embodiments.

[0026] Figure 1 and Figure 2 This is a schematic diagram of the semiconductor structure formation process in one embodiment.

[0027] Please refer to Figure 1 The method includes: providing a layer 100 to be etched; forming a first stop layer 101 on the layer 100 to be etched; forming a hard mask layer 102 on the first stop layer 101; forming a second stop layer 103 on the hard mask layer 102; forming a core layer 104 and a plurality of first openings 106 located in the core layer 104 on the second stop layer 103; and forming a sidewall 105 on the sidewall of the core layer 104.

[0028] Please refer to Figure 2 A padding layer 107 is formed within the first opening 106, on the core layer 104, and on the sidewall 105. The padding layer 107 is used to planarize the surfaces of the first opening 106, the core layer 104, and the sidewall 105, providing a smooth surface for the subsequent formation of a patterned photoresist layer, thereby ensuring the pattern accuracy of the formed photoresist layer.

[0029] After forming the pad layer 107, the process further includes: forming an anti-reflective layer (not shown) on the pad layer 107; forming a patterned photoresist layer (not shown) on the anti-reflective layer; subsequently etching the anti-reflective layer, the pad layer 107, and the core layer 104 using the patterned photoresist layer as a mask, forming a second opening (not shown) within the core layer 104; and forming a fill layer (not shown) within the second opening. The fill layer, the core layer 104, and the sidewalls 105 together serve as a pattern transfer to the layer 100 to be etched.

[0030] During the formation of the semiconductor structure, the material of the pad layer 107 includes an organic material, which includes amorphous carbon. The process of forming the pad layer 107 includes spin coating, leveling, and curing. During the curing process, some organic solvents in the pad layer 107 will evaporate.

[0031] Because the core layer 104 has several first openings 106, the amount of the padding layer 107 differs between regions with densely packed first openings 106 and regions with sparsely packed first openings 106. The densely packed first openings 106 regions have a larger amount of padding layer 107, resulting in greater evaporation of organic solvents during curing. This leads to uneven wear of the padding layer 107 between the dense and sparse regions, resulting in an uneven surface of the cured padding layer 107. Consequently, when an anti-reflective layer and a photoresist layer are subsequently formed on the padding layer 107, the pattern accuracy of the formed photoresist layer is poor, affecting the dimensional accuracy of the subsequently formed semiconductor structure and its performance.

[0032] To address the aforementioned problems, the present invention provides a method for forming a semiconductor structure. This method involves first forming a sacrificial layer within a first opening, and then forming a pad material layer on the sacrificial layer and a core layer. Because the first opening contains a sacrificial layer, the sacrificial layer and the core layer form a flat surface. The surface of the pad material layer formed on the sacrificial layer and the core layer is also relatively flat. Therefore, the dimensional accuracy of the patterned layer formed on the pad material layer is high, which is beneficial for improving the performance of the semiconductor structure.

[0033] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0034] Figures 3 to 12 This is a schematic diagram of the semiconductor structure formation process in one embodiment.

[0035] Please refer to Figure 3 Provides the layer to be etched.

[0036] The layer to be etched includes a substrate 200, which includes: a base (not shown); a device layer (not shown) on the base, the device layer including an isolation structure and a device structure located within the isolation structure, the device structure including transistors, diodes, triodes, capacitors, inductors or conductive structures, etc.; and a conductive layer (not shown) on the device layer, the conductive layer being electrically connected to the device structure.

[0037] In this embodiment, the substrate is made of silicon.

[0038] In other embodiments, the substrate material includes silicon carbide, silicon germanium, a multi-element semiconductor material composed of group III-V elements, silicon-on-insulator (SOI), or germanium-on-insulator (GOI). The multi-element semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP.

[0039] In this embodiment, the layer to be etched further includes: a first stop layer 201 located on the substrate; a hard mask layer 202 located on the first stop layer 201; and a second stop layer 203 located on the hard mask layer 202.

[0040] The material of the first stop layer 201 is different from the material of the hard mask layer 202; the material of the hard mask layer 202 is different from the material of the second stop layer 203.

[0041] The first stop layer 201 is used as an etch stop layer for subsequent etching of the hard mask layer 202; the second stop layer 203 is used as an etch stop layer for subsequent etching of the core layer.

[0042] In this embodiment, the material of the first stop layer 201 includes silicon oxide; the material of the hard mask layer 202 includes titanium nitride, titanium oxide, tantalum nitride, or tantalum oxide; and the material of the second stop layer 203 includes silicon oxide or silicon nitride.

[0043] Please refer to Figure 4 and Figure 5 , Figure 4 for Figure 5 A schematic diagram of the cross-sectional structure along section line AA1. Figure 5 for Figure 4 The top view shows a core layer 204 formed on the layer to be etched, the core layer 204 having a plurality of first openings 205, the first openings 205 exposing a portion of the surface of the layer to be etched.

[0044] The method for forming the first opening 205 includes: forming a core material layer (not shown) on the layer to be etched; forming a patterned first mask layer (not shown) on the core material layer; etching the core material layer using the patterned first mask layer as a mask until the surface of the layer to be etched is exposed, thereby forming the core layer 204 and the first opening 205 located within the core layer 204.

[0045] The material of the core layer 204 is different from the material of the surface of the layer to be etched, and the material of the core layer 204 is different from the material of the sidewalls subsequently formed. Because the material of the core layer 204 is different from the material of the surface of the layer to be etched, the etching process can stop at the surface of the layer to be etched when the core material layer is etched.

[0046] In this embodiment, the core layer 204 is made of silicon.

[0047] Please continue to refer to this. Figure 4 and Figure 5 A sidewall 206 is formed on the sidewall of the first opening 205.

[0048] The method for forming the sidewall 206 includes: forming a sidewall material layer (not shown) on the bottom surface and sidewall surface of the first opening 205 and the top surface of the core layer 204; and etching the sidewall material layer back until the surface of the core layer 204 and the surface of the layer to be etched at the bottom of the first opening 205 are exposed, thereby forming the sidewall 206.

[0049] The material of the sidewall 206 is different from the material of the core layer 204, and the material of the surface of the layer to be etched is different, that is, the material of the sidewall 206 is different from the material of the second stop layer 203. The material of the sidewall 206 is also different from the material of the sacrificial layer subsequently formed.

[0050] In this embodiment, the material of the sidewall 204 includes titanium oxide or tantalum oxide.

[0051] Please refer to Figure 6 and Figure 7 , Figure 6 for Figure 7 A schematic diagram of the cross-sectional structure along section line BB1. Figure 7 for Figure 6 A top view shows that a sacrificial layer 207 is formed within the first opening 205, the sacrificial layer 207 exposing the surface of the core layer 204, and the surface of the sacrificial layer 207 is flush with the surface of the core layer 204.

[0052] The method for forming the sacrificial layer 207 includes: forming a sacrificial material layer (not shown) inside the first opening 205 and on the core layer 204; planarizing the sacrificial material layer until the surface of the core layer 204 is exposed, thereby forming the sacrificial layer 207.

[0053] The material of the sacrificial layer 207 is different from the material of the core layer 204, and the material of the sacrificial layer 207 is different from the material of the surface of the layer to be etched, that is, the material of the sacrificial layer 207 is different from the material of the second stop layer 203.

[0054] In this embodiment, the material of the sacrificial layer 207 includes a dielectric material, which includes silicon nitride or silicon oxide.

[0055] A sacrificial layer 207 is formed within the first opening 205. The sacrificial layer 207 and the core layer 204 form a flat surface. The surface of the pad material layer subsequently formed on the sacrificial layer 207 and the core layer 204 is also relatively flat. Therefore, the dimensional accuracy of the patterned layer formed on the pad material layer is high, which is beneficial to improving the performance of the semiconductor structure.

[0056] Please refer to Figure 8 , Figure 8 In order to be in Figure 6 The schematic diagram shows that a padding material layer 208 is formed on the sacrificial layer 207 and the core layer 204.

[0057] The material of the liner layer 208 includes organic materials, including amorphous carbon or amorphous silicon.

[0058] The process for forming the gasket material layer 208 includes a spin coating process.

[0059] Please continue to refer to this. Figure 8 An antireflective material layer 209 is formed on the padding material layer 208; a patterned layer 210 is formed on the antireflective material layer 209, the patterned layer 210 exposing a portion of the surface of the sacrificial layer 207 or a portion of the surface of the antireflective material layer 209 on the core layer 204 between adjacent first openings 205.

[0060] The antireflective material layer 209 includes: a thin silicon antireflective layer (Si-ARC), an organic material bottom antireflective layer (organic BARC), a dielectric antireflective layer (DARC), or a combination of an organic bottom antireflective layer and a dielectric antireflective layer.

[0061] The material of the patterning layer 210 includes photoresist.

[0062] First, a sacrificial layer 207 is formed in the first opening 205. The sacrificial layer 207 and the core layer 204 form a flat surface, so the surface of the pad material layer 208 formed on the sacrificial layer 207 and the core layer 204 is also relatively flat. Therefore, the patterned layer 210 formed on the pad material layer 208 has high dimensional accuracy, which is beneficial to improving the performance of the semiconductor structure.

[0063] Please refer to Figure 9 and Figure 10 , Figure 9 for Figure 10 A schematic diagram of the cross-sectional structure along the section line CC1. Figure 10 for Figure 9 A top view, with the graphical layer 210 (such as...) Figure 8 As shown, the antireflective material layer 209 and the padding material layer 208 are etched using a mask until a portion of the surface of the core layer 204 or a portion of the surface of the sacrificial layer 207 is exposed, forming a mask structure.

[0064] In this embodiment, the mask structure includes a pad layer 211, an anti-reflective layer 212 on the pad layer 211, and a patterned layer 210 on the anti-reflective layer 212. The patterned layer 210 is naturally consumed during the etching of the anti-reflective material layer 209 and the pad material layer 208.

[0065] The etching process for the anti-reflective material layer 209 and the pad material layer 208 includes a dry etching process. The dry etching process can form a mask structure with good sidewall morphology and high dimensional accuracy, which is beneficial for the subsequent formation of a semiconductor structure with good dimensional accuracy.

[0066] Please refer to Figure 11 and Figure 12 , Figure 11 for Figure 12 A schematic diagram of the cross-sectional structure along section line DD1. Figure 12 for Figure 11 A top view shows the core layer 204 surface or part of the sacrificial layer 207 surface exposed by etching with the mask structure as a mask, forming a second opening (not shown) in the core layer 204 and the sacrificial layer 207; a filling layer 213 is formed in the second opening, the filling layer 213 being located between adjacent sidewalls 206.

[0067] In this embodiment, the filler layer 213 is located within the sacrificial layer 207 and the core layer 204. One filler layer 213 penetrates the sacrificial layer 207 along a first direction Y parallel to the substrate surface, and another filler layer 213 penetrates the core layer 204 located between adjacent first openings 205 along the first direction Y.

[0068] In other embodiments, the filler layer penetrates the sacrificial layer along a first direction Y parallel to the substrate surface, or the filler layer penetrates the core layer located between adjacent first openings along the first direction Y.

[0069] The method of forming a filler layer 213 within the second opening includes: forming a filler material layer (not shown) within the second opening; planarizing the filler material layer until the surface of the core layer 204 is exposed; and forming the filler layer 213 within the sacrificial layer 207 and the core layer 204.

[0070] The material of the filler layer 213 is the same as that of the sidewall 206, but different from that of the sacrificial layer 207 and the core layer 204. Therefore, the filler layer 213 suffers less damage when the sacrificial layer 207 is subsequently removed.

[0071] In this embodiment, the material of the filling layer 213 includes titanium oxide or tantalum oxide.

[0072] Please continue to refer to this. Figure 11 and Figure 12 After the filling layer 213 is formed, the sacrificial layer 207 is removed, exposing the first opening 205.

[0073] The process for removing the sacrificial layer 207 includes a dry etching process or a wet etching process.

[0074] The etching rate of the sacrificial layer 207 is greater than that of the core layer 204; the etching rate of the sacrificial layer 207 is greater than that of the sidewall 206; and the etching rate of the sacrificial layer 207 is greater than that of the surface material of the layer to be etched. Therefore, when removing the sacrificial layer 207, the removal process causes minimal damage to the core layer 204, the sidewall 206, and the surface to be etched.

[0075] Please continue to refer to this. Figure 11 and Figure 12 After removing the sacrificial layer 207, a portion of the core layer 204 is removed, forming a third opening (not shown) within the core layer 204. The third opening is located between two adjacent first openings 205 and exposes the sidewall 206 of the sidewall of the first opening 205 and the filling layer 213 within the core layer 204.

[0076] The method for removing part of the core layer 204 includes: forming a patterned second mask layer (not shown) on the core layer 204, the patterned second mask layer exposing part of the surface of the core layer 204; etching the core layer 204 with the patterned second mask layer as a mask until the surface of the layer to be etched is exposed.

[0077] The etching process for the core layer 204 includes a dry etching process or a wet etching process.

[0078] The material of the core layer 204 is different from the material of the surface of the layer to be etched, the material of the core layer 204 is different from the material of the sidewall 206, and the material of the fill layer 213. Therefore, when etching the core layer 204, the etching process can stop on the layer to be etched, while minimizing damage to the surface of the layer to be etched, the sidewall 206, and the fill layer 213, thus avoiding affecting the dimensional accuracy of the formed semiconductor structure pattern.

[0079] In this embodiment, after removing part of the core layer 204, the method further includes etching the layer to be etched using the core layer 204, sidewalls 206, and filler layer 213 as a mask.

[0080] The method of etching the layer to be etched using the core layer 204, sidewall 206 and filling layer 213 as a mask includes: etching the second stop layer 203, hard mask layer 202, first stop layer 201 and conductive layer using the core layer 204, sidewall 206 and filling layer 213 as a mask until the surface of the device layer is exposed.

[0081] The process of etching the layer to be etched using the core layer 204, sidewall 206 and filling layer 213 as a mask includes a dry etching process. The dry etching process can form a semiconductor structure with good sidewall morphology and high dimensional accuracy, thereby improving the performance of the semiconductor structure.

[0082] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: Provide the layer to be etched; A core layer is formed on the layer to be etched, and the core layer has a plurality of first openings, the first openings exposing a portion of the surface of the layer to be etched. A sidewall is formed on the sidewall of the first opening; A sacrificial layer is formed within the first opening, the sacrificial layer exposing the surface of the core layer and being flush with the surface of the core layer. The material of the sacrificial layer is different from the material of the core layer and different from the material of the surface of the layer to be etched. A padding material layer is formed on the sacrificial layer and the core layer; A patterned layer is formed on the padding material layer, the patterned layer exposing a portion of the surface of the padding material layer; The padding material layer is etched using the patterned layer as a mask until a portion of the core layer surface or a portion of the sacrificial layer surface is exposed, forming a mask structure. The core layer surface or part of the sacrificial layer surface exposed by etching with the mask structure as a mask is formed in one or both of the core layer and the sacrificial layer. A filling layer is formed in the second opening. When the second opening is located in the sacrificial layer, the filling layer penetrates the sacrificial layer in a first direction parallel to the substrate surface. When the second opening is located in the core layer, the filling layer penetrates the core layer located between adjacent first openings in the first direction. The filling layer is in contact with the sidewall, and the material of the filling layer is the same as the material of the sidewall. After the filler layer is formed, the sacrificial layer is removed; After removing the sacrificial layer, a portion of the core layer is removed.

2. The method for forming a semiconductor structure as described in claim 1, characterized in that, The sidewall material is different from the core layer material, the sidewall material is different from the surface material of the layer to be etched, and the sidewall material is different from the sacrificial layer material.

3. The method for forming a semiconductor structure as described in claim 1, characterized in that, The mask structure includes a padding layer and a patterned layer located on the padding layer.

4. The method for forming a semiconductor structure as described in claim 3, characterized in that, The process for removing the sacrificial layer includes dry etching or wet etching.

5. The method for forming a semiconductor structure as described in claim 4, characterized in that, The etching rate of the sacrificial layer is greater than that of the core layer; the etching rate of the sacrificial layer is greater than that of the sidewall; and the etching rate of the sacrificial layer is greater than that of the surface material of the layer to be etched.

6. The method for forming a semiconductor structure as described in claim 3, characterized in that, Before forming the patterned layer on the padding material layer, the method further includes: forming an anti-reflective material layer on the padding material layer; etching the anti-reflective material layer while using the patterned layer as a mask to etch the padding material layer; the mask structure further includes an anti-reflective layer located between the padding layer and the patterned layer.

7. The method for forming a semiconductor structure as described in claim 3, characterized in that, Also includes: After removing part of the core layer, the core layer, sidewalls, and filler layer are used as masks to etch the layer to be etched.

8. The method for forming a semiconductor structure as described in claim 7, characterized in that, The layer to be etched includes a substrate, the substrate including: a base; a device layer on the base, the device layer including an isolation structure and a device structure within the isolation structure, the device structure including a transistor, diode, triode, capacitor, inductor or conductive structure; a conductive layer on the device layer, the conductive layer being electrically connected to the device structure; the conductive layer is etched using the core layer, sidewalls and filler layer as masks until the surface of the device layer is exposed.

9. The method for forming a semiconductor structure as described in claim 8, characterized in that, The layer to be etched further includes: a first stop layer on the substrate; a hard mask layer on the first stop layer; a second stop layer on the hard mask layer; and etching the second stop layer, the hard mask layer, the first stop layer, and the conductive layer using the core layer, sidewalls, and filler layer as masks until the surface of the device layer is exposed.

10. The method for forming a semiconductor structure as described in claim 2, characterized in that, The sidewalls are made of oxides of titanium or tantalum.

11. The method for forming a semiconductor structure as described in claim 1, characterized in that, The method for forming the sacrificial layer includes: forming a sacrificial material layer inside the first opening and on the core layer; planarizing the sacrificial material layer until the surface of the core layer is exposed, thereby forming the sacrificial layer.

12. The method for forming a semiconductor structure as described in claim 11, characterized in that, The material of the sacrificial layer includes a dielectric material, which includes silicon nitride or silicon oxide.

13. The method for forming a semiconductor structure as described in claim 1, characterized in that, The core layer is made of silicon; the surface of the layer to be etched is made of a dielectric material, which includes silicon nitride or silicon oxide.

14. The method for forming a semiconductor structure as described in claim 1, characterized in that, The material of the liner layer includes organic materials, including amorphous carbon or amorphous silicon.

15. The method for forming a semiconductor structure as described in claim 14, characterized in that, The process for forming the gasket material layer includes a spin coating process.

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