Interconnect structures and methods of forming the same

Abstract

The present application relates to interconnect structures and methods of forming the same. A method of manufacturing an interconnect structure includes forming an opening through a dielectric layer. The opening exposes a top surface of a first conductive feature. The method also includes forming a barrier layer on sidewalls of the opening, passivating the exposed top surface of the first conductive feature with a treatment process, forming a liner layer over the barrier layer, and filling the opening with a conductive material. The liner layer can include ruthenium.

Claims

1. A method for manufacturing a structure, the method comprising: An opening is formed through the dielectric layer, which exposes the top surface of the first conductive feature; A sacrificial layer is formed on the exposed top surface of the first conductive feature; A barrier layer is formed on the sidewalls and bottom surface of the opening, wherein the formation of the barrier layer on a portion of the bottom surface of the opening is discontinuous; After the barrier layer is formed, the sacrificial layer is removed; The exposed top surface of the first conductive feature is passivated using a processing technology; A lining layer comprising ruthenium is formed on top of the barrier layer; and The opening is filled with a conductive material.

2. The method according to claim 1, wherein, The processing technology is plasma treatment including H2.

3. The method according to claim 2, wherein, The plasma treatment was performed for a period ranging from 10 seconds to 2 minutes.

4. The method according to claim 2, wherein, The plasma treatment uses a power supply in the range of 100 W to 800 W.

5. The method according to claim 1, wherein, Forming the lining layer includes: An outer liner layer, which is ruthenium, is formed over the exposed top surface of the barrier layer and the first conductive feature; and An inner lining layer, which is cobalt, is formed on top of the outer lining.

6. The method according to claim 5, further comprising: A capping layer, which is cobalt, is formed on the conductive material.

7. The method according to claim 1, wherein, Forming the lining layer includes forming a composite lining layer on the sidewall of the barrier layer, the composite lining layer comprising a mixture of ruthenium and cobalt.

8. The method according to claim 7, wherein, Forming the combined lining layer includes performing a hydrogen immersion treatment on a ruthenium layer and a cobalt layer, the cobalt layer being located on the ruthenium layer.

9. A method for manufacturing a structure, the method comprising: An etch stop layer ESL is formed on the interconnect layer, the interconnect layer including a first conductive feature; Deposit a dielectric layer on the ESL; Trenches are formed in the dielectric layer; A hole is formed that penetrates the dielectric layer and the ESL into the first conductive feature, wherein the bottom surface of the hole exposes the conductive filling layer of the first conductive feature; and Forming a second conductive feature includes: A barrier layer is deposited on the sidewalls of the hole and on the sidewalls and bottom surface of the trench; After depositing the barrier layer, plasma treatment is performed on the exposed top surface of the conductive filler layer; An outer liner comprising ruthenium is conformally formed in the holes and the grooves; An inner lining is formed on the outer lining; and A conductive filler layer is formed on the inner lining.

10. The method according to claim 9, wherein, Forming the inner lining further includes forming an upper portion of the inner lining on the top surface of the conductive filler layer.

11. The method according to claim 9, wherein, The plasma treatment includes H2.

12. The method according to claim 9, wherein, The plasma treatment is performed at a power range of 100 W to 800 W.

13. The method according to claim 9, wherein, The plasma treatment was performed for a duration ranging from 10 seconds to 2 minutes.

14. The method according to claim 9, wherein, Forming the barrier layer further includes forming a bottom of the barrier layer on the bottom surface of the second conductive feature, wherein the bottom of the barrier layer is discontinuous.

15. The method according to claim 14, wherein, The thickness of the bottom of the barrier layer is in the range of 3 Å to 8 Å.

16. The method according to claim 9, wherein, The thickness of the outer lining is in the range of 5 Å to 15 Å.

17. The method according to claim 9, wherein, The thickness of the inner lining is in the range of 5 Å to 15 Å.

18. A semiconductor structure comprising: First electrical conductivity characteristic; A dielectric layer on the first conductive feature; as well as The second conductive feature, in the dielectric layer, includes: A barrier layer, at least a portion of which is a sidewall of the second conductive feature, wherein the bottom of the barrier layer is on the bottom surface of the second conductive feature, and the bottom of the barrier layer is discontinuous; A liner layer, on the barrier layer, which is in contact with at least a portion of the first conductive feature; and A conductive filler layer is provided on the lining layer.

19. The semiconductor structure according to claim 18, wherein, The lining layer comprises: A composite liner layer, along the sidewalls of the barrier layer, comprises a mixture of ruthenium and cobalt; The outer lining portion, on the bottom surface of the second conductive feature, is ruthenium; and The inner lining portion is cobalt, which is located on the outer lining portion.

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