Preparation method of a novel integrated low leakage current voltage regulator diode

Abstract

A preparation method for a novel integrated low-leakage voltage regulator diode. It relates to semiconductor devices. The method includes the following steps: S001: Selection of N+ substrate; according to the breakdown voltage requirements of different products, select N+ substrate silicon wafers with different resistivity; S002: Boron pre-deposition and diffusion in the P region; deposit boron impurities on the surface of the N+ substrate, and through high-temperature diffusion, divide the N+ substrate silicon wafer into a P region and a collector region; S003: Oxidation; grow an oxide film on the wafer surface; S004: Selective photolithography of the first positive N+ region to be diffused: reserve the region where the emitter region is to be prepared on the upper surface of the P region, and protect the rest with photoresist; S005: Removal of the oxide film: remove the oxide film above the emitter region to be prepared, exposing the emitter region to be diffused on the front side; The present invention realizes the functions of a voltage regulator diode with low reverse leakage current, low power consumption and high reliability.

Description

Technical Field

[0001] The present invention relates to semiconductor devices, and particularly to a preparation method of a novel integrated low leakage current voltage regulator diode. Background Art

[0002] A voltage regulator diode is a diode that utilizes the reverse breakdown state of a PN junction, where the current can vary within a large range while the voltage remains basically unchanged, to achieve a voltage regulation function. Since the breakdown of the voltage regulator diode is Zener breakdown, it is also called a Zener diode. A voltage regulator diode is a semiconductor device that has a very high resistance until the critical reverse breakdown voltage. It is widely used in surge protection circuits, overvoltage protection circuits, arc suppression circuits, and voltage regulation circuits.

[0003] In the era of global Internet electronics and the popularization and application of household electronic products, the market has an increasing demand for voltage regulator diodes. Integrated circuit products have higher requirements for the quality of low-voltage voltage regulator diode chips. In today's increasingly competitive semiconductor market, it is necessary to improve the voltage regulation accuracy while also imposing more stringent requirements on the leakage current. Traditional low-voltage voltage regulator diodes generally work based on the Zener breakdown principle and are fabricated using wafers with relatively low resistivity. The main problems are as follows:

[0004] 1) The reverse leakage current of such devices is very large, increasing the power consumption of the circuit in applications and unable to meet the requirements of circuits with low power consumption.

[0005] 2) When operating in the reverse direction, the carrier mobility of wafers with low resistivity is relatively low, resulting in poor reverse performance of the device and affecting the product reliability, leading to a decline in product quality. Summary of the Invention

[0006] The present invention addresses the above problems and provides a preparation method of a novel integrated low leakage current voltage regulator diode that can reduce the leakage current of the voltage regulator diode product and has stable reliability.

[0007] The technical solution of the present invention is: A preparation method of a novel integrated low leakage current voltage regulator diode, comprising the following steps:

[0008] S001: Selection of N+ substrate;

[0009] According to the breakdown voltage requirements of different products, select N+ substrate silicon wafers with different resistivities;

[0010] S002: Boron pre-deposition and diffusion in the P region;

[0011] Deposit boron impurities on the surface of the N+ substrate, and divide the N+ substrate silicon wafer into a P region and a collector region through high-temperature diffusion;

[0012] S003: Oxidation;

[0013] Grow an oxide film on the surface of the wafer;

[0014] S004: Selective Lithography for the First Positive N+ Region to be Diffused:

[0015] Reserve the area for the emitter region to be fabricated on the upper surface of the P region, and protect the rest with photoresist;

[0016] S005: Removal of Oxide Film:

[0017] Remove the oxide film above the emitter region to be fabricated, exposing the emitter region to be diffused on the front side;

[0018] S006: Phosphorus Predeposition in N+ Region:

[0019] Remove the photoresist, deposit phosphorus impurities on the surface of the emitter region to be fabricated, and push the phosphorus junction forward through high-temperature diffusion to fabricate the emitter region;

[0020] When the phosphorus junction is pushed forward by high-temperature diffusion, an attached oxide layer is generated at the top of the emitter region;

[0021] S007: Second Selective Lithography;

[0022] Divide the wafer into several single grains, and expose the area to be etched on the grain surface, protecting other areas with photoresist;

[0023] S008: Removal of Oxide Film;

[0024] Use BOE to remove the oxide film to be etched and the attached oxide layer to be etched, exposing the Si on the surface of the area to be etched;

[0025] S009: Trench Etching;

[0026] Etch the Si exposed on the grain surface to form an outer etch opening extending to the collector region and an inner etch trench respectively, and remove the photoresist on the grain surface;

[0027] S010: Remove the oxide film and the attached oxide layer on the grain surface;

[0028] S011: SIPOS and Glass Passivation:

[0029] Deposit a layer of SIPOS film on the wafer surface; then use the knife scraping method to fill a layer of glass powder in the outer etch opening and the inner etch trench, and melt the glass powder through a high-temperature furnace to convert the glass powder inside the outer etch opening and the inner etch trench into glass to protect the PN junction;

[0030] S012: LTO Film Passivation;

[0031] Deposit a layer of oxide film passivation layer on the wafer surface by the LPCVD method;

[0032] S013: Remove the oxide layer on the electrode surface with three times of yellow light;

[0033] Retain the oxide film passivation layer between the top of the outer etching port glass area and the top of the emission area, and remove the rest;

[0034] S014: Metal evaporation: Evaporate Ag metal on both sides;

[0035] S015: Electrode surface lithography: Selective lithography to remove the metal on the glass layer and the cutting channel surface; S017: Metal corrosion: Corrode and remove the metal exposed on the wafer surface with metal corrosion liquid.

[0036] Furthermore, in step S009, the Si exposed on the grain surface is etched with a mixed acid.

[0037] Furthermore, the mixed acid includes nitric acid, hydrofluoric acid and acetic acid.

[0038] Furthermore, the ratio of the nitric acid, hydrofluoric acid and acetic acid is 2:1:1, 5:3:3 or 9:9:7.

[0039] Furthermore, in step S009, the depth ranges of the outer etching port and the inner etching groove are 8 - 22 um respectively.

[0040] This case provides a new type of integrated low leakage current voltage regulator that can reduce the leakage current of voltage regulator products. By introducing a triode into the structure of an ordinary voltage regulator diode, that is, integrating the diode and the triode into the same structure, this integrated structure changes the working principle of the voltage regulator from the original Zener breakdown to avalanche breakdown, realizing the functions of a voltage regulator device with low reverse leakage current, low power consumption and high reliability. Description of the Drawings

[0041] Figure 1 is a schematic structural diagram of step S001 of the present invention,

[0042] Figure 2 is a schematic structural diagram of step S002 of the present invention,

[0043] Figure 3 is a schematic structural diagram of step S003 of the present invention,

[0044] Figure 4 is a schematic structural diagram of step S004 of the present invention,

[0045] Figure 5 is a schematic structural diagram of step S005 of the present invention,

[0046] Figure 6 is a schematic structural diagram of step S006 of the present invention,

[0047] Figure 7It is a schematic structural diagram of step S007 of the present invention.

[0048] Figure 8 It is a schematic structural diagram of step S008 of the present invention.

[0049] Figure 9 It is a schematic structural diagram of step S009 of the present invention.

[0050] Figure 10 It is a schematic structural diagram of step S010 of the present invention.

[0051] Figure 11 It is a schematic structural diagram of step S011 of the present invention.

[0052] Figure 12 It is a schematic structural diagram of step S012 of the present invention.

[0053] Figure 13 It is a schematic structural diagram of step S013 of the present invention.

[0054] Figure 14 It is a schematic structural diagram of step S014 of the present invention.

[0055] Figure 15 It is a schematic structural diagram of step S015 of the present invention.

[0056] In the figure, 1 is the collector region, 2 is the anode region, 3 is the base region, 4 is the emitter region, 5 is the inner etched groove glass region, 6 is the outer etched opening glass region, 7 is the oxide film passivation layer, 8 is the front metal layer, and 9 is the back metal layer. Detailed implementation manners

[0057] The embodiments of the present invention will be described in detail below. The examples of the embodiments are shown in the accompanying drawings, where the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below by referring to the drawings are exemplary and are only used to explain the present invention and should not be construed as a limitation to the present invention.

[0058] Taking an NPN-type triode as an example, a novel integrated low-leakage voltage regulator diode includes:

[0059] A collector region 1, which is used to collect electrons and forms a collector junction of the triode with the P region;

[0060] A P region, which is formed above the collector region 1;

[0061] An inner etched groove glass region 5, which extends from the top of the P region into the collector region 1 and separates the P region into an anode region 2 and a base region 3;

[0062] The outer etching port glass region 6 is located outside the base region 3 and extends from the top of the base region 3 towards the collector region 1;

[0063] The inner etching groove glass region 5 is arranged in the inner etching groove; the outer etching port glass region 6 is arranged at the outer etching port; the inner etching groove and the outer etching port are respectively filled with glass powder, and the glass powder is melted by a high-temperature furnace to form the corresponding glass regions for protecting the PN junction;

[0064] The emitter region 4 extends downward from the top of the base region 3; and

[0065] The metal evaporation layer includes a front metal layer 8 arranged at the top and a back metal layer 9 arranged at the bottom of the collector region 1.

[0066] It is further defined that the cross-section of the inner etching groove glass region 5 is of a U-shaped structure.

[0067] It is further defined that the depth of the inner etching groove glass region 5 is 8 - 22 um. Since the etching groove needs to penetrate through the emitter region N+ junction and the base region P+, the etching depth is determined according to the differences in the emitter region N+ junction depth and the base region P+ junction width.

[0068] It is further extended that an oxide film passivation layer 7 is also included between the outer etching port glass region 6 and the emitter region 4. Through the oxide film passivation layer 7, not only can the solder paste be prevented from flowing onto the glass region during welding, but also the silicon at the connection between the glass region and the outer etching port can be protected.

[0069] It is further defined that the thickness of the oxide film passivation layer 7 is 3000 - 8000 angstroms. The width of the oxide layer is determined by the width of the outer etching port and the accuracy of the exposure machine, and the width is generally the width of the outer etching port + 1 mil (the width of the oxide film covering the silicon on the edge of the outer etching port is 1 mil).

[0070] A preparation method of a novel integrated low-leakage voltage regulator diode includes the following steps:

[0071] S001: Selection of N+ substrate;

[0072] Refer to Figure 1 As shown, according to the breakdown voltage requirements of different products, N+ substrate silicon wafers with different resistivities are selected;

[0073] S002: Boron pre-deposition and diffusion in the P region;

[0074] Refer to Figure 2 As shown, boron impurities are deposited on the surface of the N+ substrate, and through high-temperature diffusion, the N+ substrate silicon wafer is divided into the P region and the collector region 1;

[0075] S003: Oxidation;

[0076] Refer to Figure 3 As shown, grow an oxide film on the wafer surface (including the front and back sides);

[0077] S004: Selective lithography for the first positive N+ diffusion area to be diffused:

[0078] Refer to Figure 4 As shown, reserve the area for the emitter region to be prepared on the upper surface of the P region, and protect the rest with photoresist;

[0079] S005: Removal of the oxide film:

[0080] Refer to Figure 5 As shown, use BOE etching solution to remove the oxide film above the emitter region to be prepared, exposing the emitter region to be diffused on the front side;

[0081] S006: Phosphorus pre-deposition in the N+ region:

[0082] Refer to Figure 6 As shown, remove the photoresist, deposit phosphorus impurities on the surface of the emitter region to be prepared, and push the phosphorus junction through high-temperature diffusion to prepare the emitter region;

[0083] When the phosphorus junction is pushed through high-temperature diffusion, since the silicon wafer is in an oxygen-containing atmosphere, an attached oxide layer will be generated on the top of the emitter region;

[0084] S007: Second selective lithography;

[0085] Refer to Figure 7 As shown, divide the wafer area into several single grains of the required size, and expose the area to be etched on the grain surface, and protect other areas with photoresist;

[0086] S008: Removal of the oxide film;

[0087] Refer to Figure 8 As shown, use BOE to remove the oxide film to be etched and the attached oxide layer to be etched, exposing the Si on the surface of the area to be etched;

[0088] S009: Trench etching;

[0089] Refer to Figure 9 As shown, etch the Si exposed on the grain surface through a mixed acid to form an outer etch opening and an inner etch trench extending to the collector region 1 respectively, and remove the photoresist on the grain surface; the depth range of the outer etch opening and the inner etch trench is 8 - 22 um, the width of the inner etch trench is 50 - 100 um, and the width of the outer etch opening is generally 180 - 230 um;

[0090] Select different etching acids (the above-mentioned mixed acid) and operating conditions according to the actual aspect ratio requirements;

[0091] 1), The etching solution temperature is -6°C to 5°C, and the etching time is 150 - 300S;

[0092] 2), The ratio of the acidic etching solution is nitric acid: hydrofluoric acid: acetic acid = 2:1:1 or 5:3:3 or 9:9:7, etc., all containing nitric acid, HF, glacial acetic acid, etc. (glacial acetic acid mainly provides H ions and has a certain buffering ability during silicon etching). The etching of the silicon wafer consists of two steps: the first step is the process of nitric acid oxidizing elemental silicon to silicon dioxide, and the second step is the process of hydrofluoric acid continuously dissolving the silicon dioxide formed on the silicon surface. During the etching process, HF and nitric acid are consumed in equal amounts, and the etching rate mainly depends on the content of nitric acid and HF in the etching solution. Generally, the concentration of nitric acid in the mixed acid is greater than that of HF. Therefore, when the content of HF is lacking, the etching rate is mainly determined by the content of HF. According to the aspect ratio requirements of different products, different amounts of HF are added: the more HF content, the smaller the aspect ratio, and the less HF content, the larger the aspect ratio.

[0093] S010: Refer to Figure 10 As shown, remove the oxide film and attached oxide layer on the grain surface;

[0094] S011: SIPOS and glass passivation:

[0095] Adopt the LPCVD method to deposit a layer of SIPOS (oxygen-doped semi-insulating polysilicon) film on the wafer surface to protect the PN junction from being contaminated; then use the knife scraping method to fill a layer of glass powder in the outer etching opening and the inner etching groove, and melt the glass powder through a high-temperature furnace to convert the glass powder inside the outer etching opening and the inner etching groove into glass to protect the PN junction; refer to Figure 11 As shown, the glass melting temperature is 640 - 830°C, and the time is 15 - 20min.

[0096] S012: LTO film passivation;

[0097] Refer to Figure 12 As shown, adopt the LPCVD (low-pressure chemical vapor deposition) method to deposit a layer of oxide film passivation layer 7 (LTO film) on the wafer surface, with a thickness of 3000 - 8000 Å;

[0098] The functions of the oxide film passivation layer 7 are mainly in two aspects:

[0099] 1. Prevent the solder paste from flowing onto the glass area during welding;

[0100] 2. Protect the silicon at the edge connection of the glass area and the inner etching groove (the glass is very thin at the top silicon of the inner etching groove during knife scraping).

[0101] S013: Remove the oxide layer on the electrode surface by three times of yellow light;

[0102] Refer toFigure 13 As shown, the oxide film passivation layer 7 between the top of the outer etching port glass area 6 and the top of the emission area is retained, and the rest is removed; the distance between the inner and outer diameters of the oxide film passivation layer 7 is 70 - 120um.

[0103] S014: Metal evaporation: Refer to Figure 14 As shown, deposit Ag metal on both sides;

[0104] S015: Electrode surface lithography: Selective lithography to remove the metal on the surface of the glass layer and the scribe lane (the scribe lane refers to the cutting line set when dividing the wafer into several grains); S017: Metal corrosion: Use metal etching solution to etch and remove the metal exposed on the surface of the wafer.

[0105] The working principle of the design in this case is briefly described as follows:

[0106] The basic structure of a conventional voltage - regulating diode is the same as that of an ordinary diode, having a PN junction, and mainly using the reverse working characteristic of the PN junction to achieve the voltage - regulating function. Since the voltage - regulating diode has a voltage - regulating effect, it is applied in many circuits, such as voltage - stabilizing power supplies, limiting circuits, over - voltage protection circuits, compensation circuits, etc. The working principle of the voltage - regulating diode of the present invention is as follows:

[0107] 1. When a forward voltage is applied to the front side, the middle region (PN) conducts forwardly, and the annular NPN is short - circuited;

[0108] 2. When a forward voltage is applied to the reverse side, the NP junction is reverse - biased, and the NPN is also reverse - biased. Since the voltage VB1 of the NP junction is higher than the voltage VB2 of the NPN (triode principle), the NP junction in the central region is short - circuited, and the annular NPN triode structure comes into play (the following formula is the triode amplification formula). By adjusting the diffusion concentration of the N + region, the width of the P region, etc., the amplification factor can be adjusted, and then the voltage of the NPN triode can be adjusted. Therefore, this structure can achieve a very low value with a high resistivity, and even a 1.8V product can be achieved.

[0109] VCEO = VCBO / (1 + β)1 / n (n generally takes 4 - 6).

[0110] Regarding the content disclosed in this case, the following points need to be explained:

[0111] (1). The attached drawings of the embodiments disclosed in this case only relate to the structures involved in the embodiments disclosed in this case, and other structures can refer to the general design;

[0112] (2). Without conflict, the embodiments disclosed in this case and the features in the embodiments can be combined with each other to obtain new embodiments;

[0113] The above is only the specific implementation manners disclosed in this case, but the protection scope of this disclosure is not limited thereto. The protection scope disclosed in this case shall be subject to the protection scope of the claims.

Claims

1. A preparation method of a novel integrated low leakage current voltage regulator diode, comprising the following steps: S001: Selection of N+ substrate; According to the breakdown voltage requirements of different products, select N+ substrate silicon wafers with different resistivity; S002: Boron pre-deposition and diffusion in P region; Deposit boron impurities on the surface of the N+ substrate, and divide the N+ substrate silicon wafer into P region and collector region through high-temperature diffusion; S003: Oxidation; Grow an oxide film on the wafer surface; S004: First positive N+ region to-be-diffused area selective photolithography: Reserve the area where the emitter region is to be prepared on the upper surface of the P region, and protect the rest with photoresist; S005: Removal of oxide film; Remove the oxide film above the emitter region to be prepared, exposing the emitter region to be diffused on the front side; S006: Phosphorus pre-deposition in N+ region: Remove the photoresist, deposit phosphorus impurities on the surface of the emitter region to be prepared, and push the phosphorus junction through high-temperature diffusion to prepare the emitter region; When the phosphorus junction is pushed by high-temperature diffusion, an attached oxide layer is generated at the top of the emitter region; S007: Second selective photolithography; Divide the wafer into several single grains, and expose the area to be etched on the surface of the grains, and protect other areas with photoresist; S008: Removal of oxide film; Use BOE to remove the oxide film to be etched and the attached oxide layer to be etched, exposing the Si on the surface of the area to be etched; S009: Groove etching; Etch the Si exposed on the surface of the grains to form an outer etching opening and an inner etching groove extending to the collector region respectively, and remove the photoresist on the surface of the grains; S010: Remove the oxide film and the attached oxide layer on the surface of the grains; S011: SIPOS and glass passivation: Deposit a layer of SIPOS film on the wafer surface; then use the knife scraping method to fill a layer of glass powder in the outer etching opening and the inner etching groove, and melt the glass powder through a high-temperature furnace to convert the glass powder inside the outer etching opening and the inner etching groove into glass to protect the PN junction; S012: LTO film passivation; Deposit an oxide film passivation layer on the wafer surface by the method of LPCVD; S013: Remove the oxide layer on the electrode surface by three times of yellow light; Reserve the oxide film passivation layer between the top of the glass area of the outer etching opening and the top of the emitter region, and remove the rest; S014: Metal evaporation: Evaporate Ag metal on both sides; S015: Electrode surface photolithography: Selective photolithography to remove the metal on the glass layer and the scribe line surface; S017: Metal corrosion: Corrode and remove the metal exposed on the wafer surface with metal corrosion solution.

2. The preparation method of a novel integrated low leakage current voltage regulator diode according to claim 1, characterized in that, In step S009, the Si exposed on the surface of the grains is etched by a mixed acid.

3. The preparation method of a novel integrated low leakage current voltage regulator diode according to claim 2, characterized in that, The mixed acid includes nitric acid, hydrofluoric acid and acetic acid.

4. The preparation method of a novel integrated low leakage current voltage regulator diode according to claim 3, characterized in that, The ratio of the nitric acid, hydrofluoric acid and acetic acid is 2:1:1, 5:3:3 or 9:9:

7.

5. The preparation method of a novel integrated low leakage current voltage regulator diode according to claim 1, characterized in that, In step S009, the depth ranges of the outer etching opening and the inner etching groove are 8 - 22 um respectively.

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