Package component with composite pin structure and manufacturing method thereof

Abstract

The present invention relates to a package component with a composite pin structure and a method for manufacturing the same. A body region and a pin region are planned on a substrate, a chip is placed on the body region of the substrate, and the chip is electrically connected to a conductive layer on an opposite surface of the substrate. The pin region is predefined with a plurality of parallel pin positions. After the chip is electrically connected to the body region, a cutting tool can be used to cut along the edges of the body region and the pin positions, forming a package component body in the body region and a plurality of pins at the plurality of pin positions. The pins of the present invention are integrally formed by the substrate of the package component body, eliminating the need for a conventional lead frame.

Description

Technical Field

[0001] The present invention relates to a packaging component, and in particular to a packaging component with a composite pin structure. Background Art

[0002] The pins of traditional semiconductor packaging components are mainly composed of copper lead frames. Figure 16 Taking the power transistor shown as an example, during manufacturing, a chip 300 is bonded to the pad area of ​​a lead frame 301. The lead frame 301 has a plurality of parallel pins 302 pre-fabricated thereon. After bonding, a wire bonding step is performed to electrically connect the signal contacts on the chip 300 to different pins 302 on the lead frame 301 through wires 303. Finally, an insulating encapsulant 304 is coated on the chip 300.

[0003] Figure 17 and 18 Respectively represent the horizontal and vertical packaging methods. If the signal contacts of the chip 300 are all located on the same plane, the bonding process will be Figure 17 In a horizontal package, the signal contacts on the surface of the chip 300 are connected to the corresponding pins 302 on the lead frame 301 through wires 303; if the signal contacts of the chip 300 are located on the surface and bottom surfaces respectively, the bonding will be as follows Figure 18 In the vertical package, the signal contact on the surface of the chip 300 is connected to the corresponding pin 302 through the wire 303, and the other signal contact on the bottom surface of the chip 300 is connected to the lead frame 301 through solder such as silver or solder.

[0004] Whether using horizontal or vertical packaging, through-hole (PTH) packaging components primarily utilize pre-formed pins on a leadframe as the component pins. However, the disadvantage of using a leadframe is that a dedicated leadframe must be designed and manufactured for each packaged component. This also means that packaging manufacturers must purchase leadframes as raw materials from suppliers, resulting in relatively high packaging production costs.

[0005] On the other hand, the finished product after packaging has a relatively large overall thickness due to the thickness of the lead frame, the height of the chip, the height of the bonding wires, and the thickness of the sealing material, which is not conducive to thinning the device. Summary of the Invention

[0006] In view of this, the present invention mainly provides a packaging component with a composite pin structure and a manufacturing method thereof that does not require a lead frame as a raw material.

[0007] The package component with a composite pin structure of the present invention includes:

[0008] A package component body includes a substrate, the substrate is composed of an insulating body and a plurality of conductive layers, and the substrate is formed with a chip placement opening, and a chip is placed in the chip placement opening;

[0009] A plurality of pins extending outward from the package component body and electrically connected to the chip, each pin being a composite stacked structure, the composite stacked structure comprising:

[0010] The insulating body is integrally extended from the package component body, and the plurality of conductive layers are arranged on two opposite sides of the insulating body to electrically connect the chip.

[0011] The method for manufacturing a package component with a composite pin structure of the present invention includes:

[0012] Prepare a substrate, the substrate being divided into a body area and a pin area, wherein the pin area is pre-set with a plurality of pin positions, the substrate comprising an insulating body, and at least one conductive layer being respectively formed on two opposite surfaces of the insulating body;

[0013] A chip placement opening and at least one conducting hole are formed in the body region;

[0014] placing a chip into the chip placement port;

[0015] electrically connecting the chip to the conductive layer of the substrate and the via;

[0016] The molding package component body and pins are cut along the edges of the body area and the pin positions, so that the body area forms a package component body, and the substrate retained at the pin positions constitutes a plurality of pins, wherein each pin includes the insulating body and the conductive layers on its two opposite sides.

[0017] The present invention utilizes the same substrate to provide a chip arrangement, the chip being electrically connected to the conductive layer of the substrate. Multiple pins can be formed by cutting the substrate and the conductive layer, and the conductive layer on each pin is electrically connected to the chip, thereby forming a thin package component without the need for a traditional lead frame. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1A to Figure 1E : A schematic diagram of the production process of a preferred embodiment of the present invention.

[0019] Figure 2A-2B : Partial production process diagram of another preferred embodiment of the present invention.

[0020] Figure 3 : A schematic diagram of the operation of stitch cutting according to a preferred embodiment of the present invention.

[0021] Figure 4 : A plan view of a preferred embodiment of the present invention.

[0022] Figure 5 : A partial enlarged view of the pin of the present invention.

[0023] Figures 6A to 6E : A schematic diagram of the production process of another preferred embodiment of the present invention.

[0024] Figure 7 : Figures 6A to 6E A schematic plan view of an embodiment after forming a through hole in the pin area.

[0025] Figure 8 : Figures 6A to 6E Schematic diagram of the plan view after the pin cutting is completed in the embodiment.

[0026] Figure 9 : Figures 6A to 6E Schematic diagram of the embodiment after the pin cutting is completed.

[0027] Figure 10 : A plan view of another embodiment of the pin of the present invention.

[0028] Figure 11 : Figure 10 Diagram showing the pins after being plugged into the circuit board.

[0029] Figure 12 : A plan view of another embodiment of the pin of the present invention.

[0030] Figure 13 : Figure 12 Schematic diagram showing the pins after being plugged into the circuit board.

[0031] Figure 14 : A plan view of another embodiment of the pin of the present invention.

[0032] Figure 15 : Figure 14 Diagram showing the pins after being plugged into the circuit board.

[0033] Figure 16 : A three-dimensional perspective diagram of an existing power transistor.

[0034] Figure 17 : Schematic cross-sectional view of existing horizontal packaging components.

[0035] Figure 18 : Schematic cross-sectional view of existing vertical packaging components. DETAILED DESCRIPTION

[0036] Regarding the first embodiment of the present invention, please refer to Figures 1A to 1DAs shown, in the manufacturing process, no metal lead frame is needed as raw material, and the required pins can be formed through the panel level packaging process. This embodiment takes the pin through hole (PTH) packaging component as an example. Figure 1A As shown, in this embodiment, a copper clad laminate (CCL) is selected as the substrate. The copper clad laminate is formed by laminating copper foil on the upper and lower surfaces of an insulating body 10, and the copper foil is used as the conductive layers 11 and 12. The substrate can be pre-divided into a body area A and a pin area B. The body area A is used to accommodate chips, form conductive through-holes, or make redistribution layers (RDL) to form the body of the package component. The pin area B refers to the area where the pins of the package component will eventually be formed. In the pin area B, the position and number of each pin are planned according to the product specifications.

[0037] refer to Figure 1B and 1C As shown, a chip placement opening 13 and a via 14 are formed in the body area A. The inner wall of the via 14 is plated with a conductive material or filled with a conductive material so that the via 14 is electrically connected to the conductive layers 11 and 12. A chip 20 is placed inside the chip placement opening 13. The chip 20 has a signal contact 21. The position of the signal contact 21 is not limited and can be on the same surface of the chip 20 or on the upper or lower surface of the chip 20. Figure 1C In the embodiment, the upper and lower surfaces of the chip 20 have signal contacts 21.

[0038] refer to Figure 1D As shown, after the chip 20 is placed, different signal contacts 21 are electrically connected to the pin area B according to component requirements. The method of achieving electrical connection may include electroplating, forming one or more redistribution layers (RDL), etc. Figure 1D It is only a schematic representation of the electrical connection between the signal contact 21 and the conductive layers 11 and 12 of the pin area B. For example, an insulating layer 30 is first formed on the substrate to cover the substrate and the chip 20 and extend to the pin area B. Then, a circuit layer 40 is formed on the surface of the insulating layer 30 by a yellow light process. The circuit layer 40 is electrically connected to the corresponding signal contact 21 and also extends to the pin area B; and the signal contact 21 on the bottom surface of the chip 20 can be made into a bottom circuit layer 42 to electrically connect to the corresponding conductive layer 12, the via 14, etc.

[0039] refer to Figure 1E As shown, a protective layer (solder mask) 50 is formed on the outermost surface of the substrate body area A. The protective layer 50 does not need to extend to cover the pin area B. In this embodiment, a protective layer 50 is formed on both the upper and lower sides of the substrate body area A.

[0040] In the previous embodiment, the substrate is a copper foil substrate. Alternatively, the substrate may be an insulating substrate made of a general dielectric material, without pre-laminated copper foil on its upper and lower surfaces. The desired conductive circuit layers can be fabricated on the surface of the insulating substrate through a photolithography process, such as the conductive layers 11 and 12 and the circuit layer 40 described above.

[0041] Please refer to Figure 2A 、 2B In another embodiment, it is not necessary to additionally form the circuit layer 40 on the substrate, and the conductive layers 11 and 12 previously laminated on the upper and lower surfaces of the substrate and the bottom circuit layer 42 can be used to electrically connect to the chip 20 .

[0042] Please refer to Figure 3 、 Figure 4 As shown, a cutting tool is used to cut the body area A and the pin area B of the substrate. Cutting along the edge of the body area A forms a rectangular package component body 100. The pin area B is cut to form the pins, retaining the intended pin positions and removing unnecessary substrate areas. The remaining substrate forms the pins 60 of the package component. Figures 1A to 1E The left side of the diagram only shows the side view of a single pin 60. In reality, the package component will have multiple pins arranged in parallel. In this embodiment, a routing machine can be used to cut excess substrate to form the required pins 60. Other forming methods such as stamping, laser cutting, etc. can also be used to make the pins 60. For example, the milling cutter 200 can be controlled to cut along the Figure 3 The cutting path R is to move along the edge of the preset position of the stitch 60 .

[0043] The structure of each pin 60 is as follows Figure 5 As shown, the substrate 10 includes at least an insulating body 10 located in the middle and conductive layers on both the front and back surfaces of the insulating body 10. The conductive layers may include the copper foil layer 12 of the substrate itself or a subsequently formed circuit layer 40, bottom circuit layer 42, etc. Each pin 60 is electrically connected to the chip 20 through the conductive layer. Because the pins 60 are formed after cutting the body 10, the length / width of the pins 60 themselves and the pitch between adjacent pins 60 can be cut and formed according to product specifications and are not limited by the established specifications of traditional lead frames. The thickness of each pin 60 itself or the thickness of the surface conductive layer can also be adjusted, for example, by stacking insulating layers 30 or circuit layers 40 to increase the overall thickness of the pins 60, or by electroplating a thicker circuit layer 40 to increase the overall thickness of the pins 60.

[0044] For another embodiment of the present invention, please refer to Figures 6A to 6E As shown, Figures 1A to 1E The difference between the embodiment of FIG. 1 and FIG. 2 is that a plurality of through holes 15 are first formed in the pin area B by mechanical drilling (as shown by the arrows). Figure 7 The positions of the through holes 15 are distributed at the edges of the pin positions, and a plating layer 151 is electroplated on the inner wall of each through hole 15. When the pin area B of the package component is undergoing the pin forming step, the cutting tool cuts along the edge of the pin 60 and can simultaneously cut each through hole 15. Figure 8 、 Figure 9 As shown, the cut through holes 15 naturally form concave arc-shaped notches 601 on opposite sides of the pin 60. The surface of each notch 601 is coated with an electroplating layer 151 to increase the tin-receiving area on the side of each pin 60, thereby improving the tin wetting of the package component. In this embodiment, because the through holes 15 and the hole wall electroplating are simultaneously formed when the conductive holes 14 in the body area A are formed, no additional drilling and electroplating operations are required after the pins 60 are formed, which simplifies the process steps. However, in other embodiments, the entire surface of the pin 60 can also be electroplated after the pin 60 is formed, so that the surface of the pin 60 has more area for solder to adhere.

[0045] Please refer to Figure 10 、 Figure 11 As shown, in the step of forming the pin, the pin 60 forms a pin body 61 and a narrowed portion 62. One end of the narrowed portion 62 is connected to the bottom surface of the package component body 100, and the other end is connected to the pin body 61. The width of the narrowed portion 62 is slightly smaller than the width of the pin body 61. Because the width of the narrowed portion 62 is also smaller than the aperture of the solder hole on the circuit board P, when the pin 60 is inserted into the circuit board P, the bottom surface of the package component body 100 can be flat against the surface of the circuit board P. This embodiment can improve the stability of the surface mount component (SMT) when it is soldered to the surface of the circuit board, ensuring that the package component will not wobble on the circuit board P. When making the narrowed portion 62, a milling cutter can be used to cut along the solder hole. Figure 10 The cutting path R shown is cutting. When the milling cutter moves to the junction of the pin 60 and the bottom surface of the package body component 100, the milling cutter is controlled to move toward the center of the pin 60 to slightly cut the top of the pin 60. After the milling cutter withdraws outward, it cuts along the edge of the pin 60 to form a narrowed portion 62 at one end of the pin 60.

[0046] Refer again Figure 12 、 Figure 13As shown, during the step of forming the pins, grooves 102 can also be formed on the bottom surface of the package component body 100. The grooves 102 are located on opposite sides of each pin 60. Similarly, when the pins 60 are inserted into the circuit board P, the bottom surface of the package component body 100 can be flat against the surface of the circuit board P, so that the package component will not shake on the circuit board P. In addition, the gap formed by the grooves 102 between the package component body 100 and the surface of the circuit board P can also increase the heat dissipation effect. The grooves 102 can be made by using a milling cutter along the Figure 12 The cutting path R shown is cutting. When the milling cutter moves to the intersection of the pin 60 and the package body component 100, the milling cutter is controlled to move slightly inward toward the bottom surface of the package component body 100. After the milling cutter exits outward, it cuts along the edge of the pin 60 to form the groove 102 on the bottom surface of the package component body 100.

[0047] refer to Figure 14 、 Figure 15 As shown, compared with Figure 10 In the embodiment of the present invention, the pin 60 may further form a support portion 63. This support portion 63 is in contact with the bottom surface of the package body 100 and has a width slightly greater than that of the pin body 61. The width of this support portion 63 is also greater than the diameter of the solder hole on the circuit board P. A constricted portion 62 is formed at the bottom end of this support portion 63. The width of this constricted portion 62 is slightly less than the diameter of the solder hole on the circuit board P. When the package is plugged into the circuit board P, the lower edge of the support portion 63 abuts the surface of the circuit board P, creating a heat dissipation gap G between the bottom surface of the package body 100 and the circuit board P. The portion below the constricted portion 62 can enter the solder hole. The presence of the heat dissipation gap G between the package body 100 and the surface of the circuit board P further enhances heat dissipation.

[0048] Based on the above detailed description, the embodiments of the present invention have one or more of the following advantages:

[0049] 1. The present invention utilizes panel-level packaging (PLP) technology to manufacture packaging components, and can manufacture the pins required for the packaging components without using a lead frame.

[0050] 2. Compared with traditional packaging components, the present invention does not require the use of lead frames, wire bonding and molding, which can effectively reduce the overall thickness of the packaging component, help reduce product size and improve heat dissipation.

[0051] 3. When a notch is formed on the side of the pin, the tin-wetting area can be increased, thereby improving the solderability of the product.

[0052] 4. Molded products can be inspected for defects using automated optical inspection (AOI) for quality control.

[0053] The above description is merely a preferred embodiment of the present invention and does not constitute any form of limitation to the present invention. Although the present invention has been disclosed as a preferred embodiment, it is not intended to limit the present invention. Any technician familiar with the present profession can make some changes or modifications to equivalent embodiments of the technical contents disclosed above without departing from the scope of the technical solution of the present invention. However, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention are still within the scope of the technical solution of the present invention.

Claims

1. A package component with a composite pin structure, characterized in that: Includes: A package component body includes a substrate, the substrate is composed of an insulating body and a plurality of conductive layers, and the substrate is formed with a chip placement opening, and a chip is placed in the chip placement opening; A plurality of pins extending outward from the package component body and electrically connected to the chip, each pin being a composite stacked structure, the composite stacked structure comprising: The insulating body is integrally extended from the package component body, and the plurality of conductive layers are arranged on two opposite sides of the insulating body to electrically connect the chip.

2. The package component with a composite pin structure according to claim 1, wherein: Two opposite surfaces of the packaging component body are respectively provided with a protection layer.

3. The package component with a composite pin structure according to claim 1, wherein: A conducting hole is formed inside the package component body, and the conducting hole is electrically connected to at least one conducting layer among the plurality of conducting layers.

4. The package component with a composite pin structure according to claim 1, wherein: A plurality of arc-shaped notches are formed on the side surface of each pin, and a surface of each arc-shaped notch is provided with an electroplating layer.

5. The package component with a composite pin structure as claimed in claim 1, wherein: Each pin includes a narrow portion and a pin body, one end of the narrow portion is connected to the package component body, and the other end is connected to the pin body; The width of the narrowed portion is smaller than the width of the needle leg body.

6. The package component with a composite pin structure according to claim 1, wherein: The packaging component body is formed with a plurality of grooves on a side extending from the pin, and each pin has one groove on two opposite sides.

7. The package component with a composite pin structure according to claim 1, wherein: Each pin includes a supporting portion, a narrowing portion and a pin body extending in sequence, and one end of the supporting portion is connected to the package component body; The width of the supporting portion is greater than the width of the needle foot body, and the width of the needle foot body is greater than the width of the narrowed portion.

8. A method for manufacturing a package component with a composite pin structure, characterized in that: Include: Prepare a substrate, the substrate being divided into a body area and a pin area, wherein the pin area is pre-set with a plurality of pin positions, the substrate comprising an insulating body, and at least one conductive layer being respectively formed on two opposite surfaces of the insulating body; A chip placement opening and at least one conducting hole are formed in the body region; placing a chip into the chip placement port; electrically connecting the chip to the conductive layer of the substrate and the via; The package component body and pins are formed, and the edges of the body area and the pin positions are cut to form a package component body in the body area. The substrate retained at the pin positions constitutes a plurality of pins, wherein each pin includes the insulating body and the conductive layers on two opposite sides thereof.

9. The method for manufacturing a package component with a composite pin structure as claimed in claim 8, wherein: The step of electrically connecting the chip and the conductive layer of the substrate further includes: forming an insulating layer on the surface of the substrate, wherein the insulating layer covers the chip; A circuit layer is formed on the insulating layer, and the circuit layer is electrically connected to the chip, wherein the circuit layer extends to each pin position.

10. The method for manufacturing a package component with a composite pin structure as claimed in claim 9, wherein: In the body region, a protection layer is formed above the circuit layer and below the substrate respectively.

11. The method for manufacturing a package component with a composite pin structure as claimed in claim 8, wherein: When the wafer placement opening and the at least one conducting hole are formed in the body area, a plurality of through holes are simultaneously formed in the pin area and a conductive layer is formed on the inner wall surface of each through hole, and the positions of the plurality of through holes are dispersedly arranged along the edge of the pin position; In the step of forming the pins, the through hole is cut to form a plurality of notches on the side of each pin.

12. The method for manufacturing a package component with a composite pin structure as claimed in claim 8, wherein: In the step of forming the pins, an end of each pin adjacent to the package component body is partially cut to form a narrowed portion on each pin.

13. The method for manufacturing a package component with a composite pin structure as claimed in claim 8, wherein: In the step of forming the pins, a surface of the package component body connected to the pins is partially cut to form a groove, so that each pin has a groove on two opposite sides.

14. The method for manufacturing a package component with a composite pin structure as claimed in claim 8, wherein: In the step of forming the pins, each pin includes a supporting portion, a narrowing portion and a pin body extending in sequence, one end of the supporting portion is connected to the package component body; the width of the supporting portion is greater than the width of the pin body, and the width of the pin body is greater than the width of the narrowing portion.

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