semiconductor devices

Abstract

The present invention provides a semiconductor device. Even when a vacant area is required within a power switch circuit, a reduction in power supply capacity is suppressed. The semiconductor device comprises: a first region in which a logic circuit is configured; a second region in which a functional circuit different from the logic circuit is configured; and a first power switch circuit disposed adjacent to the second region, connecting a first power line to a second power line that supplies power to the logic circuit and the functional circuit. The first power switch circuit comprises: a first transistor having a size larger than that of a transistor used in the logic circuit, connecting the first power line to the second power line; an end cap disposed in a region adjacent to the functional circuit; and a second transistor disposed between the region in which the first transistor is configured and the end cap, having the same size as that of the transistor used in the logic circuit, connecting the first power line to the second power line.

Description

Technical Field

[0001] The present invention relates to semiconductor devices. Background Art

[0002] To reduce leakage current in semiconductor devices, a method is known in which a power switch circuit is provided between a power line and a virtual power line, which is a power line for each of a plurality of circuit blocks and is turned on when the circuit block is in operation.

[0003] In order to improve the power supply capacity of the power switch circuit, the size of the transistor used in the power switch circuit is designed to be larger than the size of the unit transistor used in the logic circuit. When transistors of different sizes are arranged adjacent to each other, the shape of the gate electrode of the smaller transistor is likely to deviate during the manufacture of the semiconductor device. In order to suppress the deviation of the shape, transistors of different sizes are arranged at intervals determined by the layout rules. For example, by providing an idle area at the end of the power switch circuit, the transistors of the power switch circuit and the transistors of the logic circuit adjacent to the power switch circuit are separated and arranged at intervals that meet the layout rules. For example, a dummy gate electrode or a dummy transistor is arranged in the idle area of ​​the power switch circuit.

[0004] Patent Document 1: U.S. Patent No. 10141336;

[0005] Patent Document 2: U.S. Patent Application Publication No. 2019 / 0244900;

[0006] Patent Document 3: U.S. Patent Application Publication No. 2019 / 0214377;

[0007] Patent Document 4: Japanese Patent Application Publication No. 2018-190760;

[0008] Patent Document 5: International Publication No. 2017 / 208887.

[0009] Recently, to achieve both high integration and reduced leakage current in semiconductor devices, transistors used in semiconductor devices have been replaced with three-dimensional structures, such as finFETs (field effect transistors), instead of planar FETs. This has led to a growing difference in the size of transistors used in logic circuits and those used in power switch circuits. Furthermore, to minimize variations in the shape of gate electrodes and other components during manufacturing, larger free areas are provided at the ends of power switch circuits.

[0010] The larger the free space, the larger the power switch circuit, which reduces the power supply capacity per unit size. Furthermore, semiconductor devices typically include multiple power switch circuits. Therefore, as the size of the power switch circuit increases, the size of the logic circuit that can be mounted on the semiconductor device decreases. While maintaining the size of the logic circuit, the chip size of the semiconductor device increases. Summary of the Invention

[0011] The present invention has been made in view of the above-mentioned points, and an object of the present invention is to suppress a reduction in power supply capability even when a vacant area is required in a power switch circuit.

[0012] In one technical solution of the present invention, a semiconductor device includes: a first region in which a logic circuit is configured; a second region in which a functional circuit different from the logic circuit is configured; and a first power switch circuit, which is arranged adjacent to the second region and connects a first power line to a second power line that supplies power to the logic circuit and the functional circuit, the first power switch circuit including: a first transistor having a size larger than that of the transistor used in the logic circuit and connecting the first power line to the second power line; an end cap, which is arranged in a region adjacent to the functional circuit; and a second transistor, which is arranged between the region in which the first transistor is configured and the end cap, has the same size as the transistor used in the logic circuit and connects the first power line to the second power line.

[0013] According to the disclosed technology, even when a vacant area is required in the power switch circuit, a decrease in power supply capability can be suppressed. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 This is a diagram showing an example of the layout of the semiconductor device according to the first embodiment.

[0015] Figure 2 Yes Figure 1 A block diagram of an example of power switch circuits SPSW and PPSW.

[0016] Figure 3 Is set to Figure 1 A diagram showing an example of the layout of power switch circuits in the surrounding area.

[0017] Figure 4 Yes Figure 3 FIG. 1 is a diagram showing an example of a layout of power supply wiring of a power supply switch circuit PPSW.

[0018] Figure 5 Yes Figure 4 Diagram of the arrangement of fins, gate electrodes and local wiring.

[0019] Figure 6 Yes Figure 3 and Figure 4 A perspective view of an example of the structure of an n2-fin×m1 transistor.

[0020] Figure 7 It means along Figure 4 A cross-section diagram of the Y1-Y1' line.

[0021] Figure 8 It means along Figure 4 A cross-sectional view of the line X1-X1'.

[0022] Figure 9 Is set to Figure 1 FIG. 1 is a diagram showing an example of the layout of power switch circuits in a standard cell region.

[0023] Figure 10 This is a diagram showing an example (comparative example) of a circuit layout of another power switch circuit.

[0024] Figure 11 This is a diagram showing an example of the layout of a semiconductor device according to the second embodiment.

[0025] Figure 12 This is a diagram showing an example of the layout of a semiconductor device according to the third embodiment.

[0026] Figure 13 This is a diagram showing an example of the layout of a semiconductor device according to the fourth embodiment.

[0027] Figure 14 This is a diagram showing an example of the layout of a semiconductor device according to the fifth embodiment.

[0028] Figure 15 This is a diagram showing an example of the layout of a semiconductor device according to the sixth embodiment.

[0029] Description of Reference Signs

[0030] 100, 102, 104, 106, 108, 110…semiconductor device; ATr1, ATr2…additional transistor; D…drain region; E1, E2…region; ECAP…end cap; G…gate electrode; MBUF…main buffer; MTr…main transistor; PA…peripheral region; PCNT…power control signal; PCNT1, PCNT2…power switch control circuit; PD, PD1, PD2, PD3, PD4…power domain; PPSW, PPSWa, PPSWb…power switch circuit; PPSWc, PPSWd, PPSWe…power switch circuit; PT1, PT2…p-channel transistor; S…source region; SBUF…subbuffer; SCA…standard cell region; SIG…signal line; SP1…spacer; SPSW…power switch circuit; STr…subtransistor; VDD…power line; VSS…power line (ground line); VVDD…virtual power line; WLT…well tap. DETAILED DESCRIPTION

[0031] Hereinafter, the power supply line for supplying power will be referred to by the power supply name and reference numeral.

[0032] (First embodiment)

[0033] Figure 1 An example of the layout of the semiconductor device according to the first embodiment is shown. Figure 1 The semiconductor device 100 shown in FIG. For example, it includes at least one power domain PD1. Within power domain PD1 are provided a standard cell area SCA, where a plurality of standard cells (not shown) are arranged, and a plurality of peripheral areas PA, where one or more random access memories (RAMs) are arranged. The standard cell area SCA is an example of a first area where logic circuits are arranged, and the peripheral areas PA are an example of a second area where functional circuits other than the logic circuits are arranged.

[0034] exist Figure 1 In FIG, only one power domain PD1 is shown, but the semiconductor device 100 may also have multiple power domains. Figure 1 The left side of the mid-power domain PD1 may also be the chip end of the semiconductor device 100. Although not particularly limited, the transistor mounted on the semiconductor device 100 is a finFET. Figure 6 Provide explanation.

[0035] In the standard cell area SCA, multiple power switch circuits SPSW are spaced apart. Furthermore, end caps ECAP, indicated by hatching, are arranged around the standard cell area SCA. The end caps ECAP include dummy gate electrodes or dummy transistors. Alternatively, the standard cell area SCA may be configured with only standard cells, rather than power switch circuits SPSW.

[0036] One or more RAMs are arranged in each peripheral area PA. In some peripheral areas PA, multiple power switch circuits PPSW and end caps ECAP are arranged adjacent to the RAMs. RAMs are an example of memory IP (Intellectual Property) as hard macros and are functional circuits with specified functions. Power switch circuit PPSW is an example of a first power switch circuit. Power switch circuit SPSW is an example of a second power switch circuit.

[0037] Figure 2 express Figure 1 The power switch circuits SPSW and PPSW are examples of power switch circuits SPSW and PPSW. The power switch circuit PPSW includes a p-channel transistor PT1 and a power switch control circuit PCNT1. The power switch circuit SPSW includes a p-channel transistor PT2 and a power switch control circuit PCNT2. In practice, each of the p-channel transistors PT1 and PT2 consists of multiple transistors connected in parallel. Furthermore, the power switch circuits SPSW and PPSW may each include n-channel transistors instead of the p-channel transistors PT1 and PT2. In this case, the sources of the n-channel transistors are connected to the ground line VSS, while the drains are connected to the logic circuits of the standard cells and to a virtual ground line that supplies the ground potential.

[0038] The source of the p-channel transistor PT1 is connected to, for example, a power supply line VDD that supplies an external power supply VDD. The drain of the p-channel transistor is connected to a virtual power supply line VVDD, which is connected to power supply terminals of the standard cells and RAM. The power supply line VDD is an example of a first power supply line, and the virtual power supply line VVDD is an example of a second power supply line. The gate electrode of the p-channel transistor PT1 is connected to the output of the power switch control circuit PCNT1.

[0039] The source of the p-channel transistor PT2 is connected to the power supply line VDD, the drain of the p-channel transistor is connected to the virtual power supply line VVDD, and the gate electrode of the p-channel transistor PT2 is connected to the output of the power switch control circuit PCNT2.

[0040] Each power switch control circuit PCNT1 and PCNT2 is connected to power line VDD and ground line VSS to maintain constant operation, and operates based on a power control signal PCNT. When power control signal PCNT indicates active mode, which activates the circuits within power domain PD1, power switch control circuit PCNT1 supplies ground voltage VSS to the gate electrode of p-channel transistor PT1. This turns on p-channel transistor PT1, connecting power line VDD to virtual power line VVDD.

[0041] When power control signal PCNT indicates active mode, power switch control circuit PCNT2 supplies ground voltage VSS to the gate electrode of p-channel transistor PT2, thereby turning on p-channel transistor PT2 and connecting power line VDD to virtual power line VVDD.

[0042] When the power control signal PCNT indicates the power-off mode, the power switch control circuit PCNT1 supplies the power supply voltage VDD to the gate electrode of the p-channel transistor PT1. This turns off the p-channel transistor PT1, disconnecting the power line VDD from the virtual power line VVDD.

[0043] When power control signal PCNT indicates power-off mode, power switch control circuit PCNT2 supplies power supply voltage VDD to the gate electrode of p-channel transistor PT2. This turns off p-channel transistor PT2, disconnecting power line VDD from virtual power line VVDD. In this way, p-channel transistors PT1 and PT2 operate based on a common power control signal PCNT, functioning as a power switch that connects power line VDD to virtual power line VVDD.

[0044] The power supply terminal of the RAM is connected to the virtual power supply line VVDD, and the ground terminal of the RAM is connected to the ground line VSS. Similarly, the power supply terminal of the standard cell is connected to the virtual power supply line VVDD, and the ground terminal of the standard cell is connected to the ground line VSS.

[0045] In active mode, p-channel transistors PT1 and PT2 are turned on, connecting power supply line VDD to virtual power supply line VVDD. Consequently, the RAM and standard cells within power domain PD1 receive power supply voltage VDD via virtual power supply line VVDD and operate in active mode. In power-off mode, on the other hand, p-channel transistors PT1 and PT2 are turned off, disconnecting power supply line VDD from virtual power supply line VVDD. Consequently, the RAM and standard cells within power domain PD1 stop receiving power supply voltage VDD and cease operation in power-off mode.

[0046] Furthermore, the plurality of p-channel transistors PT1 may receive control signals at different timings from the power switch control circuit PCNT1 via their gate electrodes and may be turned on and off in sequence. Similarly, the plurality of p-channel transistors PT2 may receive control signals at different timings from the power switch control circuit PCNT2 via their gate electrodes and may be turned on and off in sequence.

[0047] By staggering the operation timing of the p-channel transistor PT1 (or PT2), a sudden current flow from the power supply VDD to the virtual power line VVDD is suppressed, thereby alleviating power supply noise generated at the start of operation of the power switch circuits PPSW and SPSW.

[0048] Figure 3 Indicates that it is set Figure 1 An example of the layout of the power switch circuit PPSW in the peripheral area PA. Figure 3 , the power switch circuit PPSW is shown as an example using four-height cells arranged in four regions between five power supply lines (VVDD, VSS) extending in the X direction. Alternatively, the power switch circuit PPSW may be a two-height cell (two-height cell) or an eight-height cell. The X direction is an example of a first direction.

[0049] The power switch circuit PPSW includes a main transistor MTr, a sub-transistor STr, additional transistors ATr1 and ATr2, a well tap WLT, a main buffer MBUF, a sub-buffer SBUF, and two end caps ECAP. The main transistor MTr, the sub-transistor STr, and the additional transistors ATr1 and ATr2 have the same Figure 2 The p-channel transistor PT1 shown corresponds to a plurality of p-channel transistors. The main transistor MTr and the sub-transistor STr are examples of first transistors. The additional transistor ATr1 is an example of a second transistor, and the additional transistor ATr2 is an example of a fifth transistor.

[0050] The main transistor MTr includes multiple transistors having n1 fins and m1 gate electrodes (hereinafter referred to as n1-fin×m1 transistors). Furthermore, the main transistor MTr includes multiple transistors having n2 fins and m1 gate electrodes (hereinafter referred to as n2-fin×m1 transistors). The additional transistors ATr1 and ATr2 include multiple transistors having n2 fins and m2 gate electrodes (hereinafter referred to as n2-fin×m2 transistors). Here, n1, n2, m1, and m2 are arbitrary natural numbers such that the relationship n1>n2 and m1>m2 holds.

[0051] The size of each transistor varies depending on the number of fins and gate electrodes. For example, when n1=8, n2=3, m1=10, and m2=1, the size of the transistors is n1-fin×m1>n2-fin×m1>n2-fin×m2 in descending order. For example, the size of the n2-fin×m2 transistor is Figure 1 The sizes of any of the various transistors used in the logic circuit of the standard cell area SCA are the same.

[0052] The main buffer MBUF and the sub-buffer SBUF are included in Figure 2 The power switch control circuit PCNT1 shown in FIG. A main buffer unit MBUF controls the operation of the main transistor MTr and the additional transistors ATr1 and ATr2, while a sub-buffer unit SBUF controls the operation of the sub-transistor STr. Furthermore, the additional transistors ATr1 and ATr2 can also be controlled by the sub-buffer unit SBUF.

[0053] The well tap WLT supplies the power supply voltage VVDD to the well region where the p-channel transistor is formed. Figure 3 The lateral ends are the X-direction ends.

[0054] In this embodiment, according to the layout rules of semiconductor device 100, the ends of the n1-fin×m1 transistors in the X direction are separated from the ends of the layout area of ​​power switch circuit PPSW by a distance of at least SP1. The distance SP1 rule is set to suppress variations in the shape of the gate electrode and other components of the n1-fin×m1 transistors during the manufacture of semiconductor device 100 due to external factors such as other circuits adjacent to power switch circuit PPSW, thereby suppressing variations in the electrical characteristics of the transistors.

[0055] For example, the width of the end cap ECAP in the X direction is smaller than the spacing SP1, resulting in an empty area between the end cap ECAP and the n1-fin×m1 transistor. In this embodiment, an additional transistor ATr1, which functions as a power switch, is disposed in this empty area. Furthermore, an additional transistor ATr2, which also functions as a power switch, is disposed in another empty area of ​​the power switch circuit PPSW (in this example, between the main buffer MBUF and the sub-buffer SBUF).

[0056] Thus, the main transistor MTr, the sub-transistor STr, and the additional transistors ATr1 and ATr2 function as a power switch that connects the power line VDD to the virtual power line VVDD. Therefore, in the power switch circuit PPSW, the additional transistor ATr1, which is arranged in the vacant area created by the constraints of the layout rule (interval SP1), can improve the power supply capability of the power switch circuit PPSW.

[0057] In this case, the additional transistor ATr1 has the same structure as the n2-fin×m2 transistor used in the logic circuit arranged in the standard cell area SCA, thereby contributing to suppressing variations in the shape of gate electrodes and the like of circuits adjacent to the power switch circuit PPSW.

[0058] Furthermore, in the power switch circuit PPSW, the additional transistor ATr2 is arranged in a vacant area created by circuit layout, thereby improving the power supply capability of the power switch circuit PPSW. Consequently, the power supply capability can be improved without increasing the layout area of ​​the power switch circuit PPSW.

[0059] That is, by arranging the additional transistors ATr1 and ATr2 in the vacant area, it is possible to suppress an increase in the layout area of ​​the power switch circuit PPSW and improve the power supply capability of the p-channel transistor PT1.

[0060] Figure 4 express Figure 3 FIG. 1 is an example of the layout of the power supply wiring of the power supply switch circuit PPSW. Figure 4 Indicates Figure 3 In the power switch circuit PPSW, the double-height cell is arranged on the right side of the main transistor MTr. Hereinafter, the virtual power line VVDD and the ground line VSS connected from the outside of the power switch circuit PPSW are also referred to as power lines VVDD and VSS. The virtual power line VVDD and the power line VDD connected within the power switch circuit PPSW are also referred to as wiring VVDD and VDD, respectively. Figure 4 In the example, n1=8, n2=3, m1=10, and m2=1.

[0061] Two power supply lines VVDD and one power supply line VSS are formed using the M0 layer. The M0 layer is the metal wiring layer closest to the semiconductor substrate. The wiring of the M0 layer is in the X direction ( Figure 4 Between each power line VVDD and power line VSS, wiring VDD, VVDD and signal line SIG are formed using the M0 layer. For example, the signal line SIG is Figure 2 The gate wiring of the p-channel transistor PT1 is shown.

[0062] The local wiring VDD extending in the Y direction is connected to the wiring VDD of the M0 layer via a through-hole. The Y direction is an example of a second direction perpendicular to the X direction. The wiring VDD of the M0 layer is connected to the power supply line VDD formed using the upper metal wiring layer via a through-hole (not shown). The local wiring VVDD extending in the Y direction is connected to the wiring VVDD of the M0 layer and the power supply line VVDD of the M0 layer via a through-hole. In addition, the wiring VVDD of the M0 layer and the power supply line VVDD can also be connected to the power supply line VVDD formed using the upper metal wiring layer. The local wiring VDD and VVDD are arranged between the gate electrodes G extending in the Y direction.

[0063] The fins extend in the X direction and are arranged at intervals in the Y direction. For example, an n2-fin×m1 transistor has dummy gate electrodes DMYG on both sides in the X direction, and thus has m1+2 gate electrodes. An n2-fin×m2 transistor has dummy gate electrodes DMYG on both sides in the X direction, and thus has m2+2 gate electrodes. Figure 4 In the illustrated example, the end cap ECAP includes three dummy gate electrodes DMYG and dummy local wirings arranged between the dummy gate electrodes DMYG.

[0064] In n2-fin×m1 and n2-fin×m2 transistors, source regions S and drain regions D are formed between two adjacent gate electrodes G. Source regions S and drain regions D are alternately formed with gate electrodes G interposed between them. The source regions S are connected to wiring VDD, while the drain regions D are connected to wiring VVDD. Furthermore, in finFETs, the source regions S and drain regions D are each formed on a fin. Therefore, local wiring VDD is connected to the fin functioning as the source region S, and local wiring VVDD is connected to the fin functioning as the drain region D.

[0065] Figure 5 express Figure 4 The gate electrode G and the local wiring are formed in the Y direction across the fin extending in the X direction.

[0066] Figure 6 express Figure 3 and Figure 4 This is an example of an n2-fin×m1 transistor structure. The fin transistor includes a fin extending in the X direction on a semiconductor substrate and a gate electrode G extending in the Y direction across the fin. A gate insulating film is formed on the portion of the fin facing the gate electrode G, and the transistor channel is formed on the surface of the fin covered by the gate insulating film.

[0067] Furthermore, the source region S and the drain region D are respectively provided on both sides of the gate electrode G in the fin. Although not shown in the figure, local wiring VDD and local wiring VVDD are respectively provided in each source region S and each drain region D along the extending direction of the gate electrode G. Figure 4 In the power switch circuit PPSW shown in FIG. 1 , a p-channel transistor is formed, a source region S is connected to the wiring VDD, and a drain region D is connected to the wiring VVDD. Figure 6 In the embodiment, the source region S and the drain region D can also be interchanged.

[0068] Figure 7 Indicates along Figure 4 The fin is formed in an element isolation insulating film such as STI (Shallow Trench Isolation) formed on a semiconductor substrate. The upper part of the fin protruding from the element isolation insulating film is Figure 7 In the cross section shown, it is covered by the local wiring VVDD. Figure 7 In the cross section shown, each local wiring VVDD is connected to the power supply line VVDD and wiring VVDD formed in the M0 layer via a via. Each local wiring VVDD, each via, and each wiring VVDD and VDD formed in the M0 layer are electrically isolated by an interlayer insulating film.

[0069] Figure 8 Indicates along Figure 4 The cross section of the X1-X1' line. Figure 8 In the cross section shown, local wirings and gate electrodes are alternately formed on the fins. In addition, among the local wirings, the local wirings connected to the drain regions of transistors (not shown) are connected to the wiring VVDD formed in the M0 layer.

[0070] Figure 9 Indicates that it is set Figure 1 An example of the layout of the power switch circuit SPSW in the standard cell area SCA. Figure 3 The same elements are denoted by the same reference numerals, and detailed description thereof is omitted. The power switch circuit SPSW provided in the standard cell area SCA does not have an end cap ECAP and does not require a space SP1 defined by the layout rule.

[0071] However, for example, when the power switch circuit SPSW is adjacent to the end cap ECAP disposed to surround the standard cell area SCA, it is necessary to provide a gap SP1 between the power switch circuit SPSW and the end cap ECAP. Figure 9As shown in the example, an additional transistor ATr1 (n2-fin×m2 transistor) is arranged in the gap SP1. In addition, when the power switch circuit SPSW is arranged separately from the end cap ECAP arranged surrounding the standard cell area SCA, the gap SP1 and the additional transistor ATr1 arranged in the gap SP1 can also be omitted.

[0072] Other structures of the power switch circuit SPSW Figure 3 The power switch circuit PPSW has the same structure as the power switch circuit PPSW. An additional transistor ATr2 (n2-fin×m2 transistor) that functions as a power switch is arranged in the remaining free area of ​​the power switch circuit SPSW (in this example, between the main buffer MBUF and the sub-buffer SBUF).

[0073] The main transistor MTr and the sub-transistor STr provided in the power switch circuit SPSW are examples of third transistors. The additional transistor ATr1 provided in the power switch circuit SPSW is an example of a fourth transistor, and the additional transistor ATr2 is an example of a fifth transistor.

[0074] and Figure 3 Similarly to the power switch circuit PPSW shown, the main transistor MTr, sub-transistor STr, and additional transistors ATr1 and ATr2 of the power switch circuit SPSW function as a power switch that connects the power supply line VDD to the virtual power supply line VVDD. Therefore, in the power switch circuit SPSW, the additional transistor ATr1, which is arranged in the vacant area created by the constraints of the layout rule (interval SP1), can improve the power supply capability of the power switch circuit SPSW.

[0075] In this case, the additional transistor ATr1 has the same structure as the n2-fin×m2 transistor used in the logic circuit arranged in the standard cell area SCA. Therefore, the power switch circuit SPSW adjacent to the end cap ECAP can suppress variations in the shape of the gate electrode and other components caused by other circuits and other patterns arranged outside the standard cell area SCA.

[0076] Furthermore, in the power switch circuit SPSW, the additional transistor ATr2 is arranged in a vacant area due to circuit layout, thereby improving the power supply capability of the power switch circuit SPSW. As a result, the power supply capability can be improved without increasing the layout area of ​​the power switch circuit SPSW.

[0077] That is, by arranging the additional transistors ATr1 and ATr2 in the vacant area, it is possible to suppress an increase in the layout area of ​​the power switch circuit SPSW and improve the power supply capability of the p-channel transistor PT2.

[0078] Figure 10 An example of a circuit layout of another power switch circuit PSW (comparative example) is shown. Figure 3 The same elements are denoted by the same reference numerals, and detailed descriptions thereof are omitted. Figure 10 The power switch circuit PSW shown in Figure 3 The additional transistors ATr1 and ATr2 of the power switch circuit PPSW are not configured with transistors, and become vacant areas E1 and E2. In this case, the power supply capability of the power switch circuit PSW is greater than Figure 3 The power switch circuit PPSW and Figure 9 The power switch circuit SPSW goes low.

[0079] As described above, in this embodiment, the additional transistor ATr1 is arranged in the vacant area created by the layout rule constraints (interval SP1) in each of the power switch circuits PPSW and SPSW. This improves power supply capacity without increasing the layout area of ​​the power switch circuits PPSW and SPSW. In other words, even if vacant area is required within the power switch circuits PPSW and SPSW due to layout rule constraints, a reduction in power supply capacity can be suppressed.

[0080] The additional transistor ATr1 has the same structure as the 3fin×1 transistor used in the logic circuit arranged in the standard cell area SCA, thereby contributing to suppressing variations in the shapes of gate electrodes and the like of circuits adjacent to the power switch circuits PPSW and SPSW.

[0081] Furthermore, in the power switch circuits PPSW and SPSW, the additional transistor ATr2 is arranged in an unused area due to circuit layout, thereby improving the power supply capability of the power switch circuits PPSW and SPSW. This improves the power supply capability without increasing the layout area of ​​the power switch circuits PPSW and SPSW.

[0082] (Second embodiment)

[0083] Figure 11 An example of the layout of the semiconductor device according to the second embodiment is shown. Figure 1 The same elements are denoted by the same reference numerals, and detailed descriptions thereof are omitted. Figure 10 The semiconductor device 102 shown is, for example, Figure 1 The power domain PD1 shown has power domains PD2 and PD3 on the left side in the X direction.

[0084] The power domain PD2 has the same circuits as the power domain PD1. The power domain PD3 has circuits that always operate while power is supplied to the semiconductor device 102, and therefore does not include power switch circuits PPSW and SPSW.

[0085] As described above, in this embodiment, even when a plurality of power domains PD1 , PD2 , and PD3 are adjacent to each other, the power supply capability can be improved without increasing the layout area of ​​the power switch circuits PPSW and SPSW, similar to the above-mentioned embodiment.

[0086] (Third embodiment)

[0087] Figure 12 An example of the layout of the semiconductor device according to the third embodiment is shown. Figure 1 The same elements are denoted by the same reference numerals, and detailed descriptions thereof are omitted. Figure 11 The semiconductor device 104 shown has RAM and analog IP arranged in the peripheral area PA.

[0088] In semiconductor device 104, circuits other than analog IPs always operate while power is supplied to semiconductor device 104. Therefore, power switch circuits PPSW are arranged on both sides of the analog IPs in the X direction, and the analog IPs and power switch circuits PPSW belong to power domain PD4.

[0089] As described above, in this embodiment as well, similarly to the above-described embodiments, the power supply capacity can be improved without increasing the layout area of ​​the power switch circuit PPSW.

[0090] (Fourth embodiment)

[0091] Figure 13 An example of the layout of the semiconductor device according to the fourth embodiment is shown. Figure 1 The same elements are denoted by the same reference numerals, and detailed descriptions thereof are omitted. Figure 13 The semiconductor device 106 shown in FIG. 1 is provided with two power switch circuit arrays in a region adjacent to the RAM. The power switch circuit arrays include a plurality of power switch circuits PPSW arranged in the Y direction. Figure 1 Compared with the semiconductor device 100, the number of power switch circuits PPSW is increased. The other structures of the semiconductor device 106 are similar to those of the semiconductor device 100. Figure 1 The structure of the semiconductor device 100 is the same.

[0092] As described above, in this embodiment, as in the above-described embodiments, the power supply capacity can be improved without increasing the layout area of ​​the power switch circuit PPSW. Furthermore, in this embodiment, if there is an empty area within the power domain PD1 of the semiconductor device 106, the empty area can be utilized to add the power switch circuit PPSW, thereby further improving the power supply capacity of the power domain PD1.

[0093] (Fifth embodiment)

[0094] Figure 14 An example of the layout of the semiconductor device according to the fifth embodiment is shown. Figure 1 The same elements are denoted by the same reference numerals, and detailed descriptions thereof are omitted. Figure 14 The semiconductor device 108 shown has a plurality of power switch circuits PPSW (PPSWa, PPSWb, PPSWc), and the power switch circuits PPSW are arranged in a power switch region provided around the standard cell region SCA. Figure 1 Therefore, the power supply VVDD, which is the operating power supply for the circuits arranged in the standard cell area SCA, is supplied from the power switch circuit PPSW via an upper wiring layer (not shown).

[0095] The power switch circuit PPSWa is arranged on both sides of the standard cell area SCA in the X direction. The power switch circuit PPSWa includes an n2-fin×m1 transistor and an n1-fin×m1 transistor arranged in the center in the X direction. Furthermore, the power switch circuit PPSWa includes n2-fin×m2 transistors and end caps (ECAPs) arranged on both sides of the X direction, which is the direction in which the gate electrodes of the n2-fin×m1 and n1-fin×m1 transistors are arranged.

[0096] The n2-fin×m2 transistor is arranged adjacent to the n2-fin×m1 transistor and the n1-fin×m1 transistor. The end cap ECAP is placed on the side of the n2-fin×m2 transistor opposite to the n2-fin×m1 and n1-fin×m1 transistors. Furthermore, the end cap ECAP and the adjacent n2-fin×m2 transistor maintain the spacing SP1 defined by the layout rule.

[0097] Power switch circuit PPSWb is located at a corner around the standard cell area SCA. End caps ECAP are also located around power switch circuit PPSWb, except for the end portion on the power switch circuit PPSWc side. Furthermore, power switch circuit PPSWb includes an n2-fin×m2 transistor adjacent to the end cap ECAP located at the end in the X direction, and an n1-fin×m1 transistor and an n2-fin×m1 transistor located adjacent to the column of n2-fin×m2 transistors. In power switch circuit PPSWb, the end cap ECAP and the n2-fin×m2 transistor adjacent to the end cap ECAP also ensure a gap SP1.

[0098] The power switch circuit PPSWc is arranged on both sides of the standard cell area SCA in the Y direction. The power switch circuit PPSWc has a structure obtained by removing the n2-fin×m2 transistor and the end cap ECAP adjacent to the n2-fin×m2 transistor in the X direction from the power switch circuit PPSWb.

[0099] Furthermore, each power switch circuit PPSWa, PPSWb, PPSWc may not include the main buffer unit MBUF and the sub-buffer unit SBUF. In this case, Figure 2 The power switch control circuit PCNT1 shown is provided outside each of the power switch circuits PPSWa, PPSWb, and PPSWc.

[0100] As described above, in this embodiment, as in the previous embodiment, power supply capacity can be improved without increasing the layout area of ​​the power switch circuit PPSW. Furthermore, in this embodiment, by arranging the power switch circuits PPSWa, PPSWb, and PPSWc around the standard cell area SCA, the power switch circuit SPSW within the standard cell area SCA can be eliminated. Therefore, logic circuits within the standard cell area SCA can be connected without affecting the power switch circuit SPSW, minimizing signal transmission delay. This, in turn, contributes to improved performance of the semiconductor device 108.

[0101] (Sixth embodiment)

[0102] Figure 15 An example of the layout of the semiconductor device according to the sixth embodiment is shown. Figure 1 and Figure 14 The same elements are denoted by the same reference numerals, and detailed descriptions thereof are omitted. Figure 15The semiconductor device 110 shown includes a plurality of power switch circuits PPSW (PPSWb, PPSWc, PPSWd, PPSWe), and the power switch circuits PPSW are arranged in a power switch region provided adjacent to one side in the Y direction of the standard cell region SCA. Figure 14 Likewise, SCA is not configured in the standard cell area Figure 1 Therefore, the power supply VVDD, which is the operating power supply for the circuits arranged in the standard cell area SCA, is supplied from the power switch circuit PPSW via an upper wiring layer (not shown).

[0103] In this embodiment, the power switch circuit PPSWe is arranged inside the power switch circuits PPSWb, PPSWc, and PPSWd arranged in a ring shape. The power switch circuits PPSWb and PPSWc have the same Figure 14 The power switch circuits PPSWb and PPSWc have the same structure.

[0104] The power switch circuit PPSWd includes an n2-fin×m1 transistor and an n1-fin×m1 transistor arranged on the left side in the X direction. Furthermore, the power switch circuit PPSWd includes an n2-fin×m2 transistor and an end cap ECAP arranged in this order in the X direction on the opposite side of the power switch circuit PPSWe.

[0105] Furthermore, the interval SP1 is ensured by the n2-fin×m2 transistor and the end cap ECAP adjacent to the n2-fin×m2 transistor. Figure 14 The power switch circuit PPSWa is constructed by removing one column of n2-fin×m2 transistors and one end cap ECAP. This is because one end of the power switch circuit PPSWd in the X direction is not adjacent to the standard cell area SCA.

[0106] Because power switch circuit PPSWe is located inside power switch circuits PPSWb, PPSWc, and PPSWd, it lacks the n2-fin×m2 transistors and end caps ECAP required to ensure spacing SP1. Consequently, power switch circuit PPSWe consists only of n2-fin×m1 and n2-fin×m1 transistors.

[0107] As described above, in this embodiment as well, similarly to the above-described embodiments, the power supply capacity can be improved without increasing the layout area of ​​the power switch circuit PPSW.

[0108] In addition, the above-mentioned embodiment describes an example of application to power switch circuits PSW1 and PSW2 having finFETs, but can also be applied to power switch circuits having planar transistors, nanowire transistors, nanosheet transistors, fork-sheet transistors, CFETs (Complementary FETs: complementary field-effect transistors), vertical nanowire transistors, etc.

[0109] The present invention has been described above based on the various embodiments, but the present invention is not limited to the requirements shown in the above embodiments. In this regard, changes can be made within the scope of the present invention and can be appropriately determined according to its application.

Claims

1. A semiconductor device comprising: A first area is configured with a logic circuit; a second region configured with a functional circuit different from the logic circuit; as well as a first power switch circuit provided adjacent to the second region and connecting a first power line to a second power line supplying power to the logic circuit and the functional circuit; The first power switch circuit has: a first transistor having a size larger than that of a transistor used in the logic circuit, connecting the first power supply line and the second power supply line; an end cap, which is disposed in an area adjacent to the functional circuit; as well as The second transistor is provided between the region where the first transistor is arranged and the end cap, has the same size as the transistor used in the logic circuit, and connects the first power line and the second power line.

2. The semiconductor device according to claim 1, wherein The semiconductor device includes a second power switch circuit, which is provided in the first region and connects the first power line and the second power line. The second power switch circuit has: a third transistor having a size larger than that of a transistor used in the logic circuit and connecting the first power supply line and the second power supply line; as well as a fourth transistor, which is provided adjacent to an end of the third transistor in the arrangement direction of the gate electrode of the third transistor, has the same size as the transistor used in the logic circuit, and connects the first power line and the second power line; The size of a region where the fourth transistor is arranged is the same as the size of a region where the second transistor of the first power switch circuit is arranged.

3. The semiconductor device according to claim 1, wherein The first power switch circuit includes a fifth transistor having the same size as the second transistor and connecting the first power line and the second power line.

4. The semiconductor device according to claim 1, wherein Each of the first transistor and the second transistor has a plurality of gate electrodes arranged in a first direction, The first transistor, the second transistor, and the end cap are arranged along the first direction.

5. The semiconductor device according to any one of claims 1 to 4, wherein The functional circuit is a memory IP.

6. The semiconductor device according to any one of claims 1 to 4, wherein The functional circuit is a hard macro IP.

7. The semiconductor device according to any one of claims 1 to 4, wherein The functional circuit is an analog IP.

8. A semiconductor device comprising: A first region in which a logic circuit is arranged; and a power switch region, which is provided adjacent to the first region and is provided with a plurality of power switch circuits, the power switch circuits connecting the first power line and the second power line that supplies power to the logic circuit; The plurality of power supply switch circuits include a first transistor having a size larger than that of a transistor used in the logic circuit and connecting the first power supply line and the second power supply line. At least one of the plurality of power switch circuits further comprises: a second transistor provided adjacent to an end portion in a first direction in which the gate electrodes of the first transistors are arranged in a region where the first transistors are arranged, having the same size as the transistor used in the logic circuit, and connecting the first power supply line to the second power supply line; and An end cap is provided adjacent to a side opposite to the first transistor in a region where the second transistor is arranged.

9. The semiconductor device according to claim 8, wherein The power switch area is arranged in a ring shape around the first area, The second transistor and the end cap are arranged adjacent to both ends of the first region in the first direction, and the power switch circuit including the second transistor and the end cap has the second transistor and the end cap arranged on both sides of the first transistor in the first direction.

10. The semiconductor device according to claim 8, wherein The power switch area is adjacent to the first area along a second direction orthogonal to the first direction. The power switch circuits arranged at both ends of the first direction in the power switch region include the second transistors and the end caps arranged along the first direction. The power switch circuits other than the power switch circuits arranged at both ends in the first direction in the power switch region do not include the second transistors and the end caps arranged along the first direction.

11. The semiconductor device according to claim 1 or 8, wherein The first transistor and the second transistor are finFETs.

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